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Correct trap tracing information
[thirdparty/binutils-gdb.git] / sim / d10v / simops.c
1 #include <signal.h>
2 #include <errno.h>
3 #include <sys/types.h>
4 #include <sys/stat.h>
5 #include <unistd.h>
6
7 #include "d10v_sim.h"
8 #include "simops.h"
9 #include "sys/syscall.h"
10
11 enum op_types {
12 OP_VOID,
13 OP_REG,
14 OP_REG_OUTPUT,
15 OP_DREG,
16 OP_DREG_OUTPUT,
17 OP_ACCUM,
18 OP_ACCUM_OUTPUT,
19 OP_ACCUM_REVERSE,
20 OP_CR,
21 OP_CR_OUTPUT,
22 OP_CR_REVERSE,
23 OP_FLAG,
24 OP_FLAG_OUTPUT,
25 OP_CONSTANT16,
26 OP_CONSTANT3,
27 OP_CONSTANT4,
28 OP_MEMREF,
29 OP_MEMREF2,
30 OP_POSTDEC,
31 OP_POSTINC,
32 OP_PREDEC
33 };
34
35 #ifdef DEBUG
36 static void trace_input PARAMS ((char *name,
37 enum op_types in1,
38 enum op_types in2,
39 enum op_types in3));
40
41 static void trace_output PARAMS ((enum op_types result));
42
43 #ifndef SIZE_INSTRUCTION
44 #define SIZE_INSTRUCTION 10
45 #endif
46
47 #ifndef SIZE_OPERANDS
48 #define SIZE_OPERANDS 24
49 #endif
50
51 #ifndef SIZE_VALUES
52 #define SIZE_VALUES 13
53 #endif
54
55 static void
56 trace_input (name, in1, in2, in3)
57 char *name;
58 enum op_types in1;
59 enum op_types in2;
60 enum op_types in3;
61 {
62 char *comma;
63 enum op_types in[3];
64 int i;
65 char buf[80];
66 char *p;
67 long tmp;
68 char *type;
69
70 if ((d10v_debug & DEBUG_TRACE) == 0)
71 return;
72
73 switch (State.ins_type)
74 {
75 default:
76 case INS_UNKNOWN: type = " ?"; break;
77 case INS_LEFT: type = " L"; break;
78 case INS_RIGHT: type = " R"; break;
79 case INS_LEFT_PARALLEL: type = "*L"; break;
80 case INS_RIGHT_PARALLEL: type = "*R"; break;
81 case INS_LONG: type = " B"; break;
82 }
83
84 (*d10v_callback->printf_filtered) (d10v_callback,
85 "0x%.6x %s: %-*s",
86 (unsigned)PC, type,
87 SIZE_INSTRUCTION, name);
88
89 in[0] = in1;
90 in[1] = in2;
91 in[2] = in3;
92 comma = "";
93 p = buf;
94 for (i = 0; i < 3; i++)
95 {
96 switch (in[i])
97 {
98 case OP_VOID:
99 break;
100
101 case OP_REG:
102 case OP_REG_OUTPUT:
103 case OP_DREG:
104 case OP_DREG_OUTPUT:
105 sprintf (p, "%sr%d", comma, OP[i]);
106 p += strlen (p);
107 comma = ",";
108 break;
109
110 case OP_CR:
111 case OP_CR_OUTPUT:
112 case OP_CR_REVERSE:
113 sprintf (p, "%scr%d", comma, OP[i]);
114 p += strlen (p);
115 comma = ",";
116 break;
117
118 case OP_ACCUM:
119 case OP_ACCUM_OUTPUT:
120 case OP_ACCUM_REVERSE:
121 sprintf (p, "%sa%d", comma, OP[i]);
122 p += strlen (p);
123 comma = ",";
124 break;
125
126 case OP_CONSTANT16:
127 sprintf (p, "%s%d", comma, OP[i]);
128 p += strlen (p);
129 comma = ",";
130 break;
131
132 case OP_CONSTANT4:
133 sprintf (p, "%s%d", comma, SEXT4(OP[i]));
134 p += strlen (p);
135 comma = ",";
136 break;
137
138 case OP_CONSTANT3:
139 sprintf (p, "%s%d", comma, SEXT3(OP[i]));
140 p += strlen (p);
141 comma = ",";
142 break;
143
144 case OP_MEMREF:
145 sprintf (p, "%s@r%d", comma, OP[i]);
146 p += strlen (p);
147 comma = ",";
148 break;
149
150 case OP_MEMREF2:
151 sprintf (p, "%s@(%d,r%d)", comma, (int16)OP[i], OP[i+1]);
152 p += strlen (p);
153 comma = ",";
154 break;
155
156 case OP_POSTINC:
157 sprintf (p, "%s@r%d+", comma, OP[i]);
158 p += strlen (p);
159 comma = ",";
160 break;
161
162 case OP_POSTDEC:
163 sprintf (p, "%s@r%d-", comma, OP[i]);
164 p += strlen (p);
165 comma = ",";
166 break;
167
168 case OP_PREDEC:
169 sprintf (p, "%s@-r%d", comma, OP[i]);
170 p += strlen (p);
171 comma = ",";
172 break;
173
174 case OP_FLAG:
175 case OP_FLAG_OUTPUT:
176 if (OP[i] == 0)
177 sprintf (p, "%sf0", comma);
178
179 else if (OP[i] == 1)
180 sprintf (p, "%sf1", comma);
181
182 else
183 sprintf (p, "%sc", comma);
184
185 p += strlen (p);
186 comma = ",";
187 break;
188 }
189 }
190
191 if ((d10v_debug & DEBUG_VALUES) == 0)
192 {
193 *p++ = '\n';
194 *p = '\0';
195 (*d10v_callback->printf_filtered) (d10v_callback, "%s", buf);
196 }
197 else
198 {
199 *p = '\0';
200 (*d10v_callback->printf_filtered) (d10v_callback, "%-*s", SIZE_OPERANDS, buf);
201
202 p = buf;
203 for (i = 0; i < 3; i++)
204 {
205 buf[0] = '\0';
206 switch (in[i])
207 {
208 case OP_VOID:
209 (*d10v_callback->printf_filtered) (d10v_callback, "%*s", SIZE_VALUES, "");
210 break;
211
212 case OP_REG_OUTPUT:
213 case OP_DREG_OUTPUT:
214 case OP_CR_OUTPUT:
215 case OP_ACCUM_OUTPUT:
216 case OP_FLAG_OUTPUT:
217 (*d10v_callback->printf_filtered) (d10v_callback, "%*s", SIZE_VALUES, "---");
218 break;
219
220 case OP_REG:
221 case OP_MEMREF:
222 case OP_POSTDEC:
223 case OP_POSTINC:
224 case OP_PREDEC:
225 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
226 (uint16)State.regs[OP[i]]);
227 break;
228
229 case OP_DREG:
230 tmp = (long)((((uint32) State.regs[OP[i]]) << 16) | ((uint32) State.regs[OP[i]+1]));
231 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.8lx", SIZE_VALUES-10, "", tmp);
232 break;
233
234 case OP_CR:
235 case OP_CR_REVERSE:
236 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
237 (uint16)State.cregs[OP[i]]);
238 break;
239
240 case OP_ACCUM:
241 case OP_ACCUM_REVERSE:
242 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.2x%.8lx", SIZE_VALUES-12, "",
243 ((int)(State.a[OP[i]] >> 32) & 0xff),
244 ((unsigned long)State.a[OP[i]]) & 0xffffffff);
245 break;
246
247 case OP_CONSTANT16:
248 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
249 (uint16)OP[i]);
250 break;
251
252 case OP_CONSTANT4:
253 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
254 (uint16)SEXT4(OP[i]));
255 break;
256
257 case OP_CONSTANT3:
258 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
259 (uint16)SEXT3(OP[i]));
260 break;
261
262 case OP_FLAG:
263 if (OP[i] == 0)
264 (*d10v_callback->printf_filtered) (d10v_callback, "%*sF0 = %d", SIZE_VALUES-6, "",
265 State.F0 != 0);
266
267 else if (OP[i] == 1)
268 (*d10v_callback->printf_filtered) (d10v_callback, "%*sF1 = %d", SIZE_VALUES-6, "",
269 State.F1 != 0);
270
271 else
272 (*d10v_callback->printf_filtered) (d10v_callback, "%*sC = %d", SIZE_VALUES-5, "",
273 State.C != 0);
274
275 break;
276
277 case OP_MEMREF2:
278 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
279 (uint16)OP[i]);
280 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
281 (uint16)State.regs[OP[++i]]);
282 break;
283 }
284 }
285 }
286 }
287
288 static void
289 trace_output (result)
290 enum op_types result;
291 {
292 if ((d10v_debug & (DEBUG_TRACE | DEBUG_VALUES)) == (DEBUG_TRACE | DEBUG_VALUES))
293 {
294 long tmp;
295
296 switch (result)
297 {
298 default:
299 putchar ('\n');
300 break;
301
302 case OP_REG:
303 case OP_REG_OUTPUT:
304 (*d10v_callback->printf_filtered) (d10v_callback, " :: %*s0x%.4x F0=%d F1=%d C=%d\n", SIZE_VALUES-6, "",
305 (uint16)State.regs[OP[0]],
306 State.F0 != 0, State.F1 != 0, State.C != 0);
307 break;
308
309 case OP_DREG:
310 case OP_DREG_OUTPUT:
311 tmp = (long)((((uint32) State.regs[OP[0]]) << 16) | ((uint32) State.regs[OP[0]+1]));
312 (*d10v_callback->printf_filtered) (d10v_callback, " :: %*s0x%.8lx F0=%d F1=%d C=%d\n", SIZE_VALUES-10, "", tmp,
313 State.F0 != 0, State.F1 != 0, State.C != 0);
314 break;
315
316 case OP_CR:
317 case OP_CR_OUTPUT:
318 (*d10v_callback->printf_filtered) (d10v_callback, " :: %*s0x%.4x F0=%d F1=%d C=%d\n", SIZE_VALUES-6, "",
319 (uint16)State.cregs[OP[0]],
320 State.F0 != 0, State.F1 != 0, State.C != 0);
321 break;
322
323 case OP_CR_REVERSE:
324 (*d10v_callback->printf_filtered) (d10v_callback, " :: %*s0x%.4x F0=%d F1=%d C=%d\n", SIZE_VALUES-6, "",
325 (uint16)State.cregs[OP[1]],
326 State.F0 != 0, State.F1 != 0, State.C != 0);
327 break;
328
329 case OP_ACCUM:
330 case OP_ACCUM_OUTPUT:
331 (*d10v_callback->printf_filtered) (d10v_callback, " :: %*s0x%.2x%.8lx F0=%d F1=%d C=%d\n", SIZE_VALUES-12, "",
332 ((int)(State.a[OP[0]] >> 32) & 0xff),
333 ((unsigned long)State.a[OP[0]]) & 0xffffffff,
334 State.F0 != 0, State.F1 != 0, State.C != 0);
335 break;
336
337 case OP_ACCUM_REVERSE:
338 (*d10v_callback->printf_filtered) (d10v_callback, " :: %*s0x%.2x%.8lx F0=%d F1=%d C=%d\n", SIZE_VALUES-12, "",
339 ((int)(State.a[OP[1]] >> 32) & 0xff),
340 ((unsigned long)State.a[OP[1]]) & 0xffffffff,
341 State.F0 != 0, State.F1 != 0, State.C != 0);
342 break;
343
344 case OP_FLAG:
345 case OP_FLAG_OUTPUT:
346 (*d10v_callback->printf_filtered) (d10v_callback, " :: %*s F0=%d F1=%d C=%d\n", SIZE_VALUES, "",
347 State.F0 != 0, State.F1 != 0, State.C != 0);
348 break;
349 }
350 }
351 }
352
353 #else
354 #define trace_input(NAME, IN1, IN2, IN3)
355 #define trace_output(RESULT)
356 #endif
357
358 /* abs */
359 void
360 OP_4607 ()
361 {
362 trace_input ("abs", OP_REG, OP_VOID, OP_VOID);
363 State.F1 = State.F0;
364 if ((int16)(State.regs[OP[0]]) < 0)
365 {
366 State.regs[OP[0]] = -(int16)(State.regs[OP[0]]);
367 State.F0 = 1;
368 }
369 else
370 State.F0 = 0;
371 trace_output (OP_REG);
372 }
373
374 /* abs */
375 void
376 OP_5607 ()
377 {
378 int64 tmp;
379
380 trace_input ("abs", OP_ACCUM, OP_VOID, OP_VOID);
381 State.F1 = State.F0;
382 State.a[OP[0]] = SEXT40(State.a[OP[0]]);
383
384 if (State.a[OP[0]] < 0 )
385 {
386 tmp = -State.a[OP[0]];
387 if (State.ST)
388 {
389 if (tmp > MAX32)
390 State.a[OP[0]] = MAX32;
391 else if (tmp < MIN32)
392 State.a[OP[0]] = MIN32;
393 else
394 State.a[OP[0]] = tmp & MASK40;
395 }
396 else
397 State.a[OP[0]] = tmp & MASK40;
398 State.F0 = 1;
399 }
400 else
401 State.F0 = 0;
402 trace_output (OP_ACCUM);
403 }
404
405 /* add */
406 void
407 OP_200 ()
408 {
409 uint16 tmp = State.regs[OP[0]];
410 trace_input ("add", OP_REG, OP_REG, OP_VOID);
411 State.regs[OP[0]] += State.regs[OP[1]];
412 if ( tmp > State.regs[OP[0]])
413 State.C = 1;
414 else
415 State.C = 0;
416 trace_output (OP_REG);
417 }
418
419 /* add */
420 void
421 OP_1201 ()
422 {
423 int64 tmp;
424 tmp = SEXT40(State.a[OP[0]]) + (SEXT16 (State.regs[OP[1]]) << 16 | State.regs[OP[1]+1]);
425
426 trace_input ("add", OP_ACCUM, OP_REG, OP_VOID);
427 if (State.ST)
428 {
429 if ( tmp > MAX32)
430 State.a[OP[0]] = MAX32;
431 else if ( tmp < MIN32)
432 State.a[OP[0]] = MIN32;
433 else
434 State.a[OP[0]] = tmp & MASK40;
435 }
436 else
437 State.a[OP[0]] = tmp & MASK40;
438 trace_output (OP_ACCUM);
439 }
440
441 /* add */
442 void
443 OP_1203 ()
444 {
445 int64 tmp;
446 tmp = SEXT40(State.a[OP[0]]) + SEXT40(State.a[OP[1]]);
447
448 trace_input ("add", OP_ACCUM, OP_ACCUM, OP_VOID);
449 if (State.ST)
450 {
451 if (tmp > MAX32)
452 State.a[OP[0]] = MAX32;
453 else if ( tmp < MIN32)
454 State.a[OP[0]] = MIN32;
455 else
456 State.a[OP[0]] = tmp & MASK40;
457 }
458 else
459 State.a[OP[0]] = tmp & MASK40;
460 trace_output (OP_ACCUM);
461 }
462
463 /* add2w */
464 void
465 OP_1200 ()
466 {
467 uint32 tmp;
468 uint32 tmp1 = (State.regs[OP[0]]) << 16 | State.regs[OP[0]+1];
469 uint32 tmp2 = (State.regs[OP[1]]) << 16 | State.regs[OP[1]+1];
470
471 trace_input ("add2w", OP_DREG, OP_DREG, OP_VOID);
472 tmp = tmp1 + tmp2;
473 if ( (tmp < tmp1) || (tmp < tmp2) )
474 State.C = 1;
475 else
476 State.C = 0;
477 State.regs[OP[0]] = tmp >> 16;
478 State.regs[OP[0]+1] = tmp & 0xFFFF;
479 trace_output (OP_DREG);
480 }
481
482 /* add3 */
483 void
484 OP_1000000 ()
485 {
486 uint16 tmp = State.regs[OP[0]];
487 State.regs[OP[0]] = State.regs[OP[1]] + OP[2];
488
489 trace_input ("add3", OP_REG_OUTPUT, OP_REG, OP_CONSTANT16);
490 if ( tmp > State.regs[OP[0]])
491 State.C = 1;
492 else
493 State.C = 0;
494 trace_output (OP_REG);
495 }
496
497 /* addac3 */
498 void
499 OP_17000200 ()
500 {
501 int64 tmp;
502 tmp = SEXT40(State.a[OP[2]]) + SEXT40 ((State.regs[OP[1]] << 16) | State.regs[OP[1]+1]);
503
504 trace_input ("addac3", OP_DREG_OUTPUT, OP_DREG, OP_ACCUM);
505 State.regs[OP[0]] = (tmp >> 16) & 0xffff;
506 State.regs[OP[0]+1] = tmp & 0xffff;
507 trace_output (OP_DREG);
508 }
509
510 /* addac3 */
511 void
512 OP_17000202 ()
513 {
514 int64 tmp;
515 tmp = SEXT40(State.a[OP[1]]) + SEXT40(State.a[OP[2]]);
516
517 trace_input ("addac3", OP_DREG_OUTPUT, OP_ACCUM, OP_ACCUM);
518 State.regs[OP[0]] = (tmp >> 16) & 0xffff;
519 State.regs[OP[0]+1] = tmp & 0xffff;
520 trace_output (OP_DREG);
521 }
522
523 /* addac3s */
524 void
525 OP_17001200 ()
526 {
527 int64 tmp;
528 State.F1 = State.F0;
529
530 trace_input ("addac3s", OP_DREG_OUTPUT, OP_DREG, OP_ACCUM);
531 tmp = SEXT40(State.a[OP[2]]) + SEXT40 ((State.regs[OP[1]] << 16) | State.regs[OP[1]+1]);
532 if ( tmp > MAX32)
533 {
534 State.regs[OP[0]] = 0x7fff;
535 State.regs[OP[0]+1] = 0xffff;
536 State.F0 = 1;
537 }
538 else if (tmp < MIN32)
539 {
540 State.regs[OP[0]] = 0x8000;
541 State.regs[OP[0]+1] = 0;
542 State.F0 = 1;
543 }
544 else
545 {
546 State.regs[OP[0]] = (tmp >> 16) & 0xffff;
547 State.regs[OP[0]+1] = tmp & 0xffff;
548 State.F0 = 0;
549 }
550 trace_output (OP_DREG);
551 }
552
553 /* addac3s */
554 void
555 OP_17001202 ()
556 {
557 int64 tmp;
558 State.F1 = State.F0;
559
560 trace_input ("addac3s", OP_DREG_OUTPUT, OP_ACCUM, OP_ACCUM);
561 tmp = SEXT40(State.a[OP[1]]) + SEXT40(State.a[OP[2]]);
562 if ( tmp > MAX32)
563 {
564 State.regs[OP[0]] = 0x7fff;
565 State.regs[OP[0]+1] = 0xffff;
566 State.F0 = 1;
567 }
568 else if (tmp < MIN32)
569 {
570 State.regs[OP[0]] = 0x8000;
571 State.regs[OP[0]+1] = 0;
572 State.F0 = 1;
573 }
574 else
575 {
576 State.regs[OP[0]] = (tmp >> 16) & 0xffff;
577 State.regs[OP[0]+1] = tmp & 0xffff;
578 State.F0 = 0;
579 }
580 trace_output (OP_DREG);
581 }
582
583 /* addi */
584 void
585 OP_201 ()
586 {
587 uint tmp = State.regs[OP[0]];
588 if (OP[1] == 0)
589 OP[1] = 16;
590 trace_input ("addi", OP_REG, OP_CONSTANT16, OP_VOID);
591 State.regs[OP[0]] += OP[1];
592 if (tmp > State.regs[OP[0]])
593 State.C = 1;
594 else
595 State.C = 0;
596 trace_output (OP_REG);
597 }
598
599 /* and */
600 void
601 OP_C00 ()
602 {
603 trace_input ("and", OP_REG, OP_REG, OP_VOID);
604 State.regs[OP[0]] &= State.regs[OP[1]];
605 trace_output (OP_REG);
606 }
607
608 /* and3 */
609 void
610 OP_6000000 ()
611 {
612 trace_input ("and3", OP_REG_OUTPUT, OP_REG, OP_CONSTANT16);
613 State.regs[OP[0]] = State.regs[OP[1]] & OP[2];
614 trace_output (OP_REG);
615 }
616
617 /* bclri */
618 void
619 OP_C01 ()
620 {
621 trace_input ("bclri", OP_REG, OP_CONSTANT16, OP_VOID);
622 State.regs[OP[0]] &= ~(0x8000 >> OP[1]);
623 trace_output (OP_REG);
624 }
625
626 /* bl.s */
627 void
628 OP_4900 ()
629 {
630 trace_input ("bl.s", OP_CONSTANT16, OP_VOID, OP_VOID);
631 State.regs[13] = PC+1;
632 PC += SEXT8 (OP[0]);
633 trace_output (OP_VOID);
634 }
635
636 /* bl.l */
637 void
638 OP_24800000 ()
639 {
640 trace_input ("bl.l", OP_CONSTANT16, OP_VOID, OP_VOID);
641 State.regs[13] = PC+1;
642 PC += OP[0];
643 trace_output (OP_VOID);
644 }
645
646 /* bnoti */
647 void
648 OP_A01 ()
649 {
650 trace_input ("bnoti", OP_REG, OP_CONSTANT16, OP_VOID);
651 State.regs[OP[0]] ^= 0x8000 >> OP[1];
652 trace_output (OP_REG);
653 }
654
655 /* bra.s */
656 void
657 OP_4800 ()
658 {
659 trace_input ("bra.s", OP_CONSTANT16, OP_VOID, OP_VOID);
660 PC += SEXT8 (OP[0]);
661 trace_output (OP_VOID);
662 }
663
664 /* bra.l */
665 void
666 OP_24000000 ()
667 {
668 trace_input ("bra.l", OP_CONSTANT16, OP_VOID, OP_VOID);
669 PC += OP[0];
670 trace_output (OP_VOID);
671 }
672
673 /* brf0f.s */
674 void
675 OP_4A00 ()
676 {
677 trace_input ("brf0f.s", OP_CONSTANT16, OP_VOID, OP_VOID);
678 if (State.F0 == 0)
679 PC += SEXT8 (OP[0]);
680 trace_output (OP_FLAG);
681 }
682
683 /* brf0f.l */
684 void
685 OP_25000000 ()
686 {
687 trace_input ("brf0f.l", OP_CONSTANT16, OP_VOID, OP_VOID);
688 if (State.F0 == 0)
689 PC += OP[0];
690 trace_output (OP_FLAG);
691 }
692
693 /* brf0t.s */
694 void
695 OP_4B00 ()
696 {
697 trace_input ("brf0t.s", OP_CONSTANT16, OP_VOID, OP_VOID);
698 if (State.F0)
699 PC += SEXT8 (OP[0]);
700 trace_output (OP_FLAG);
701 }
702
703 /* brf0t.l */
704 void
705 OP_25800000 ()
706 {
707 trace_input ("brf0t.l", OP_CONSTANT16, OP_VOID, OP_VOID);
708 if (State.F0)
709 PC += OP[0];
710 trace_output (OP_FLAG);
711 }
712
713 /* bseti */
714 void
715 OP_801 ()
716 {
717 trace_input ("bseti", OP_REG, OP_CONSTANT16, OP_VOID);
718 State.regs[OP[0]] |= 0x8000 >> OP[1];
719 trace_output (OP_REG);
720 }
721
722 /* btsti */
723 void
724 OP_E01 ()
725 {
726 trace_input ("btsti", OP_REG, OP_CONSTANT16, OP_VOID);
727 State.F1 = State.F0;
728 State.F0 = (State.regs[OP[0]] & (0x8000 >> OP[1])) ? 1 : 0;
729 trace_output (OP_FLAG);
730 }
731
732 /* clrac */
733 void
734 OP_5601 ()
735 {
736 trace_input ("clrac", OP_ACCUM_OUTPUT, OP_VOID, OP_VOID);
737 State.a[OP[0]] = 0;
738 trace_output (OP_ACCUM);
739 }
740
741 /* cmp */
742 void
743 OP_600 ()
744 {
745 trace_input ("cmp", OP_REG, OP_REG, OP_VOID);
746 State.F1 = State.F0;
747 State.F0 = ((int16)(State.regs[OP[0]]) < (int16)(State.regs[OP[1]])) ? 1 : 0;
748 trace_output (OP_FLAG);
749 }
750
751 /* cmp */
752 void
753 OP_1603 ()
754 {
755 trace_input ("cmp", OP_ACCUM, OP_ACCUM, OP_VOID);
756 State.F1 = State.F0;
757 State.F0 = (SEXT40(State.a[OP[0]]) < SEXT40(State.a[OP[1]])) ? 1 : 0;
758 trace_output (OP_FLAG);
759 }
760
761 /* cmpeq */
762 void
763 OP_400 ()
764 {
765 trace_input ("cmpeq", OP_REG, OP_REG, OP_VOID);
766 State.F1 = State.F0;
767 State.F0 = (State.regs[OP[0]] == State.regs[OP[1]]) ? 1 : 0;
768 trace_output (OP_FLAG);
769 }
770
771 /* cmpeq */
772 void
773 OP_1403 ()
774 {
775 trace_input ("cmpeq", OP_ACCUM, OP_ACCUM, OP_VOID);
776 State.F1 = State.F0;
777 State.F0 = (State.a[OP[0]] == State.a[OP[1]]) ? 1 : 0;
778 trace_output (OP_FLAG);
779 }
780
781 /* cmpeqi.s */
782 void
783 OP_401 ()
784 {
785 trace_input ("cmpeqi.s", OP_REG, OP_CONSTANT16, OP_VOID);
786 State.F1 = State.F0;
787 State.F0 = (State.regs[OP[0]] == SEXT4(OP[1])) ? 1 : 0;
788 trace_output (OP_FLAG);
789 }
790
791 /* cmpeqi.l */
792 void
793 OP_2000000 ()
794 {
795 trace_input ("cmpeqi.l", OP_REG, OP_CONSTANT16, OP_VOID);
796 State.F1 = State.F0;
797 State.F0 = (State.regs[OP[0]] == OP[1]) ? 1 : 0;
798 trace_output (OP_FLAG);
799 }
800
801 /* cmpi.s */
802 void
803 OP_601 ()
804 {
805 trace_input ("cmpi.s", OP_REG, OP_CONSTANT4, OP_VOID);
806 State.F1 = State.F0;
807 State.F0 = ((int16)(State.regs[OP[0]]) < SEXT4(OP[1])) ? 1 : 0;
808 trace_output (OP_FLAG);
809 }
810
811 /* cmpi.l */
812 void
813 OP_3000000 ()
814 {
815 trace_input ("cmpi.l", OP_REG, OP_CONSTANT16, OP_VOID);
816 State.F1 = State.F0;
817 State.F0 = ((int16)(State.regs[OP[0]]) < (int16)(OP[1])) ? 1 : 0;
818 trace_output (OP_FLAG);
819 }
820
821 /* cmpu */
822 void
823 OP_4600 ()
824 {
825 trace_input ("cmpu", OP_REG, OP_REG, OP_VOID);
826 State.F1 = State.F0;
827 State.F0 = (State.regs[OP[0]] < State.regs[OP[1]]) ? 1 : 0;
828 trace_output (OP_FLAG);
829 }
830
831 /* cmpui */
832 void
833 OP_23000000 ()
834 {
835 trace_input ("cmpui", OP_REG, OP_CONSTANT16, OP_VOID);
836 State.F1 = State.F0;
837 State.F0 = (State.regs[OP[0]] < OP[1]) ? 1 : 0;
838 trace_output (OP_FLAG);
839 }
840
841 /* cpfg */
842 void
843 OP_4E09 ()
844 {
845 uint8 *src, *dst;
846
847 trace_input ("cpfg", OP_FLAG_OUTPUT, OP_FLAG, OP_VOID);
848 if (OP[0] == 0)
849 dst = &State.F0;
850 else
851 dst = &State.F1;
852
853 if (OP[1] == 0)
854 src = &State.F0;
855 else if (OP[1] == 1)
856 src = &State.F1;
857 else
858 src = &State.C;
859
860 *dst = *src;
861 trace_output (OP_FLAG);
862 }
863
864 /* dbt */
865 void
866 OP_5F20 ()
867 {
868 d10v_callback->printf_filtered(d10v_callback, "***** DBT ***** PC=%x\n",PC);
869 State.exception = SIGTRAP;
870 }
871
872 /* divs */
873 void
874 OP_14002800 ()
875 {
876 uint16 foo, tmp, tmpf;
877
878 trace_input ("divs", OP_DREG, OP_REG, OP_VOID);
879 foo = (State.regs[OP[0]] << 1) | (State.regs[OP[0]+1] >> 15);
880 tmp = (int16)foo - (int16)(State.regs[OP[1]]);
881 tmpf = (foo >= State.regs[OP[1]]) ? 1 : 0;
882 State.regs[OP[0]] = (tmpf == 1) ? tmp : foo;
883 State.regs[OP[0]+1] = (State.regs[OP[0]+1] << 1) | tmpf;
884 trace_output (OP_DREG);
885 }
886
887 /* exef0f */
888 void
889 OP_4E04 ()
890 {
891 trace_input ("exef0f", OP_VOID, OP_VOID, OP_VOID);
892 State.exe = (State.F0 == 0);
893 trace_output (OP_FLAG);
894 }
895
896 /* exef0t */
897 void
898 OP_4E24 ()
899 {
900 trace_input ("exef0t", OP_VOID, OP_VOID, OP_VOID);
901 State.exe = (State.F0 != 0);
902 trace_output (OP_FLAG);
903 }
904
905 /* exef1f */
906 void
907 OP_4E40 ()
908 {
909 trace_input ("exef1f", OP_VOID, OP_VOID, OP_VOID);
910 State.exe = (State.F1 == 0);
911 trace_output (OP_FLAG);
912 }
913
914 /* exef1t */
915 void
916 OP_4E42 ()
917 {
918 trace_input ("exef1t", OP_VOID, OP_VOID, OP_VOID);
919 State.exe = (State.F1 != 0);
920 trace_output (OP_FLAG);
921 }
922
923 /* exefaf */
924 void
925 OP_4E00 ()
926 {
927 trace_input ("exefaf", OP_VOID, OP_VOID, OP_VOID);
928 State.exe = (State.F0 == 0) & (State.F1 == 0);
929 trace_output (OP_FLAG);
930 }
931
932 /* exefat */
933 void
934 OP_4E02 ()
935 {
936 trace_input ("exefat", OP_VOID, OP_VOID, OP_VOID);
937 State.exe = (State.F0 == 0) & (State.F1 != 0);
938 trace_output (OP_FLAG);
939 }
940
941 /* exetaf */
942 void
943 OP_4E20 ()
944 {
945 trace_input ("exetaf", OP_VOID, OP_VOID, OP_VOID);
946 State.exe = (State.F0 != 0) & (State.F1 == 0);
947 trace_output (OP_FLAG);
948 }
949
950 /* exetat */
951 void
952 OP_4E22 ()
953 {
954 trace_input ("exetat", OP_VOID, OP_VOID, OP_VOID);
955 State.exe = (State.F0 != 0) & (State.F1 != 0);
956 trace_output (OP_FLAG);
957 }
958
959 /* exp */
960 void
961 OP_15002A00 ()
962 {
963 uint32 tmp, foo;
964 int i;
965
966 trace_input ("exp", OP_REG_OUTPUT, OP_DREG, OP_VOID);
967 if (((int16)State.regs[OP[1]]) >= 0)
968 tmp = (State.regs[OP[1]] << 16) | State.regs[OP[1]+1];
969 else
970 tmp = ~((State.regs[OP[1]] << 16) | State.regs[OP[1]+1]);
971
972 foo = 0x40000000;
973 for (i=1;i<17;i++)
974 {
975 if (tmp & foo)
976 {
977 State.regs[OP[0]] = i-1;
978 trace_output (OP_REG);
979 return;
980 }
981 foo >>= 1;
982 }
983 State.regs[OP[0]] = 16;
984 trace_output (OP_REG);
985 }
986
987 /* exp */
988 void
989 OP_15002A02 ()
990 {
991 int64 tmp, foo;
992 int i;
993
994 trace_input ("exp", OP_REG_OUTPUT, OP_ACCUM, OP_VOID);
995 if (SEXT40(State.a[OP[1]]) >= 0)
996 tmp = State.a[OP[1]];
997 else
998 tmp = ~(State.a[OP[1]]);
999
1000 foo = 0x4000000000LL;
1001 for (i=1;i<25;i++)
1002 {
1003 if (tmp & foo)
1004 {
1005 State.regs[OP[0]] = i-9;
1006 trace_output (OP_REG);
1007 return;
1008 }
1009 foo >>= 1;
1010 }
1011 State.regs[OP[0]] = 16;
1012 trace_output (OP_REG);
1013 }
1014
1015 /* jl */
1016 void
1017 OP_4D00 ()
1018 {
1019 trace_input ("jl", OP_REG, OP_VOID, OP_VOID);
1020 State.regs[13] = PC+1;
1021 PC = State.regs[OP[0]];
1022 trace_output (OP_VOID);
1023 }
1024
1025 /* jmp */
1026 void
1027 OP_4C00 ()
1028 {
1029 trace_input ("jmp", OP_REG, OP_VOID, OP_VOID);
1030 PC = State.regs[OP[0]];
1031 trace_output (OP_VOID);
1032 }
1033
1034 /* ld */
1035 void
1036 OP_30000000 ()
1037 {
1038 trace_input ("ld", OP_REG_OUTPUT, OP_MEMREF2, OP_VOID);
1039 State.regs[OP[0]] = RW (OP[1] + State.regs[OP[2]]);
1040 trace_output (OP_REG);
1041 }
1042
1043 /* ld */
1044 void
1045 OP_6401 ()
1046 {
1047 trace_input ("ld", OP_REG_OUTPUT, OP_POSTDEC, OP_VOID);
1048 State.regs[OP[0]] = RW (State.regs[OP[1]]);
1049 INC_ADDR(State.regs[OP[1]],-2);
1050 trace_output (OP_REG);
1051 }
1052
1053 /* ld */
1054 void
1055 OP_6001 ()
1056 {
1057 trace_input ("ld", OP_REG_OUTPUT, OP_POSTINC, OP_VOID);
1058 State.regs[OP[0]] = RW (State.regs[OP[1]]);
1059 INC_ADDR(State.regs[OP[1]],2);
1060 trace_output (OP_REG);
1061 }
1062
1063 /* ld */
1064 void
1065 OP_6000 ()
1066 {
1067 trace_input ("ld", OP_REG_OUTPUT, OP_MEMREF, OP_VOID);
1068 State.regs[OP[0]] = RW (State.regs[OP[1]]);
1069 trace_output (OP_REG);
1070 }
1071
1072 /* ld2w */
1073 void
1074 OP_31000000 ()
1075 {
1076 trace_input ("ld2w", OP_REG_OUTPUT, OP_MEMREF2, OP_VOID);
1077 State.regs[OP[0]] = RW (OP[1] + State.regs[OP[2]]);
1078 State.regs[OP[0]+1] = RW (OP[1] + State.regs[OP[2]] + 2);
1079 trace_output (OP_DREG);
1080 }
1081
1082 /* ld2w */
1083 void
1084 OP_6601 ()
1085 {
1086 trace_input ("ld2w", OP_REG_OUTPUT, OP_POSTDEC, OP_VOID);
1087 State.regs[OP[0]] = RW (State.regs[OP[1]]);
1088 State.regs[OP[0]+1] = RW (State.regs[OP[1]]+2);
1089 INC_ADDR(State.regs[OP[1]],-4);
1090 trace_output (OP_DREG);
1091 }
1092
1093 /* ld2w */
1094 void
1095 OP_6201 ()
1096 {
1097 trace_input ("ld2w", OP_REG_OUTPUT, OP_POSTINC, OP_VOID);
1098 State.regs[OP[0]] = RW (State.regs[OP[1]]);
1099 State.regs[OP[0]+1] = RW (State.regs[OP[1]]+2);
1100 INC_ADDR(State.regs[OP[1]],4);
1101 trace_output (OP_REG);
1102 }
1103
1104 /* ld2w */
1105 void
1106 OP_6200 ()
1107 {
1108 trace_input ("ld", OP_REG_OUTPUT, OP_MEMREF, OP_VOID);
1109 State.regs[OP[0]] = RW (State.regs[OP[1]]);
1110 State.regs[OP[0]+1] = RW (State.regs[OP[1]]+2);
1111 trace_output (OP_REG);
1112 }
1113
1114 /* ldb */
1115 void
1116 OP_38000000 ()
1117 {
1118 trace_input ("ldb", OP_REG_OUTPUT, OP_MEMREF2, OP_VOID);
1119 State.regs[OP[0]] = RB (OP[1] + State.regs[OP[2]]);
1120 SEXT8 (State.regs[OP[0]]);
1121 trace_output (OP_REG);
1122 }
1123
1124 /* ldb */
1125 void
1126 OP_7000 ()
1127 {
1128 trace_input ("ldb", OP_REG_OUTPUT, OP_MEMREF, OP_VOID);
1129 State.regs[OP[0]] = RB (State.regs[OP[1]]);
1130 SEXT8 (State.regs[OP[0]]);
1131 trace_output (OP_REG);
1132 }
1133
1134 /* ldi.s */
1135 void
1136 OP_4001 ()
1137 {
1138 trace_input ("ldi.s", OP_REG_OUTPUT, OP_CONSTANT4, OP_VOID);
1139 State.regs[OP[0]] = SEXT4(OP[1]);
1140 trace_output (OP_REG);
1141 }
1142
1143 /* ldi.l */
1144 void
1145 OP_20000000 ()
1146 {
1147 trace_input ("ldi.s", OP_REG_OUTPUT, OP_CONSTANT16, OP_VOID);
1148 State.regs[OP[0]] = OP[1];
1149 trace_output (OP_REG);
1150 }
1151
1152 /* ldub */
1153 void
1154 OP_39000000 ()
1155 {
1156 trace_input ("ldub", OP_REG_OUTPUT, OP_MEMREF2, OP_VOID);
1157 State.regs[OP[0]] = RB (OP[1] + State.regs[OP[2]]);
1158 trace_output (OP_REG);
1159 }
1160
1161 /* ldub */
1162 void
1163 OP_7200 ()
1164 {
1165 trace_input ("ldub", OP_REG_OUTPUT, OP_MEMREF, OP_VOID);
1166 State.regs[OP[0]] = RB (State.regs[OP[1]]);
1167 trace_output (OP_REG);
1168 }
1169
1170 /* mac */
1171 void
1172 OP_2A00 ()
1173 {
1174 int64 tmp;
1175
1176 trace_input ("mac", OP_ACCUM, OP_REG, OP_REG);
1177 tmp = SEXT40 ((int16)(State.regs[OP[1]]) * (int16)(State.regs[OP[2]]));
1178
1179 if (State.FX)
1180 tmp = SEXT40( (tmp << 1) & MASK40);
1181
1182 if (State.ST && tmp > MAX32)
1183 tmp = MAX32;
1184
1185 tmp += SEXT40(State.a[OP[0]]);
1186 if (State.ST)
1187 {
1188 if (tmp > MAX32)
1189 State.a[OP[0]] = MAX32;
1190 else if (tmp < MIN32)
1191 State.a[OP[0]] = MIN32;
1192 else
1193 State.a[OP[0]] = tmp & MASK40;
1194 }
1195 else
1196 State.a[OP[0]] = tmp & MASK40;
1197 trace_output (OP_ACCUM);
1198 }
1199
1200 /* macsu */
1201 void
1202 OP_1A00 ()
1203 {
1204 int64 tmp;
1205
1206 trace_input ("macsu", OP_ACCUM, OP_REG, OP_REG);
1207 tmp = SEXT40 ((int16)State.regs[OP[1]] * State.regs[OP[2]]);
1208 if (State.FX)
1209 tmp = SEXT40( (tmp << 1) & MASK40);
1210
1211 State.a[OP[0]] = (SEXT40 (State.a[OP[0]]) + tmp) & MASK40;
1212 trace_output (OP_ACCUM);
1213 }
1214
1215 /* macu */
1216 void
1217 OP_3A00 ()
1218 {
1219 int64 tmp;
1220
1221 trace_input ("macu", OP_ACCUM, OP_REG, OP_REG);
1222 tmp = SEXT40 (State.regs[OP[1]] * State.regs[OP[2]]);
1223 if (State.FX)
1224 tmp = SEXT40( (tmp << 1) & MASK40);
1225 State.a[OP[0]] = (SEXT40 (State.a[OP[0]]) + tmp) & MASK40;
1226 trace_output (OP_ACCUM);
1227 }
1228
1229 /* max */
1230 void
1231 OP_2600 ()
1232 {
1233 trace_input ("max", OP_REG, OP_REG, OP_VOID);
1234 State.F1 = State.F0;
1235 if ((int16)State.regs[OP[1]] > (int16)State.regs[OP[0]])
1236 {
1237 State.regs[OP[0]] = State.regs[OP[1]];
1238 State.F0 = 1;
1239 }
1240 else
1241 State.F0 = 0;
1242 trace_output (OP_REG);
1243 }
1244
1245 /* max */
1246 void
1247 OP_3600 ()
1248 {
1249 int64 tmp;
1250
1251 trace_input ("max", OP_ACCUM, OP_DREG, OP_VOID);
1252 State.F1 = State.F0;
1253 tmp = SEXT16 (State.regs[OP[1]]) << 16 | State.regs[OP[1]+1];
1254 if (tmp > SEXT40(State.a[OP[0]]))
1255 {
1256 State.a[OP[0]] = tmp & MASK40;
1257 State.F0 = 1;
1258 }
1259 else
1260 State.F0 = 0;
1261 trace_output (OP_ACCUM);
1262 }
1263
1264 /* max */
1265 void
1266 OP_3602 ()
1267 {
1268 trace_input ("max", OP_ACCUM, OP_ACCUM, OP_VOID);
1269 State.F1 = State.F0;
1270 if (SEXT40(State.a[OP[1]]) > SEXT40(State.a[OP[0]]))
1271 {
1272 State.a[OP[0]] = State.a[OP[1]];
1273 State.F0 = 1;
1274 }
1275 else
1276 State.F0 = 0;
1277 trace_output (OP_ACCUM);
1278 }
1279
1280
1281 /* min */
1282 void
1283 OP_2601 ()
1284 {
1285 trace_input ("min", OP_REG, OP_REG, OP_VOID);
1286 State.F1 = State.F0;
1287 if ((int16)State.regs[OP[1]] < (int16)State.regs[OP[0]])
1288 {
1289 State.regs[OP[0]] = State.regs[OP[1]];
1290 State.F0 = 1;
1291 }
1292 else
1293 State.F0 = 0;
1294 trace_output (OP_REG);
1295 }
1296
1297 /* min */
1298 void
1299 OP_3601 ()
1300 {
1301 int64 tmp;
1302
1303 trace_input ("min", OP_ACCUM, OP_DREG, OP_VOID);
1304 State.F1 = State.F0;
1305 tmp = SEXT16 (State.regs[OP[1]]) << 16 | State.regs[OP[1]+1];
1306 if (tmp < SEXT40(State.a[OP[0]]))
1307 {
1308 State.a[OP[0]] = tmp & MASK40;
1309 State.F0 = 1;
1310 }
1311 else
1312 State.F0 = 0;
1313 trace_output (OP_ACCUM);
1314 }
1315
1316 /* min */
1317 void
1318 OP_3603 ()
1319 {
1320 trace_input ("min", OP_ACCUM, OP_ACCUM, OP_VOID);
1321 State.F1 = State.F0;
1322 if (SEXT40(State.a[OP[1]]) < SEXT40(State.a[OP[0]]))
1323 {
1324 State.a[OP[0]] = State.a[OP[1]];
1325 State.F0 = 1;
1326 }
1327 else
1328 State.F0 = 0;
1329 trace_output (OP_ACCUM);
1330 }
1331
1332 /* msb */
1333 void
1334 OP_2800 ()
1335 {
1336 int64 tmp;
1337
1338 trace_input ("msb", OP_ACCUM, OP_REG, OP_REG);
1339 tmp = SEXT40 ((int16)(State.regs[OP[1]]) * (int16)(State.regs[OP[2]]));
1340
1341 if (State.FX)
1342 tmp = SEXT40 ((tmp << 1) & MASK40);
1343
1344 if (State.ST && tmp > MAX32)
1345 tmp = MAX32;
1346
1347 tmp = SEXT40(State.a[OP[0]]) - tmp;
1348 if (State.ST)
1349 {
1350 if (tmp > MAX32)
1351 State.a[OP[0]] = MAX32;
1352 else if (tmp < MIN32)
1353 State.a[OP[0]] = MIN32;
1354 else
1355 State.a[OP[0]] = tmp & MASK40;
1356 }
1357 else
1358 State.a[OP[0]] = tmp & MASK40;
1359 trace_output (OP_ACCUM);
1360 }
1361
1362 /* msbsu */
1363 void
1364 OP_1800 ()
1365 {
1366 int64 tmp;
1367
1368 trace_input ("msbsu", OP_ACCUM, OP_REG, OP_REG);
1369 tmp = SEXT40 ((int16)State.regs[OP[1]] * State.regs[OP[2]]);
1370 if (State.FX)
1371 tmp = SEXT40( (tmp << 1) & MASK40);
1372
1373 State.a[OP[0]] = (SEXT40 (State.a[OP[0]]) - tmp) & MASK40;
1374 trace_output (OP_ACCUM);
1375 }
1376
1377 /* msbu */
1378 void
1379 OP_3800 ()
1380 {
1381 int64 tmp;
1382
1383 trace_input ("msbu", OP_ACCUM, OP_REG, OP_REG);
1384 tmp = SEXT40 (State.regs[OP[1]] * State.regs[OP[2]]);
1385 if (State.FX)
1386 tmp = SEXT40( (tmp << 1) & MASK40);
1387
1388 State.a[OP[0]] = (SEXT40 (State.a[OP[0]]) - tmp) & MASK40;
1389 trace_output (OP_ACCUM);
1390 }
1391
1392 /* mul */
1393 void
1394 OP_2E00 ()
1395 {
1396 trace_input ("mul", OP_REG, OP_REG, OP_VOID);
1397 State.regs[OP[0]] *= State.regs[OP[1]];
1398 trace_output (OP_REG);
1399 }
1400
1401 /* mulx */
1402 void
1403 OP_2C00 ()
1404 {
1405 int64 tmp;
1406
1407 trace_input ("mulx", OP_ACCUM_OUTPUT, OP_REG, OP_REG);
1408 tmp = SEXT40 ((int16)(State.regs[OP[1]]) * (int16)(State.regs[OP[2]]));
1409
1410 if (State.FX)
1411 tmp = SEXT40 ((tmp << 1) & MASK40);
1412
1413 if (State.ST && tmp > MAX32)
1414 State.a[OP[0]] = MAX32;
1415 else
1416 State.a[OP[0]] = tmp & MASK40;
1417 trace_output (OP_ACCUM);
1418 }
1419
1420 /* mulxsu */
1421 void
1422 OP_1C00 ()
1423 {
1424 int64 tmp;
1425
1426 trace_input ("mulxsu", OP_ACCUM_OUTPUT, OP_REG, OP_REG);
1427 tmp = SEXT40 ((int16)(State.regs[OP[1]]) * State.regs[OP[2]]);
1428
1429 if (State.FX)
1430 tmp <<= 1;
1431
1432 State.a[OP[0]] = tmp & MASK40;
1433 trace_output (OP_ACCUM);
1434 }
1435
1436 /* mulxu */
1437 void
1438 OP_3C00 ()
1439 {
1440 int64 tmp;
1441
1442 trace_input ("mulxu", OP_ACCUM_OUTPUT, OP_REG, OP_REG);
1443 tmp = SEXT40 (State.regs[OP[1]] * State.regs[OP[2]]);
1444
1445 if (State.FX)
1446 tmp <<= 1;
1447
1448 State.a[OP[0]] = tmp & MASK40;
1449 trace_output (OP_ACCUM);
1450 }
1451
1452 /* mv */
1453 void
1454 OP_4000 ()
1455 {
1456 trace_input ("mv", OP_REG_OUTPUT, OP_REG, OP_VOID);
1457 State.regs[OP[0]] = State.regs[OP[1]];
1458 trace_output (OP_REG);
1459 }
1460
1461 /* mv2w */
1462 void
1463 OP_5000 ()
1464 {
1465 trace_input ("mv2w", OP_DREG_OUTPUT, OP_DREG, OP_VOID);
1466 State.regs[OP[0]] = State.regs[OP[1]];
1467 State.regs[OP[0]+1] = State.regs[OP[1]+1];
1468 trace_output (OP_DREG);
1469 }
1470
1471 /* mv2wfac */
1472 void
1473 OP_3E00 ()
1474 {
1475 trace_input ("mv2wfac", OP_DREG_OUTPUT, OP_ACCUM, OP_VOID);
1476 State.regs[OP[0]] = (State.a[OP[1]] >> 16) & 0xffff;
1477 State.regs[OP[0]+1] = State.a[OP[1]] & 0xffff;
1478 trace_output (OP_DREG);
1479 }
1480
1481 /* mv2wtac */
1482 void
1483 OP_3E01 ()
1484 {
1485 trace_input ("mv2wtac", OP_ACCUM_OUTPUT, OP_DREG, OP_VOID);
1486 State.a[OP[1]] = (SEXT16 (State.regs[OP[0]]) << 16 | State.regs[OP[0]+1]) & MASK40;
1487 trace_output (OP_ACCUM);
1488 }
1489
1490 /* mvac */
1491 void
1492 OP_3E03 ()
1493 {
1494 trace_input ("mvac", OP_ACCUM_OUTPUT, OP_ACCUM, OP_VOID);
1495 State.a[OP[0]] = State.a[OP[1]];
1496 trace_output (OP_ACCUM);
1497 }
1498
1499 /* mvb */
1500 void
1501 OP_5400 ()
1502 {
1503 trace_input ("mvb", OP_REG_OUTPUT, OP_REG, OP_VOID);
1504 State.regs[OP[0]] = SEXT8 (State.regs[OP[1]] & 0xff);
1505 trace_output (OP_REG);
1506 }
1507
1508 /* mvf0f */
1509 void
1510 OP_4400 ()
1511 {
1512 trace_input ("mf0f", OP_REG_OUTPUT, OP_REG, OP_VOID);
1513 if (State.F0 == 0)
1514 State.regs[OP[0]] = State.regs[OP[1]];
1515 trace_output (OP_REG);
1516 }
1517
1518 /* mvf0t */
1519 void
1520 OP_4401 ()
1521 {
1522 trace_input ("mf0t", OP_REG_OUTPUT, OP_REG, OP_VOID);
1523 if (State.F0)
1524 State.regs[OP[0]] = State.regs[OP[1]];
1525 trace_output (OP_REG);
1526 }
1527
1528 /* mvfacg */
1529 void
1530 OP_1E04 ()
1531 {
1532 trace_input ("mvfacg", OP_REG_OUTPUT, OP_ACCUM, OP_VOID);
1533 State.regs[OP[0]] = (State.a[OP[1]] >> 32) & 0xff;
1534 trace_output (OP_ACCUM);
1535 }
1536
1537 /* mvfachi */
1538 void
1539 OP_1E00 ()
1540 {
1541 trace_input ("mvfachi", OP_REG_OUTPUT, OP_ACCUM, OP_VOID);
1542 State.regs[OP[0]] = (State.a[OP[1]] >> 16) & 0xffff;
1543 trace_output (OP_REG);
1544 }
1545
1546 /* mvfaclo */
1547 void
1548 OP_1E02 ()
1549 {
1550 trace_input ("mvfaclo", OP_REG_OUTPUT, OP_ACCUM, OP_VOID);
1551 State.regs[OP[0]] = State.a[OP[1]] & 0xffff;
1552 trace_output (OP_REG);
1553 }
1554
1555 /* mvfc */
1556 void
1557 OP_5200 ()
1558 {
1559 trace_input ("mvfc", OP_REG_OUTPUT, OP_CR, OP_VOID);
1560 if (OP[1] == 0)
1561 {
1562 /* PSW is treated specially */
1563 PSW = 0;
1564 if (State.SM) PSW |= 0x8000;
1565 if (State.EA) PSW |= 0x2000;
1566 if (State.DB) PSW |= 0x1000;
1567 if (State.IE) PSW |= 0x400;
1568 if (State.RP) PSW |= 0x200;
1569 if (State.MD) PSW |= 0x100;
1570 if (State.FX) PSW |= 0x80;
1571 if (State.ST) PSW |= 0x40;
1572 if (State.F0) PSW |= 8;
1573 if (State.F1) PSW |= 4;
1574 if (State.C) PSW |= 1;
1575 }
1576 State.regs[OP[0]] = State.cregs[OP[1]];
1577 trace_output (OP_REG);
1578 }
1579
1580 /* mvtacg */
1581 void
1582 OP_1E41 ()
1583 {
1584 trace_input ("mvtacg", OP_REG, OP_ACCUM, OP_VOID);
1585 State.a[OP[1]] &= MASK32;
1586 State.a[OP[1]] |= (int64)(State.regs[OP[0]] & 0xff) << 32;
1587 trace_output (OP_ACCUM_REVERSE);
1588 }
1589
1590 /* mvtachi */
1591 void
1592 OP_1E01 ()
1593 {
1594 uint16 tmp;
1595
1596 trace_input ("mvtachi", OP_REG, OP_ACCUM, OP_VOID);
1597 tmp = State.a[OP[1]] & 0xffff;
1598 State.a[OP[1]] = (SEXT16 (State.regs[OP[0]]) << 16 | tmp) & MASK40;
1599 trace_output (OP_ACCUM_REVERSE);
1600 }
1601
1602 /* mvtaclo */
1603 void
1604 OP_1E21 ()
1605 {
1606 trace_input ("mvtaclo", OP_REG, OP_ACCUM, OP_VOID);
1607 State.a[OP[1]] = (SEXT16 (State.regs[OP[0]])) & MASK40;
1608 trace_output (OP_ACCUM_REVERSE);
1609 }
1610
1611 /* mvtc */
1612 void
1613 OP_5600 ()
1614 {
1615 trace_input ("mvtc", OP_REG, OP_CR_OUTPUT, OP_VOID);
1616 State.cregs[OP[1]] = State.regs[OP[0]];
1617 if (OP[1] == 0)
1618 {
1619 /* PSW is treated specially */
1620 State.SM = (PSW & 0x8000) ? 1 : 0;
1621 State.EA = (PSW & 0x2000) ? 1 : 0;
1622 State.DB = (PSW & 0x1000) ? 1 : 0;
1623 State.IE = (PSW & 0x400) ? 1 : 0;
1624 State.RP = (PSW & 0x200) ? 1 : 0;
1625 State.MD = (PSW & 0x100) ? 1 : 0;
1626 State.FX = (PSW & 0x80) ? 1 : 0;
1627 State.ST = (PSW & 0x40) ? 1 : 0;
1628 State.F0 = (PSW & 8) ? 1 : 0;
1629 State.F1 = (PSW & 4) ? 1 : 0;
1630 State.C = PSW & 1;
1631 if (State.ST && !State.FX)
1632 {
1633 (*d10v_callback->printf_filtered) (d10v_callback,
1634 "ERROR at PC 0x%x: ST can only be set when FX is set.\n",
1635 PC<<2);
1636 State.exception = SIGILL;
1637 }
1638 }
1639 trace_output (OP_CR_REVERSE);
1640 }
1641
1642 /* mvub */
1643 void
1644 OP_5401 ()
1645 {
1646 trace_input ("mvub", OP_REG_OUTPUT, OP_REG, OP_VOID);
1647 State.regs[OP[0]] = State.regs[OP[1]] & 0xff;
1648 trace_output (OP_REG);
1649 }
1650
1651 /* neg */
1652 void
1653 OP_4605 ()
1654 {
1655 trace_input ("neg", OP_REG, OP_VOID, OP_VOID);
1656 State.regs[OP[0]] = 0 - State.regs[OP[0]];
1657 trace_output (OP_REG);
1658 }
1659
1660 /* neg */
1661 void
1662 OP_5605 ()
1663 {
1664 int64 tmp;
1665
1666 trace_input ("neg", OP_ACCUM, OP_VOID, OP_VOID);
1667 tmp = -SEXT40(State.a[OP[0]]);
1668 if (State.ST)
1669 {
1670 if ( tmp > MAX32)
1671 State.a[OP[0]] = MAX32;
1672 else if (tmp < MIN32)
1673 State.a[OP[0]] = MIN32;
1674 else
1675 State.a[OP[0]] = tmp & MASK40;
1676 }
1677 else
1678 State.a[OP[0]] = tmp & MASK40;
1679 trace_output (OP_ACCUM);
1680 }
1681
1682
1683 /* nop */
1684 void
1685 OP_5E00 ()
1686 {
1687 trace_input ("nop", OP_VOID, OP_VOID, OP_VOID);
1688 trace_output (OP_VOID);
1689
1690 if (State.ins_type == INS_LEFT || State.ins_type == INS_LEFT_PARALLEL)
1691 left_nops++;
1692 else
1693 right_nops++;
1694 }
1695
1696 /* not */
1697 void
1698 OP_4603 ()
1699 {
1700 trace_input ("not", OP_REG, OP_VOID, OP_VOID);
1701 State.regs[OP[0]] = ~(State.regs[OP[0]]);
1702 trace_output (OP_REG);
1703 }
1704
1705 /* or */
1706 void
1707 OP_800 ()
1708 {
1709 trace_input ("or", OP_REG, OP_REG, OP_VOID);
1710 State.regs[OP[0]] |= State.regs[OP[1]];
1711 trace_output (OP_REG);
1712 }
1713
1714 /* or3 */
1715 void
1716 OP_4000000 ()
1717 {
1718 trace_input ("or3", OP_REG_OUTPUT, OP_REG, OP_CONSTANT16);
1719 State.regs[OP[0]] = State.regs[OP[1]] | OP[2];
1720 trace_output (OP_REG);
1721 }
1722
1723 /* rac */
1724 void
1725 OP_5201 ()
1726 {
1727 int64 tmp;
1728 int shift = SEXT3 (OP[2]);
1729
1730 trace_input ("rac", OP_DREG_OUTPUT, OP_ACCUM, OP_CONSTANT3);
1731 if (OP[1] != 0)
1732 {
1733 (*d10v_callback->printf_filtered) (d10v_callback,
1734 "ERROR at PC 0x%x: instruction only valid for A0\n",
1735 PC<<2);
1736 State.exception = SIGILL;
1737 }
1738
1739 State.F1 = State.F0;
1740 if (shift >=0)
1741 tmp = ((State.a[0] << 16) | (State.a[1] & 0xffff)) << shift;
1742 else
1743 tmp = ((State.a[0] << 16) | (State.a[1] & 0xffff)) >> -shift;
1744 tmp = ( SEXT60(tmp) + 0x8000 ) >> 16;
1745 if (tmp > MAX32)
1746 {
1747 State.regs[OP[0]] = 0x7fff;
1748 State.regs[OP[0]+1] = 0xffff;
1749 State.F0 = 1;
1750 }
1751 else if (tmp < MIN32)
1752 {
1753 State.regs[OP[0]] = 0x8000;
1754 State.regs[OP[0]+1] = 0;
1755 State.F0 = 1;
1756 }
1757 else
1758 {
1759 State.regs[OP[0]] = (tmp >> 16) & 0xffff;
1760 State.regs[OP[0]+1] = tmp & 0xffff;
1761 State.F0 = 0;
1762 }
1763 trace_output (OP_DREG);
1764 }
1765
1766 /* rachi */
1767 void
1768 OP_4201 ()
1769 {
1770 int64 tmp;
1771 int shift = SEXT3 (OP[2]);
1772
1773 trace_input ("rachi", OP_REG_OUTPUT, OP_ACCUM, OP_CONSTANT3);
1774 State.F1 = State.F0;
1775 if (shift >=0)
1776 tmp = SEXT44 (State.a[1]) << shift;
1777 else
1778 tmp = SEXT44 (State.a[1]) >> -shift;
1779 tmp += 0x8000;
1780
1781 if (tmp > MAX32)
1782 {
1783 State.regs[OP[0]] = 0x7fff;
1784 State.F0 = 1;
1785 }
1786 else if (tmp < 0xfff80000000LL)
1787 {
1788 State.regs[OP[0]] = 0x8000;
1789 State.F0 = 1;
1790 }
1791 else
1792 {
1793 State.regs[OP[0]] = (tmp >> 16) & 0xffff;
1794 State.F0 = 0;
1795 }
1796 trace_output (OP_REG);
1797 }
1798
1799 /* rep */
1800 void
1801 OP_27000000 ()
1802 {
1803 trace_input ("rep", OP_REG, OP_CONSTANT16, OP_VOID);
1804 RPT_S = PC + 1;
1805 RPT_E = PC + OP[1];
1806 RPT_C = State.regs[OP[0]];
1807 State.RP = 1;
1808 if (RPT_C == 0)
1809 {
1810 (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: rep with count=0 is illegal.\n");
1811 State.exception = SIGILL;
1812 }
1813 if (OP[1] < 4)
1814 {
1815 (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: rep must include at least 4 instructions.\n");
1816 State.exception = SIGILL;
1817 }
1818 trace_output (OP_VOID);
1819 }
1820
1821 /* repi */
1822 void
1823 OP_2F000000 ()
1824 {
1825 trace_input ("repi", OP_CONSTANT16, OP_CONSTANT16, OP_VOID);
1826 RPT_S = PC + 1;
1827 RPT_E = PC + OP[1];
1828 RPT_C = OP[0];
1829 State.RP = 1;
1830 if (RPT_C == 0)
1831 {
1832 (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: repi with count=0 is illegal.\n");
1833 State.exception = SIGILL;
1834 }
1835 if (OP[1] < 4)
1836 {
1837 (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: repi must include at least 4 instructions.\n");
1838 State.exception = SIGILL;
1839 }
1840 trace_output (OP_VOID);
1841 }
1842
1843 /* rtd */
1844 void
1845 OP_5F60 ()
1846 {
1847 d10v_callback->printf_filtered(d10v_callback, "ERROR: rtd - NOT IMPLEMENTED\n");
1848 State.exception = SIGILL;
1849 }
1850
1851 /* rte */
1852 void
1853 OP_5F40 ()
1854 {
1855 trace_input ("rte", OP_VOID, OP_VOID, OP_VOID);
1856 PC = BPC;
1857 PSW = BPSW;
1858 trace_output (OP_VOID);
1859 }
1860
1861 /* sadd */
1862 void
1863 OP_1223 ()
1864 {
1865 int64 tmp;
1866
1867 trace_input ("sadd", OP_ACCUM, OP_ACCUM, OP_VOID);
1868 tmp = SEXT40(State.a[OP[0]]) + (SEXT40(State.a[OP[1]]) >> 16);
1869 if (State.ST)
1870 {
1871 if (tmp > MAX32)
1872 State.a[OP[0]] = MAX32;
1873 else if (tmp < MIN32)
1874 State.a[OP[0]] = MIN32;
1875 else
1876 State.a[OP[0]] = tmp & MASK40;
1877 }
1878 else
1879 State.a[OP[0]] = tmp & MASK40;
1880 trace_output (OP_ACCUM);
1881 }
1882
1883 /* setf0f */
1884 void
1885 OP_4611 ()
1886 {
1887 trace_input ("setf0f", OP_REG_OUTPUT, OP_VOID, OP_VOID);
1888 State.regs[OP[0]] = (State.F0 == 0) ? 1 : 0;
1889 trace_output (OP_REG);
1890 }
1891
1892 /* setf0t */
1893 void
1894 OP_4613 ()
1895 {
1896 trace_input ("setf0t", OP_REG_OUTPUT, OP_VOID, OP_VOID);
1897 State.regs[OP[0]] = (State.F0 == 1) ? 1 : 0;
1898 trace_output (OP_REG);
1899 }
1900
1901 /* sleep */
1902 void
1903 OP_5FC0 ()
1904 {
1905 trace_input ("sleep", OP_VOID, OP_VOID, OP_VOID);
1906 State.IE = 1;
1907 trace_output (OP_VOID);
1908 }
1909
1910 /* sll */
1911 void
1912 OP_2200 ()
1913 {
1914 trace_input ("sll", OP_REG, OP_REG, OP_VOID);
1915 State.regs[OP[0]] <<= (State.regs[OP[1]] & 0xf);
1916 trace_output (OP_REG);
1917 }
1918
1919 /* sll */
1920 void
1921 OP_3200 ()
1922 {
1923 int64 tmp;
1924 trace_input ("sll", OP_ACCUM, OP_REG, OP_VOID);
1925 if ((State.regs[OP[1]] & 31) <= 16)
1926 tmp = SEXT40 (State.a[OP[0]]) << (State.regs[OP[1]] & 31);
1927 else
1928 {
1929 (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: shift value %d too large.\n", State.regs[OP[1]] & 31);
1930 State.exception = SIGILL;
1931 return;
1932 }
1933
1934 if (State.ST)
1935 {
1936 if (tmp > MAX32)
1937 State.a[OP[0]] = MAX32;
1938 else if (tmp < 0xffffff80000000LL)
1939 State.a[OP[0]] = MIN32;
1940 else
1941 State.a[OP[0]] = tmp & MASK40;
1942 }
1943 else
1944 State.a[OP[0]] = tmp & MASK40;
1945 trace_output (OP_ACCUM);
1946 }
1947
1948 /* slli */
1949 void
1950 OP_2201 ()
1951 {
1952 trace_input ("slli", OP_REG, OP_CONSTANT16, OP_VOID);
1953 State.regs[OP[0]] <<= OP[1];
1954 trace_output (OP_REG);
1955 }
1956
1957 /* slli */
1958 void
1959 OP_3201 ()
1960 {
1961 int64 tmp;
1962
1963 if (OP[1] == 0)
1964 OP[1] = 16;
1965
1966 trace_input ("slli", OP_ACCUM, OP_CONSTANT16, OP_VOID);
1967 tmp = SEXT40(State.a[OP[0]]) << OP[1];
1968
1969 if (State.ST)
1970 {
1971 if (tmp > MAX32)
1972 State.a[OP[0]] = MAX32;
1973 else if (tmp < 0xffffff80000000LL)
1974 State.a[OP[0]] = MIN32;
1975 else
1976 State.a[OP[0]] = tmp & MASK40;
1977 }
1978 else
1979 State.a[OP[0]] = tmp & MASK40;
1980 trace_output (OP_ACCUM);
1981 }
1982
1983 /* slx */
1984 void
1985 OP_460B ()
1986 {
1987 uint16 tmp;
1988
1989 trace_input ("slx", OP_REG, OP_FLAG, OP_VOID);
1990 State.regs[OP[0]] = (State.regs[OP[0]] << 1) | State.F0;
1991 trace_output (OP_REG);
1992 }
1993
1994 /* sra */
1995 void
1996 OP_2400 ()
1997 {
1998 trace_input ("sra", OP_REG, OP_REG, OP_VOID);
1999 State.regs[OP[0]] = ((int16)(State.regs[OP[0]])) >> (State.regs[OP[1]] & 0xf);
2000 trace_output (OP_REG);
2001 }
2002
2003 /* sra */
2004 void
2005 OP_3400 ()
2006 {
2007 trace_input ("sra", OP_ACCUM, OP_REG, OP_VOID);
2008 if ((State.regs[OP[1]] & 31) <= 16)
2009 State.a[OP[0]] >>= (State.regs[OP[1]] & 31);
2010 else
2011 {
2012 (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: shift value %d too large.\n", State.regs[OP[1]] & 31);
2013 State.exception = SIGILL;
2014 return;
2015 }
2016
2017 trace_output (OP_ACCUM);
2018 }
2019
2020 /* srai */
2021 void
2022 OP_2401 ()
2023 {
2024 trace_input ("srai", OP_REG, OP_CONSTANT16, OP_VOID);
2025 State.regs[OP[0]] = ((int16)(State.regs[OP[0]])) >> OP[1];
2026 trace_output (OP_REG);
2027 }
2028
2029 /* srai */
2030 void
2031 OP_3401 ()
2032 {
2033 if (OP[1] == 0)
2034 OP[1] = 16;
2035
2036 trace_input ("srai", OP_ACCUM, OP_CONSTANT16, OP_VOID);
2037 State.a[OP[0]] >>= OP[1];
2038 trace_output (OP_ACCUM);
2039 }
2040
2041 /* srl */
2042 void
2043 OP_2000 ()
2044 {
2045 trace_input ("srl", OP_REG, OP_REG, OP_VOID);
2046 State.regs[OP[0]] >>= (State.regs[OP[1]] & 0xf);
2047 trace_output (OP_REG);
2048 }
2049
2050 /* srl */
2051 void
2052 OP_3000 ()
2053 {
2054 trace_input ("srl", OP_ACCUM, OP_REG, OP_VOID);
2055 if ((State.regs[OP[1]] & 31) <= 16)
2056 State.a[OP[0]] >>= (State.regs[OP[1]] & 31);
2057 else
2058 {
2059 (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: shift value %d too large.\n", State.regs[OP[1]] & 31);
2060 State.exception = SIGILL;
2061 return;
2062 }
2063
2064 trace_output (OP_ACCUM);
2065 }
2066
2067 /* srli */
2068 void
2069 OP_2001 ()
2070 {
2071 trace_input ("srli", OP_REG, OP_CONSTANT16, OP_VOID);
2072 State.regs[OP[0]] >>= OP[1];
2073 trace_output (OP_REG);
2074 }
2075
2076 /* srli */
2077 void
2078 OP_3001 ()
2079 {
2080 if (OP[1] == 0)
2081 OP[1] = 16;
2082
2083 trace_input ("srli", OP_ACCUM, OP_CONSTANT16, OP_VOID);
2084 State.a[OP[0]] >>= OP[1];
2085 trace_output (OP_ACCUM);
2086 }
2087
2088 /* srx */
2089 void
2090 OP_4609 ()
2091 {
2092 uint16 tmp;
2093
2094 trace_input ("srx", OP_REG, OP_FLAG, OP_VOID);
2095 tmp = State.F0 << 15;
2096 State.regs[OP[0]] = (State.regs[OP[0]] >> 1) | tmp;
2097 trace_output (OP_REG);
2098 }
2099
2100 /* st */
2101 void
2102 OP_34000000 ()
2103 {
2104 trace_input ("st", OP_REG, OP_MEMREF2, OP_VOID);
2105 SW (OP[1] + State.regs[OP[2]], State.regs[OP[0]]);
2106 trace_output (OP_VOID);
2107 }
2108
2109 /* st */
2110 void
2111 OP_6800 ()
2112 {
2113 trace_input ("st", OP_REG, OP_MEMREF, OP_VOID);
2114 SW (State.regs[OP[1]], State.regs[OP[0]]);
2115 trace_output (OP_VOID);
2116 }
2117
2118 /* st */
2119 void
2120 OP_6C1F ()
2121 {
2122 trace_input ("st", OP_REG, OP_PREDEC, OP_VOID);
2123 if ( OP[1] != 15 )
2124 {
2125 (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: cannot pre-decrement any registers but r15 (SP).\n");
2126 State.exception = SIGILL;
2127 return;
2128 }
2129 State.regs[OP[1]] -= 2;
2130 SW (State.regs[OP[1]], State.regs[OP[0]]);
2131 trace_output (OP_VOID);
2132 }
2133
2134 /* st */
2135 void
2136 OP_6801 ()
2137 {
2138 trace_input ("st", OP_REG, OP_POSTINC, OP_VOID);
2139 SW (State.regs[OP[1]], State.regs[OP[0]]);
2140 INC_ADDR (State.regs[OP[1]],2);
2141 trace_output (OP_VOID);
2142 }
2143
2144 /* st */
2145 void
2146 OP_6C01 ()
2147 {
2148 trace_input ("st", OP_REG, OP_POSTDEC, OP_VOID);
2149 SW (State.regs[OP[1]], State.regs[OP[0]]);
2150 INC_ADDR (State.regs[OP[1]],-2);
2151 trace_output (OP_VOID);
2152 }
2153
2154 /* st2w */
2155 void
2156 OP_35000000 ()
2157 {
2158 trace_input ("st2w", OP_DREG, OP_MEMREF2, OP_VOID);
2159 SW (State.regs[OP[2]]+OP[1], State.regs[OP[0]]);
2160 SW (State.regs[OP[2]]+OP[1]+2, State.regs[OP[0]+1]);
2161 trace_output (OP_VOID);
2162 }
2163
2164 /* st2w */
2165 void
2166 OP_6A00 ()
2167 {
2168 trace_input ("st2w", OP_REG, OP_MEMREF, OP_VOID);
2169 SW (State.regs[OP[1]], State.regs[OP[0]]);
2170 SW (State.regs[OP[1]]+2, State.regs[OP[0]+1]);
2171 trace_output (OP_VOID);
2172 }
2173
2174 /* st2w */
2175 void
2176 OP_6E1F ()
2177 {
2178 trace_input ("st2w", OP_REG, OP_PREDEC, OP_VOID);
2179 if ( OP[1] != 15 )
2180 {
2181 (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: cannot pre-decrement any registers but r15 (SP).\n");
2182 State.exception = SIGILL;
2183 return;
2184 }
2185 State.regs[OP[1]] -= 4;
2186 SW (State.regs[OP[1]], State.regs[OP[0]]);
2187 SW (State.regs[OP[1]]+2, State.regs[OP[0]+1]);
2188 trace_output (OP_VOID);
2189 }
2190
2191 /* st2w */
2192 void
2193 OP_6A01 ()
2194 {
2195 trace_input ("st2w", OP_REG, OP_POSTDEC, OP_VOID);
2196 SW (State.regs[OP[1]], State.regs[OP[0]]);
2197 SW (State.regs[OP[1]]+2, State.regs[OP[0]+1]);
2198 INC_ADDR (State.regs[OP[1]],4);
2199 trace_output (OP_VOID);
2200 }
2201
2202 /* st2w */
2203 void
2204 OP_6E01 ()
2205 {
2206 trace_input ("st2w", OP_REG, OP_POSTINC, OP_VOID);
2207 SW (State.regs[OP[1]], State.regs[OP[0]]);
2208 SW (State.regs[OP[1]]+2, State.regs[OP[0]+1]);
2209 INC_ADDR (State.regs[OP[1]],-4);
2210 trace_output (OP_VOID);
2211 }
2212
2213 /* stb */
2214 void
2215 OP_3C000000 ()
2216 {
2217 trace_input ("stb", OP_REG, OP_MEMREF2, OP_VOID);
2218 SB (State.regs[OP[2]]+OP[1], State.regs[OP[0]]);
2219 trace_output (OP_VOID);
2220 }
2221
2222 /* stb */
2223 void
2224 OP_7800 ()
2225 {
2226 trace_input ("stb", OP_REG, OP_MEMREF, OP_VOID);
2227 SB (State.regs[OP[1]], State.regs[OP[0]]);
2228 trace_output (OP_VOID);
2229 }
2230
2231 /* stop */
2232 void
2233 OP_5FE0 ()
2234 {
2235 trace_input ("stop", OP_VOID, OP_VOID, OP_VOID);
2236 State.exception = SIGQUIT;
2237 trace_output (OP_VOID);
2238 }
2239
2240 /* sub */
2241 void
2242 OP_0 ()
2243 {
2244 int32 tmp;
2245
2246 trace_input ("sub", OP_REG, OP_REG, OP_VOID);
2247 tmp = (int16)State.regs[OP[0]]- (int16)State.regs[OP[1]];
2248 State.C = (tmp & 0xffff0000) ? 1 : 0;
2249 State.regs[OP[0]] = tmp & 0xffff;
2250 trace_output (OP_REG);
2251 }
2252
2253 /* sub */
2254 void
2255 OP_1001 ()
2256 {
2257 int64 tmp;
2258
2259 trace_input ("sub", OP_ACCUM, OP_DREG, OP_VOID);
2260 tmp = SEXT40(State.a[OP[0]]) - (SEXT16 (State.regs[OP[1]]) << 16 | State.regs[OP[1]+1]);
2261 if (State.ST)
2262 {
2263 if ( tmp > MAX32)
2264 State.a[OP[0]] = MAX32;
2265 else if ( tmp < MIN32)
2266 State.a[OP[0]] = MIN32;
2267 else
2268 State.a[OP[0]] = tmp & MASK40;
2269 }
2270 else
2271 State.a[OP[0]] = tmp & MASK40;
2272
2273 trace_output (OP_ACCUM);
2274 }
2275
2276 /* sub */
2277
2278 void
2279 OP_1003 ()
2280 {
2281 int64 tmp;
2282
2283 trace_input ("sub", OP_ACCUM, OP_ACCUM, OP_VOID);
2284 tmp = SEXT40(State.a[OP[0]]) - SEXT40(State.a[OP[1]]);
2285 if (State.ST)
2286 {
2287 if (tmp > MAX32)
2288 State.a[OP[0]] = MAX32;
2289 else if ( tmp < MIN32)
2290 State.a[OP[0]] = MIN32;
2291 else
2292 State.a[OP[0]] = tmp & MASK40;
2293 }
2294 else
2295 State.a[OP[0]] = tmp & MASK40;
2296
2297 trace_output (OP_ACCUM);
2298 }
2299
2300 /* sub2w */
2301 void
2302 OP_1000 ()
2303 {
2304 int64 tmp;
2305 int32 a,b;
2306
2307 trace_input ("sub2w", OP_DREG, OP_DREG, OP_VOID);
2308 a = (int32)((State.regs[OP[0]] << 16) | State.regs[OP[0]+1]);
2309 b = (int32)((State.regs[OP[1]] << 16) | State.regs[OP[1]+1]);
2310 tmp = a-b;
2311 State.C = (tmp & 0xffffffff00000000LL) ? 1 : 0;
2312 State.regs[OP[0]] = (tmp >> 16) & 0xffff;
2313 State.regs[OP[0]+1] = tmp & 0xffff;
2314 trace_output (OP_DREG);
2315 }
2316
2317 /* subac3 */
2318 void
2319 OP_17000000 ()
2320 {
2321 int64 tmp;
2322
2323 trace_input ("subac3", OP_DREG_OUTPUT, OP_DREG, OP_ACCUM);
2324 tmp = SEXT40 ((State.regs[OP[1]] << 16) | State.regs[OP[1]+1]) - SEXT40 (State.a[OP[2]]);
2325 State.regs[OP[0]] = (tmp >> 16) & 0xffff;
2326 State.regs[OP[0]+1] = tmp & 0xffff;
2327 trace_output (OP_DREG);
2328 }
2329
2330 /* subac3 */
2331 void
2332 OP_17000002 ()
2333 {
2334 int64 tmp;
2335
2336 trace_input ("subac3", OP_DREG_OUTPUT, OP_ACCUM, OP_ACCUM);
2337 tmp = SEXT40(State.a[OP[1]]) - SEXT40(State.a[OP[2]]);
2338 State.regs[OP[0]] = (tmp >> 16) & 0xffff;
2339 State.regs[OP[0]+1] = tmp & 0xffff;
2340 trace_output (OP_DREG);
2341 }
2342
2343 /* subac3s */
2344 void
2345 OP_17001000 ()
2346 {
2347 int64 tmp;
2348
2349 trace_input ("subac3s", OP_DREG_OUTPUT, OP_DREG, OP_ACCUM);
2350 State.F1 = State.F0;
2351 tmp = SEXT40 ((State.regs[OP[1]] << 16) | State.regs[OP[1]+1]) - SEXT40(State.a[OP[2]]);
2352 if ( tmp > MAX32)
2353 {
2354 State.regs[OP[0]] = 0x7fff;
2355 State.regs[OP[0]+1] = 0xffff;
2356 State.F0 = 1;
2357 }
2358 else if (tmp < MIN32)
2359 {
2360 State.regs[OP[0]] = 0x8000;
2361 State.regs[OP[0]+1] = 0;
2362 State.F0 = 1;
2363 }
2364 else
2365 {
2366 State.regs[OP[0]] = (tmp >> 16) & 0xffff;
2367 State.regs[OP[0]+1] = tmp & 0xffff;
2368 State.F0 = 0;
2369 }
2370 trace_output (OP_DREG);
2371 }
2372
2373 /* subac3s */
2374 void
2375 OP_17001002 ()
2376 {
2377 int64 tmp;
2378
2379 trace_input ("subac3s", OP_DREG_OUTPUT, OP_ACCUM, OP_ACCUM);
2380 State.F1 = State.F0;
2381 tmp = SEXT40(State.a[OP[1]]) - SEXT40(State.a[OP[2]]);
2382 if ( tmp > MAX32)
2383 {
2384 State.regs[OP[0]] = 0x7fff;
2385 State.regs[OP[0]+1] = 0xffff;
2386 State.F0 = 1;
2387 }
2388 else if (tmp < MIN32)
2389 {
2390 State.regs[OP[0]] = 0x8000;
2391 State.regs[OP[0]+1] = 0;
2392 State.F0 = 1;
2393 }
2394 else
2395 {
2396 State.regs[OP[0]] = (tmp >> 16) & 0xffff;
2397 State.regs[OP[0]+1] = tmp & 0xffff;
2398 State.F0 = 0;
2399 }
2400 trace_output (OP_DREG);
2401 }
2402
2403 /* subi */
2404 void
2405 OP_1 ()
2406 {
2407 int32 tmp;
2408 if (OP[1] == 0)
2409 OP[1] = 16;
2410
2411 trace_input ("subi", OP_REG, OP_CONSTANT16, OP_VOID);
2412 tmp = (int16)State.regs[OP[0]] - OP[1];
2413 State.C = (tmp & 0xffff0000) ? 1 : 0;
2414 State.regs[OP[0]] = tmp & 0xffff;
2415 trace_output (OP_REG);
2416 }
2417
2418 /* trap */
2419 void
2420 OP_5F00 ()
2421 {
2422 trace_input ("trap", OP_CONSTANT4, OP_VOID, OP_VOID);
2423 trace_output (OP_VOID);
2424
2425 switch (OP[0])
2426 {
2427 default:
2428 (*d10v_callback->printf_filtered) (d10v_callback, "Unknown trap code %d\n", OP[0]);
2429 State.exception = SIGILL;
2430
2431 case 0:
2432 /* Trap 0 is used for simulating low-level I/O */
2433 {
2434 int save_errno = errno;
2435 errno = 0;
2436
2437 /* Registers passed to trap 0 */
2438
2439 #define FUNC State.regs[2] /* function number, return value */
2440 #define PARM1 State.regs[3] /* optional parm 1 */
2441 #define PARM2 State.regs[4] /* optional parm 2 */
2442 #define PARM3 State.regs[5] /* optional parm 3 */
2443
2444 /* Registers set by trap 0 */
2445
2446 #define RETVAL State.regs[2] /* return value */
2447 #define RETERR State.regs[3] /* return error code */
2448
2449 /* Turn a pointer in a register into a pointer into real memory. */
2450
2451 #define MEMPTR(x) ((char *)((x) + State.imem))
2452
2453 switch (FUNC)
2454 {
2455 #if !defined(__GO32__) && !defined(_WIN32)
2456 #ifdef SYS_fork
2457 case SYS_fork:
2458 RETVAL = fork ();
2459 break;
2460 #endif
2461 #ifdef SYS_execve
2462 case SYS_execve:
2463 RETVAL = execve (MEMPTR (PARM1), (char **) MEMPTR (PARM2),
2464 (char **)MEMPTR (PARM3));
2465 break;
2466 #endif
2467 #ifdef SYS_execv
2468 case SYS_execv:
2469 RETVAL = execve (MEMPTR (PARM1), (char **) MEMPTR (PARM2), NULL);
2470 break;
2471 #endif
2472 #ifdef SYS_pipe
2473 case SYS_pipe:
2474 {
2475 reg_t buf;
2476 int host_fd[2];
2477
2478 buf = PARM1;
2479 RETVAL = pipe (host_fd);
2480 SW (buf, host_fd[0]);
2481 buf += sizeof(uint16);
2482 SW (buf, host_fd[1]);
2483 }
2484 break;
2485 #endif
2486 #ifdef SYS_wait
2487 case SYS_wait:
2488 {
2489 int status;
2490
2491 RETVAL = wait (&status);
2492 SW (PARM1, status);
2493 }
2494 break;
2495 #endif
2496 #endif
2497
2498 #ifdef SYS_read
2499 case SYS_read:
2500 RETVAL = d10v_callback->read (d10v_callback, PARM1, MEMPTR (PARM2),
2501 PARM3);
2502 break;
2503 #endif
2504 #ifdef SYS_write
2505 case SYS_write:
2506 if (PARM1 == 1)
2507 RETVAL = (int)d10v_callback->write_stdout (d10v_callback,
2508 MEMPTR (PARM2), PARM3);
2509 else
2510 RETVAL = (int)d10v_callback->write (d10v_callback, PARM1,
2511 MEMPTR (PARM2), PARM3);
2512 break;
2513 #endif
2514 #ifdef SYS_lseek
2515 case SYS_lseek:
2516 RETVAL = d10v_callback->lseek (d10v_callback, PARM1, PARM2, PARM3);
2517 break;
2518 #endif
2519 #ifdef SYS_close
2520 case SYS_close:
2521 RETVAL = d10v_callback->close (d10v_callback, PARM1);
2522 break;
2523 #endif
2524 #ifdef SYS_open
2525 case SYS_open:
2526 RETVAL = d10v_callback->open (d10v_callback, MEMPTR (PARM1), PARM2);
2527 break;
2528 #endif
2529 #ifdef SYS_exit
2530 case SYS_exit:
2531 /* EXIT - caller can look in PARM1 to work out the
2532 reason */
2533 State.exception = SIGQUIT;
2534 break;
2535 #endif
2536
2537 #ifdef SYS_stat
2538 case SYS_stat:
2539 /* stat system call */
2540 {
2541 struct stat host_stat;
2542 reg_t buf;
2543
2544 RETVAL = stat (MEMPTR (PARM1), &host_stat);
2545
2546 buf = PARM2;
2547
2548 /* The hard-coded offsets and sizes were determined by using
2549 * the D10V compiler on a test program that used struct stat.
2550 */
2551 SW (buf, host_stat.st_dev);
2552 SW (buf+2, host_stat.st_ino);
2553 SW (buf+4, host_stat.st_mode);
2554 SW (buf+6, host_stat.st_nlink);
2555 SW (buf+8, host_stat.st_uid);
2556 SW (buf+10, host_stat.st_gid);
2557 SW (buf+12, host_stat.st_rdev);
2558 SLW (buf+16, host_stat.st_size);
2559 SLW (buf+20, host_stat.st_atime);
2560 SLW (buf+28, host_stat.st_mtime);
2561 SLW (buf+36, host_stat.st_ctime);
2562 }
2563 break;
2564 #endif
2565
2566 #ifdef SYS_chown
2567 case SYS_chown:
2568 RETVAL = chown (MEMPTR (PARM1), PARM2, PARM3);
2569 break;
2570 #endif
2571 #ifdef SYS_chmod
2572 case SYS_chmod:
2573 RETVAL = chmod (MEMPTR (PARM1), PARM2);
2574 break;
2575 #endif
2576 #ifdef SYS_utime
2577 case SYS_utime:
2578 /* Cast the second argument to void *, to avoid type mismatch
2579 if a prototype is present. */
2580 RETVAL = utime (MEMPTR (PARM1), (void *) MEMPTR (PARM2));
2581 break;
2582 #endif
2583 default:
2584 abort ();
2585 }
2586 RETERR = errno;
2587 errno = save_errno;
2588 break;
2589 }
2590
2591 case 1:
2592 /* Trap 1 prints a string */
2593 {
2594 char *fstr = State.regs[2] + State.imem;
2595 fputs (fstr, stdout);
2596 break;
2597 }
2598
2599 case 2:
2600 /* Trap 2 calls printf */
2601 {
2602 char *fstr = State.regs[2] + State.imem;
2603 (*d10v_callback->printf_filtered) (d10v_callback, fstr,
2604 (int16)State.regs[3],
2605 (int16)State.regs[4],
2606 (int16)State.regs[5]);
2607 break;
2608 }
2609
2610 case 3:
2611 /* Trap 3 writes a character */
2612 putchar (State.regs[2]);
2613 break;
2614 }
2615 }
2616
2617 /* tst0i */
2618 void
2619 OP_7000000 ()
2620 {
2621 trace_input ("tst0i", OP_REG, OP_CONSTANT16, OP_VOID);
2622 State.F1 = State.F0;
2623 State.F0 = (State.regs[OP[0]] & OP[1]) ? 1 : 0;
2624 trace_output (OP_FLAG);
2625 }
2626
2627 /* tst1i */
2628 void
2629 OP_F000000 ()
2630 {
2631 trace_input ("tst1i", OP_REG, OP_CONSTANT16, OP_VOID);
2632 State.F1 = State.F0;
2633 State.F0 = (~(State.regs[OP[0]]) & OP[1]) ? 1 : 0;
2634 trace_output (OP_FLAG);
2635 }
2636
2637 /* wait */
2638 void
2639 OP_5F80 ()
2640 {
2641 trace_input ("wait", OP_VOID, OP_VOID, OP_VOID);
2642 State.IE = 1;
2643 trace_output (OP_VOID);
2644 }
2645
2646 /* xor */
2647 void
2648 OP_A00 ()
2649 {
2650 trace_input ("xor", OP_REG, OP_REG, OP_VOID);
2651 State.regs[OP[0]] ^= State.regs[OP[1]];
2652 trace_output (OP_REG);
2653 }
2654
2655 /* xor3 */
2656 void
2657 OP_5000000 ()
2658 {
2659 trace_input ("xor3", OP_REG_OUTPUT, OP_REG, OP_CONSTANT16);
2660 State.regs[OP[0]] = State.regs[OP[1]] ^ OP[2];
2661 trace_output (OP_REG);
2662 }
2663
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