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Fix tracing info
[thirdparty/binutils-gdb.git] / sim / d10v / simops.c
1 #include <signal.h>
2 #include <errno.h>
3 #include <sys/types.h>
4 #include <sys/stat.h>
5 #include <unistd.h>
6
7 #include "d10v_sim.h"
8 #include "simops.h"
9 #include "sys/syscall.h"
10 #include "bfd.h"
11
12 enum op_types {
13 OP_VOID,
14 OP_REG,
15 OP_REG_OUTPUT,
16 OP_DREG,
17 OP_DREG_OUTPUT,
18 OP_ACCUM,
19 OP_ACCUM_OUTPUT,
20 OP_ACCUM_REVERSE,
21 OP_CR,
22 OP_CR_OUTPUT,
23 OP_CR_REVERSE,
24 OP_FLAG,
25 OP_FLAG_OUTPUT,
26 OP_CONSTANT16,
27 OP_CONSTANT3,
28 OP_CONSTANT4,
29 OP_MEMREF,
30 OP_MEMREF2,
31 OP_POSTDEC,
32 OP_POSTINC,
33 OP_PREDEC
34 };
35
36 #ifdef DEBUG
37 static void trace_input_func PARAMS ((char *name,
38 enum op_types in1,
39 enum op_types in2,
40 enum op_types in3));
41
42 #define trace_input(name, in1, in2, in3) do { if (d10v_debug) trace_input_func (name, in1, in2, in3); } while (0)
43
44 static void trace_output_func PARAMS ((enum op_types result));
45
46 #define trace_output(result) do { if (d10v_debug) trace_output_func (result); } while (0)
47
48 static int init_text_p = 0;
49 static asection *text;
50 static bfd_vma text_start;
51 static bfd_vma text_end;
52 extern bfd *exec_bfd;
53
54 #ifndef SIZE_INSTRUCTION
55 #define SIZE_INSTRUCTION 8
56 #endif
57
58 #ifndef SIZE_OPERANDS
59 #define SIZE_OPERANDS 18
60 #endif
61
62 #ifndef SIZE_VALUES
63 #define SIZE_VALUES 13
64 #endif
65
66 #ifndef SIZE_LOCATION
67 #define SIZE_LOCATION 20
68 #endif
69
70 #ifndef SIZE_PC
71 #define SIZE_PC 6
72 #endif
73
74 #ifndef SIZE_LINE_NUMBER
75 #define SIZE_LINE_NUMBER 4
76 #endif
77
78 static void
79 trace_input_func (name, in1, in2, in3)
80 char *name;
81 enum op_types in1;
82 enum op_types in2;
83 enum op_types in3;
84 {
85 char *comma;
86 enum op_types in[3];
87 int i;
88 char buf[1024];
89 char *p;
90 long tmp;
91 char *type;
92 asection *s;
93 const char *filename;
94 const char *functionname;
95 unsigned int linenumber;
96 bfd_vma byte_pc;
97
98 if ((d10v_debug & DEBUG_TRACE) == 0)
99 return;
100
101 switch (State.ins_type)
102 {
103 default:
104 case INS_UNKNOWN: type = " ?"; break;
105 case INS_LEFT: type = " L"; break;
106 case INS_RIGHT: type = " R"; break;
107 case INS_LEFT_PARALLEL: type = "*L"; break;
108 case INS_RIGHT_PARALLEL: type = "*R"; break;
109 case INS_LONG: type = " B"; break;
110 }
111
112 if ((d10v_debug & DEBUG_LINE_NUMBER) == 0)
113 (*d10v_callback->printf_filtered) (d10v_callback,
114 "0x%.*x %s: %-*s ",
115 SIZE_PC, (unsigned)PC,
116 type,
117 SIZE_INSTRUCTION, name);
118
119 else
120 {
121 if (!init_text_p)
122 {
123 init_text_p = 1;
124 for (s = exec_bfd->sections; s; s = s->next)
125 if (strcmp (bfd_get_section_name (exec_bfd, s), ".text") == 0)
126 {
127 text = s;
128 text_start = bfd_get_section_vma (exec_bfd, s);
129 text_end = text_start + bfd_section_size (exec_bfd, s);
130 break;
131 }
132 }
133
134 buf[0] = '\0';
135 byte_pc = (bfd_vma)PC << 2;
136 if (text && byte_pc >= text_start && byte_pc < text_end)
137 {
138 filename = (const char *)0;
139 functionname = (const char *)0;
140 linenumber = 0;
141 if (bfd_find_nearest_line (exec_bfd, text, (struct symbol_cache_entry **)0, byte_pc - text_start,
142 &filename, &functionname, &linenumber))
143 {
144 p = buf;
145 if (linenumber)
146 {
147 sprintf (p, "#%-*d ", SIZE_LINE_NUMBER, linenumber);
148 p += strlen (p);
149 }
150 else
151 {
152 sprintf (p, "%-*s ", SIZE_LINE_NUMBER+1, "---");
153 p += SIZE_LINE_NUMBER+2;
154 }
155
156 if (functionname)
157 {
158 sprintf (p, "%s ", functionname);
159 p += strlen (p);
160 }
161 else if (filename)
162 {
163 char *q = (char *) strrchr (filename, '/');
164 sprintf (p, "%s ", (q) ? q+1 : filename);
165 p += strlen (p);
166 }
167
168 if (*p == ' ')
169 *p = '\0';
170 }
171 }
172
173 (*d10v_callback->printf_filtered) (d10v_callback,
174 "0x%.*x %s: %-*.*s %-*s ",
175 SIZE_PC, (unsigned)PC,
176 type,
177 SIZE_LOCATION, SIZE_LOCATION, buf,
178 SIZE_INSTRUCTION, name);
179 }
180
181 in[0] = in1;
182 in[1] = in2;
183 in[2] = in3;
184 comma = "";
185 p = buf;
186 for (i = 0; i < 3; i++)
187 {
188 switch (in[i])
189 {
190 case OP_VOID:
191 break;
192
193 case OP_REG:
194 case OP_REG_OUTPUT:
195 case OP_DREG:
196 case OP_DREG_OUTPUT:
197 sprintf (p, "%sr%d", comma, OP[i]);
198 p += strlen (p);
199 comma = ",";
200 break;
201
202 case OP_CR:
203 case OP_CR_OUTPUT:
204 case OP_CR_REVERSE:
205 sprintf (p, "%scr%d", comma, OP[i]);
206 p += strlen (p);
207 comma = ",";
208 break;
209
210 case OP_ACCUM:
211 case OP_ACCUM_OUTPUT:
212 case OP_ACCUM_REVERSE:
213 sprintf (p, "%sa%d", comma, OP[i]);
214 p += strlen (p);
215 comma = ",";
216 break;
217
218 case OP_CONSTANT16:
219 sprintf (p, "%s%d", comma, OP[i]);
220 p += strlen (p);
221 comma = ",";
222 break;
223
224 case OP_CONSTANT4:
225 sprintf (p, "%s%d", comma, SEXT4(OP[i]));
226 p += strlen (p);
227 comma = ",";
228 break;
229
230 case OP_CONSTANT3:
231 sprintf (p, "%s%d", comma, SEXT3(OP[i]));
232 p += strlen (p);
233 comma = ",";
234 break;
235
236 case OP_MEMREF:
237 sprintf (p, "%s@r%d", comma, OP[i]);
238 p += strlen (p);
239 comma = ",";
240 break;
241
242 case OP_MEMREF2:
243 sprintf (p, "%s@(%d,r%d)", comma, (int16)OP[i], OP[i+1]);
244 p += strlen (p);
245 comma = ",";
246 break;
247
248 case OP_POSTINC:
249 sprintf (p, "%s@r%d+", comma, OP[i]);
250 p += strlen (p);
251 comma = ",";
252 break;
253
254 case OP_POSTDEC:
255 sprintf (p, "%s@r%d-", comma, OP[i]);
256 p += strlen (p);
257 comma = ",";
258 break;
259
260 case OP_PREDEC:
261 sprintf (p, "%s@-r%d", comma, OP[i]);
262 p += strlen (p);
263 comma = ",";
264 break;
265
266 case OP_FLAG:
267 case OP_FLAG_OUTPUT:
268 if (OP[i] == 0)
269 sprintf (p, "%sf0", comma);
270
271 else if (OP[i] == 1)
272 sprintf (p, "%sf1", comma);
273
274 else
275 sprintf (p, "%sc", comma);
276
277 p += strlen (p);
278 comma = ",";
279 break;
280 }
281 }
282
283 if ((d10v_debug & DEBUG_VALUES) == 0)
284 {
285 *p++ = '\n';
286 *p = '\0';
287 (*d10v_callback->printf_filtered) (d10v_callback, "%s", buf);
288 }
289 else
290 {
291 *p = '\0';
292 (*d10v_callback->printf_filtered) (d10v_callback, "%-*s", SIZE_OPERANDS, buf);
293
294 p = buf;
295 for (i = 0; i < 3; i++)
296 {
297 buf[0] = '\0';
298 switch (in[i])
299 {
300 case OP_VOID:
301 (*d10v_callback->printf_filtered) (d10v_callback, "%*s", SIZE_VALUES, "");
302 break;
303
304 case OP_REG_OUTPUT:
305 case OP_DREG_OUTPUT:
306 case OP_CR_OUTPUT:
307 case OP_ACCUM_OUTPUT:
308 case OP_FLAG_OUTPUT:
309 (*d10v_callback->printf_filtered) (d10v_callback, "%*s", SIZE_VALUES, "---");
310 break;
311
312 case OP_REG:
313 case OP_MEMREF:
314 case OP_POSTDEC:
315 case OP_POSTINC:
316 case OP_PREDEC:
317 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
318 (uint16)State.regs[OP[i]]);
319 break;
320
321 case OP_DREG:
322 tmp = (long)((((uint32) State.regs[OP[i]]) << 16) | ((uint32) State.regs[OP[i]+1]));
323 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.8lx", SIZE_VALUES-10, "", tmp);
324 break;
325
326 case OP_CR:
327 case OP_CR_REVERSE:
328 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
329 (uint16)State.cregs[OP[i]]);
330 break;
331
332 case OP_ACCUM:
333 case OP_ACCUM_REVERSE:
334 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.2x%.8lx", SIZE_VALUES-12, "",
335 ((int)(State.a[OP[i]] >> 32) & 0xff),
336 ((unsigned long)State.a[OP[i]]) & 0xffffffff);
337 break;
338
339 case OP_CONSTANT16:
340 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
341 (uint16)OP[i]);
342 break;
343
344 case OP_CONSTANT4:
345 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
346 (uint16)SEXT4(OP[i]));
347 break;
348
349 case OP_CONSTANT3:
350 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
351 (uint16)SEXT3(OP[i]));
352 break;
353
354 case OP_FLAG:
355 if (OP[i] == 0)
356 (*d10v_callback->printf_filtered) (d10v_callback, "%*sF0 = %d", SIZE_VALUES-6, "",
357 State.F0 != 0);
358
359 else if (OP[i] == 1)
360 (*d10v_callback->printf_filtered) (d10v_callback, "%*sF1 = %d", SIZE_VALUES-6, "",
361 State.F1 != 0);
362
363 else
364 (*d10v_callback->printf_filtered) (d10v_callback, "%*sC = %d", SIZE_VALUES-5, "",
365 State.C != 0);
366
367 break;
368
369 case OP_MEMREF2:
370 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
371 (uint16)OP[i]);
372 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
373 (uint16)State.regs[OP[++i]]);
374 break;
375 }
376 }
377 }
378 }
379
380 static void
381 trace_output_func (result)
382 enum op_types result;
383 {
384 if ((d10v_debug & (DEBUG_TRACE | DEBUG_VALUES)) == (DEBUG_TRACE | DEBUG_VALUES))
385 {
386 long tmp;
387
388 switch (result)
389 {
390 default:
391 putchar ('\n');
392 break;
393
394 case OP_REG:
395 case OP_REG_OUTPUT:
396 (*d10v_callback->printf_filtered) (d10v_callback, " :: %*s0x%.4x F0=%d F1=%d C=%d\n", SIZE_VALUES-6, "",
397 (uint16)State.regs[OP[0]],
398 State.F0 != 0, State.F1 != 0, State.C != 0);
399 break;
400
401 case OP_DREG:
402 case OP_DREG_OUTPUT:
403 tmp = (long)((((uint32) State.regs[OP[0]]) << 16) | ((uint32) State.regs[OP[0]+1]));
404 (*d10v_callback->printf_filtered) (d10v_callback, " :: %*s0x%.8lx F0=%d F1=%d C=%d\n", SIZE_VALUES-10, "", tmp,
405 State.F0 != 0, State.F1 != 0, State.C != 0);
406 break;
407
408 case OP_CR:
409 case OP_CR_OUTPUT:
410 (*d10v_callback->printf_filtered) (d10v_callback, " :: %*s0x%.4x F0=%d F1=%d C=%d\n", SIZE_VALUES-6, "",
411 (uint16)State.cregs[OP[0]],
412 State.F0 != 0, State.F1 != 0, State.C != 0);
413 break;
414
415 case OP_CR_REVERSE:
416 (*d10v_callback->printf_filtered) (d10v_callback, " :: %*s0x%.4x F0=%d F1=%d C=%d\n", SIZE_VALUES-6, "",
417 (uint16)State.cregs[OP[1]],
418 State.F0 != 0, State.F1 != 0, State.C != 0);
419 break;
420
421 case OP_ACCUM:
422 case OP_ACCUM_OUTPUT:
423 (*d10v_callback->printf_filtered) (d10v_callback, " :: %*s0x%.2x%.8lx F0=%d F1=%d C=%d\n", SIZE_VALUES-12, "",
424 ((int)(State.a[OP[0]] >> 32) & 0xff),
425 ((unsigned long)State.a[OP[0]]) & 0xffffffff,
426 State.F0 != 0, State.F1 != 0, State.C != 0);
427 break;
428
429 case OP_ACCUM_REVERSE:
430 (*d10v_callback->printf_filtered) (d10v_callback, " :: %*s0x%.2x%.8lx F0=%d F1=%d C=%d\n", SIZE_VALUES-12, "",
431 ((int)(State.a[OP[1]] >> 32) & 0xff),
432 ((unsigned long)State.a[OP[1]]) & 0xffffffff,
433 State.F0 != 0, State.F1 != 0, State.C != 0);
434 break;
435
436 case OP_FLAG:
437 case OP_FLAG_OUTPUT:
438 (*d10v_callback->printf_filtered) (d10v_callback, " :: %*s F0=%d F1=%d C=%d\n", SIZE_VALUES, "",
439 State.F0 != 0, State.F1 != 0, State.C != 0);
440 break;
441 }
442 }
443 }
444
445 #else
446 #define trace_input(NAME, IN1, IN2, IN3)
447 #define trace_output(RESULT)
448 #endif
449
450 /* abs */
451 void
452 OP_4607 ()
453 {
454 trace_input ("abs", OP_REG, OP_VOID, OP_VOID);
455 State.F1 = State.F0;
456 if ((int16)(State.regs[OP[0]]) < 0)
457 {
458 State.regs[OP[0]] = -(int16)(State.regs[OP[0]]);
459 State.F0 = 1;
460 }
461 else
462 State.F0 = 0;
463 trace_output (OP_REG);
464 }
465
466 /* abs */
467 void
468 OP_5607 ()
469 {
470 int64 tmp;
471
472 trace_input ("abs", OP_ACCUM, OP_VOID, OP_VOID);
473 State.F1 = State.F0;
474 State.a[OP[0]] = SEXT40(State.a[OP[0]]);
475
476 if (State.a[OP[0]] < 0 )
477 {
478 tmp = -State.a[OP[0]];
479 if (State.ST)
480 {
481 if (tmp > MAX32)
482 State.a[OP[0]] = MAX32;
483 else if (tmp < MIN32)
484 State.a[OP[0]] = MIN32;
485 else
486 State.a[OP[0]] = tmp & MASK40;
487 }
488 else
489 State.a[OP[0]] = tmp & MASK40;
490 State.F0 = 1;
491 }
492 else
493 State.F0 = 0;
494 trace_output (OP_ACCUM);
495 }
496
497 /* add */
498 void
499 OP_200 ()
500 {
501 uint16 tmp = State.regs[OP[0]];
502 trace_input ("add", OP_REG, OP_REG, OP_VOID);
503 State.regs[OP[0]] += State.regs[OP[1]];
504 if ( tmp > State.regs[OP[0]])
505 State.C = 1;
506 else
507 State.C = 0;
508 trace_output (OP_REG);
509 }
510
511 /* add */
512 void
513 OP_1201 ()
514 {
515 int64 tmp;
516 tmp = SEXT40(State.a[OP[0]]) + (SEXT16 (State.regs[OP[1]]) << 16 | State.regs[OP[1]+1]);
517
518 trace_input ("add", OP_ACCUM, OP_REG, OP_VOID);
519 if (State.ST)
520 {
521 if ( tmp > MAX32)
522 State.a[OP[0]] = MAX32;
523 else if ( tmp < MIN32)
524 State.a[OP[0]] = MIN32;
525 else
526 State.a[OP[0]] = tmp & MASK40;
527 }
528 else
529 State.a[OP[0]] = tmp & MASK40;
530 trace_output (OP_ACCUM);
531 }
532
533 /* add */
534 void
535 OP_1203 ()
536 {
537 int64 tmp;
538 tmp = SEXT40(State.a[OP[0]]) + SEXT40(State.a[OP[1]]);
539
540 trace_input ("add", OP_ACCUM, OP_ACCUM, OP_VOID);
541 if (State.ST)
542 {
543 if (tmp > MAX32)
544 State.a[OP[0]] = MAX32;
545 else if ( tmp < MIN32)
546 State.a[OP[0]] = MIN32;
547 else
548 State.a[OP[0]] = tmp & MASK40;
549 }
550 else
551 State.a[OP[0]] = tmp & MASK40;
552 trace_output (OP_ACCUM);
553 }
554
555 /* add2w */
556 void
557 OP_1200 ()
558 {
559 uint32 tmp;
560 uint32 tmp1 = (State.regs[OP[0]]) << 16 | State.regs[OP[0]+1];
561 uint32 tmp2 = (State.regs[OP[1]]) << 16 | State.regs[OP[1]+1];
562
563 trace_input ("add2w", OP_DREG, OP_DREG, OP_VOID);
564 tmp = tmp1 + tmp2;
565 if ( (tmp < tmp1) || (tmp < tmp2) )
566 State.C = 1;
567 else
568 State.C = 0;
569 State.regs[OP[0]] = tmp >> 16;
570 State.regs[OP[0]+1] = tmp & 0xFFFF;
571 trace_output (OP_DREG);
572 }
573
574 /* add3 */
575 void
576 OP_1000000 ()
577 {
578 uint16 tmp = State.regs[OP[0]];
579 State.regs[OP[0]] = State.regs[OP[1]] + OP[2];
580
581 trace_input ("add3", OP_REG_OUTPUT, OP_REG, OP_CONSTANT16);
582 if ( tmp > State.regs[OP[0]])
583 State.C = 1;
584 else
585 State.C = 0;
586 trace_output (OP_REG);
587 }
588
589 /* addac3 */
590 void
591 OP_17000200 ()
592 {
593 int64 tmp;
594 tmp = SEXT40(State.a[OP[2]]) + SEXT40 ((State.regs[OP[1]] << 16) | State.regs[OP[1]+1]);
595
596 trace_input ("addac3", OP_DREG_OUTPUT, OP_DREG, OP_ACCUM);
597 State.regs[OP[0]] = (tmp >> 16) & 0xffff;
598 State.regs[OP[0]+1] = tmp & 0xffff;
599 trace_output (OP_DREG);
600 }
601
602 /* addac3 */
603 void
604 OP_17000202 ()
605 {
606 int64 tmp;
607 tmp = SEXT40(State.a[OP[1]]) + SEXT40(State.a[OP[2]]);
608
609 trace_input ("addac3", OP_DREG_OUTPUT, OP_ACCUM, OP_ACCUM);
610 State.regs[OP[0]] = (tmp >> 16) & 0xffff;
611 State.regs[OP[0]+1] = tmp & 0xffff;
612 trace_output (OP_DREG);
613 }
614
615 /* addac3s */
616 void
617 OP_17001200 ()
618 {
619 int64 tmp;
620 State.F1 = State.F0;
621
622 trace_input ("addac3s", OP_DREG_OUTPUT, OP_DREG, OP_ACCUM);
623 tmp = SEXT40(State.a[OP[2]]) + SEXT40 ((State.regs[OP[1]] << 16) | State.regs[OP[1]+1]);
624 if ( tmp > MAX32)
625 {
626 State.regs[OP[0]] = 0x7fff;
627 State.regs[OP[0]+1] = 0xffff;
628 State.F0 = 1;
629 }
630 else if (tmp < MIN32)
631 {
632 State.regs[OP[0]] = 0x8000;
633 State.regs[OP[0]+1] = 0;
634 State.F0 = 1;
635 }
636 else
637 {
638 State.regs[OP[0]] = (tmp >> 16) & 0xffff;
639 State.regs[OP[0]+1] = tmp & 0xffff;
640 State.F0 = 0;
641 }
642 trace_output (OP_DREG);
643 }
644
645 /* addac3s */
646 void
647 OP_17001202 ()
648 {
649 int64 tmp;
650 State.F1 = State.F0;
651
652 trace_input ("addac3s", OP_DREG_OUTPUT, OP_ACCUM, OP_ACCUM);
653 tmp = SEXT40(State.a[OP[1]]) + SEXT40(State.a[OP[2]]);
654 if ( tmp > MAX32)
655 {
656 State.regs[OP[0]] = 0x7fff;
657 State.regs[OP[0]+1] = 0xffff;
658 State.F0 = 1;
659 }
660 else if (tmp < MIN32)
661 {
662 State.regs[OP[0]] = 0x8000;
663 State.regs[OP[0]+1] = 0;
664 State.F0 = 1;
665 }
666 else
667 {
668 State.regs[OP[0]] = (tmp >> 16) & 0xffff;
669 State.regs[OP[0]+1] = tmp & 0xffff;
670 State.F0 = 0;
671 }
672 trace_output (OP_DREG);
673 }
674
675 /* addi */
676 void
677 OP_201 ()
678 {
679 uint tmp = State.regs[OP[0]];
680 if (OP[1] == 0)
681 OP[1] = 16;
682 trace_input ("addi", OP_REG, OP_CONSTANT16, OP_VOID);
683 State.regs[OP[0]] += OP[1];
684 if (tmp > State.regs[OP[0]])
685 State.C = 1;
686 else
687 State.C = 0;
688 trace_output (OP_REG);
689 }
690
691 /* and */
692 void
693 OP_C00 ()
694 {
695 trace_input ("and", OP_REG, OP_REG, OP_VOID);
696 State.regs[OP[0]] &= State.regs[OP[1]];
697 trace_output (OP_REG);
698 }
699
700 /* and3 */
701 void
702 OP_6000000 ()
703 {
704 trace_input ("and3", OP_REG_OUTPUT, OP_REG, OP_CONSTANT16);
705 State.regs[OP[0]] = State.regs[OP[1]] & OP[2];
706 trace_output (OP_REG);
707 }
708
709 /* bclri */
710 void
711 OP_C01 ()
712 {
713 trace_input ("bclri", OP_REG, OP_CONSTANT16, OP_VOID);
714 State.regs[OP[0]] &= ~(0x8000 >> OP[1]);
715 trace_output (OP_REG);
716 }
717
718 /* bl.s */
719 void
720 OP_4900 ()
721 {
722 trace_input ("bl.s", OP_CONSTANT16, OP_VOID, OP_VOID);
723 State.regs[13] = PC+1;
724 PC += SEXT8 (OP[0]);
725 trace_output (OP_VOID);
726 }
727
728 /* bl.l */
729 void
730 OP_24800000 ()
731 {
732 trace_input ("bl.l", OP_CONSTANT16, OP_VOID, OP_VOID);
733 State.regs[13] = PC+1;
734 PC += OP[0];
735 trace_output (OP_VOID);
736 }
737
738 /* bnoti */
739 void
740 OP_A01 ()
741 {
742 trace_input ("bnoti", OP_REG, OP_CONSTANT16, OP_VOID);
743 State.regs[OP[0]] ^= 0x8000 >> OP[1];
744 trace_output (OP_REG);
745 }
746
747 /* bra.s */
748 void
749 OP_4800 ()
750 {
751 trace_input ("bra.s", OP_CONSTANT16, OP_VOID, OP_VOID);
752 PC += SEXT8 (OP[0]);
753 trace_output (OP_VOID);
754 }
755
756 /* bra.l */
757 void
758 OP_24000000 ()
759 {
760 trace_input ("bra.l", OP_CONSTANT16, OP_VOID, OP_VOID);
761 PC += OP[0];
762 trace_output (OP_VOID);
763 }
764
765 /* brf0f.s */
766 void
767 OP_4A00 ()
768 {
769 trace_input ("brf0f.s", OP_CONSTANT16, OP_VOID, OP_VOID);
770 if (State.F0 == 0)
771 PC += SEXT8 (OP[0]);
772 trace_output (OP_FLAG);
773 }
774
775 /* brf0f.l */
776 void
777 OP_25000000 ()
778 {
779 trace_input ("brf0f.l", OP_CONSTANT16, OP_VOID, OP_VOID);
780 if (State.F0 == 0)
781 PC += OP[0];
782 trace_output (OP_FLAG);
783 }
784
785 /* brf0t.s */
786 void
787 OP_4B00 ()
788 {
789 trace_input ("brf0t.s", OP_CONSTANT16, OP_VOID, OP_VOID);
790 if (State.F0)
791 PC += SEXT8 (OP[0]);
792 trace_output (OP_FLAG);
793 }
794
795 /* brf0t.l */
796 void
797 OP_25800000 ()
798 {
799 trace_input ("brf0t.l", OP_CONSTANT16, OP_VOID, OP_VOID);
800 if (State.F0)
801 PC += OP[0];
802 trace_output (OP_FLAG);
803 }
804
805 /* bseti */
806 void
807 OP_801 ()
808 {
809 trace_input ("bseti", OP_REG, OP_CONSTANT16, OP_VOID);
810 State.regs[OP[0]] |= 0x8000 >> OP[1];
811 trace_output (OP_REG);
812 }
813
814 /* btsti */
815 void
816 OP_E01 ()
817 {
818 trace_input ("btsti", OP_REG, OP_CONSTANT16, OP_VOID);
819 State.F1 = State.F0;
820 State.F0 = (State.regs[OP[0]] & (0x8000 >> OP[1])) ? 1 : 0;
821 trace_output (OP_FLAG);
822 }
823
824 /* clrac */
825 void
826 OP_5601 ()
827 {
828 trace_input ("clrac", OP_ACCUM_OUTPUT, OP_VOID, OP_VOID);
829 State.a[OP[0]] = 0;
830 trace_output (OP_ACCUM);
831 }
832
833 /* cmp */
834 void
835 OP_600 ()
836 {
837 trace_input ("cmp", OP_REG, OP_REG, OP_VOID);
838 State.F1 = State.F0;
839 State.F0 = ((int16)(State.regs[OP[0]]) < (int16)(State.regs[OP[1]])) ? 1 : 0;
840 trace_output (OP_FLAG);
841 }
842
843 /* cmp */
844 void
845 OP_1603 ()
846 {
847 trace_input ("cmp", OP_ACCUM, OP_ACCUM, OP_VOID);
848 State.F1 = State.F0;
849 State.F0 = (SEXT40(State.a[OP[0]]) < SEXT40(State.a[OP[1]])) ? 1 : 0;
850 trace_output (OP_FLAG);
851 }
852
853 /* cmpeq */
854 void
855 OP_400 ()
856 {
857 trace_input ("cmpeq", OP_REG, OP_REG, OP_VOID);
858 State.F1 = State.F0;
859 State.F0 = (State.regs[OP[0]] == State.regs[OP[1]]) ? 1 : 0;
860 trace_output (OP_FLAG);
861 }
862
863 /* cmpeq */
864 void
865 OP_1403 ()
866 {
867 trace_input ("cmpeq", OP_ACCUM, OP_ACCUM, OP_VOID);
868 State.F1 = State.F0;
869 State.F0 = (State.a[OP[0]] == State.a[OP[1]]) ? 1 : 0;
870 trace_output (OP_FLAG);
871 }
872
873 /* cmpeqi.s */
874 void
875 OP_401 ()
876 {
877 trace_input ("cmpeqi.s", OP_REG, OP_CONSTANT16, OP_VOID);
878 State.F1 = State.F0;
879 State.F0 = (State.regs[OP[0]] == SEXT4(OP[1])) ? 1 : 0;
880 trace_output (OP_FLAG);
881 }
882
883 /* cmpeqi.l */
884 void
885 OP_2000000 ()
886 {
887 trace_input ("cmpeqi.l", OP_REG, OP_CONSTANT16, OP_VOID);
888 State.F1 = State.F0;
889 State.F0 = (State.regs[OP[0]] == OP[1]) ? 1 : 0;
890 trace_output (OP_FLAG);
891 }
892
893 /* cmpi.s */
894 void
895 OP_601 ()
896 {
897 trace_input ("cmpi.s", OP_REG, OP_CONSTANT4, OP_VOID);
898 State.F1 = State.F0;
899 State.F0 = ((int16)(State.regs[OP[0]]) < SEXT4(OP[1])) ? 1 : 0;
900 trace_output (OP_FLAG);
901 }
902
903 /* cmpi.l */
904 void
905 OP_3000000 ()
906 {
907 trace_input ("cmpi.l", OP_REG, OP_CONSTANT16, OP_VOID);
908 State.F1 = State.F0;
909 State.F0 = ((int16)(State.regs[OP[0]]) < (int16)(OP[1])) ? 1 : 0;
910 trace_output (OP_FLAG);
911 }
912
913 /* cmpu */
914 void
915 OP_4600 ()
916 {
917 trace_input ("cmpu", OP_REG, OP_REG, OP_VOID);
918 State.F1 = State.F0;
919 State.F0 = (State.regs[OP[0]] < State.regs[OP[1]]) ? 1 : 0;
920 trace_output (OP_FLAG);
921 }
922
923 /* cmpui */
924 void
925 OP_23000000 ()
926 {
927 trace_input ("cmpui", OP_REG, OP_CONSTANT16, OP_VOID);
928 State.F1 = State.F0;
929 State.F0 = (State.regs[OP[0]] < OP[1]) ? 1 : 0;
930 trace_output (OP_FLAG);
931 }
932
933 /* cpfg */
934 void
935 OP_4E09 ()
936 {
937 uint8 *src, *dst;
938
939 trace_input ("cpfg", OP_FLAG_OUTPUT, OP_FLAG, OP_VOID);
940 if (OP[0] == 0)
941 dst = &State.F0;
942 else
943 dst = &State.F1;
944
945 if (OP[1] == 0)
946 src = &State.F0;
947 else if (OP[1] == 1)
948 src = &State.F1;
949 else
950 src = &State.C;
951
952 *dst = *src;
953 trace_output (OP_FLAG);
954 }
955
956 /* dbt */
957 void
958 OP_5F20 ()
959 {
960 /* d10v_callback->printf_filtered(d10v_callback, "***** DBT ***** PC=%x\n",PC); */
961 State.exception = SIGTRAP;
962 }
963
964 /* divs */
965 void
966 OP_14002800 ()
967 {
968 uint16 foo, tmp, tmpf;
969
970 trace_input ("divs", OP_DREG, OP_REG, OP_VOID);
971 foo = (State.regs[OP[0]] << 1) | (State.regs[OP[0]+1] >> 15);
972 tmp = (int16)foo - (int16)(State.regs[OP[1]]);
973 tmpf = (foo >= State.regs[OP[1]]) ? 1 : 0;
974 State.regs[OP[0]] = (tmpf == 1) ? tmp : foo;
975 State.regs[OP[0]+1] = (State.regs[OP[0]+1] << 1) | tmpf;
976 trace_output (OP_DREG);
977 }
978
979 /* exef0f */
980 void
981 OP_4E04 ()
982 {
983 trace_input ("exef0f", OP_VOID, OP_VOID, OP_VOID);
984 State.exe = (State.F0 == 0);
985 trace_output (OP_FLAG);
986 }
987
988 /* exef0t */
989 void
990 OP_4E24 ()
991 {
992 trace_input ("exef0t", OP_VOID, OP_VOID, OP_VOID);
993 State.exe = (State.F0 != 0);
994 trace_output (OP_FLAG);
995 }
996
997 /* exef1f */
998 void
999 OP_4E40 ()
1000 {
1001 trace_input ("exef1f", OP_VOID, OP_VOID, OP_VOID);
1002 State.exe = (State.F1 == 0);
1003 trace_output (OP_FLAG);
1004 }
1005
1006 /* exef1t */
1007 void
1008 OP_4E42 ()
1009 {
1010 trace_input ("exef1t", OP_VOID, OP_VOID, OP_VOID);
1011 State.exe = (State.F1 != 0);
1012 trace_output (OP_FLAG);
1013 }
1014
1015 /* exefaf */
1016 void
1017 OP_4E00 ()
1018 {
1019 trace_input ("exefaf", OP_VOID, OP_VOID, OP_VOID);
1020 State.exe = (State.F0 == 0) & (State.F1 == 0);
1021 trace_output (OP_FLAG);
1022 }
1023
1024 /* exefat */
1025 void
1026 OP_4E02 ()
1027 {
1028 trace_input ("exefat", OP_VOID, OP_VOID, OP_VOID);
1029 State.exe = (State.F0 == 0) & (State.F1 != 0);
1030 trace_output (OP_FLAG);
1031 }
1032
1033 /* exetaf */
1034 void
1035 OP_4E20 ()
1036 {
1037 trace_input ("exetaf", OP_VOID, OP_VOID, OP_VOID);
1038 State.exe = (State.F0 != 0) & (State.F1 == 0);
1039 trace_output (OP_FLAG);
1040 }
1041
1042 /* exetat */
1043 void
1044 OP_4E22 ()
1045 {
1046 trace_input ("exetat", OP_VOID, OP_VOID, OP_VOID);
1047 State.exe = (State.F0 != 0) & (State.F1 != 0);
1048 trace_output (OP_FLAG);
1049 }
1050
1051 /* exp */
1052 void
1053 OP_15002A00 ()
1054 {
1055 uint32 tmp, foo;
1056 int i;
1057
1058 trace_input ("exp", OP_REG_OUTPUT, OP_DREG, OP_VOID);
1059 if (((int16)State.regs[OP[1]]) >= 0)
1060 tmp = (State.regs[OP[1]] << 16) | State.regs[OP[1]+1];
1061 else
1062 tmp = ~((State.regs[OP[1]] << 16) | State.regs[OP[1]+1]);
1063
1064 foo = 0x40000000;
1065 for (i=1;i<17;i++)
1066 {
1067 if (tmp & foo)
1068 {
1069 State.regs[OP[0]] = i-1;
1070 trace_output (OP_REG);
1071 return;
1072 }
1073 foo >>= 1;
1074 }
1075 State.regs[OP[0]] = 16;
1076 trace_output (OP_REG);
1077 }
1078
1079 /* exp */
1080 void
1081 OP_15002A02 ()
1082 {
1083 int64 tmp, foo;
1084 int i;
1085
1086 trace_input ("exp", OP_REG_OUTPUT, OP_ACCUM, OP_VOID);
1087 if (SEXT40(State.a[OP[1]]) >= 0)
1088 tmp = State.a[OP[1]];
1089 else
1090 tmp = ~(State.a[OP[1]]);
1091
1092 foo = 0x4000000000LL;
1093 for (i=1;i<25;i++)
1094 {
1095 if (tmp & foo)
1096 {
1097 State.regs[OP[0]] = i-9;
1098 trace_output (OP_REG);
1099 return;
1100 }
1101 foo >>= 1;
1102 }
1103 State.regs[OP[0]] = 16;
1104 trace_output (OP_REG);
1105 }
1106
1107 /* jl */
1108 void
1109 OP_4D00 ()
1110 {
1111 trace_input ("jl", OP_REG, OP_VOID, OP_VOID);
1112 State.regs[13] = PC+1;
1113 PC = State.regs[OP[0]];
1114 trace_output (OP_VOID);
1115 }
1116
1117 /* jmp */
1118 void
1119 OP_4C00 ()
1120 {
1121 trace_input ("jmp", OP_REG, OP_VOID, OP_VOID);
1122 PC = State.regs[OP[0]];
1123 trace_output (OP_VOID);
1124 }
1125
1126 /* ld */
1127 void
1128 OP_30000000 ()
1129 {
1130 trace_input ("ld", OP_REG_OUTPUT, OP_MEMREF2, OP_VOID);
1131 State.regs[OP[0]] = RW (OP[1] + State.regs[OP[2]]);
1132 trace_output (OP_REG);
1133 }
1134
1135 /* ld */
1136 void
1137 OP_6401 ()
1138 {
1139 trace_input ("ld", OP_REG_OUTPUT, OP_POSTDEC, OP_VOID);
1140 State.regs[OP[0]] = RW (State.regs[OP[1]]);
1141 INC_ADDR(State.regs[OP[1]],-2);
1142 trace_output (OP_REG);
1143 }
1144
1145 /* ld */
1146 void
1147 OP_6001 ()
1148 {
1149 trace_input ("ld", OP_REG_OUTPUT, OP_POSTINC, OP_VOID);
1150 State.regs[OP[0]] = RW (State.regs[OP[1]]);
1151 INC_ADDR(State.regs[OP[1]],2);
1152 trace_output (OP_REG);
1153 }
1154
1155 /* ld */
1156 void
1157 OP_6000 ()
1158 {
1159 trace_input ("ld", OP_REG_OUTPUT, OP_MEMREF, OP_VOID);
1160 State.regs[OP[0]] = RW (State.regs[OP[1]]);
1161 trace_output (OP_REG);
1162 }
1163
1164 /* ld2w */
1165 void
1166 OP_31000000 ()
1167 {
1168 trace_input ("ld2w", OP_REG_OUTPUT, OP_MEMREF2, OP_VOID);
1169 State.regs[OP[0]] = RW (OP[1] + State.regs[OP[2]]);
1170 State.regs[OP[0]+1] = RW (OP[1] + State.regs[OP[2]] + 2);
1171 trace_output (OP_DREG);
1172 }
1173
1174 /* ld2w */
1175 void
1176 OP_6601 ()
1177 {
1178 trace_input ("ld2w", OP_REG_OUTPUT, OP_POSTDEC, OP_VOID);
1179 State.regs[OP[0]] = RW (State.regs[OP[1]]);
1180 State.regs[OP[0]+1] = RW (State.regs[OP[1]]+2);
1181 INC_ADDR(State.regs[OP[1]],-4);
1182 trace_output (OP_DREG);
1183 }
1184
1185 /* ld2w */
1186 void
1187 OP_6201 ()
1188 {
1189 trace_input ("ld2w", OP_REG_OUTPUT, OP_POSTINC, OP_VOID);
1190 State.regs[OP[0]] = RW (State.regs[OP[1]]);
1191 State.regs[OP[0]+1] = RW (State.regs[OP[1]]+2);
1192 INC_ADDR(State.regs[OP[1]],4);
1193 trace_output (OP_REG);
1194 }
1195
1196 /* ld2w */
1197 void
1198 OP_6200 ()
1199 {
1200 trace_input ("ld2w", OP_REG_OUTPUT, OP_MEMREF, OP_VOID);
1201 State.regs[OP[0]] = RW (State.regs[OP[1]]);
1202 State.regs[OP[0]+1] = RW (State.regs[OP[1]]+2);
1203 trace_output (OP_REG);
1204 }
1205
1206 /* ldb */
1207 void
1208 OP_38000000 ()
1209 {
1210 trace_input ("ldb", OP_REG_OUTPUT, OP_MEMREF2, OP_VOID);
1211 State.regs[OP[0]] = RB (OP[1] + State.regs[OP[2]]);
1212 SEXT8 (State.regs[OP[0]]);
1213 trace_output (OP_REG);
1214 }
1215
1216 /* ldb */
1217 void
1218 OP_7000 ()
1219 {
1220 trace_input ("ldb", OP_REG_OUTPUT, OP_MEMREF, OP_VOID);
1221 State.regs[OP[0]] = RB (State.regs[OP[1]]);
1222 SEXT8 (State.regs[OP[0]]);
1223 trace_output (OP_REG);
1224 }
1225
1226 /* ldi.s */
1227 void
1228 OP_4001 ()
1229 {
1230 trace_input ("ldi.s", OP_REG_OUTPUT, OP_CONSTANT4, OP_VOID);
1231 State.regs[OP[0]] = SEXT4(OP[1]);
1232 trace_output (OP_REG);
1233 }
1234
1235 /* ldi.l */
1236 void
1237 OP_20000000 ()
1238 {
1239 trace_input ("ldi.s", OP_REG_OUTPUT, OP_CONSTANT16, OP_VOID);
1240 State.regs[OP[0]] = OP[1];
1241 trace_output (OP_REG);
1242 }
1243
1244 /* ldub */
1245 void
1246 OP_39000000 ()
1247 {
1248 trace_input ("ldub", OP_REG_OUTPUT, OP_MEMREF2, OP_VOID);
1249 State.regs[OP[0]] = RB (OP[1] + State.regs[OP[2]]);
1250 trace_output (OP_REG);
1251 }
1252
1253 /* ldub */
1254 void
1255 OP_7200 ()
1256 {
1257 trace_input ("ldub", OP_REG_OUTPUT, OP_MEMREF, OP_VOID);
1258 State.regs[OP[0]] = RB (State.regs[OP[1]]);
1259 trace_output (OP_REG);
1260 }
1261
1262 /* mac */
1263 void
1264 OP_2A00 ()
1265 {
1266 int64 tmp;
1267
1268 trace_input ("mac", OP_ACCUM, OP_REG, OP_REG);
1269 tmp = SEXT40 ((int16)(State.regs[OP[1]]) * (int16)(State.regs[OP[2]]));
1270
1271 if (State.FX)
1272 tmp = SEXT40( (tmp << 1) & MASK40);
1273
1274 if (State.ST && tmp > MAX32)
1275 tmp = MAX32;
1276
1277 tmp += SEXT40(State.a[OP[0]]);
1278 if (State.ST)
1279 {
1280 if (tmp > MAX32)
1281 State.a[OP[0]] = MAX32;
1282 else if (tmp < MIN32)
1283 State.a[OP[0]] = MIN32;
1284 else
1285 State.a[OP[0]] = tmp & MASK40;
1286 }
1287 else
1288 State.a[OP[0]] = tmp & MASK40;
1289 trace_output (OP_ACCUM);
1290 }
1291
1292 /* macsu */
1293 void
1294 OP_1A00 ()
1295 {
1296 int64 tmp;
1297
1298 trace_input ("macsu", OP_ACCUM, OP_REG, OP_REG);
1299 tmp = SEXT40 ((int16)State.regs[OP[1]] * State.regs[OP[2]]);
1300 if (State.FX)
1301 tmp = SEXT40( (tmp << 1) & MASK40);
1302
1303 State.a[OP[0]] = (SEXT40 (State.a[OP[0]]) + tmp) & MASK40;
1304 trace_output (OP_ACCUM);
1305 }
1306
1307 /* macu */
1308 void
1309 OP_3A00 ()
1310 {
1311 int64 tmp;
1312
1313 trace_input ("macu", OP_ACCUM, OP_REG, OP_REG);
1314 tmp = SEXT40 (State.regs[OP[1]] * State.regs[OP[2]]);
1315 if (State.FX)
1316 tmp = SEXT40( (tmp << 1) & MASK40);
1317 State.a[OP[0]] = (SEXT40 (State.a[OP[0]]) + tmp) & MASK40;
1318 trace_output (OP_ACCUM);
1319 }
1320
1321 /* max */
1322 void
1323 OP_2600 ()
1324 {
1325 trace_input ("max", OP_REG, OP_REG, OP_VOID);
1326 State.F1 = State.F0;
1327 if ((int16)State.regs[OP[1]] > (int16)State.regs[OP[0]])
1328 {
1329 State.regs[OP[0]] = State.regs[OP[1]];
1330 State.F0 = 1;
1331 }
1332 else
1333 State.F0 = 0;
1334 trace_output (OP_REG);
1335 }
1336
1337 /* max */
1338 void
1339 OP_3600 ()
1340 {
1341 int64 tmp;
1342
1343 trace_input ("max", OP_ACCUM, OP_DREG, OP_VOID);
1344 State.F1 = State.F0;
1345 tmp = SEXT16 (State.regs[OP[1]]) << 16 | State.regs[OP[1]+1];
1346 if (tmp > SEXT40(State.a[OP[0]]))
1347 {
1348 State.a[OP[0]] = tmp & MASK40;
1349 State.F0 = 1;
1350 }
1351 else
1352 State.F0 = 0;
1353 trace_output (OP_ACCUM);
1354 }
1355
1356 /* max */
1357 void
1358 OP_3602 ()
1359 {
1360 trace_input ("max", OP_ACCUM, OP_ACCUM, OP_VOID);
1361 State.F1 = State.F0;
1362 if (SEXT40(State.a[OP[1]]) > SEXT40(State.a[OP[0]]))
1363 {
1364 State.a[OP[0]] = State.a[OP[1]];
1365 State.F0 = 1;
1366 }
1367 else
1368 State.F0 = 0;
1369 trace_output (OP_ACCUM);
1370 }
1371
1372
1373 /* min */
1374 void
1375 OP_2601 ()
1376 {
1377 trace_input ("min", OP_REG, OP_REG, OP_VOID);
1378 State.F1 = State.F0;
1379 if ((int16)State.regs[OP[1]] < (int16)State.regs[OP[0]])
1380 {
1381 State.regs[OP[0]] = State.regs[OP[1]];
1382 State.F0 = 1;
1383 }
1384 else
1385 State.F0 = 0;
1386 trace_output (OP_REG);
1387 }
1388
1389 /* min */
1390 void
1391 OP_3601 ()
1392 {
1393 int64 tmp;
1394
1395 trace_input ("min", OP_ACCUM, OP_DREG, OP_VOID);
1396 State.F1 = State.F0;
1397 tmp = SEXT16 (State.regs[OP[1]]) << 16 | State.regs[OP[1]+1];
1398 if (tmp < SEXT40(State.a[OP[0]]))
1399 {
1400 State.a[OP[0]] = tmp & MASK40;
1401 State.F0 = 1;
1402 }
1403 else
1404 State.F0 = 0;
1405 trace_output (OP_ACCUM);
1406 }
1407
1408 /* min */
1409 void
1410 OP_3603 ()
1411 {
1412 trace_input ("min", OP_ACCUM, OP_ACCUM, OP_VOID);
1413 State.F1 = State.F0;
1414 if (SEXT40(State.a[OP[1]]) < SEXT40(State.a[OP[0]]))
1415 {
1416 State.a[OP[0]] = State.a[OP[1]];
1417 State.F0 = 1;
1418 }
1419 else
1420 State.F0 = 0;
1421 trace_output (OP_ACCUM);
1422 }
1423
1424 /* msb */
1425 void
1426 OP_2800 ()
1427 {
1428 int64 tmp;
1429
1430 trace_input ("msb", OP_ACCUM, OP_REG, OP_REG);
1431 tmp = SEXT40 ((int16)(State.regs[OP[1]]) * (int16)(State.regs[OP[2]]));
1432
1433 if (State.FX)
1434 tmp = SEXT40 ((tmp << 1) & MASK40);
1435
1436 if (State.ST && tmp > MAX32)
1437 tmp = MAX32;
1438
1439 tmp = SEXT40(State.a[OP[0]]) - tmp;
1440 if (State.ST)
1441 {
1442 if (tmp > MAX32)
1443 State.a[OP[0]] = MAX32;
1444 else if (tmp < MIN32)
1445 State.a[OP[0]] = MIN32;
1446 else
1447 State.a[OP[0]] = tmp & MASK40;
1448 }
1449 else
1450 State.a[OP[0]] = tmp & MASK40;
1451 trace_output (OP_ACCUM);
1452 }
1453
1454 /* msbsu */
1455 void
1456 OP_1800 ()
1457 {
1458 int64 tmp;
1459
1460 trace_input ("msbsu", OP_ACCUM, OP_REG, OP_REG);
1461 tmp = SEXT40 ((int16)State.regs[OP[1]] * State.regs[OP[2]]);
1462 if (State.FX)
1463 tmp = SEXT40( (tmp << 1) & MASK40);
1464
1465 State.a[OP[0]] = (SEXT40 (State.a[OP[0]]) - tmp) & MASK40;
1466 trace_output (OP_ACCUM);
1467 }
1468
1469 /* msbu */
1470 void
1471 OP_3800 ()
1472 {
1473 int64 tmp;
1474
1475 trace_input ("msbu", OP_ACCUM, OP_REG, OP_REG);
1476 tmp = SEXT40 (State.regs[OP[1]] * State.regs[OP[2]]);
1477 if (State.FX)
1478 tmp = SEXT40( (tmp << 1) & MASK40);
1479
1480 State.a[OP[0]] = (SEXT40 (State.a[OP[0]]) - tmp) & MASK40;
1481 trace_output (OP_ACCUM);
1482 }
1483
1484 /* mul */
1485 void
1486 OP_2E00 ()
1487 {
1488 trace_input ("mul", OP_REG, OP_REG, OP_VOID);
1489 State.regs[OP[0]] *= State.regs[OP[1]];
1490 trace_output (OP_REG);
1491 }
1492
1493 /* mulx */
1494 void
1495 OP_2C00 ()
1496 {
1497 int64 tmp;
1498
1499 trace_input ("mulx", OP_ACCUM_OUTPUT, OP_REG, OP_REG);
1500 tmp = SEXT40 ((int16)(State.regs[OP[1]]) * (int16)(State.regs[OP[2]]));
1501
1502 if (State.FX)
1503 tmp = SEXT40 ((tmp << 1) & MASK40);
1504
1505 if (State.ST && tmp > MAX32)
1506 State.a[OP[0]] = MAX32;
1507 else
1508 State.a[OP[0]] = tmp & MASK40;
1509 trace_output (OP_ACCUM);
1510 }
1511
1512 /* mulxsu */
1513 void
1514 OP_1C00 ()
1515 {
1516 int64 tmp;
1517
1518 trace_input ("mulxsu", OP_ACCUM_OUTPUT, OP_REG, OP_REG);
1519 tmp = SEXT40 ((int16)(State.regs[OP[1]]) * State.regs[OP[2]]);
1520
1521 if (State.FX)
1522 tmp <<= 1;
1523
1524 State.a[OP[0]] = tmp & MASK40;
1525 trace_output (OP_ACCUM);
1526 }
1527
1528 /* mulxu */
1529 void
1530 OP_3C00 ()
1531 {
1532 int64 tmp;
1533
1534 trace_input ("mulxu", OP_ACCUM_OUTPUT, OP_REG, OP_REG);
1535 tmp = SEXT40 (State.regs[OP[1]] * State.regs[OP[2]]);
1536
1537 if (State.FX)
1538 tmp <<= 1;
1539
1540 State.a[OP[0]] = tmp & MASK40;
1541 trace_output (OP_ACCUM);
1542 }
1543
1544 /* mv */
1545 void
1546 OP_4000 ()
1547 {
1548 trace_input ("mv", OP_REG_OUTPUT, OP_REG, OP_VOID);
1549 State.regs[OP[0]] = State.regs[OP[1]];
1550 trace_output (OP_REG);
1551 }
1552
1553 /* mv2w */
1554 void
1555 OP_5000 ()
1556 {
1557 trace_input ("mv2w", OP_DREG_OUTPUT, OP_DREG, OP_VOID);
1558 State.regs[OP[0]] = State.regs[OP[1]];
1559 State.regs[OP[0]+1] = State.regs[OP[1]+1];
1560 trace_output (OP_DREG);
1561 }
1562
1563 /* mv2wfac */
1564 void
1565 OP_3E00 ()
1566 {
1567 trace_input ("mv2wfac", OP_DREG_OUTPUT, OP_ACCUM, OP_VOID);
1568 State.regs[OP[0]] = (State.a[OP[1]] >> 16) & 0xffff;
1569 State.regs[OP[0]+1] = State.a[OP[1]] & 0xffff;
1570 trace_output (OP_DREG);
1571 }
1572
1573 /* mv2wtac */
1574 void
1575 OP_3E01 ()
1576 {
1577 trace_input ("mv2wtac", OP_ACCUM_OUTPUT, OP_DREG, OP_VOID);
1578 State.a[OP[1]] = (SEXT16 (State.regs[OP[0]]) << 16 | State.regs[OP[0]+1]) & MASK40;
1579 trace_output (OP_ACCUM);
1580 }
1581
1582 /* mvac */
1583 void
1584 OP_3E03 ()
1585 {
1586 trace_input ("mvac", OP_ACCUM_OUTPUT, OP_ACCUM, OP_VOID);
1587 State.a[OP[0]] = State.a[OP[1]];
1588 trace_output (OP_ACCUM);
1589 }
1590
1591 /* mvb */
1592 void
1593 OP_5400 ()
1594 {
1595 trace_input ("mvb", OP_REG_OUTPUT, OP_REG, OP_VOID);
1596 State.regs[OP[0]] = SEXT8 (State.regs[OP[1]] & 0xff);
1597 trace_output (OP_REG);
1598 }
1599
1600 /* mvf0f */
1601 void
1602 OP_4400 ()
1603 {
1604 trace_input ("mf0f", OP_REG_OUTPUT, OP_REG, OP_VOID);
1605 if (State.F0 == 0)
1606 State.regs[OP[0]] = State.regs[OP[1]];
1607 trace_output (OP_REG);
1608 }
1609
1610 /* mvf0t */
1611 void
1612 OP_4401 ()
1613 {
1614 trace_input ("mf0t", OP_REG_OUTPUT, OP_REG, OP_VOID);
1615 if (State.F0)
1616 State.regs[OP[0]] = State.regs[OP[1]];
1617 trace_output (OP_REG);
1618 }
1619
1620 /* mvfacg */
1621 void
1622 OP_1E04 ()
1623 {
1624 trace_input ("mvfacg", OP_REG_OUTPUT, OP_ACCUM, OP_VOID);
1625 State.regs[OP[0]] = (State.a[OP[1]] >> 32) & 0xff;
1626 trace_output (OP_ACCUM);
1627 }
1628
1629 /* mvfachi */
1630 void
1631 OP_1E00 ()
1632 {
1633 trace_input ("mvfachi", OP_REG_OUTPUT, OP_ACCUM, OP_VOID);
1634 State.regs[OP[0]] = (State.a[OP[1]] >> 16) & 0xffff;
1635 trace_output (OP_REG);
1636 }
1637
1638 /* mvfaclo */
1639 void
1640 OP_1E02 ()
1641 {
1642 trace_input ("mvfaclo", OP_REG_OUTPUT, OP_ACCUM, OP_VOID);
1643 State.regs[OP[0]] = State.a[OP[1]] & 0xffff;
1644 trace_output (OP_REG);
1645 }
1646
1647 /* mvfc */
1648 void
1649 OP_5200 ()
1650 {
1651 trace_input ("mvfc", OP_REG_OUTPUT, OP_CR, OP_VOID);
1652 if (OP[1] == 0)
1653 {
1654 /* PSW is treated specially */
1655 PSW = 0;
1656 if (State.SM) PSW |= 0x8000;
1657 if (State.EA) PSW |= 0x2000;
1658 if (State.DB) PSW |= 0x1000;
1659 if (State.IE) PSW |= 0x400;
1660 if (State.RP) PSW |= 0x200;
1661 if (State.MD) PSW |= 0x100;
1662 if (State.FX) PSW |= 0x80;
1663 if (State.ST) PSW |= 0x40;
1664 if (State.F0) PSW |= 8;
1665 if (State.F1) PSW |= 4;
1666 if (State.C) PSW |= 1;
1667 }
1668 State.regs[OP[0]] = State.cregs[OP[1]];
1669 trace_output (OP_REG);
1670 }
1671
1672 /* mvtacg */
1673 void
1674 OP_1E41 ()
1675 {
1676 trace_input ("mvtacg", OP_REG, OP_ACCUM, OP_VOID);
1677 State.a[OP[1]] &= MASK32;
1678 State.a[OP[1]] |= (int64)(State.regs[OP[0]] & 0xff) << 32;
1679 trace_output (OP_ACCUM_REVERSE);
1680 }
1681
1682 /* mvtachi */
1683 void
1684 OP_1E01 ()
1685 {
1686 uint16 tmp;
1687
1688 trace_input ("mvtachi", OP_REG, OP_ACCUM, OP_VOID);
1689 tmp = State.a[OP[1]] & 0xffff;
1690 State.a[OP[1]] = (SEXT16 (State.regs[OP[0]]) << 16 | tmp) & MASK40;
1691 trace_output (OP_ACCUM_REVERSE);
1692 }
1693
1694 /* mvtaclo */
1695 void
1696 OP_1E21 ()
1697 {
1698 trace_input ("mvtaclo", OP_REG, OP_ACCUM, OP_VOID);
1699 State.a[OP[1]] = (SEXT16 (State.regs[OP[0]])) & MASK40;
1700 trace_output (OP_ACCUM_REVERSE);
1701 }
1702
1703 /* mvtc */
1704 void
1705 OP_5600 ()
1706 {
1707 trace_input ("mvtc", OP_REG, OP_CR_OUTPUT, OP_VOID);
1708 State.cregs[OP[1]] = State.regs[OP[0]];
1709 if (OP[1] == 0)
1710 {
1711 /* PSW is treated specially */
1712 State.SM = (PSW & 0x8000) ? 1 : 0;
1713 State.EA = (PSW & 0x2000) ? 1 : 0;
1714 State.DB = (PSW & 0x1000) ? 1 : 0;
1715 State.IE = (PSW & 0x400) ? 1 : 0;
1716 State.RP = (PSW & 0x200) ? 1 : 0;
1717 State.MD = (PSW & 0x100) ? 1 : 0;
1718 State.FX = (PSW & 0x80) ? 1 : 0;
1719 State.ST = (PSW & 0x40) ? 1 : 0;
1720 State.F0 = (PSW & 8) ? 1 : 0;
1721 State.F1 = (PSW & 4) ? 1 : 0;
1722 State.C = PSW & 1;
1723 if (State.ST && !State.FX)
1724 {
1725 (*d10v_callback->printf_filtered) (d10v_callback,
1726 "ERROR at PC 0x%x: ST can only be set when FX is set.\n",
1727 PC<<2);
1728 State.exception = SIGILL;
1729 }
1730 }
1731 trace_output (OP_CR_REVERSE);
1732 }
1733
1734 /* mvub */
1735 void
1736 OP_5401 ()
1737 {
1738 trace_input ("mvub", OP_REG_OUTPUT, OP_REG, OP_VOID);
1739 State.regs[OP[0]] = State.regs[OP[1]] & 0xff;
1740 trace_output (OP_REG);
1741 }
1742
1743 /* neg */
1744 void
1745 OP_4605 ()
1746 {
1747 trace_input ("neg", OP_REG, OP_VOID, OP_VOID);
1748 State.regs[OP[0]] = 0 - State.regs[OP[0]];
1749 trace_output (OP_REG);
1750 }
1751
1752 /* neg */
1753 void
1754 OP_5605 ()
1755 {
1756 int64 tmp;
1757
1758 trace_input ("neg", OP_ACCUM, OP_VOID, OP_VOID);
1759 tmp = -SEXT40(State.a[OP[0]]);
1760 if (State.ST)
1761 {
1762 if ( tmp > MAX32)
1763 State.a[OP[0]] = MAX32;
1764 else if (tmp < MIN32)
1765 State.a[OP[0]] = MIN32;
1766 else
1767 State.a[OP[0]] = tmp & MASK40;
1768 }
1769 else
1770 State.a[OP[0]] = tmp & MASK40;
1771 trace_output (OP_ACCUM);
1772 }
1773
1774
1775 /* nop */
1776 void
1777 OP_5E00 ()
1778 {
1779 trace_input ("nop", OP_VOID, OP_VOID, OP_VOID);
1780 trace_output (OP_VOID);
1781
1782 if (State.ins_type == INS_LEFT || State.ins_type == INS_LEFT_PARALLEL)
1783 left_nops++;
1784 else
1785 right_nops++;
1786 }
1787
1788 /* not */
1789 void
1790 OP_4603 ()
1791 {
1792 trace_input ("not", OP_REG, OP_VOID, OP_VOID);
1793 State.regs[OP[0]] = ~(State.regs[OP[0]]);
1794 trace_output (OP_REG);
1795 }
1796
1797 /* or */
1798 void
1799 OP_800 ()
1800 {
1801 trace_input ("or", OP_REG, OP_REG, OP_VOID);
1802 State.regs[OP[0]] |= State.regs[OP[1]];
1803 trace_output (OP_REG);
1804 }
1805
1806 /* or3 */
1807 void
1808 OP_4000000 ()
1809 {
1810 trace_input ("or3", OP_REG_OUTPUT, OP_REG, OP_CONSTANT16);
1811 State.regs[OP[0]] = State.regs[OP[1]] | OP[2];
1812 trace_output (OP_REG);
1813 }
1814
1815 /* rac */
1816 void
1817 OP_5201 ()
1818 {
1819 int64 tmp;
1820 int shift = SEXT3 (OP[2]);
1821
1822 trace_input ("rac", OP_DREG_OUTPUT, OP_ACCUM, OP_CONSTANT3);
1823 if (OP[1] != 0)
1824 {
1825 (*d10v_callback->printf_filtered) (d10v_callback,
1826 "ERROR at PC 0x%x: instruction only valid for A0\n",
1827 PC<<2);
1828 State.exception = SIGILL;
1829 }
1830
1831 State.F1 = State.F0;
1832 if (shift >=0)
1833 tmp = ((State.a[0] << 16) | (State.a[1] & 0xffff)) << shift;
1834 else
1835 tmp = ((State.a[0] << 16) | (State.a[1] & 0xffff)) >> -shift;
1836 tmp = ( SEXT60(tmp) + 0x8000 ) >> 16;
1837 if (tmp > MAX32)
1838 {
1839 State.regs[OP[0]] = 0x7fff;
1840 State.regs[OP[0]+1] = 0xffff;
1841 State.F0 = 1;
1842 }
1843 else if (tmp < MIN32)
1844 {
1845 State.regs[OP[0]] = 0x8000;
1846 State.regs[OP[0]+1] = 0;
1847 State.F0 = 1;
1848 }
1849 else
1850 {
1851 State.regs[OP[0]] = (tmp >> 16) & 0xffff;
1852 State.regs[OP[0]+1] = tmp & 0xffff;
1853 State.F0 = 0;
1854 }
1855 trace_output (OP_DREG);
1856 }
1857
1858 /* rachi */
1859 void
1860 OP_4201 ()
1861 {
1862 int64 tmp;
1863 int shift = SEXT3 (OP[2]);
1864
1865 trace_input ("rachi", OP_REG_OUTPUT, OP_ACCUM, OP_CONSTANT3);
1866 State.F1 = State.F0;
1867 if (shift >=0)
1868 tmp = SEXT44 (State.a[1]) << shift;
1869 else
1870 tmp = SEXT44 (State.a[1]) >> -shift;
1871 tmp += 0x8000;
1872
1873 if (tmp > MAX32)
1874 {
1875 State.regs[OP[0]] = 0x7fff;
1876 State.F0 = 1;
1877 }
1878 else if (tmp < 0xfff80000000LL)
1879 {
1880 State.regs[OP[0]] = 0x8000;
1881 State.F0 = 1;
1882 }
1883 else
1884 {
1885 State.regs[OP[0]] = (tmp >> 16) & 0xffff;
1886 State.F0 = 0;
1887 }
1888 trace_output (OP_REG);
1889 }
1890
1891 /* rep */
1892 void
1893 OP_27000000 ()
1894 {
1895 trace_input ("rep", OP_REG, OP_CONSTANT16, OP_VOID);
1896 RPT_S = PC + 1;
1897 RPT_E = PC + OP[1];
1898 RPT_C = State.regs[OP[0]];
1899 State.RP = 1;
1900 if (RPT_C == 0)
1901 {
1902 (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: rep with count=0 is illegal.\n");
1903 State.exception = SIGILL;
1904 }
1905 if (OP[1] < 4)
1906 {
1907 (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: rep must include at least 4 instructions.\n");
1908 State.exception = SIGILL;
1909 }
1910 trace_output (OP_VOID);
1911 }
1912
1913 /* repi */
1914 void
1915 OP_2F000000 ()
1916 {
1917 trace_input ("repi", OP_CONSTANT16, OP_CONSTANT16, OP_VOID);
1918 RPT_S = PC + 1;
1919 RPT_E = PC + OP[1];
1920 RPT_C = OP[0];
1921 State.RP = 1;
1922 if (RPT_C == 0)
1923 {
1924 (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: repi with count=0 is illegal.\n");
1925 State.exception = SIGILL;
1926 }
1927 if (OP[1] < 4)
1928 {
1929 (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: repi must include at least 4 instructions.\n");
1930 State.exception = SIGILL;
1931 }
1932 trace_output (OP_VOID);
1933 }
1934
1935 /* rtd */
1936 void
1937 OP_5F60 ()
1938 {
1939 d10v_callback->printf_filtered(d10v_callback, "ERROR: rtd - NOT IMPLEMENTED\n");
1940 State.exception = SIGILL;
1941 }
1942
1943 /* rte */
1944 void
1945 OP_5F40 ()
1946 {
1947 trace_input ("rte", OP_VOID, OP_VOID, OP_VOID);
1948 PC = BPC;
1949 PSW = BPSW;
1950 trace_output (OP_VOID);
1951 }
1952
1953 /* sadd */
1954 void
1955 OP_1223 ()
1956 {
1957 int64 tmp;
1958
1959 trace_input ("sadd", OP_ACCUM, OP_ACCUM, OP_VOID);
1960 tmp = SEXT40(State.a[OP[0]]) + (SEXT40(State.a[OP[1]]) >> 16);
1961 if (State.ST)
1962 {
1963 if (tmp > MAX32)
1964 State.a[OP[0]] = MAX32;
1965 else if (tmp < MIN32)
1966 State.a[OP[0]] = MIN32;
1967 else
1968 State.a[OP[0]] = tmp & MASK40;
1969 }
1970 else
1971 State.a[OP[0]] = tmp & MASK40;
1972 trace_output (OP_ACCUM);
1973 }
1974
1975 /* setf0f */
1976 void
1977 OP_4611 ()
1978 {
1979 trace_input ("setf0f", OP_REG_OUTPUT, OP_VOID, OP_VOID);
1980 State.regs[OP[0]] = (State.F0 == 0) ? 1 : 0;
1981 trace_output (OP_REG);
1982 }
1983
1984 /* setf0t */
1985 void
1986 OP_4613 ()
1987 {
1988 trace_input ("setf0t", OP_REG_OUTPUT, OP_VOID, OP_VOID);
1989 State.regs[OP[0]] = (State.F0 == 1) ? 1 : 0;
1990 trace_output (OP_REG);
1991 }
1992
1993 /* sleep */
1994 void
1995 OP_5FC0 ()
1996 {
1997 trace_input ("sleep", OP_VOID, OP_VOID, OP_VOID);
1998 State.IE = 1;
1999 trace_output (OP_VOID);
2000 }
2001
2002 /* sll */
2003 void
2004 OP_2200 ()
2005 {
2006 trace_input ("sll", OP_REG, OP_REG, OP_VOID);
2007 State.regs[OP[0]] <<= (State.regs[OP[1]] & 0xf);
2008 trace_output (OP_REG);
2009 }
2010
2011 /* sll */
2012 void
2013 OP_3200 ()
2014 {
2015 int64 tmp;
2016 trace_input ("sll", OP_ACCUM, OP_REG, OP_VOID);
2017 if ((State.regs[OP[1]] & 31) <= 16)
2018 tmp = SEXT40 (State.a[OP[0]]) << (State.regs[OP[1]] & 31);
2019 else
2020 {
2021 (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: shift value %d too large.\n", State.regs[OP[1]] & 31);
2022 State.exception = SIGILL;
2023 return;
2024 }
2025
2026 if (State.ST)
2027 {
2028 if (tmp > MAX32)
2029 State.a[OP[0]] = MAX32;
2030 else if (tmp < 0xffffff80000000LL)
2031 State.a[OP[0]] = MIN32;
2032 else
2033 State.a[OP[0]] = tmp & MASK40;
2034 }
2035 else
2036 State.a[OP[0]] = tmp & MASK40;
2037 trace_output (OP_ACCUM);
2038 }
2039
2040 /* slli */
2041 void
2042 OP_2201 ()
2043 {
2044 trace_input ("slli", OP_REG, OP_CONSTANT16, OP_VOID);
2045 State.regs[OP[0]] <<= OP[1];
2046 trace_output (OP_REG);
2047 }
2048
2049 /* slli */
2050 void
2051 OP_3201 ()
2052 {
2053 int64 tmp;
2054
2055 if (OP[1] == 0)
2056 OP[1] = 16;
2057
2058 trace_input ("slli", OP_ACCUM, OP_CONSTANT16, OP_VOID);
2059 tmp = SEXT40(State.a[OP[0]]) << OP[1];
2060
2061 if (State.ST)
2062 {
2063 if (tmp > MAX32)
2064 State.a[OP[0]] = MAX32;
2065 else if (tmp < 0xffffff80000000LL)
2066 State.a[OP[0]] = MIN32;
2067 else
2068 State.a[OP[0]] = tmp & MASK40;
2069 }
2070 else
2071 State.a[OP[0]] = tmp & MASK40;
2072 trace_output (OP_ACCUM);
2073 }
2074
2075 /* slx */
2076 void
2077 OP_460B ()
2078 {
2079 uint16 tmp;
2080
2081 trace_input ("slx", OP_REG, OP_FLAG, OP_VOID);
2082 State.regs[OP[0]] = (State.regs[OP[0]] << 1) | State.F0;
2083 trace_output (OP_REG);
2084 }
2085
2086 /* sra */
2087 void
2088 OP_2400 ()
2089 {
2090 trace_input ("sra", OP_REG, OP_REG, OP_VOID);
2091 State.regs[OP[0]] = ((int16)(State.regs[OP[0]])) >> (State.regs[OP[1]] & 0xf);
2092 trace_output (OP_REG);
2093 }
2094
2095 /* sra */
2096 void
2097 OP_3400 ()
2098 {
2099 trace_input ("sra", OP_ACCUM, OP_REG, OP_VOID);
2100 if ((State.regs[OP[1]] & 31) <= 16)
2101 State.a[OP[0]] >>= (State.regs[OP[1]] & 31);
2102 else
2103 {
2104 (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: shift value %d too large.\n", State.regs[OP[1]] & 31);
2105 State.exception = SIGILL;
2106 return;
2107 }
2108
2109 trace_output (OP_ACCUM);
2110 }
2111
2112 /* srai */
2113 void
2114 OP_2401 ()
2115 {
2116 trace_input ("srai", OP_REG, OP_CONSTANT16, OP_VOID);
2117 State.regs[OP[0]] = ((int16)(State.regs[OP[0]])) >> OP[1];
2118 trace_output (OP_REG);
2119 }
2120
2121 /* srai */
2122 void
2123 OP_3401 ()
2124 {
2125 if (OP[1] == 0)
2126 OP[1] = 16;
2127
2128 trace_input ("srai", OP_ACCUM, OP_CONSTANT16, OP_VOID);
2129 State.a[OP[0]] >>= OP[1];
2130 trace_output (OP_ACCUM);
2131 }
2132
2133 /* srl */
2134 void
2135 OP_2000 ()
2136 {
2137 trace_input ("srl", OP_REG, OP_REG, OP_VOID);
2138 State.regs[OP[0]] >>= (State.regs[OP[1]] & 0xf);
2139 trace_output (OP_REG);
2140 }
2141
2142 /* srl */
2143 void
2144 OP_3000 ()
2145 {
2146 trace_input ("srl", OP_ACCUM, OP_REG, OP_VOID);
2147 if ((State.regs[OP[1]] & 31) <= 16)
2148 State.a[OP[0]] >>= (State.regs[OP[1]] & 31);
2149 else
2150 {
2151 (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: shift value %d too large.\n", State.regs[OP[1]] & 31);
2152 State.exception = SIGILL;
2153 return;
2154 }
2155
2156 trace_output (OP_ACCUM);
2157 }
2158
2159 /* srli */
2160 void
2161 OP_2001 ()
2162 {
2163 trace_input ("srli", OP_REG, OP_CONSTANT16, OP_VOID);
2164 State.regs[OP[0]] >>= OP[1];
2165 trace_output (OP_REG);
2166 }
2167
2168 /* srli */
2169 void
2170 OP_3001 ()
2171 {
2172 if (OP[1] == 0)
2173 OP[1] = 16;
2174
2175 trace_input ("srli", OP_ACCUM, OP_CONSTANT16, OP_VOID);
2176 State.a[OP[0]] >>= OP[1];
2177 trace_output (OP_ACCUM);
2178 }
2179
2180 /* srx */
2181 void
2182 OP_4609 ()
2183 {
2184 uint16 tmp;
2185
2186 trace_input ("srx", OP_REG, OP_FLAG, OP_VOID);
2187 tmp = State.F0 << 15;
2188 State.regs[OP[0]] = (State.regs[OP[0]] >> 1) | tmp;
2189 trace_output (OP_REG);
2190 }
2191
2192 /* st */
2193 void
2194 OP_34000000 ()
2195 {
2196 trace_input ("st", OP_REG, OP_MEMREF2, OP_VOID);
2197 SW (OP[1] + State.regs[OP[2]], State.regs[OP[0]]);
2198 trace_output (OP_VOID);
2199 }
2200
2201 /* st */
2202 void
2203 OP_6800 ()
2204 {
2205 trace_input ("st", OP_REG, OP_MEMREF, OP_VOID);
2206 SW (State.regs[OP[1]], State.regs[OP[0]]);
2207 trace_output (OP_VOID);
2208 }
2209
2210 /* st */
2211 void
2212 OP_6C1F ()
2213 {
2214 trace_input ("st", OP_REG, OP_PREDEC, OP_VOID);
2215 if ( OP[1] != 15 )
2216 {
2217 (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: cannot pre-decrement any registers but r15 (SP).\n");
2218 State.exception = SIGILL;
2219 return;
2220 }
2221 State.regs[OP[1]] -= 2;
2222 SW (State.regs[OP[1]], State.regs[OP[0]]);
2223 trace_output (OP_VOID);
2224 }
2225
2226 /* st */
2227 void
2228 OP_6801 ()
2229 {
2230 trace_input ("st", OP_REG, OP_POSTINC, OP_VOID);
2231 SW (State.regs[OP[1]], State.regs[OP[0]]);
2232 INC_ADDR (State.regs[OP[1]],2);
2233 trace_output (OP_VOID);
2234 }
2235
2236 /* st */
2237 void
2238 OP_6C01 ()
2239 {
2240 trace_input ("st", OP_REG, OP_POSTDEC, OP_VOID);
2241 SW (State.regs[OP[1]], State.regs[OP[0]]);
2242 INC_ADDR (State.regs[OP[1]],-2);
2243 trace_output (OP_VOID);
2244 }
2245
2246 /* st2w */
2247 void
2248 OP_35000000 ()
2249 {
2250 trace_input ("st2w", OP_DREG, OP_MEMREF2, OP_VOID);
2251 SW (State.regs[OP[2]]+OP[1], State.regs[OP[0]]);
2252 SW (State.regs[OP[2]]+OP[1]+2, State.regs[OP[0]+1]);
2253 trace_output (OP_VOID);
2254 }
2255
2256 /* st2w */
2257 void
2258 OP_6A00 ()
2259 {
2260 trace_input ("st2w", OP_REG, OP_MEMREF, OP_VOID);
2261 SW (State.regs[OP[1]], State.regs[OP[0]]);
2262 SW (State.regs[OP[1]]+2, State.regs[OP[0]+1]);
2263 trace_output (OP_VOID);
2264 }
2265
2266 /* st2w */
2267 void
2268 OP_6E1F ()
2269 {
2270 trace_input ("st2w", OP_REG, OP_PREDEC, OP_VOID);
2271 if ( OP[1] != 15 )
2272 {
2273 (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: cannot pre-decrement any registers but r15 (SP).\n");
2274 State.exception = SIGILL;
2275 return;
2276 }
2277 State.regs[OP[1]] -= 4;
2278 SW (State.regs[OP[1]], State.regs[OP[0]]);
2279 SW (State.regs[OP[1]]+2, State.regs[OP[0]+1]);
2280 trace_output (OP_VOID);
2281 }
2282
2283 /* st2w */
2284 void
2285 OP_6A01 ()
2286 {
2287 trace_input ("st2w", OP_REG, OP_POSTDEC, OP_VOID);
2288 SW (State.regs[OP[1]], State.regs[OP[0]]);
2289 SW (State.regs[OP[1]]+2, State.regs[OP[0]+1]);
2290 INC_ADDR (State.regs[OP[1]],4);
2291 trace_output (OP_VOID);
2292 }
2293
2294 /* st2w */
2295 void
2296 OP_6E01 ()
2297 {
2298 trace_input ("st2w", OP_REG, OP_POSTINC, OP_VOID);
2299 SW (State.regs[OP[1]], State.regs[OP[0]]);
2300 SW (State.regs[OP[1]]+2, State.regs[OP[0]+1]);
2301 INC_ADDR (State.regs[OP[1]],-4);
2302 trace_output (OP_VOID);
2303 }
2304
2305 /* stb */
2306 void
2307 OP_3C000000 ()
2308 {
2309 trace_input ("stb", OP_REG, OP_MEMREF2, OP_VOID);
2310 SB (State.regs[OP[2]]+OP[1], State.regs[OP[0]]);
2311 trace_output (OP_VOID);
2312 }
2313
2314 /* stb */
2315 void
2316 OP_7800 ()
2317 {
2318 trace_input ("stb", OP_REG, OP_MEMREF, OP_VOID);
2319 SB (State.regs[OP[1]], State.regs[OP[0]]);
2320 trace_output (OP_VOID);
2321 }
2322
2323 /* stop */
2324 void
2325 OP_5FE0 ()
2326 {
2327 trace_input ("stop", OP_VOID, OP_VOID, OP_VOID);
2328 State.exception = SIG_D10V_STOP;
2329 trace_output (OP_VOID);
2330 }
2331
2332 /* sub */
2333 void
2334 OP_0 ()
2335 {
2336 int32 tmp;
2337
2338 trace_input ("sub", OP_REG, OP_REG, OP_VOID);
2339 tmp = (int16)State.regs[OP[0]]- (int16)State.regs[OP[1]];
2340 State.C = (tmp & 0xffff0000) ? 1 : 0;
2341 State.regs[OP[0]] = tmp & 0xffff;
2342 trace_output (OP_REG);
2343 }
2344
2345 /* sub */
2346 void
2347 OP_1001 ()
2348 {
2349 int64 tmp;
2350
2351 trace_input ("sub", OP_ACCUM, OP_DREG, OP_VOID);
2352 tmp = SEXT40(State.a[OP[0]]) - (SEXT16 (State.regs[OP[1]]) << 16 | State.regs[OP[1]+1]);
2353 if (State.ST)
2354 {
2355 if ( tmp > MAX32)
2356 State.a[OP[0]] = MAX32;
2357 else if ( tmp < MIN32)
2358 State.a[OP[0]] = MIN32;
2359 else
2360 State.a[OP[0]] = tmp & MASK40;
2361 }
2362 else
2363 State.a[OP[0]] = tmp & MASK40;
2364
2365 trace_output (OP_ACCUM);
2366 }
2367
2368 /* sub */
2369
2370 void
2371 OP_1003 ()
2372 {
2373 int64 tmp;
2374
2375 trace_input ("sub", OP_ACCUM, OP_ACCUM, OP_VOID);
2376 tmp = SEXT40(State.a[OP[0]]) - SEXT40(State.a[OP[1]]);
2377 if (State.ST)
2378 {
2379 if (tmp > MAX32)
2380 State.a[OP[0]] = MAX32;
2381 else if ( tmp < MIN32)
2382 State.a[OP[0]] = MIN32;
2383 else
2384 State.a[OP[0]] = tmp & MASK40;
2385 }
2386 else
2387 State.a[OP[0]] = tmp & MASK40;
2388
2389 trace_output (OP_ACCUM);
2390 }
2391
2392 /* sub2w */
2393 void
2394 OP_1000 ()
2395 {
2396 int64 tmp;
2397 int32 a,b;
2398
2399 trace_input ("sub2w", OP_DREG, OP_DREG, OP_VOID);
2400 a = (int32)((State.regs[OP[0]] << 16) | State.regs[OP[0]+1]);
2401 b = (int32)((State.regs[OP[1]] << 16) | State.regs[OP[1]+1]);
2402 tmp = a-b;
2403 State.C = (tmp & 0xffffffff00000000LL) ? 1 : 0;
2404 State.regs[OP[0]] = (tmp >> 16) & 0xffff;
2405 State.regs[OP[0]+1] = tmp & 0xffff;
2406 trace_output (OP_DREG);
2407 }
2408
2409 /* subac3 */
2410 void
2411 OP_17000000 ()
2412 {
2413 int64 tmp;
2414
2415 trace_input ("subac3", OP_DREG_OUTPUT, OP_DREG, OP_ACCUM);
2416 tmp = SEXT40 ((State.regs[OP[1]] << 16) | State.regs[OP[1]+1]) - SEXT40 (State.a[OP[2]]);
2417 State.regs[OP[0]] = (tmp >> 16) & 0xffff;
2418 State.regs[OP[0]+1] = tmp & 0xffff;
2419 trace_output (OP_DREG);
2420 }
2421
2422 /* subac3 */
2423 void
2424 OP_17000002 ()
2425 {
2426 int64 tmp;
2427
2428 trace_input ("subac3", OP_DREG_OUTPUT, OP_ACCUM, OP_ACCUM);
2429 tmp = SEXT40(State.a[OP[1]]) - SEXT40(State.a[OP[2]]);
2430 State.regs[OP[0]] = (tmp >> 16) & 0xffff;
2431 State.regs[OP[0]+1] = tmp & 0xffff;
2432 trace_output (OP_DREG);
2433 }
2434
2435 /* subac3s */
2436 void
2437 OP_17001000 ()
2438 {
2439 int64 tmp;
2440
2441 trace_input ("subac3s", OP_DREG_OUTPUT, OP_DREG, OP_ACCUM);
2442 State.F1 = State.F0;
2443 tmp = SEXT40 ((State.regs[OP[1]] << 16) | State.regs[OP[1]+1]) - SEXT40(State.a[OP[2]]);
2444 if ( tmp > MAX32)
2445 {
2446 State.regs[OP[0]] = 0x7fff;
2447 State.regs[OP[0]+1] = 0xffff;
2448 State.F0 = 1;
2449 }
2450 else if (tmp < MIN32)
2451 {
2452 State.regs[OP[0]] = 0x8000;
2453 State.regs[OP[0]+1] = 0;
2454 State.F0 = 1;
2455 }
2456 else
2457 {
2458 State.regs[OP[0]] = (tmp >> 16) & 0xffff;
2459 State.regs[OP[0]+1] = tmp & 0xffff;
2460 State.F0 = 0;
2461 }
2462 trace_output (OP_DREG);
2463 }
2464
2465 /* subac3s */
2466 void
2467 OP_17001002 ()
2468 {
2469 int64 tmp;
2470
2471 trace_input ("subac3s", OP_DREG_OUTPUT, OP_ACCUM, OP_ACCUM);
2472 State.F1 = State.F0;
2473 tmp = SEXT40(State.a[OP[1]]) - SEXT40(State.a[OP[2]]);
2474 if ( tmp > MAX32)
2475 {
2476 State.regs[OP[0]] = 0x7fff;
2477 State.regs[OP[0]+1] = 0xffff;
2478 State.F0 = 1;
2479 }
2480 else if (tmp < MIN32)
2481 {
2482 State.regs[OP[0]] = 0x8000;
2483 State.regs[OP[0]+1] = 0;
2484 State.F0 = 1;
2485 }
2486 else
2487 {
2488 State.regs[OP[0]] = (tmp >> 16) & 0xffff;
2489 State.regs[OP[0]+1] = tmp & 0xffff;
2490 State.F0 = 0;
2491 }
2492 trace_output (OP_DREG);
2493 }
2494
2495 /* subi */
2496 void
2497 OP_1 ()
2498 {
2499 int32 tmp;
2500 if (OP[1] == 0)
2501 OP[1] = 16;
2502
2503 trace_input ("subi", OP_REG, OP_CONSTANT16, OP_VOID);
2504 tmp = (int16)State.regs[OP[0]] - OP[1];
2505 State.C = (tmp & 0xffff0000) ? 1 : 0;
2506 State.regs[OP[0]] = tmp & 0xffff;
2507 trace_output (OP_REG);
2508 }
2509
2510 /* trap */
2511 void
2512 OP_5F00 ()
2513 {
2514 trace_input ("trap", OP_CONSTANT4, OP_VOID, OP_VOID);
2515 trace_output (OP_VOID);
2516
2517 switch (OP[0])
2518 {
2519 default:
2520 #if 0
2521 (*d10v_callback->printf_filtered) (d10v_callback, "Unknown trap code %d\n", OP[0]);
2522 State.exception = SIGILL;
2523 #else
2524 /* Use any other traps for batch debugging. */
2525 {
2526 int i;
2527 static int first_time = 1;
2528
2529 if (first_time)
2530 {
2531 first_time = 0;
2532 (*d10v_callback->printf_filtered) (d10v_callback, "Trap # PC ");
2533 for (i = 0; i < 16; i++)
2534 (*d10v_callback->printf_filtered) (d10v_callback, " %sr%d", (i > 9) ? "" : " ", i);
2535 (*d10v_callback->printf_filtered) (d10v_callback, " a0 a1 f0 f1 c\n");
2536 }
2537
2538 (*d10v_callback->printf_filtered) (d10v_callback, "Trap %2d 0x%.4x:", (int)OP[0], (int)PC);
2539
2540 for (i = 0; i < 16; i++)
2541 (*d10v_callback->printf_filtered) (d10v_callback, " %.4x", (int) State.regs[i]);
2542
2543 for (i = 0; i < 2; i++)
2544 (*d10v_callback->printf_filtered) (d10v_callback, " %.2x%.8lx",
2545 ((int)(State.a[OP[i]] >> 32) & 0xff),
2546 ((unsigned long)State.a[OP[i]]) & 0xffffffff);
2547
2548 (*d10v_callback->printf_filtered) (d10v_callback, " %d %d %d\n",
2549 State.F0 != 0, State.F1 != 0, State.C != 0);
2550 break;
2551 #endif
2552
2553 case 0:
2554 /* Trap 0 is used for simulating low-level I/O */
2555 {
2556 int save_errno = errno;
2557 errno = 0;
2558
2559 /* Registers passed to trap 0 */
2560
2561 #define FUNC State.regs[6] /* function number */
2562 #define PARM1 State.regs[2] /* optional parm 1 */
2563 #define PARM2 State.regs[3] /* optional parm 2 */
2564 #define PARM3 State.regs[4] /* optional parm 3 */
2565 #define PARM4 State.regs[5] /* optional parm 3 */
2566
2567 /* Registers set by trap 0 */
2568
2569 #define RETVAL State.regs[2] /* return value */
2570 #define RETVAL_HIGH State.regs[2] /* return value */
2571 #define RETVAL_LOW State.regs[3] /* return value */
2572 #define RETERR State.regs[4] /* return error code */
2573
2574 /* Turn a pointer in a register into a pointer into real memory. */
2575
2576 #define MEMPTR(x) ((char *)((x) + State.imem))
2577
2578 switch (FUNC)
2579 {
2580 #if !defined(__GO32__) && !defined(_WIN32)
2581 case SYS_fork:
2582 RETVAL = fork ();
2583 break;
2584 case SYS_execve:
2585 RETVAL = execve (MEMPTR (PARM1), (char **) MEMPTR (PARM2),
2586 (char **)MEMPTR (PARM3));
2587 break;
2588 case SYS_execv:
2589 RETVAL = execve (MEMPTR (PARM1), (char **) MEMPTR (PARM2), NULL);
2590 break;
2591 case SYS_pipe:
2592 {
2593 reg_t buf;
2594 int host_fd[2];
2595
2596 buf = PARM1;
2597 RETVAL = pipe (host_fd);
2598 SW (buf, host_fd[0]);
2599 buf += sizeof(uint16);
2600 SW (buf, host_fd[1]);
2601 }
2602 break;
2603 case SYS_wait:
2604 {
2605 int status;
2606
2607 RETVAL = wait (&status);
2608 SW (PARM1, status);
2609 }
2610 break;
2611 #endif
2612 case SYS_read:
2613 RETVAL = d10v_callback->read (d10v_callback, PARM1, MEMPTR (PARM2),
2614 PARM3);
2615 break;
2616 case SYS_write:
2617 if (PARM1 == 1)
2618 RETVAL = (int)d10v_callback->write_stdout (d10v_callback,
2619 MEMPTR (PARM2), PARM3);
2620 else
2621 RETVAL = (int)d10v_callback->write (d10v_callback, PARM1,
2622 MEMPTR (PARM2), PARM3);
2623 break;
2624 case SYS_lseek:
2625 {
2626 unsigned long ret = d10v_callback->lseek (d10v_callback, PARM1,
2627 (((unsigned long)PARM2) << 16) || (unsigned long)PARM3,
2628 PARM4);
2629 RETVAL_HIGH = ret >> 16;
2630 RETVAL_LOW = ret & 0xffff;
2631 }
2632 break;
2633 case SYS_close:
2634 RETVAL = d10v_callback->close (d10v_callback, PARM1);
2635 break;
2636 case SYS_open:
2637 RETVAL = d10v_callback->open (d10v_callback, MEMPTR (PARM1), PARM2);
2638 break;
2639 case SYS_exit:
2640 State.exception = SIG_D10V_EXIT;
2641 break;
2642
2643 case SYS_stat:
2644 /* stat system call */
2645 {
2646 struct stat host_stat;
2647 reg_t buf;
2648
2649 RETVAL = stat (MEMPTR (PARM1), &host_stat);
2650
2651 buf = PARM2;
2652
2653 /* The hard-coded offsets and sizes were determined by using
2654 * the D10V compiler on a test program that used struct stat.
2655 */
2656 SW (buf, host_stat.st_dev);
2657 SW (buf+2, host_stat.st_ino);
2658 SW (buf+4, host_stat.st_mode);
2659 SW (buf+6, host_stat.st_nlink);
2660 SW (buf+8, host_stat.st_uid);
2661 SW (buf+10, host_stat.st_gid);
2662 SW (buf+12, host_stat.st_rdev);
2663 SLW (buf+16, host_stat.st_size);
2664 SLW (buf+20, host_stat.st_atime);
2665 SLW (buf+28, host_stat.st_mtime);
2666 SLW (buf+36, host_stat.st_ctime);
2667 }
2668 break;
2669
2670 case SYS_chown:
2671 RETVAL = chown (MEMPTR (PARM1), PARM2, PARM3);
2672 break;
2673 case SYS_chmod:
2674 RETVAL = chmod (MEMPTR (PARM1), PARM2);
2675 break;
2676 case SYS_utime:
2677 /* Cast the second argument to void *, to avoid type mismatch
2678 if a prototype is present. */
2679 RETVAL = utime (MEMPTR (PARM1), (void *) MEMPTR (PARM2));
2680 break;
2681 default:
2682 abort ();
2683 }
2684 RETERR = d10v_callback->get_errno(d10v_callback);
2685 break;
2686 }
2687
2688 case 1:
2689 /* Trap 1 prints a string */
2690 {
2691 char *fstr = State.regs[2] + State.imem;
2692 fputs (fstr, stdout);
2693 break;
2694 }
2695
2696 case 2:
2697 /* Trap 2 calls printf */
2698 {
2699 char *fstr = State.regs[2] + State.imem;
2700 (*d10v_callback->printf_filtered) (d10v_callback, fstr,
2701 (int16)State.regs[3],
2702 (int16)State.regs[4],
2703 (int16)State.regs[5]);
2704 break;
2705 }
2706
2707 case 3:
2708 /* Trap 3 writes a character */
2709 putchar (State.regs[2]);
2710 break;
2711 }
2712 }
2713 }
2714
2715 /* tst0i */
2716 void
2717 OP_7000000 ()
2718 {
2719 trace_input ("tst0i", OP_REG, OP_CONSTANT16, OP_VOID);
2720 State.F1 = State.F0;
2721 State.F0 = (State.regs[OP[0]] & OP[1]) ? 1 : 0;
2722 trace_output (OP_FLAG);
2723 }
2724
2725 /* tst1i */
2726 void
2727 OP_F000000 ()
2728 {
2729 trace_input ("tst1i", OP_REG, OP_CONSTANT16, OP_VOID);
2730 State.F1 = State.F0;
2731 State.F0 = (~(State.regs[OP[0]]) & OP[1]) ? 1 : 0;
2732 trace_output (OP_FLAG);
2733 }
2734
2735 /* wait */
2736 void
2737 OP_5F80 ()
2738 {
2739 trace_input ("wait", OP_VOID, OP_VOID, OP_VOID);
2740 State.IE = 1;
2741 trace_output (OP_VOID);
2742 }
2743
2744 /* xor */
2745 void
2746 OP_A00 ()
2747 {
2748 trace_input ("xor", OP_REG, OP_REG, OP_VOID);
2749 State.regs[OP[0]] ^= State.regs[OP[1]];
2750 trace_output (OP_REG);
2751 }
2752
2753 /* xor3 */
2754 void
2755 OP_5000000 ()
2756 {
2757 trace_input ("xor3", OP_REG_OUTPUT, OP_REG, OP_CONSTANT16);
2758 State.regs[OP[0]] = State.regs[OP[1]] ^ OP[2];
2759 trace_output (OP_REG);
2760 }
2761
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