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[thirdparty/binutils-gdb.git] / sim / d10v / simops.c
1 #include "config.h"
2
3 #include <signal.h>
4 #include <errno.h>
5 #include <sys/types.h>
6 #include <sys/stat.h>
7 #ifdef HAVE_UNISTD_H
8 #include <unistd.h>
9 #endif
10 #ifdef HAVE_STRING_H
11 #include <string.h>
12 #endif
13
14 #include "d10v_sim.h"
15 #include "simops.h"
16 #include "targ-vals.h"
17
18 enum op_types {
19 OP_VOID,
20 OP_REG,
21 OP_REG_OUTPUT,
22 OP_DREG,
23 OP_DREG_OUTPUT,
24 OP_ACCUM,
25 OP_ACCUM_OUTPUT,
26 OP_ACCUM_REVERSE,
27 OP_CR,
28 OP_CR_OUTPUT,
29 OP_CR_REVERSE,
30 OP_FLAG,
31 OP_FLAG_OUTPUT,
32 OP_CONSTANT16,
33 OP_CONSTANT8,
34 OP_CONSTANT3,
35 OP_CONSTANT4,
36 OP_MEMREF,
37 OP_MEMREF2,
38 OP_MEMREF3,
39 OP_POSTDEC,
40 OP_POSTINC,
41 OP_PREDEC,
42 OP_R0,
43 OP_R1,
44 OP_R2,
45 };
46
47
48 enum {
49 PSW_MASK = (PSW_SM_BIT
50 | PSW_EA_BIT
51 | PSW_DB_BIT
52 | PSW_IE_BIT
53 | PSW_RP_BIT
54 | PSW_MD_BIT
55 | PSW_FX_BIT
56 | PSW_ST_BIT
57 | PSW_F0_BIT
58 | PSW_F1_BIT
59 | PSW_C_BIT),
60 /* The following bits in the PSW _can't_ be set by instructions such
61 as mvtc. */
62 PSW_HW_MASK = (PSW_MASK | PSW_DM_BIT)
63 };
64
65 reg_t
66 move_to_cr (int cr, reg_t mask, reg_t val, int psw_hw_p)
67 {
68 /* A MASK bit is set when the corresponding bit in the CR should
69 be left alone */
70 /* This assumes that (VAL & MASK) == 0 */
71 switch (cr)
72 {
73 case PSW_CR:
74 if (psw_hw_p)
75 val &= PSW_HW_MASK;
76 else
77 val &= PSW_MASK;
78 if ((mask & PSW_SM_BIT) == 0)
79 {
80 int new_psw_sm = (val & PSW_SM_BIT) != 0;
81 /* save old SP */
82 SET_HELD_SP (PSW_SM, GPR (SP_IDX));
83 if (PSW_SM != new_psw_sm)
84 /* restore new SP */
85 SET_GPR (SP_IDX, HELD_SP (new_psw_sm));
86 }
87 if ((mask & (PSW_ST_BIT | PSW_FX_BIT)) == 0)
88 {
89 if (val & PSW_ST_BIT && !(val & PSW_FX_BIT))
90 {
91 (*d10v_callback->printf_filtered)
92 (d10v_callback,
93 "ERROR at PC 0x%x: ST can only be set when FX is set.\n",
94 PC<<2);
95 State.exception = SIGILL;
96 }
97 }
98 /* keep an up-to-date psw around for tracing */
99 State.trace.psw = (State.trace.psw & mask) | val;
100 break;
101 case BPSW_CR:
102 case DPSW_CR:
103 /* Just like PSW, mask things like DM out. */
104 if (psw_hw_p)
105 val &= PSW_HW_MASK;
106 else
107 val &= PSW_MASK;
108 break;
109 case MOD_S_CR:
110 case MOD_E_CR:
111 val &= ~1;
112 break;
113 default:
114 break;
115 }
116 /* only issue an update if the register is being changed */
117 if ((State.cregs[cr] & ~mask) != val)
118 SLOT_PEND_MASK (State.cregs[cr], mask, val);
119 return val;
120 }
121
122 #ifdef DEBUG
123 static void trace_input_func (const char *name,
124 enum op_types in1,
125 enum op_types in2,
126 enum op_types in3);
127
128 #define trace_input(name, in1, in2, in3) do { if (d10v_debug) trace_input_func (name, in1, in2, in3); } while (0)
129
130 #ifndef SIZE_INSTRUCTION
131 #define SIZE_INSTRUCTION 8
132 #endif
133
134 #ifndef SIZE_OPERANDS
135 #define SIZE_OPERANDS 18
136 #endif
137
138 #ifndef SIZE_VALUES
139 #define SIZE_VALUES 13
140 #endif
141
142 #ifndef SIZE_LOCATION
143 #define SIZE_LOCATION 20
144 #endif
145
146 #ifndef SIZE_PC
147 #define SIZE_PC 6
148 #endif
149
150 #ifndef SIZE_LINE_NUMBER
151 #define SIZE_LINE_NUMBER 4
152 #endif
153
154 static void
155 trace_input_func (const char *name, enum op_types in1, enum op_types in2, enum op_types in3)
156 {
157 char *comma;
158 enum op_types in[3];
159 int i;
160 char buf[1024];
161 char *p;
162 long tmp;
163 char *type;
164 const char *filename;
165 const char *functionname;
166 unsigned int linenumber;
167 bfd_vma byte_pc;
168
169 if ((d10v_debug & DEBUG_TRACE) == 0)
170 return;
171
172 switch (State.ins_type)
173 {
174 default:
175 case INS_UNKNOWN: type = " ?"; break;
176 case INS_LEFT: type = " L"; break;
177 case INS_RIGHT: type = " R"; break;
178 case INS_LEFT_PARALLEL: type = "*L"; break;
179 case INS_RIGHT_PARALLEL: type = "*R"; break;
180 case INS_LEFT_COND_TEST: type = "?L"; break;
181 case INS_RIGHT_COND_TEST: type = "?R"; break;
182 case INS_LEFT_COND_EXE: type = "&L"; break;
183 case INS_RIGHT_COND_EXE: type = "&R"; break;
184 case INS_LONG: type = " B"; break;
185 }
186
187 if ((d10v_debug & DEBUG_LINE_NUMBER) == 0)
188 (*d10v_callback->printf_filtered) (d10v_callback,
189 "0x%.*x %s: %-*s ",
190 SIZE_PC, (unsigned)PC,
191 type,
192 SIZE_INSTRUCTION, name);
193
194 else
195 {
196 buf[0] = '\0';
197 byte_pc = decode_pc ();
198 if (text && byte_pc >= text_start && byte_pc < text_end)
199 {
200 filename = (const char *)0;
201 functionname = (const char *)0;
202 linenumber = 0;
203 if (bfd_find_nearest_line (prog_bfd, text, (struct bfd_symbol **)0, byte_pc - text_start,
204 &filename, &functionname, &linenumber))
205 {
206 p = buf;
207 if (linenumber)
208 {
209 sprintf (p, "#%-*d ", SIZE_LINE_NUMBER, linenumber);
210 p += strlen (p);
211 }
212 else
213 {
214 sprintf (p, "%-*s ", SIZE_LINE_NUMBER+1, "---");
215 p += SIZE_LINE_NUMBER+2;
216 }
217
218 if (functionname)
219 {
220 sprintf (p, "%s ", functionname);
221 p += strlen (p);
222 }
223 else if (filename)
224 {
225 char *q = strrchr (filename, '/');
226 sprintf (p, "%s ", (q) ? q+1 : filename);
227 p += strlen (p);
228 }
229
230 if (*p == ' ')
231 *p = '\0';
232 }
233 }
234
235 (*d10v_callback->printf_filtered) (d10v_callback,
236 "0x%.*x %s: %-*.*s %-*s ",
237 SIZE_PC, (unsigned)PC,
238 type,
239 SIZE_LOCATION, SIZE_LOCATION, buf,
240 SIZE_INSTRUCTION, name);
241 }
242
243 in[0] = in1;
244 in[1] = in2;
245 in[2] = in3;
246 comma = "";
247 p = buf;
248 for (i = 0; i < 3; i++)
249 {
250 switch (in[i])
251 {
252 case OP_VOID:
253 case OP_R0:
254 case OP_R1:
255 case OP_R2:
256 break;
257
258 case OP_REG:
259 case OP_REG_OUTPUT:
260 case OP_DREG:
261 case OP_DREG_OUTPUT:
262 sprintf (p, "%sr%d", comma, OP[i]);
263 p += strlen (p);
264 comma = ",";
265 break;
266
267 case OP_CR:
268 case OP_CR_OUTPUT:
269 case OP_CR_REVERSE:
270 sprintf (p, "%scr%d", comma, OP[i]);
271 p += strlen (p);
272 comma = ",";
273 break;
274
275 case OP_ACCUM:
276 case OP_ACCUM_OUTPUT:
277 case OP_ACCUM_REVERSE:
278 sprintf (p, "%sa%d", comma, OP[i]);
279 p += strlen (p);
280 comma = ",";
281 break;
282
283 case OP_CONSTANT16:
284 sprintf (p, "%s%d", comma, OP[i]);
285 p += strlen (p);
286 comma = ",";
287 break;
288
289 case OP_CONSTANT8:
290 sprintf (p, "%s%d", comma, SEXT8(OP[i]));
291 p += strlen (p);
292 comma = ",";
293 break;
294
295 case OP_CONSTANT4:
296 sprintf (p, "%s%d", comma, SEXT4(OP[i]));
297 p += strlen (p);
298 comma = ",";
299 break;
300
301 case OP_CONSTANT3:
302 sprintf (p, "%s%d", comma, SEXT3(OP[i]));
303 p += strlen (p);
304 comma = ",";
305 break;
306
307 case OP_MEMREF:
308 sprintf (p, "%s@r%d", comma, OP[i]);
309 p += strlen (p);
310 comma = ",";
311 break;
312
313 case OP_MEMREF2:
314 sprintf (p, "%s@(%d,r%d)", comma, (int16)OP[i], OP[i+1]);
315 p += strlen (p);
316 comma = ",";
317 break;
318
319 case OP_MEMREF3:
320 sprintf (p, "%s@%d", comma, OP[i]);
321 p += strlen (p);
322 comma = ",";
323 break;
324
325 case OP_POSTINC:
326 sprintf (p, "%s@r%d+", comma, OP[i]);
327 p += strlen (p);
328 comma = ",";
329 break;
330
331 case OP_POSTDEC:
332 sprintf (p, "%s@r%d-", comma, OP[i]);
333 p += strlen (p);
334 comma = ",";
335 break;
336
337 case OP_PREDEC:
338 sprintf (p, "%s@-r%d", comma, OP[i]);
339 p += strlen (p);
340 comma = ",";
341 break;
342
343 case OP_FLAG:
344 case OP_FLAG_OUTPUT:
345 if (OP[i] == 0)
346 sprintf (p, "%sf0", comma);
347
348 else if (OP[i] == 1)
349 sprintf (p, "%sf1", comma);
350
351 else
352 sprintf (p, "%sc", comma);
353
354 p += strlen (p);
355 comma = ",";
356 break;
357 }
358 }
359
360 if ((d10v_debug & DEBUG_VALUES) == 0)
361 {
362 *p++ = '\n';
363 *p = '\0';
364 (*d10v_callback->printf_filtered) (d10v_callback, "%s", buf);
365 }
366 else
367 {
368 *p = '\0';
369 (*d10v_callback->printf_filtered) (d10v_callback, "%-*s", SIZE_OPERANDS, buf);
370
371 p = buf;
372 for (i = 0; i < 3; i++)
373 {
374 buf[0] = '\0';
375 switch (in[i])
376 {
377 case OP_VOID:
378 (*d10v_callback->printf_filtered) (d10v_callback, "%*s", SIZE_VALUES, "");
379 break;
380
381 case OP_REG_OUTPUT:
382 case OP_DREG_OUTPUT:
383 case OP_CR_OUTPUT:
384 case OP_ACCUM_OUTPUT:
385 case OP_FLAG_OUTPUT:
386 (*d10v_callback->printf_filtered) (d10v_callback, "%*s", SIZE_VALUES, "---");
387 break;
388
389 case OP_REG:
390 case OP_MEMREF:
391 case OP_POSTDEC:
392 case OP_POSTINC:
393 case OP_PREDEC:
394 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
395 (uint16) GPR (OP[i]));
396 break;
397
398 case OP_MEMREF3:
399 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "", (uint16) OP[i]);
400 break;
401
402 case OP_DREG:
403 tmp = (long)((((uint32) GPR (OP[i])) << 16) | ((uint32) GPR (OP[i] + 1)));
404 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.8lx", SIZE_VALUES-10, "", tmp);
405 break;
406
407 case OP_CR:
408 case OP_CR_REVERSE:
409 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
410 (uint16) CREG (OP[i]));
411 break;
412
413 case OP_ACCUM:
414 case OP_ACCUM_REVERSE:
415 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.2x%.8lx", SIZE_VALUES-12, "",
416 ((int)(ACC (OP[i]) >> 32) & 0xff),
417 ((unsigned long) ACC (OP[i])) & 0xffffffff);
418 break;
419
420 case OP_CONSTANT16:
421 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
422 (uint16)OP[i]);
423 break;
424
425 case OP_CONSTANT4:
426 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
427 (uint16)SEXT4(OP[i]));
428 break;
429
430 case OP_CONSTANT8:
431 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
432 (uint16)SEXT8(OP[i]));
433 break;
434
435 case OP_CONSTANT3:
436 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
437 (uint16)SEXT3(OP[i]));
438 break;
439
440 case OP_FLAG:
441 if (OP[i] == 0)
442 (*d10v_callback->printf_filtered) (d10v_callback, "%*sF0 = %d", SIZE_VALUES-6, "",
443 PSW_F0 != 0);
444
445 else if (OP[i] == 1)
446 (*d10v_callback->printf_filtered) (d10v_callback, "%*sF1 = %d", SIZE_VALUES-6, "",
447 PSW_F1 != 0);
448
449 else
450 (*d10v_callback->printf_filtered) (d10v_callback, "%*sC = %d", SIZE_VALUES-5, "",
451 PSW_C != 0);
452
453 break;
454
455 case OP_MEMREF2:
456 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
457 (uint16)OP[i]);
458 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
459 (uint16)GPR (OP[i + 1]));
460 i++;
461 break;
462
463 case OP_R0:
464 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
465 (uint16) GPR (0));
466 break;
467
468 case OP_R1:
469 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
470 (uint16) GPR (1));
471 break;
472
473 case OP_R2:
474 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
475 (uint16) GPR (2));
476 break;
477
478 }
479 }
480 }
481
482 (*d10v_callback->flush_stdout) (d10v_callback);
483 }
484
485 static void
486 do_trace_output_flush (void)
487 {
488 (*d10v_callback->flush_stdout) (d10v_callback);
489 }
490
491 static void
492 do_trace_output_finish (void)
493 {
494 (*d10v_callback->printf_filtered) (d10v_callback,
495 " F0=%d F1=%d C=%d\n",
496 (State.trace.psw & PSW_F0_BIT) != 0,
497 (State.trace.psw & PSW_F1_BIT) != 0,
498 (State.trace.psw & PSW_C_BIT) != 0);
499 (*d10v_callback->flush_stdout) (d10v_callback);
500 }
501
502 static void
503 trace_output_40 (uint64 val)
504 {
505 if ((d10v_debug & (DEBUG_TRACE | DEBUG_VALUES)) == (DEBUG_TRACE | DEBUG_VALUES))
506 {
507 (*d10v_callback->printf_filtered) (d10v_callback,
508 " :: %*s0x%.2x%.8lx",
509 SIZE_VALUES - 12,
510 "",
511 ((int)(val >> 32) & 0xff),
512 ((unsigned long) val) & 0xffffffff);
513 do_trace_output_finish ();
514 }
515 }
516
517 static void
518 trace_output_32 (uint32 val)
519 {
520 if ((d10v_debug & (DEBUG_TRACE | DEBUG_VALUES)) == (DEBUG_TRACE | DEBUG_VALUES))
521 {
522 (*d10v_callback->printf_filtered) (d10v_callback,
523 " :: %*s0x%.8x",
524 SIZE_VALUES - 10,
525 "",
526 (int) val);
527 do_trace_output_finish ();
528 }
529 }
530
531 static void
532 trace_output_16 (uint16 val)
533 {
534 if ((d10v_debug & (DEBUG_TRACE | DEBUG_VALUES)) == (DEBUG_TRACE | DEBUG_VALUES))
535 {
536 (*d10v_callback->printf_filtered) (d10v_callback,
537 " :: %*s0x%.4x",
538 SIZE_VALUES - 6,
539 "",
540 (int) val);
541 do_trace_output_finish ();
542 }
543 }
544
545 static void
546 trace_output_void (void)
547 {
548 if ((d10v_debug & (DEBUG_TRACE | DEBUG_VALUES)) == (DEBUG_TRACE | DEBUG_VALUES))
549 {
550 (*d10v_callback->printf_filtered) (d10v_callback, "\n");
551 do_trace_output_flush ();
552 }
553 }
554
555 static void
556 trace_output_flag (void)
557 {
558 if ((d10v_debug & (DEBUG_TRACE | DEBUG_VALUES)) == (DEBUG_TRACE | DEBUG_VALUES))
559 {
560 (*d10v_callback->printf_filtered) (d10v_callback,
561 " :: %*s",
562 SIZE_VALUES,
563 "");
564 do_trace_output_finish ();
565 }
566 }
567
568
569
570
571 #else
572 #define trace_input(NAME, IN1, IN2, IN3)
573 #define trace_output(RESULT)
574 #endif
575
576 /* abs */
577 void
578 OP_4607 (void)
579 {
580 int16 tmp;
581 trace_input ("abs", OP_REG, OP_VOID, OP_VOID);
582 SET_PSW_F1 (PSW_F0);
583 tmp = GPR(OP[0]);
584 if (tmp < 0)
585 {
586 tmp = - tmp;
587 SET_PSW_F0 (1);
588 }
589 else
590 SET_PSW_F0 (0);
591 SET_GPR (OP[0], tmp);
592 trace_output_16 (tmp);
593 }
594
595 /* abs */
596 void
597 OP_5607 (void)
598 {
599 int64 tmp;
600 trace_input ("abs", OP_ACCUM, OP_VOID, OP_VOID);
601 SET_PSW_F1 (PSW_F0);
602
603 tmp = SEXT40 (ACC (OP[0]));
604 if (tmp < 0 )
605 {
606 tmp = - tmp;
607 if (PSW_ST)
608 {
609 if (tmp > SEXT40(MAX32))
610 tmp = (MAX32);
611 else if (tmp < SEXT40(MIN32))
612 tmp = (MIN32);
613 else
614 tmp = (tmp & MASK40);
615 }
616 else
617 tmp = (tmp & MASK40);
618 SET_PSW_F0 (1);
619 }
620 else
621 {
622 tmp = (tmp & MASK40);
623 SET_PSW_F0 (0);
624 }
625 SET_ACC (OP[0], tmp);
626 trace_output_40 (tmp);
627 }
628
629 /* add */
630 void
631 OP_200 (void)
632 {
633 uint16 a = GPR (OP[0]);
634 uint16 b = GPR (OP[1]);
635 uint16 tmp = (a + b);
636 trace_input ("add", OP_REG, OP_REG, OP_VOID);
637 SET_PSW_C (a > tmp);
638 SET_GPR (OP[0], tmp);
639 trace_output_16 (tmp);
640 }
641
642 /* add */
643 void
644 OP_1201 (void)
645 {
646 int64 tmp;
647 tmp = SEXT40(ACC (OP[0])) + (SEXT16 (GPR (OP[1])) << 16 | GPR (OP[1] + 1));
648
649 trace_input ("add", OP_ACCUM, OP_REG, OP_VOID);
650 if (PSW_ST)
651 {
652 if (tmp > SEXT40(MAX32))
653 tmp = (MAX32);
654 else if (tmp < SEXT40(MIN32))
655 tmp = (MIN32);
656 else
657 tmp = (tmp & MASK40);
658 }
659 else
660 tmp = (tmp & MASK40);
661 SET_ACC (OP[0], tmp);
662 trace_output_40 (tmp);
663 }
664
665 /* add */
666 void
667 OP_1203 (void)
668 {
669 int64 tmp;
670 tmp = SEXT40(ACC (OP[0])) + SEXT40(ACC (OP[1]));
671
672 trace_input ("add", OP_ACCUM, OP_ACCUM, OP_VOID);
673 if (PSW_ST)
674 {
675 if (tmp > SEXT40(MAX32))
676 tmp = (MAX32);
677 else if (tmp < SEXT40(MIN32))
678 tmp = (MIN32);
679 else
680 tmp = (tmp & MASK40);
681 }
682 else
683 tmp = (tmp & MASK40);
684 SET_ACC (OP[0], tmp);
685 trace_output_40 (tmp);
686 }
687
688 /* add2w */
689 void
690 OP_1200 (void)
691 {
692 uint32 tmp;
693 uint32 a = (GPR (OP[0])) << 16 | GPR (OP[0] + 1);
694 uint32 b = (GPR (OP[1])) << 16 | GPR (OP[1] + 1);
695 trace_input ("add2w", OP_DREG, OP_DREG, OP_VOID);
696 tmp = a + b;
697 SET_PSW_C (tmp < a);
698 SET_GPR (OP[0] + 0, (tmp >> 16));
699 SET_GPR (OP[0] + 1, (tmp & 0xFFFF));
700 trace_output_32 (tmp);
701 }
702
703 /* add3 */
704 void
705 OP_1000000 (void)
706 {
707 uint16 a = GPR (OP[1]);
708 uint16 b = OP[2];
709 uint16 tmp = (a + b);
710 trace_input ("add3", OP_REG_OUTPUT, OP_REG, OP_CONSTANT16);
711 SET_PSW_C (tmp < a);
712 SET_GPR (OP[0], tmp);
713 trace_output_16 (tmp);
714 }
715
716 /* addac3 */
717 void
718 OP_17000200 (void)
719 {
720 int64 tmp;
721 tmp = SEXT40(ACC (OP[2])) + SEXT40 ((GPR (OP[1]) << 16) | GPR (OP[1] + 1));
722
723 trace_input ("addac3", OP_DREG_OUTPUT, OP_DREG, OP_ACCUM);
724 SET_GPR (OP[0] + 0, ((tmp >> 16) & 0xffff));
725 SET_GPR (OP[0] + 1, (tmp & 0xffff));
726 trace_output_32 (tmp);
727 }
728
729 /* addac3 */
730 void
731 OP_17000202 (void)
732 {
733 int64 tmp;
734 tmp = SEXT40(ACC (OP[1])) + SEXT40(ACC (OP[2]));
735
736 trace_input ("addac3", OP_DREG_OUTPUT, OP_ACCUM, OP_ACCUM);
737 SET_GPR (OP[0] + 0, (tmp >> 16) & 0xffff);
738 SET_GPR (OP[0] + 1, tmp & 0xffff);
739 trace_output_32 (tmp);
740 }
741
742 /* addac3s */
743 void
744 OP_17001200 (void)
745 {
746 int64 tmp;
747 SET_PSW_F1 (PSW_F0);
748
749 trace_input ("addac3s", OP_DREG_OUTPUT, OP_DREG, OP_ACCUM);
750 tmp = SEXT40 (ACC (OP[2])) + SEXT40 ((GPR (OP[1]) << 16) | GPR (OP[1] + 1));
751 if (tmp > SEXT40(MAX32))
752 {
753 tmp = (MAX32);
754 SET_PSW_F0 (1);
755 }
756 else if (tmp < SEXT40(MIN32))
757 {
758 tmp = (MIN32);
759 SET_PSW_F0 (1);
760 }
761 else
762 {
763 SET_PSW_F0 (0);
764 }
765 SET_GPR (OP[0] + 0, (tmp >> 16) & 0xffff);
766 SET_GPR (OP[0] + 1, (tmp & 0xffff));
767 trace_output_32 (tmp);
768 }
769
770 /* addac3s */
771 void
772 OP_17001202 (void)
773 {
774 int64 tmp;
775 SET_PSW_F1 (PSW_F0);
776
777 trace_input ("addac3s", OP_DREG_OUTPUT, OP_ACCUM, OP_ACCUM);
778 tmp = SEXT40(ACC (OP[1])) + SEXT40(ACC (OP[2]));
779 if (tmp > SEXT40(MAX32))
780 {
781 tmp = (MAX32);
782 SET_PSW_F0 (1);
783 }
784 else if (tmp < SEXT40(MIN32))
785 {
786 tmp = (MIN32);
787 SET_PSW_F0 (1);
788 }
789 else
790 {
791 SET_PSW_F0 (0);
792 }
793 SET_GPR (OP[0] + 0, (tmp >> 16) & 0xffff);
794 SET_GPR (OP[0] + 1, (tmp & 0xffff));
795 trace_output_32 (tmp);
796 }
797
798 /* addi */
799 void
800 OP_201 (void)
801 {
802 uint16 a = GPR (OP[0]);
803 uint16 b;
804 uint16 tmp;
805 if (OP[1] == 0)
806 OP[1] = 16;
807 b = OP[1];
808 tmp = (a + b);
809 trace_input ("addi", OP_REG, OP_CONSTANT16, OP_VOID);
810 SET_PSW_C (tmp < a);
811 SET_GPR (OP[0], tmp);
812 trace_output_16 (tmp);
813 }
814
815 /* and */
816 void
817 OP_C00 (void)
818 {
819 uint16 tmp = GPR (OP[0]) & GPR (OP[1]);
820 trace_input ("and", OP_REG, OP_REG, OP_VOID);
821 SET_GPR (OP[0], tmp);
822 trace_output_16 (tmp);
823 }
824
825 /* and3 */
826 void
827 OP_6000000 (void)
828 {
829 uint16 tmp = GPR (OP[1]) & OP[2];
830 trace_input ("and3", OP_REG_OUTPUT, OP_REG, OP_CONSTANT16);
831 SET_GPR (OP[0], tmp);
832 trace_output_16 (tmp);
833 }
834
835 /* bclri */
836 void
837 OP_C01 (void)
838 {
839 int16 tmp;
840 trace_input ("bclri", OP_REG, OP_CONSTANT16, OP_VOID);
841 tmp = (GPR (OP[0]) &~(0x8000 >> OP[1]));
842 SET_GPR (OP[0], tmp);
843 trace_output_16 (tmp);
844 }
845
846 /* bl.s */
847 void
848 OP_4900 (void)
849 {
850 trace_input ("bl.s", OP_CONSTANT8, OP_R0, OP_R1);
851 SET_GPR (13, PC + 1);
852 JMP( PC + SEXT8 (OP[0]));
853 trace_output_void ();
854 }
855
856 /* bl.l */
857 void
858 OP_24800000 (void)
859 {
860 trace_input ("bl.l", OP_CONSTANT16, OP_R0, OP_R1);
861 SET_GPR (13, (PC + 1));
862 JMP (PC + OP[0]);
863 trace_output_void ();
864 }
865
866 /* bnoti */
867 void
868 OP_A01 (void)
869 {
870 int16 tmp;
871 trace_input ("bnoti", OP_REG, OP_CONSTANT16, OP_VOID);
872 tmp = (GPR (OP[0]) ^ (0x8000 >> OP[1]));
873 SET_GPR (OP[0], tmp);
874 trace_output_16 (tmp);
875 }
876
877 /* bra.s */
878 void
879 OP_4800 (void)
880 {
881 trace_input ("bra.s", OP_CONSTANT8, OP_VOID, OP_VOID);
882 JMP (PC + SEXT8 (OP[0]));
883 trace_output_void ();
884 }
885
886 /* bra.l */
887 void
888 OP_24000000 (void)
889 {
890 trace_input ("bra.l", OP_CONSTANT16, OP_VOID, OP_VOID);
891 JMP (PC + OP[0]);
892 trace_output_void ();
893 }
894
895 /* brf0f.s */
896 void
897 OP_4A00 (void)
898 {
899 trace_input ("brf0f.s", OP_CONSTANT8, OP_VOID, OP_VOID);
900 if (!PSW_F0)
901 JMP (PC + SEXT8 (OP[0]));
902 trace_output_flag ();
903 }
904
905 /* brf0f.l */
906 void
907 OP_25000000 (void)
908 {
909 trace_input ("brf0f.l", OP_CONSTANT16, OP_VOID, OP_VOID);
910 if (!PSW_F0)
911 JMP (PC + OP[0]);
912 trace_output_flag ();
913 }
914
915 /* brf0t.s */
916 void
917 OP_4B00 (void)
918 {
919 trace_input ("brf0t.s", OP_CONSTANT8, OP_VOID, OP_VOID);
920 if (PSW_F0)
921 JMP (PC + SEXT8 (OP[0]));
922 trace_output_flag ();
923 }
924
925 /* brf0t.l */
926 void
927 OP_25800000 (void)
928 {
929 trace_input ("brf0t.l", OP_CONSTANT16, OP_VOID, OP_VOID);
930 if (PSW_F0)
931 JMP (PC + OP[0]);
932 trace_output_flag ();
933 }
934
935 /* bseti */
936 void
937 OP_801 (void)
938 {
939 int16 tmp;
940 trace_input ("bseti", OP_REG, OP_CONSTANT16, OP_VOID);
941 tmp = (GPR (OP[0]) | (0x8000 >> OP[1]));
942 SET_GPR (OP[0], tmp);
943 trace_output_16 (tmp);
944 }
945
946 /* btsti */
947 void
948 OP_E01 (void)
949 {
950 trace_input ("btsti", OP_REG, OP_CONSTANT16, OP_VOID);
951 SET_PSW_F1 (PSW_F0);
952 SET_PSW_F0 ((GPR (OP[0]) & (0x8000 >> OP[1])) ? 1 : 0);
953 trace_output_flag ();
954 }
955
956 /* clrac */
957 void
958 OP_5601 (void)
959 {
960 trace_input ("clrac", OP_ACCUM_OUTPUT, OP_VOID, OP_VOID);
961 SET_ACC (OP[0], 0);
962 trace_output_40 (0);
963 }
964
965 /* cmp */
966 void
967 OP_600 (void)
968 {
969 trace_input ("cmp", OP_REG, OP_REG, OP_VOID);
970 SET_PSW_F1 (PSW_F0);
971 SET_PSW_F0 (((int16)(GPR (OP[0])) < (int16)(GPR (OP[1]))) ? 1 : 0);
972 trace_output_flag ();
973 }
974
975 /* cmp */
976 void
977 OP_1603 (void)
978 {
979 trace_input ("cmp", OP_ACCUM, OP_ACCUM, OP_VOID);
980 SET_PSW_F1 (PSW_F0);
981 SET_PSW_F0 ((SEXT40(ACC (OP[0])) < SEXT40(ACC (OP[1]))) ? 1 : 0);
982 trace_output_flag ();
983 }
984
985 /* cmpeq */
986 void
987 OP_400 (void)
988 {
989 trace_input ("cmpeq", OP_REG, OP_REG, OP_VOID);
990 SET_PSW_F1 (PSW_F0);
991 SET_PSW_F0 ((GPR (OP[0]) == GPR (OP[1])) ? 1 : 0);
992 trace_output_flag ();
993 }
994
995 /* cmpeq */
996 void
997 OP_1403 (void)
998 {
999 trace_input ("cmpeq", OP_ACCUM, OP_ACCUM, OP_VOID);
1000 SET_PSW_F1 (PSW_F0);
1001 SET_PSW_F0 (((ACC (OP[0]) & MASK40) == (ACC (OP[1]) & MASK40)) ? 1 : 0);
1002 trace_output_flag ();
1003 }
1004
1005 /* cmpeqi.s */
1006 void
1007 OP_401 (void)
1008 {
1009 trace_input ("cmpeqi.s", OP_REG, OP_CONSTANT4, OP_VOID);
1010 SET_PSW_F1 (PSW_F0);
1011 SET_PSW_F0 ((GPR (OP[0]) == (reg_t) SEXT4 (OP[1])) ? 1 : 0);
1012 trace_output_flag ();
1013 }
1014
1015 /* cmpeqi.l */
1016 void
1017 OP_2000000 (void)
1018 {
1019 trace_input ("cmpeqi.l", OP_REG, OP_CONSTANT16, OP_VOID);
1020 SET_PSW_F1 (PSW_F0);
1021 SET_PSW_F0 ((GPR (OP[0]) == (reg_t)OP[1]) ? 1 : 0);
1022 trace_output_flag ();
1023 }
1024
1025 /* cmpi.s */
1026 void
1027 OP_601 (void)
1028 {
1029 trace_input ("cmpi.s", OP_REG, OP_CONSTANT4, OP_VOID);
1030 SET_PSW_F1 (PSW_F0);
1031 SET_PSW_F0 (((int16)(GPR (OP[0])) < (int16)SEXT4(OP[1])) ? 1 : 0);
1032 trace_output_flag ();
1033 }
1034
1035 /* cmpi.l */
1036 void
1037 OP_3000000 (void)
1038 {
1039 trace_input ("cmpi.l", OP_REG, OP_CONSTANT16, OP_VOID);
1040 SET_PSW_F1 (PSW_F0);
1041 SET_PSW_F0 (((int16)(GPR (OP[0])) < (int16)(OP[1])) ? 1 : 0);
1042 trace_output_flag ();
1043 }
1044
1045 /* cmpu */
1046 void
1047 OP_4600 (void)
1048 {
1049 trace_input ("cmpu", OP_REG, OP_REG, OP_VOID);
1050 SET_PSW_F1 (PSW_F0);
1051 SET_PSW_F0 ((GPR (OP[0]) < GPR (OP[1])) ? 1 : 0);
1052 trace_output_flag ();
1053 }
1054
1055 /* cmpui */
1056 void
1057 OP_23000000 (void)
1058 {
1059 trace_input ("cmpui", OP_REG, OP_CONSTANT16, OP_VOID);
1060 SET_PSW_F1 (PSW_F0);
1061 SET_PSW_F0 ((GPR (OP[0]) < (reg_t)OP[1]) ? 1 : 0);
1062 trace_output_flag ();
1063 }
1064
1065 /* cpfg */
1066 void
1067 OP_4E09 (void)
1068 {
1069 uint8 val;
1070
1071 trace_input ("cpfg", OP_FLAG_OUTPUT, OP_FLAG, OP_VOID);
1072
1073 if (OP[1] == 0)
1074 val = PSW_F0;
1075 else if (OP[1] == 1)
1076 val = PSW_F1;
1077 else
1078 val = PSW_C;
1079 if (OP[0] == 0)
1080 SET_PSW_F0 (val);
1081 else
1082 SET_PSW_F1 (val);
1083
1084 trace_output_flag ();
1085 }
1086
1087 /* cpfg */
1088 void
1089 OP_4E0F (void)
1090 {
1091 uint8 val;
1092
1093 trace_input ("cpfg", OP_FLAG_OUTPUT, OP_FLAG, OP_VOID);
1094
1095 if (OP[1] == 0)
1096 val = PSW_F0;
1097 else if (OP[1] == 1)
1098 val = PSW_F1;
1099 else
1100 val = PSW_C;
1101 if (OP[0] == 0)
1102 SET_PSW_F0 (val);
1103 else
1104 SET_PSW_F1 (val);
1105
1106 trace_output_flag ();
1107 }
1108
1109 /* dbt */
1110 void
1111 OP_5F20 (void)
1112 {
1113 /* d10v_callback->printf_filtered(d10v_callback, "***** DBT ***** PC=%x\n",PC); */
1114
1115 /* GDB uses the instruction pair ``dbt || nop'' as a break-point.
1116 The conditional below is for either of the instruction pairs
1117 ``dbt -> XXX'' or ``dbt <- XXX'' and treats them as as cases
1118 where the dbt instruction should be interpreted.
1119
1120 The module `sim-break' provides a more effective mechanism for
1121 detecting GDB planted breakpoints. The code below may,
1122 eventually, be changed to use that mechanism. */
1123
1124 if (State.ins_type == INS_LEFT
1125 || State.ins_type == INS_RIGHT)
1126 {
1127 trace_input ("dbt", OP_VOID, OP_VOID, OP_VOID);
1128 SET_DPC (PC + 1);
1129 SET_DPSW (PSW);
1130 SET_HW_PSW (PSW_DM_BIT | (PSW & (PSW_F0_BIT | PSW_F1_BIT | PSW_C_BIT)));
1131 JMP (DBT_VECTOR_START);
1132 trace_output_void ();
1133 }
1134 else
1135 {
1136 State.exception = SIGTRAP;
1137 }
1138 }
1139
1140 /* divs */
1141 void
1142 OP_14002800 (void)
1143 {
1144 uint16 foo, tmp, tmpf;
1145 uint16 hi;
1146 uint16 lo;
1147
1148 trace_input ("divs", OP_DREG, OP_REG, OP_VOID);
1149 foo = (GPR (OP[0]) << 1) | (GPR (OP[0] + 1) >> 15);
1150 tmp = (int16)foo - (int16)(GPR (OP[1]));
1151 tmpf = (foo >= GPR (OP[1])) ? 1 : 0;
1152 hi = ((tmpf == 1) ? tmp : foo);
1153 lo = ((GPR (OP[0] + 1) << 1) | tmpf);
1154 SET_GPR (OP[0] + 0, hi);
1155 SET_GPR (OP[0] + 1, lo);
1156 trace_output_32 (((uint32) hi << 16) | lo);
1157 }
1158
1159 /* exef0f */
1160 void
1161 OP_4E04 (void)
1162 {
1163 trace_input ("exef0f", OP_VOID, OP_VOID, OP_VOID);
1164 State.exe = (PSW_F0 == 0);
1165 trace_output_flag ();
1166 }
1167
1168 /* exef0t */
1169 void
1170 OP_4E24 (void)
1171 {
1172 trace_input ("exef0t", OP_VOID, OP_VOID, OP_VOID);
1173 State.exe = (PSW_F0 != 0);
1174 trace_output_flag ();
1175 }
1176
1177 /* exef1f */
1178 void
1179 OP_4E40 (void)
1180 {
1181 trace_input ("exef1f", OP_VOID, OP_VOID, OP_VOID);
1182 State.exe = (PSW_F1 == 0);
1183 trace_output_flag ();
1184 }
1185
1186 /* exef1t */
1187 void
1188 OP_4E42 (void)
1189 {
1190 trace_input ("exef1t", OP_VOID, OP_VOID, OP_VOID);
1191 State.exe = (PSW_F1 != 0);
1192 trace_output_flag ();
1193 }
1194
1195 /* exefaf */
1196 void
1197 OP_4E00 (void)
1198 {
1199 trace_input ("exefaf", OP_VOID, OP_VOID, OP_VOID);
1200 State.exe = (PSW_F0 == 0) & (PSW_F1 == 0);
1201 trace_output_flag ();
1202 }
1203
1204 /* exefat */
1205 void
1206 OP_4E02 (void)
1207 {
1208 trace_input ("exefat", OP_VOID, OP_VOID, OP_VOID);
1209 State.exe = (PSW_F0 == 0) & (PSW_F1 != 0);
1210 trace_output_flag ();
1211 }
1212
1213 /* exetaf */
1214 void
1215 OP_4E20 (void)
1216 {
1217 trace_input ("exetaf", OP_VOID, OP_VOID, OP_VOID);
1218 State.exe = (PSW_F0 != 0) & (PSW_F1 == 0);
1219 trace_output_flag ();
1220 }
1221
1222 /* exetat */
1223 void
1224 OP_4E22 (void)
1225 {
1226 trace_input ("exetat", OP_VOID, OP_VOID, OP_VOID);
1227 State.exe = (PSW_F0 != 0) & (PSW_F1 != 0);
1228 trace_output_flag ();
1229 }
1230
1231 /* exp */
1232 void
1233 OP_15002A00 (void)
1234 {
1235 uint32 tmp, foo;
1236 int i;
1237
1238 trace_input ("exp", OP_REG_OUTPUT, OP_DREG, OP_VOID);
1239 if (((int16)GPR (OP[1])) >= 0)
1240 tmp = (GPR (OP[1]) << 16) | GPR (OP[1] + 1);
1241 else
1242 tmp = ~((GPR (OP[1]) << 16) | GPR (OP[1] + 1));
1243
1244 foo = 0x40000000;
1245 for (i=1;i<17;i++)
1246 {
1247 if (tmp & foo)
1248 {
1249 SET_GPR (OP[0], (i - 1));
1250 trace_output_16 (i - 1);
1251 return;
1252 }
1253 foo >>= 1;
1254 }
1255 SET_GPR (OP[0], 16);
1256 trace_output_16 (16);
1257 }
1258
1259 /* exp */
1260 void
1261 OP_15002A02 (void)
1262 {
1263 int64 tmp, foo;
1264 int i;
1265
1266 trace_input ("exp", OP_REG_OUTPUT, OP_ACCUM, OP_VOID);
1267 tmp = SEXT40(ACC (OP[1]));
1268 if (tmp < 0)
1269 tmp = ~tmp & MASK40;
1270
1271 foo = 0x4000000000LL;
1272 for (i=1;i<25;i++)
1273 {
1274 if (tmp & foo)
1275 {
1276 SET_GPR (OP[0], i - 9);
1277 trace_output_16 (i - 9);
1278 return;
1279 }
1280 foo >>= 1;
1281 }
1282 SET_GPR (OP[0], 16);
1283 trace_output_16 (16);
1284 }
1285
1286 /* jl */
1287 void
1288 OP_4D00 (void)
1289 {
1290 trace_input ("jl", OP_REG, OP_R0, OP_R1);
1291 SET_GPR (13, PC + 1);
1292 JMP (GPR (OP[0]));
1293 trace_output_void ();
1294 }
1295
1296 /* jmp */
1297 void
1298 OP_4C00 (void)
1299 {
1300 trace_input ("jmp", OP_REG,
1301 (OP[0] == 13) ? OP_R0 : OP_VOID,
1302 (OP[0] == 13) ? OP_R1 : OP_VOID);
1303
1304 JMP (GPR (OP[0]));
1305 trace_output_void ();
1306 }
1307
1308 /* ld */
1309 void
1310 OP_30000000 (void)
1311 {
1312 uint16 tmp;
1313 uint16 addr = OP[1] + GPR (OP[2]);
1314 trace_input ("ld", OP_REG_OUTPUT, OP_MEMREF2, OP_VOID);
1315 if ((addr & 1))
1316 {
1317 State.exception = SIG_D10V_BUS;
1318 State.pc_changed = 1; /* Don't increment the PC. */
1319 trace_output_void ();
1320 return;
1321 }
1322 tmp = RW (addr);
1323 SET_GPR (OP[0], tmp);
1324 trace_output_16 (tmp);
1325 }
1326
1327 /* ld */
1328 void
1329 OP_6401 (void)
1330 {
1331 uint16 tmp;
1332 uint16 addr = GPR (OP[1]);
1333 trace_input ("ld", OP_REG_OUTPUT, OP_POSTDEC, OP_VOID);
1334 if ((addr & 1))
1335 {
1336 State.exception = SIG_D10V_BUS;
1337 State.pc_changed = 1; /* Don't increment the PC. */
1338 trace_output_void ();
1339 return;
1340 }
1341 tmp = RW (addr);
1342 SET_GPR (OP[0], tmp);
1343 if (OP[0] != OP[1])
1344 INC_ADDR (OP[1], -2);
1345 trace_output_16 (tmp);
1346 }
1347
1348 /* ld */
1349 void
1350 OP_6001 (void)
1351 {
1352 uint16 tmp;
1353 uint16 addr = GPR (OP[1]);
1354 trace_input ("ld", OP_REG_OUTPUT, OP_POSTINC, OP_VOID);
1355 if ((addr & 1))
1356 {
1357 State.exception = SIG_D10V_BUS;
1358 State.pc_changed = 1; /* Don't increment the PC. */
1359 trace_output_void ();
1360 return;
1361 }
1362 tmp = RW (addr);
1363 SET_GPR (OP[0], tmp);
1364 if (OP[0] != OP[1])
1365 INC_ADDR (OP[1], 2);
1366 trace_output_16 (tmp);
1367 }
1368
1369 /* ld */
1370 void
1371 OP_6000 (void)
1372 {
1373 uint16 tmp;
1374 uint16 addr = GPR (OP[1]);
1375 trace_input ("ld", OP_REG_OUTPUT, OP_MEMREF, OP_VOID);
1376 if ((addr & 1))
1377 {
1378 State.exception = SIG_D10V_BUS;
1379 State.pc_changed = 1; /* Don't increment the PC. */
1380 trace_output_void ();
1381 return;
1382 }
1383 tmp = RW (addr);
1384 SET_GPR (OP[0], tmp);
1385 trace_output_16 (tmp);
1386 }
1387
1388 /* ld */
1389 void
1390 OP_32010000 (void)
1391 {
1392 uint16 tmp;
1393 uint16 addr = OP[1];
1394 trace_input ("ld", OP_REG_OUTPUT, OP_MEMREF3, OP_VOID);
1395 if ((addr & 1))
1396 {
1397 State.exception = SIG_D10V_BUS;
1398 State.pc_changed = 1; /* Don't increment the PC. */
1399 trace_output_void ();
1400 return;
1401 }
1402 tmp = RW (addr);
1403 SET_GPR (OP[0], tmp);
1404 trace_output_16 (tmp);
1405 }
1406
1407 /* ld2w */
1408 void
1409 OP_31000000 (void)
1410 {
1411 int32 tmp;
1412 uint16 addr = OP[1] + GPR (OP[2]);
1413 trace_input ("ld2w", OP_REG_OUTPUT, OP_MEMREF2, OP_VOID);
1414 if ((addr & 1))
1415 {
1416 State.exception = SIG_D10V_BUS;
1417 State.pc_changed = 1; /* Don't increment the PC. */
1418 trace_output_void ();
1419 return;
1420 }
1421 tmp = RLW (addr);
1422 SET_GPR32 (OP[0], tmp);
1423 trace_output_32 (tmp);
1424 }
1425
1426 /* ld2w */
1427 void
1428 OP_6601 (void)
1429 {
1430 uint16 addr = GPR (OP[1]);
1431 int32 tmp;
1432 trace_input ("ld2w", OP_REG_OUTPUT, OP_POSTDEC, OP_VOID);
1433 if ((addr & 1))
1434 {
1435 State.exception = SIG_D10V_BUS;
1436 State.pc_changed = 1; /* Don't increment the PC. */
1437 trace_output_void ();
1438 return;
1439 }
1440 tmp = RLW (addr);
1441 SET_GPR32 (OP[0], tmp);
1442 if (OP[0] != OP[1] && ((OP[0] + 1) != OP[1]))
1443 INC_ADDR (OP[1], -4);
1444 trace_output_32 (tmp);
1445 }
1446
1447 /* ld2w */
1448 void
1449 OP_6201 (void)
1450 {
1451 int32 tmp;
1452 uint16 addr = GPR (OP[1]);
1453 trace_input ("ld2w", OP_REG_OUTPUT, OP_POSTINC, OP_VOID);
1454 if ((addr & 1))
1455 {
1456 State.exception = SIG_D10V_BUS;
1457 State.pc_changed = 1; /* Don't increment the PC. */
1458 trace_output_void ();
1459 return;
1460 }
1461 tmp = RLW (addr);
1462 SET_GPR32 (OP[0], tmp);
1463 if (OP[0] != OP[1] && ((OP[0] + 1) != OP[1]))
1464 INC_ADDR (OP[1], 4);
1465 trace_output_32 (tmp);
1466 }
1467
1468 /* ld2w */
1469 void
1470 OP_6200 (void)
1471 {
1472 uint16 addr = GPR (OP[1]);
1473 int32 tmp;
1474 trace_input ("ld2w", OP_REG_OUTPUT, OP_MEMREF, OP_VOID);
1475 if ((addr & 1))
1476 {
1477 State.exception = SIG_D10V_BUS;
1478 State.pc_changed = 1; /* Don't increment the PC. */
1479 trace_output_void ();
1480 return;
1481 }
1482 tmp = RLW (addr);
1483 SET_GPR32 (OP[0], tmp);
1484 trace_output_32 (tmp);
1485 }
1486
1487 /* ld2w */
1488 void
1489 OP_33010000 (void)
1490 {
1491 int32 tmp;
1492 uint16 addr = OP[1];
1493 trace_input ("ld2w", OP_REG_OUTPUT, OP_MEMREF3, OP_VOID);
1494 if ((addr & 1))
1495 {
1496 State.exception = SIG_D10V_BUS;
1497 State.pc_changed = 1; /* Don't increment the PC. */
1498 trace_output_void ();
1499 return;
1500 }
1501 tmp = RLW (addr);
1502 SET_GPR32 (OP[0], tmp);
1503 trace_output_32 (tmp);
1504 }
1505
1506 /* ldb */
1507 void
1508 OP_38000000 (void)
1509 {
1510 int16 tmp;
1511 trace_input ("ldb", OP_REG_OUTPUT, OP_MEMREF2, OP_VOID);
1512 tmp = SEXT8 (RB (OP[1] + GPR (OP[2])));
1513 SET_GPR (OP[0], tmp);
1514 trace_output_16 (tmp);
1515 }
1516
1517 /* ldb */
1518 void
1519 OP_7000 (void)
1520 {
1521 int16 tmp;
1522 trace_input ("ldb", OP_REG_OUTPUT, OP_MEMREF, OP_VOID);
1523 tmp = SEXT8 (RB (GPR (OP[1])));
1524 SET_GPR (OP[0], tmp);
1525 trace_output_16 (tmp);
1526 }
1527
1528 /* ldi.s */
1529 void
1530 OP_4001 (void)
1531 {
1532 int16 tmp;
1533 trace_input ("ldi.s", OP_REG_OUTPUT, OP_CONSTANT4, OP_VOID);
1534 tmp = SEXT4 (OP[1]);
1535 SET_GPR (OP[0], tmp);
1536 trace_output_16 (tmp);
1537 }
1538
1539 /* ldi.l */
1540 void
1541 OP_20000000 (void)
1542 {
1543 int16 tmp;
1544 trace_input ("ldi.l", OP_REG_OUTPUT, OP_CONSTANT16, OP_VOID);
1545 tmp = OP[1];
1546 SET_GPR (OP[0], tmp);
1547 trace_output_16 (tmp);
1548 }
1549
1550 /* ldub */
1551 void
1552 OP_39000000 (void)
1553 {
1554 int16 tmp;
1555 trace_input ("ldub", OP_REG_OUTPUT, OP_MEMREF2, OP_VOID);
1556 tmp = RB (OP[1] + GPR (OP[2]));
1557 SET_GPR (OP[0], tmp);
1558 trace_output_16 (tmp);
1559 }
1560
1561 /* ldub */
1562 void
1563 OP_7200 (void)
1564 {
1565 int16 tmp;
1566 trace_input ("ldub", OP_REG_OUTPUT, OP_MEMREF, OP_VOID);
1567 tmp = RB (GPR (OP[1]));
1568 SET_GPR (OP[0], tmp);
1569 trace_output_16 (tmp);
1570 }
1571
1572 /* mac */
1573 void
1574 OP_2A00 (void)
1575 {
1576 int64 tmp;
1577
1578 trace_input ("mac", OP_ACCUM, OP_REG, OP_REG);
1579 tmp = SEXT40 ((int16)(GPR (OP[1])) * (int16)(GPR (OP[2])));
1580
1581 if (PSW_FX)
1582 tmp = SEXT40( (tmp << 1) & MASK40);
1583
1584 if (PSW_ST && tmp > SEXT40(MAX32))
1585 tmp = (MAX32);
1586
1587 tmp += SEXT40 (ACC (OP[0]));
1588 if (PSW_ST)
1589 {
1590 if (tmp > SEXT40(MAX32))
1591 tmp = (MAX32);
1592 else if (tmp < SEXT40(MIN32))
1593 tmp = (MIN32);
1594 else
1595 tmp = (tmp & MASK40);
1596 }
1597 else
1598 tmp = (tmp & MASK40);
1599 SET_ACC (OP[0], tmp);
1600 trace_output_40 (tmp);
1601 }
1602
1603 /* macsu */
1604 void
1605 OP_1A00 (void)
1606 {
1607 int64 tmp;
1608
1609 trace_input ("macsu", OP_ACCUM, OP_REG, OP_REG);
1610 tmp = SEXT40 ((int16) GPR (OP[1]) * GPR (OP[2]));
1611 if (PSW_FX)
1612 tmp = SEXT40 ((tmp << 1) & MASK40);
1613 tmp = ((SEXT40 (ACC (OP[0])) + tmp) & MASK40);
1614 SET_ACC (OP[0], tmp);
1615 trace_output_40 (tmp);
1616 }
1617
1618 /* macu */
1619 void
1620 OP_3A00 (void)
1621 {
1622 uint64 tmp;
1623 uint32 src1;
1624 uint32 src2;
1625
1626 trace_input ("macu", OP_ACCUM, OP_REG, OP_REG);
1627 src1 = (uint16) GPR (OP[1]);
1628 src2 = (uint16) GPR (OP[2]);
1629 tmp = src1 * src2;
1630 if (PSW_FX)
1631 tmp = (tmp << 1);
1632 tmp = ((ACC (OP[0]) + tmp) & MASK40);
1633 SET_ACC (OP[0], tmp);
1634 trace_output_40 (tmp);
1635 }
1636
1637 /* max */
1638 void
1639 OP_2600 (void)
1640 {
1641 int16 tmp;
1642 trace_input ("max", OP_REG, OP_REG, OP_VOID);
1643 SET_PSW_F1 (PSW_F0);
1644 if ((int16) GPR (OP[1]) > (int16)GPR (OP[0]))
1645 {
1646 tmp = GPR (OP[1]);
1647 SET_PSW_F0 (1);
1648 }
1649 else
1650 {
1651 tmp = GPR (OP[0]);
1652 SET_PSW_F0 (0);
1653 }
1654 SET_GPR (OP[0], tmp);
1655 trace_output_16 (tmp);
1656 }
1657
1658 /* max */
1659 void
1660 OP_3600 (void)
1661 {
1662 int64 tmp;
1663
1664 trace_input ("max", OP_ACCUM, OP_DREG, OP_VOID);
1665 SET_PSW_F1 (PSW_F0);
1666 tmp = SEXT16 (GPR (OP[1])) << 16 | GPR (OP[1] + 1);
1667 if (tmp > SEXT40 (ACC (OP[0])))
1668 {
1669 tmp = (tmp & MASK40);
1670 SET_PSW_F0 (1);
1671 }
1672 else
1673 {
1674 tmp = ACC (OP[0]);
1675 SET_PSW_F0 (0);
1676 }
1677 SET_ACC (OP[0], tmp);
1678 trace_output_40 (tmp);
1679 }
1680
1681 /* max */
1682 void
1683 OP_3602 (void)
1684 {
1685 int64 tmp;
1686 trace_input ("max", OP_ACCUM, OP_ACCUM, OP_VOID);
1687 SET_PSW_F1 (PSW_F0);
1688 if (SEXT40 (ACC (OP[1])) > SEXT40 (ACC (OP[0])))
1689 {
1690 tmp = ACC (OP[1]);
1691 SET_PSW_F0 (1);
1692 }
1693 else
1694 {
1695 tmp = ACC (OP[0]);
1696 SET_PSW_F0 (0);
1697 }
1698 SET_ACC (OP[0], tmp);
1699 trace_output_40 (tmp);
1700 }
1701
1702
1703 /* min */
1704 void
1705 OP_2601 (void)
1706 {
1707 int16 tmp;
1708 trace_input ("min", OP_REG, OP_REG, OP_VOID);
1709 SET_PSW_F1 (PSW_F0);
1710 if ((int16)GPR (OP[1]) < (int16)GPR (OP[0]))
1711 {
1712 tmp = GPR (OP[1]);
1713 SET_PSW_F0 (1);
1714 }
1715 else
1716 {
1717 tmp = GPR (OP[0]);
1718 SET_PSW_F0 (0);
1719 }
1720 SET_GPR (OP[0], tmp);
1721 trace_output_16 (tmp);
1722 }
1723
1724 /* min */
1725 void
1726 OP_3601 (void)
1727 {
1728 int64 tmp;
1729
1730 trace_input ("min", OP_ACCUM, OP_DREG, OP_VOID);
1731 SET_PSW_F1 (PSW_F0);
1732 tmp = SEXT16 (GPR (OP[1])) << 16 | GPR (OP[1] + 1);
1733 if (tmp < SEXT40(ACC (OP[0])))
1734 {
1735 tmp = (tmp & MASK40);
1736 SET_PSW_F0 (1);
1737 }
1738 else
1739 {
1740 tmp = ACC (OP[0]);
1741 SET_PSW_F0 (0);
1742 }
1743 SET_ACC (OP[0], tmp);
1744 trace_output_40 (tmp);
1745 }
1746
1747 /* min */
1748 void
1749 OP_3603 (void)
1750 {
1751 int64 tmp;
1752 trace_input ("min", OP_ACCUM, OP_ACCUM, OP_VOID);
1753 SET_PSW_F1 (PSW_F0);
1754 if (SEXT40(ACC (OP[1])) < SEXT40(ACC (OP[0])))
1755 {
1756 tmp = ACC (OP[1]);
1757 SET_PSW_F0 (1);
1758 }
1759 else
1760 {
1761 tmp = ACC (OP[0]);
1762 SET_PSW_F0 (0);
1763 }
1764 SET_ACC (OP[0], tmp);
1765 trace_output_40 (tmp);
1766 }
1767
1768 /* msb */
1769 void
1770 OP_2800 (void)
1771 {
1772 int64 tmp;
1773
1774 trace_input ("msb", OP_ACCUM, OP_REG, OP_REG);
1775 tmp = SEXT40 ((int16)(GPR (OP[1])) * (int16)(GPR (OP[2])));
1776
1777 if (PSW_FX)
1778 tmp = SEXT40 ((tmp << 1) & MASK40);
1779
1780 if (PSW_ST && tmp > SEXT40(MAX32))
1781 tmp = (MAX32);
1782
1783 tmp = SEXT40(ACC (OP[0])) - tmp;
1784 if (PSW_ST)
1785 {
1786 if (tmp > SEXT40(MAX32))
1787 tmp = (MAX32);
1788 else if (tmp < SEXT40(MIN32))
1789 tmp = (MIN32);
1790 else
1791 tmp = (tmp & MASK40);
1792 }
1793 else
1794 {
1795 tmp = (tmp & MASK40);
1796 }
1797 SET_ACC (OP[0], tmp);
1798 trace_output_40 (tmp);
1799 }
1800
1801 /* msbsu */
1802 void
1803 OP_1800 (void)
1804 {
1805 int64 tmp;
1806
1807 trace_input ("msbsu", OP_ACCUM, OP_REG, OP_REG);
1808 tmp = SEXT40 ((int16)GPR (OP[1]) * GPR (OP[2]));
1809 if (PSW_FX)
1810 tmp = SEXT40( (tmp << 1) & MASK40);
1811 tmp = ((SEXT40 (ACC (OP[0])) - tmp) & MASK40);
1812 SET_ACC (OP[0], tmp);
1813 trace_output_40 (tmp);
1814 }
1815
1816 /* msbu */
1817 void
1818 OP_3800 (void)
1819 {
1820 uint64 tmp;
1821 uint32 src1;
1822 uint32 src2;
1823
1824 trace_input ("msbu", OP_ACCUM, OP_REG, OP_REG);
1825 src1 = (uint16) GPR (OP[1]);
1826 src2 = (uint16) GPR (OP[2]);
1827 tmp = src1 * src2;
1828 if (PSW_FX)
1829 tmp = (tmp << 1);
1830 tmp = ((ACC (OP[0]) - tmp) & MASK40);
1831 SET_ACC (OP[0], tmp);
1832 trace_output_40 (tmp);
1833 }
1834
1835 /* mul */
1836 void
1837 OP_2E00 (void)
1838 {
1839 int16 tmp;
1840 trace_input ("mul", OP_REG, OP_REG, OP_VOID);
1841 tmp = GPR (OP[0]) * GPR (OP[1]);
1842 SET_GPR (OP[0], tmp);
1843 trace_output_16 (tmp);
1844 }
1845
1846 /* mulx */
1847 void
1848 OP_2C00 (void)
1849 {
1850 int64 tmp;
1851
1852 trace_input ("mulx", OP_ACCUM_OUTPUT, OP_REG, OP_REG);
1853 tmp = SEXT40 ((int16)(GPR (OP[1])) * (int16)(GPR (OP[2])));
1854
1855 if (PSW_FX)
1856 tmp = SEXT40 ((tmp << 1) & MASK40);
1857
1858 if (PSW_ST && tmp > SEXT40(MAX32))
1859 tmp = (MAX32);
1860 else
1861 tmp = (tmp & MASK40);
1862 SET_ACC (OP[0], tmp);
1863 trace_output_40 (tmp);
1864 }
1865
1866 /* mulxsu */
1867 void
1868 OP_1C00 (void)
1869 {
1870 int64 tmp;
1871
1872 trace_input ("mulxsu", OP_ACCUM_OUTPUT, OP_REG, OP_REG);
1873 tmp = SEXT40 ((int16)(GPR (OP[1])) * GPR (OP[2]));
1874
1875 if (PSW_FX)
1876 tmp <<= 1;
1877 tmp = (tmp & MASK40);
1878 SET_ACC (OP[0], tmp);
1879 trace_output_40 (tmp);
1880 }
1881
1882 /* mulxu */
1883 void
1884 OP_3C00 (void)
1885 {
1886 uint64 tmp;
1887 uint32 src1;
1888 uint32 src2;
1889
1890 trace_input ("mulxu", OP_ACCUM_OUTPUT, OP_REG, OP_REG);
1891 src1 = (uint16) GPR (OP[1]);
1892 src2 = (uint16) GPR (OP[2]);
1893 tmp = src1 * src2;
1894 if (PSW_FX)
1895 tmp <<= 1;
1896 tmp = (tmp & MASK40);
1897 SET_ACC (OP[0], tmp);
1898 trace_output_40 (tmp);
1899 }
1900
1901 /* mv */
1902 void
1903 OP_4000 (void)
1904 {
1905 int16 tmp;
1906 trace_input ("mv", OP_REG_OUTPUT, OP_REG, OP_VOID);
1907 tmp = GPR (OP[1]);
1908 SET_GPR (OP[0], tmp);
1909 trace_output_16 (tmp);
1910 }
1911
1912 /* mv2w */
1913 void
1914 OP_5000 (void)
1915 {
1916 int32 tmp;
1917 trace_input ("mv2w", OP_DREG_OUTPUT, OP_DREG, OP_VOID);
1918 tmp = GPR32 (OP[1]);
1919 SET_GPR32 (OP[0], tmp);
1920 trace_output_32 (tmp);
1921 }
1922
1923 /* mv2wfac */
1924 void
1925 OP_3E00 (void)
1926 {
1927 int32 tmp;
1928 trace_input ("mv2wfac", OP_DREG_OUTPUT, OP_ACCUM, OP_VOID);
1929 tmp = ACC (OP[1]);
1930 SET_GPR32 (OP[0], tmp);
1931 trace_output_32 (tmp);
1932 }
1933
1934 /* mv2wtac */
1935 void
1936 OP_3E01 (void)
1937 {
1938 int64 tmp;
1939 trace_input ("mv2wtac", OP_DREG, OP_ACCUM_OUTPUT, OP_VOID);
1940 tmp = ((SEXT16 (GPR (OP[0])) << 16 | GPR (OP[0] + 1)) & MASK40);
1941 SET_ACC (OP[1], tmp);
1942 trace_output_40 (tmp);
1943 }
1944
1945 /* mvac */
1946 void
1947 OP_3E03 (void)
1948 {
1949 int64 tmp;
1950 trace_input ("mvac", OP_ACCUM_OUTPUT, OP_ACCUM, OP_VOID);
1951 tmp = ACC (OP[1]);
1952 SET_ACC (OP[0], tmp);
1953 trace_output_40 (tmp);
1954 }
1955
1956 /* mvb */
1957 void
1958 OP_5400 (void)
1959 {
1960 int16 tmp;
1961 trace_input ("mvb", OP_REG_OUTPUT, OP_REG, OP_VOID);
1962 tmp = SEXT8 (GPR (OP[1]) & 0xff);
1963 SET_GPR (OP[0], tmp);
1964 trace_output_16 (tmp);
1965 }
1966
1967 /* mvf0f */
1968 void
1969 OP_4400 (void)
1970 {
1971 int16 tmp;
1972 trace_input ("mvf0f", OP_REG_OUTPUT, OP_REG, OP_VOID);
1973 if (PSW_F0 == 0)
1974 {
1975 tmp = GPR (OP[1]);
1976 SET_GPR (OP[0], tmp);
1977 }
1978 else
1979 tmp = GPR (OP[0]);
1980 trace_output_16 (tmp);
1981 }
1982
1983 /* mvf0t */
1984 void
1985 OP_4401 (void)
1986 {
1987 int16 tmp;
1988 trace_input ("mvf0t", OP_REG_OUTPUT, OP_REG, OP_VOID);
1989 if (PSW_F0)
1990 {
1991 tmp = GPR (OP[1]);
1992 SET_GPR (OP[0], tmp);
1993 }
1994 else
1995 tmp = GPR (OP[0]);
1996 trace_output_16 (tmp);
1997 }
1998
1999 /* mvfacg */
2000 void
2001 OP_1E04 (void)
2002 {
2003 int16 tmp;
2004 trace_input ("mvfacg", OP_REG_OUTPUT, OP_ACCUM, OP_VOID);
2005 tmp = ((ACC (OP[1]) >> 32) & 0xff);
2006 SET_GPR (OP[0], tmp);
2007 trace_output_16 (tmp);
2008 }
2009
2010 /* mvfachi */
2011 void
2012 OP_1E00 (void)
2013 {
2014 int16 tmp;
2015 trace_input ("mvfachi", OP_REG_OUTPUT, OP_ACCUM, OP_VOID);
2016 tmp = (ACC (OP[1]) >> 16);
2017 SET_GPR (OP[0], tmp);
2018 trace_output_16 (tmp);
2019 }
2020
2021 /* mvfaclo */
2022 void
2023 OP_1E02 (void)
2024 {
2025 int16 tmp;
2026 trace_input ("mvfaclo", OP_REG_OUTPUT, OP_ACCUM, OP_VOID);
2027 tmp = ACC (OP[1]);
2028 SET_GPR (OP[0], tmp);
2029 trace_output_16 (tmp);
2030 }
2031
2032 /* mvfc */
2033 void
2034 OP_5200 (void)
2035 {
2036 int16 tmp;
2037 trace_input ("mvfc", OP_REG_OUTPUT, OP_CR, OP_VOID);
2038 tmp = CREG (OP[1]);
2039 SET_GPR (OP[0], tmp);
2040 trace_output_16 (tmp);
2041 }
2042
2043 /* mvtacg */
2044 void
2045 OP_1E41 (void)
2046 {
2047 int64 tmp;
2048 trace_input ("mvtacg", OP_REG, OP_ACCUM, OP_VOID);
2049 tmp = ((ACC (OP[1]) & MASK32)
2050 | ((int64)(GPR (OP[0]) & 0xff) << 32));
2051 SET_ACC (OP[1], tmp);
2052 trace_output_40 (tmp);
2053 }
2054
2055 /* mvtachi */
2056 void
2057 OP_1E01 (void)
2058 {
2059 uint64 tmp;
2060 trace_input ("mvtachi", OP_REG, OP_ACCUM, OP_VOID);
2061 tmp = ACC (OP[1]) & 0xffff;
2062 tmp = ((SEXT16 (GPR (OP[0])) << 16 | tmp) & MASK40);
2063 SET_ACC (OP[1], tmp);
2064 trace_output_40 (tmp);
2065 }
2066
2067 /* mvtaclo */
2068 void
2069 OP_1E21 (void)
2070 {
2071 int64 tmp;
2072 trace_input ("mvtaclo", OP_REG, OP_ACCUM, OP_VOID);
2073 tmp = ((SEXT16 (GPR (OP[0]))) & MASK40);
2074 SET_ACC (OP[1], tmp);
2075 trace_output_40 (tmp);
2076 }
2077
2078 /* mvtc */
2079 void
2080 OP_5600 (void)
2081 {
2082 int16 tmp;
2083 trace_input ("mvtc", OP_REG, OP_CR_OUTPUT, OP_VOID);
2084 tmp = GPR (OP[0]);
2085 tmp = SET_CREG (OP[1], tmp);
2086 trace_output_16 (tmp);
2087 }
2088
2089 /* mvub */
2090 void
2091 OP_5401 (void)
2092 {
2093 int16 tmp;
2094 trace_input ("mvub", OP_REG_OUTPUT, OP_REG, OP_VOID);
2095 tmp = (GPR (OP[1]) & 0xff);
2096 SET_GPR (OP[0], tmp);
2097 trace_output_16 (tmp);
2098 }
2099
2100 /* neg */
2101 void
2102 OP_4605 (void)
2103 {
2104 int16 tmp;
2105 trace_input ("neg", OP_REG, OP_VOID, OP_VOID);
2106 tmp = - GPR (OP[0]);
2107 SET_GPR (OP[0], tmp);
2108 trace_output_16 (tmp);
2109 }
2110
2111 /* neg */
2112 void
2113 OP_5605 (void)
2114 {
2115 int64 tmp;
2116
2117 trace_input ("neg", OP_ACCUM, OP_VOID, OP_VOID);
2118 tmp = -SEXT40(ACC (OP[0]));
2119 if (PSW_ST)
2120 {
2121 if (tmp > SEXT40(MAX32))
2122 tmp = (MAX32);
2123 else if (tmp < SEXT40(MIN32))
2124 tmp = (MIN32);
2125 else
2126 tmp = (tmp & MASK40);
2127 }
2128 else
2129 tmp = (tmp & MASK40);
2130 SET_ACC (OP[0], tmp);
2131 trace_output_40 (tmp);
2132 }
2133
2134
2135 /* nop */
2136 void
2137 OP_5E00 (void)
2138 {
2139 trace_input ("nop", OP_VOID, OP_VOID, OP_VOID);
2140
2141 ins_type_counters[ (int)State.ins_type ]--; /* don't count nops as normal instructions */
2142 switch (State.ins_type)
2143 {
2144 default:
2145 ins_type_counters[ (int)INS_UNKNOWN ]++;
2146 break;
2147
2148 case INS_LEFT_PARALLEL:
2149 /* Don't count a parallel op that includes a NOP as a true parallel op */
2150 ins_type_counters[ (int)INS_RIGHT_PARALLEL ]--;
2151 ins_type_counters[ (int)INS_RIGHT ]++;
2152 ins_type_counters[ (int)INS_LEFT_NOPS ]++;
2153 break;
2154
2155 case INS_LEFT:
2156 case INS_LEFT_COND_EXE:
2157 ins_type_counters[ (int)INS_LEFT_NOPS ]++;
2158 break;
2159
2160 case INS_RIGHT_PARALLEL:
2161 /* Don't count a parallel op that includes a NOP as a true parallel op */
2162 ins_type_counters[ (int)INS_LEFT_PARALLEL ]--;
2163 ins_type_counters[ (int)INS_LEFT ]++;
2164 ins_type_counters[ (int)INS_RIGHT_NOPS ]++;
2165 break;
2166
2167 case INS_RIGHT:
2168 case INS_RIGHT_COND_EXE:
2169 ins_type_counters[ (int)INS_RIGHT_NOPS ]++;
2170 break;
2171 }
2172
2173 trace_output_void ();
2174 }
2175
2176 /* not */
2177 void
2178 OP_4603 (void)
2179 {
2180 int16 tmp;
2181 trace_input ("not", OP_REG, OP_VOID, OP_VOID);
2182 tmp = ~GPR (OP[0]);
2183 SET_GPR (OP[0], tmp);
2184 trace_output_16 (tmp);
2185 }
2186
2187 /* or */
2188 void
2189 OP_800 (void)
2190 {
2191 int16 tmp;
2192 trace_input ("or", OP_REG, OP_REG, OP_VOID);
2193 tmp = (GPR (OP[0]) | GPR (OP[1]));
2194 SET_GPR (OP[0], tmp);
2195 trace_output_16 (tmp);
2196 }
2197
2198 /* or3 */
2199 void
2200 OP_4000000 (void)
2201 {
2202 int16 tmp;
2203 trace_input ("or3", OP_REG_OUTPUT, OP_REG, OP_CONSTANT16);
2204 tmp = (GPR (OP[1]) | OP[2]);
2205 SET_GPR (OP[0], tmp);
2206 trace_output_16 (tmp);
2207 }
2208
2209 /* rac */
2210 void
2211 OP_5201 (void)
2212 {
2213 int64 tmp;
2214 int shift = SEXT3 (OP[2]);
2215
2216 trace_input ("rac", OP_DREG_OUTPUT, OP_ACCUM, OP_CONSTANT3);
2217 if (OP[1] != 0)
2218 {
2219 (*d10v_callback->printf_filtered) (d10v_callback,
2220 "ERROR at PC 0x%x: instruction only valid for A0\n",
2221 PC<<2);
2222 State.exception = SIGILL;
2223 }
2224
2225 SET_PSW_F1 (PSW_F0);
2226 tmp = SEXT56 ((ACC (0) << 16) | (ACC (1) & 0xffff));
2227 if (shift >=0)
2228 tmp <<= shift;
2229 else
2230 tmp >>= -shift;
2231 tmp += 0x8000;
2232 tmp >>= 16; /* look at bits 0:43 */
2233 if (tmp > SEXT44 (SIGNED64 (0x0007fffffff)))
2234 {
2235 tmp = 0x7fffffff;
2236 SET_PSW_F0 (1);
2237 }
2238 else if (tmp < SEXT44 (SIGNED64 (0xfff80000000)))
2239 {
2240 tmp = 0x80000000;
2241 SET_PSW_F0 (1);
2242 }
2243 else
2244 {
2245 SET_PSW_F0 (0);
2246 }
2247 SET_GPR32 (OP[0], tmp);
2248 trace_output_32 (tmp);
2249 }
2250
2251 /* rachi */
2252 void
2253 OP_4201 (void)
2254 {
2255 signed64 tmp;
2256 int shift = SEXT3 (OP[2]);
2257
2258 trace_input ("rachi", OP_REG_OUTPUT, OP_ACCUM, OP_CONSTANT3);
2259 SET_PSW_F1 (PSW_F0);
2260 if (shift >=0)
2261 tmp = SEXT40 (ACC (OP[1])) << shift;
2262 else
2263 tmp = SEXT40 (ACC (OP[1])) >> -shift;
2264 tmp += 0x8000;
2265
2266 if (tmp > SEXT44 (SIGNED64 (0x0007fffffff)))
2267 {
2268 tmp = 0x7fff;
2269 SET_PSW_F0 (1);
2270 }
2271 else if (tmp < SEXT44 (SIGNED64 (0xfff80000000)))
2272 {
2273 tmp = 0x8000;
2274 SET_PSW_F0 (1);
2275 }
2276 else
2277 {
2278 tmp = (tmp >> 16);
2279 SET_PSW_F0 (0);
2280 }
2281 SET_GPR (OP[0], tmp);
2282 trace_output_16 (tmp);
2283 }
2284
2285 /* rep */
2286 void
2287 OP_27000000 (void)
2288 {
2289 trace_input ("rep", OP_REG, OP_CONSTANT16, OP_VOID);
2290 SET_RPT_S (PC + 1);
2291 SET_RPT_E (PC + OP[1]);
2292 SET_RPT_C (GPR (OP[0]));
2293 SET_PSW_RP (1);
2294 if (GPR (OP[0]) == 0)
2295 {
2296 (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: rep with count=0 is illegal.\n");
2297 State.exception = SIGILL;
2298 }
2299 if (OP[1] < 4)
2300 {
2301 (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: rep must include at least 4 instructions.\n");
2302 State.exception = SIGILL;
2303 }
2304 trace_output_void ();
2305 }
2306
2307 /* repi */
2308 void
2309 OP_2F000000 (void)
2310 {
2311 trace_input ("repi", OP_CONSTANT16, OP_CONSTANT16, OP_VOID);
2312 SET_RPT_S (PC + 1);
2313 SET_RPT_E (PC + OP[1]);
2314 SET_RPT_C (OP[0]);
2315 SET_PSW_RP (1);
2316 if (OP[0] == 0)
2317 {
2318 (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: repi with count=0 is illegal.\n");
2319 State.exception = SIGILL;
2320 }
2321 if (OP[1] < 4)
2322 {
2323 (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: repi must include at least 4 instructions.\n");
2324 State.exception = SIGILL;
2325 }
2326 trace_output_void ();
2327 }
2328
2329 /* rtd */
2330 void
2331 OP_5F60 (void)
2332 {
2333 trace_input ("rtd", OP_VOID, OP_VOID, OP_VOID);
2334 SET_CREG (PSW_CR, DPSW);
2335 JMP(DPC);
2336 trace_output_void ();
2337 }
2338
2339 /* rte */
2340 void
2341 OP_5F40 (void)
2342 {
2343 trace_input ("rte", OP_VOID, OP_VOID, OP_VOID);
2344 SET_CREG (PSW_CR, BPSW);
2345 JMP(BPC);
2346 trace_output_void ();
2347 }
2348
2349 /* sac */
2350 void OP_5209 (void)
2351 {
2352 int64 tmp;
2353
2354 trace_input ("sac", OP_REG_OUTPUT, OP_ACCUM, OP_VOID);
2355
2356 tmp = SEXT40(ACC (OP[1]));
2357
2358 SET_PSW_F1 (PSW_F0);
2359
2360 if (tmp > SEXT40(MAX32))
2361 {
2362 tmp = (MAX32);
2363 SET_PSW_F0 (1);
2364 }
2365 else if (tmp < SEXT40(MIN32))
2366 {
2367 tmp = 0x80000000;
2368 SET_PSW_F0 (1);
2369 }
2370 else
2371 {
2372 tmp = (tmp & MASK32);
2373 SET_PSW_F0 (0);
2374 }
2375
2376 SET_GPR32 (OP[0], tmp);
2377
2378 trace_output_40 (tmp);
2379 }
2380
2381 /* sachi */
2382 void
2383 OP_4209 (void)
2384 {
2385 int64 tmp;
2386
2387 trace_input ("sachi", OP_REG_OUTPUT, OP_ACCUM, OP_VOID);
2388
2389 tmp = SEXT40(ACC (OP[1]));
2390
2391 SET_PSW_F1 (PSW_F0);
2392
2393 if (tmp > SEXT40(MAX32))
2394 {
2395 tmp = 0x7fff;
2396 SET_PSW_F0 (1);
2397 }
2398 else if (tmp < SEXT40(MIN32))
2399 {
2400 tmp = 0x8000;
2401 SET_PSW_F0 (1);
2402 }
2403 else
2404 {
2405 tmp >>= 16;
2406 SET_PSW_F0 (0);
2407 }
2408
2409 SET_GPR (OP[0], tmp);
2410
2411 trace_output_16 (OP[0]);
2412 }
2413
2414 /* sadd */
2415 void
2416 OP_1223 (void)
2417 {
2418 int64 tmp;
2419
2420 trace_input ("sadd", OP_ACCUM, OP_ACCUM, OP_VOID);
2421 tmp = SEXT40(ACC (OP[0])) + (SEXT40(ACC (OP[1])) >> 16);
2422 if (PSW_ST)
2423 {
2424 if (tmp > SEXT40(MAX32))
2425 tmp = (MAX32);
2426 else if (tmp < SEXT40(MIN32))
2427 tmp = (MIN32);
2428 else
2429 tmp = (tmp & MASK40);
2430 }
2431 else
2432 tmp = (tmp & MASK40);
2433 SET_ACC (OP[0], tmp);
2434 trace_output_40 (tmp);
2435 }
2436
2437 /* setf0f */
2438 void
2439 OP_4611 (void)
2440 {
2441 int16 tmp;
2442 trace_input ("setf0f", OP_REG_OUTPUT, OP_VOID, OP_VOID);
2443 tmp = ((PSW_F0 == 0) ? 1 : 0);
2444 SET_GPR (OP[0], tmp);
2445 trace_output_16 (tmp);
2446 }
2447
2448 /* setf0t */
2449 void
2450 OP_4613 (void)
2451 {
2452 int16 tmp;
2453 trace_input ("setf0t", OP_REG_OUTPUT, OP_VOID, OP_VOID);
2454 tmp = ((PSW_F0 == 1) ? 1 : 0);
2455 SET_GPR (OP[0], tmp);
2456 trace_output_16 (tmp);
2457 }
2458
2459 /* slae */
2460 void
2461 OP_3220 (void)
2462 {
2463 int64 tmp;
2464 int16 reg;
2465
2466 trace_input ("slae", OP_ACCUM, OP_REG, OP_VOID);
2467
2468 reg = SEXT16 (GPR (OP[1]));
2469
2470 if (reg >= 17 || reg <= -17)
2471 {
2472 (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: shift value %d too large.\n", reg);
2473 State.exception = SIGILL;
2474 return;
2475 }
2476
2477 tmp = SEXT40 (ACC (OP[0]));
2478
2479 if (PSW_ST && (tmp < SEXT40 (MIN32) || tmp > SEXT40 (MAX32)))
2480 {
2481 (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: accumulator value 0x%.2x%.8lx out of range\n", ((int)(tmp >> 32) & 0xff), ((unsigned long) tmp) & 0xffffffff);
2482 State.exception = SIGILL;
2483 return;
2484 }
2485
2486 if (reg >= 0 && reg <= 16)
2487 {
2488 tmp = SEXT56 ((SEXT56 (tmp)) << (GPR (OP[1])));
2489 if (PSW_ST)
2490 {
2491 if (tmp > SEXT40(MAX32))
2492 tmp = (MAX32);
2493 else if (tmp < SEXT40(MIN32))
2494 tmp = (MIN32);
2495 else
2496 tmp = (tmp & MASK40);
2497 }
2498 else
2499 tmp = (tmp & MASK40);
2500 }
2501 else
2502 {
2503 tmp = (SEXT40 (ACC (OP[0]))) >> (-GPR (OP[1]));
2504 }
2505
2506 SET_ACC(OP[0], tmp);
2507
2508 trace_output_40(tmp);
2509 }
2510
2511 /* sleep */
2512 void
2513 OP_5FC0 (void)
2514 {
2515 trace_input ("sleep", OP_VOID, OP_VOID, OP_VOID);
2516 SET_PSW_IE (1);
2517 trace_output_void ();
2518 }
2519
2520 /* sll */
2521 void
2522 OP_2200 (void)
2523 {
2524 int16 tmp;
2525 trace_input ("sll", OP_REG, OP_REG, OP_VOID);
2526 tmp = (GPR (OP[0]) << (GPR (OP[1]) & 0xf));
2527 SET_GPR (OP[0], tmp);
2528 trace_output_16 (tmp);
2529 }
2530
2531 /* sll */
2532 void
2533 OP_3200 (void)
2534 {
2535 int64 tmp;
2536 trace_input ("sll", OP_ACCUM, OP_REG, OP_VOID);
2537 if ((GPR (OP[1]) & 31) <= 16)
2538 tmp = SEXT40 (ACC (OP[0])) << (GPR (OP[1]) & 31);
2539 else
2540 {
2541 (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: shift value %d too large.\n", GPR (OP[1]) & 31);
2542 State.exception = SIGILL;
2543 return;
2544 }
2545
2546 if (PSW_ST)
2547 {
2548 if (tmp > SEXT40(MAX32))
2549 tmp = (MAX32);
2550 else if (tmp < SEXT40(MIN32))
2551 tmp = (MIN32);
2552 else
2553 tmp = (tmp & MASK40);
2554 }
2555 else
2556 tmp = (tmp & MASK40);
2557 SET_ACC (OP[0], tmp);
2558 trace_output_40 (tmp);
2559 }
2560
2561 /* slli */
2562 void
2563 OP_2201 (void)
2564 {
2565 int16 tmp;
2566 trace_input ("slli", OP_REG, OP_CONSTANT16, OP_VOID);
2567 tmp = (GPR (OP[0]) << OP[1]);
2568 SET_GPR (OP[0], tmp);
2569 trace_output_16 (tmp);
2570 }
2571
2572 /* slli */
2573 void
2574 OP_3201 (void)
2575 {
2576 int64 tmp;
2577
2578 if (OP[1] == 0)
2579 OP[1] = 16;
2580
2581 trace_input ("slli", OP_ACCUM, OP_CONSTANT16, OP_VOID);
2582 tmp = SEXT40(ACC (OP[0])) << OP[1];
2583
2584 if (PSW_ST)
2585 {
2586 if (tmp > SEXT40(MAX32))
2587 tmp = (MAX32);
2588 else if (tmp < SEXT40(MIN32))
2589 tmp = (MIN32);
2590 else
2591 tmp = (tmp & MASK40);
2592 }
2593 else
2594 tmp = (tmp & MASK40);
2595 SET_ACC (OP[0], tmp);
2596 trace_output_40 (tmp);
2597 }
2598
2599 /* slx */
2600 void
2601 OP_460B (void)
2602 {
2603 int16 tmp;
2604 trace_input ("slx", OP_REG, OP_VOID, OP_VOID);
2605 tmp = ((GPR (OP[0]) << 1) | PSW_F0);
2606 SET_GPR (OP[0], tmp);
2607 trace_output_16 (tmp);
2608 }
2609
2610 /* sra */
2611 void
2612 OP_2400 (void)
2613 {
2614 int16 tmp;
2615 trace_input ("sra", OP_REG, OP_REG, OP_VOID);
2616 tmp = (((int16)(GPR (OP[0]))) >> (GPR (OP[1]) & 0xf));
2617 SET_GPR (OP[0], tmp);
2618 trace_output_16 (tmp);
2619 }
2620
2621 /* sra */
2622 void
2623 OP_3400 (void)
2624 {
2625 trace_input ("sra", OP_ACCUM, OP_REG, OP_VOID);
2626 if ((GPR (OP[1]) & 31) <= 16)
2627 {
2628 int64 tmp = ((SEXT40(ACC (OP[0])) >> (GPR (OP[1]) & 31)) & MASK40);
2629 SET_ACC (OP[0], tmp);
2630 trace_output_40 (tmp);
2631 }
2632 else
2633 {
2634 (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: shift value %d too large.\n", GPR (OP[1]) & 31);
2635 State.exception = SIGILL;
2636 return;
2637 }
2638 }
2639
2640 /* srai */
2641 void
2642 OP_2401 (void)
2643 {
2644 int16 tmp;
2645 trace_input ("srai", OP_REG, OP_CONSTANT16, OP_VOID);
2646 tmp = (((int16)(GPR (OP[0]))) >> OP[1]);
2647 SET_GPR (OP[0], tmp);
2648 trace_output_16 (tmp);
2649 }
2650
2651 /* srai */
2652 void
2653 OP_3401 (void)
2654 {
2655 int64 tmp;
2656 if (OP[1] == 0)
2657 OP[1] = 16;
2658
2659 trace_input ("srai", OP_ACCUM, OP_CONSTANT16, OP_VOID);
2660 tmp = ((SEXT40(ACC (OP[0])) >> OP[1]) & MASK40);
2661 SET_ACC (OP[0], tmp);
2662 trace_output_40 (tmp);
2663 }
2664
2665 /* srl */
2666 void
2667 OP_2000 (void)
2668 {
2669 int16 tmp;
2670 trace_input ("srl", OP_REG, OP_REG, OP_VOID);
2671 tmp = (GPR (OP[0]) >> (GPR (OP[1]) & 0xf));
2672 SET_GPR (OP[0], tmp);
2673 trace_output_16 (tmp);
2674 }
2675
2676 /* srl */
2677 void
2678 OP_3000 (void)
2679 {
2680 trace_input ("srl", OP_ACCUM, OP_REG, OP_VOID);
2681 if ((GPR (OP[1]) & 31) <= 16)
2682 {
2683 int64 tmp = ((uint64)((ACC (OP[0]) & MASK40) >> (GPR (OP[1]) & 31)));
2684 SET_ACC (OP[0], tmp);
2685 trace_output_40 (tmp);
2686 }
2687 else
2688 {
2689 (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: shift value %d too large.\n", GPR (OP[1]) & 31);
2690 State.exception = SIGILL;
2691 return;
2692 }
2693
2694 }
2695
2696 /* srli */
2697 void
2698 OP_2001 (void)
2699 {
2700 int16 tmp;
2701 trace_input ("srli", OP_REG, OP_CONSTANT16, OP_VOID);
2702 tmp = (GPR (OP[0]) >> OP[1]);
2703 SET_GPR (OP[0], tmp);
2704 trace_output_16 (tmp);
2705 }
2706
2707 /* srli */
2708 void
2709 OP_3001 (void)
2710 {
2711 int64 tmp;
2712 if (OP[1] == 0)
2713 OP[1] = 16;
2714
2715 trace_input ("srli", OP_ACCUM, OP_CONSTANT16, OP_VOID);
2716 tmp = ((uint64)(ACC (OP[0]) & MASK40) >> OP[1]);
2717 SET_ACC (OP[0], tmp);
2718 trace_output_40 (tmp);
2719 }
2720
2721 /* srx */
2722 void
2723 OP_4609 (void)
2724 {
2725 uint16 tmp;
2726 trace_input ("srx", OP_REG, OP_VOID, OP_VOID);
2727 tmp = PSW_F0 << 15;
2728 tmp = ((GPR (OP[0]) >> 1) | tmp);
2729 SET_GPR (OP[0], tmp);
2730 trace_output_16 (tmp);
2731 }
2732
2733 /* st */
2734 void
2735 OP_34000000 (void)
2736 {
2737 uint16 addr = OP[1] + GPR (OP[2]);
2738 trace_input ("st", OP_REG, OP_MEMREF2, OP_VOID);
2739 if ((addr & 1))
2740 {
2741 State.exception = SIG_D10V_BUS;
2742 State.pc_changed = 1; /* Don't increment the PC. */
2743 trace_output_void ();
2744 return;
2745 }
2746 SW (addr, GPR (OP[0]));
2747 trace_output_void ();
2748 }
2749
2750 /* st */
2751 void
2752 OP_6800 (void)
2753 {
2754 uint16 addr = GPR (OP[1]);
2755 trace_input ("st", OP_REG, OP_MEMREF, OP_VOID);
2756 if ((addr & 1))
2757 {
2758 State.exception = SIG_D10V_BUS;
2759 State.pc_changed = 1; /* Don't increment the PC. */
2760 trace_output_void ();
2761 return;
2762 }
2763 SW (addr, GPR (OP[0]));
2764 trace_output_void ();
2765 }
2766
2767 /* st */
2768 /* st Rsrc1,@-SP */
2769 void
2770 OP_6C1F (void)
2771 {
2772 uint16 addr = GPR (OP[1]) - 2;
2773 trace_input ("st", OP_REG, OP_PREDEC, OP_VOID);
2774 if (OP[1] != 15)
2775 {
2776 (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: cannot pre-decrement any registers but r15 (SP).\n");
2777 State.exception = SIGILL;
2778 return;
2779 }
2780 if ((addr & 1))
2781 {
2782 State.exception = SIG_D10V_BUS;
2783 State.pc_changed = 1; /* Don't increment the PC. */
2784 trace_output_void ();
2785 return;
2786 }
2787 SW (addr, GPR (OP[0]));
2788 SET_GPR (OP[1], addr);
2789 trace_output_void ();
2790 }
2791
2792 /* st */
2793 void
2794 OP_6801 (void)
2795 {
2796 uint16 addr = GPR (OP[1]);
2797 trace_input ("st", OP_REG, OP_POSTINC, OP_VOID);
2798 if ((addr & 1))
2799 {
2800 State.exception = SIG_D10V_BUS;
2801 State.pc_changed = 1; /* Don't increment the PC. */
2802 trace_output_void ();
2803 return;
2804 }
2805 SW (addr, GPR (OP[0]));
2806 INC_ADDR (OP[1], 2);
2807 trace_output_void ();
2808 }
2809
2810 /* st */
2811 void
2812 OP_6C01 (void)
2813 {
2814 uint16 addr = GPR (OP[1]);
2815 trace_input ("st", OP_REG, OP_POSTDEC, OP_VOID);
2816 if ( OP[1] == 15 )
2817 {
2818 (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: cannot post-decrement register r15 (SP).\n");
2819 State.exception = SIGILL;
2820 return;
2821 }
2822 if ((addr & 1))
2823 {
2824 State.exception = SIG_D10V_BUS;
2825 State.pc_changed = 1; /* Don't increment the PC. */
2826 trace_output_void ();
2827 return;
2828 }
2829 SW (addr, GPR (OP[0]));
2830 INC_ADDR (OP[1], -2);
2831 trace_output_void ();
2832 }
2833
2834 /* st */
2835 void
2836 OP_36010000 (void)
2837 {
2838 uint16 addr = OP[1];
2839 trace_input ("st", OP_REG, OP_MEMREF3, OP_VOID);
2840 if ((addr & 1))
2841 {
2842 State.exception = SIG_D10V_BUS;
2843 State.pc_changed = 1; /* Don't increment the PC. */
2844 trace_output_void ();
2845 return;
2846 }
2847 SW (addr, GPR (OP[0]));
2848 trace_output_void ();
2849 }
2850
2851 /* st2w */
2852 void
2853 OP_35000000 (void)
2854 {
2855 uint16 addr = GPR (OP[2])+ OP[1];
2856 trace_input ("st2w", OP_DREG, OP_MEMREF2, OP_VOID);
2857 if ((addr & 1))
2858 {
2859 State.exception = SIG_D10V_BUS;
2860 State.pc_changed = 1; /* Don't increment the PC. */
2861 trace_output_void ();
2862 return;
2863 }
2864 SW (addr + 0, GPR (OP[0] + 0));
2865 SW (addr + 2, GPR (OP[0] + 1));
2866 trace_output_void ();
2867 }
2868
2869 /* st2w */
2870 void
2871 OP_6A00 (void)
2872 {
2873 uint16 addr = GPR (OP[1]);
2874 trace_input ("st2w", OP_DREG, OP_MEMREF, OP_VOID);
2875 if ((addr & 1))
2876 {
2877 State.exception = SIG_D10V_BUS;
2878 State.pc_changed = 1; /* Don't increment the PC. */
2879 trace_output_void ();
2880 return;
2881 }
2882 SW (addr + 0, GPR (OP[0] + 0));
2883 SW (addr + 2, GPR (OP[0] + 1));
2884 trace_output_void ();
2885 }
2886
2887 /* st2w */
2888 void
2889 OP_6E1F (void)
2890 {
2891 uint16 addr = GPR (OP[1]) - 4;
2892 trace_input ("st2w", OP_DREG, OP_PREDEC, OP_VOID);
2893 if ( OP[1] != 15 )
2894 {
2895 (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: cannot pre-decrement any registers but r15 (SP).\n");
2896 State.exception = SIGILL;
2897 return;
2898 }
2899 if ((addr & 1))
2900 {
2901 State.exception = SIG_D10V_BUS;
2902 State.pc_changed = 1; /* Don't increment the PC. */
2903 trace_output_void ();
2904 return;
2905 }
2906 SW (addr + 0, GPR (OP[0] + 0));
2907 SW (addr + 2, GPR (OP[0] + 1));
2908 SET_GPR (OP[1], addr);
2909 trace_output_void ();
2910 }
2911
2912 /* st2w */
2913 void
2914 OP_6A01 (void)
2915 {
2916 uint16 addr = GPR (OP[1]);
2917 trace_input ("st2w", OP_DREG, OP_POSTINC, OP_VOID);
2918 if ((addr & 1))
2919 {
2920 State.exception = SIG_D10V_BUS;
2921 State.pc_changed = 1; /* Don't increment the PC. */
2922 trace_output_void ();
2923 return;
2924 }
2925 SW (addr + 0, GPR (OP[0] + 0));
2926 SW (addr + 2, GPR (OP[0] + 1));
2927 INC_ADDR (OP[1], 4);
2928 trace_output_void ();
2929 }
2930
2931 /* st2w */
2932 void
2933 OP_6E01 (void)
2934 {
2935 uint16 addr = GPR (OP[1]);
2936 trace_input ("st2w", OP_DREG, OP_POSTDEC, OP_VOID);
2937 if ( OP[1] == 15 )
2938 {
2939 (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: cannot post-decrement register r15 (SP).\n");
2940 State.exception = SIGILL;
2941 return;
2942 }
2943 if ((addr & 1))
2944 {
2945 State.exception = SIG_D10V_BUS;
2946 State.pc_changed = 1; /* Don't increment the PC. */
2947 trace_output_void ();
2948 return;
2949 }
2950 SW (addr + 0, GPR (OP[0] + 0));
2951 SW (addr + 2, GPR (OP[0] + 1));
2952 INC_ADDR (OP[1], -4);
2953 trace_output_void ();
2954 }
2955
2956 /* st2w */
2957 void
2958 OP_37010000 (void)
2959 {
2960 uint16 addr = OP[1];
2961 trace_input ("st2w", OP_DREG, OP_MEMREF3, OP_VOID);
2962 if ((addr & 1))
2963 {
2964 State.exception = SIG_D10V_BUS;
2965 State.pc_changed = 1; /* Don't increment the PC. */
2966 trace_output_void ();
2967 return;
2968 }
2969 SW (addr + 0, GPR (OP[0] + 0));
2970 SW (addr + 2, GPR (OP[0] + 1));
2971 trace_output_void ();
2972 }
2973
2974 /* stb */
2975 void
2976 OP_3C000000 (void)
2977 {
2978 trace_input ("stb", OP_REG, OP_MEMREF2, OP_VOID);
2979 SB (GPR (OP[2]) + OP[1], GPR (OP[0]));
2980 trace_output_void ();
2981 }
2982
2983 /* stb */
2984 void
2985 OP_7800 (void)
2986 {
2987 trace_input ("stb", OP_REG, OP_MEMREF, OP_VOID);
2988 SB (GPR (OP[1]), GPR (OP[0]));
2989 trace_output_void ();
2990 }
2991
2992 /* stop */
2993 void
2994 OP_5FE0 (void)
2995 {
2996 trace_input ("stop", OP_VOID, OP_VOID, OP_VOID);
2997 State.exception = SIG_D10V_STOP;
2998 trace_output_void ();
2999 }
3000
3001 /* sub */
3002 void
3003 OP_0 (void)
3004 {
3005 uint16 a = GPR (OP[0]);
3006 uint16 b = GPR (OP[1]);
3007 uint16 tmp = (a - b);
3008 trace_input ("sub", OP_REG, OP_REG, OP_VOID);
3009 /* see ../common/sim-alu.h for a more extensive discussion on how to
3010 compute the carry/overflow bits. */
3011 SET_PSW_C (a >= b);
3012 SET_GPR (OP[0], tmp);
3013 trace_output_16 (tmp);
3014 }
3015
3016 /* sub */
3017 void
3018 OP_1001 (void)
3019 {
3020 int64 tmp;
3021
3022 trace_input ("sub", OP_ACCUM, OP_DREG, OP_VOID);
3023 tmp = SEXT40(ACC (OP[0])) - (SEXT16 (GPR (OP[1])) << 16 | GPR (OP[1] + 1));
3024 if (PSW_ST)
3025 {
3026 if (tmp > SEXT40(MAX32))
3027 tmp = (MAX32);
3028 else if (tmp < SEXT40(MIN32))
3029 tmp = (MIN32);
3030 else
3031 tmp = (tmp & MASK40);
3032 }
3033 else
3034 tmp = (tmp & MASK40);
3035 SET_ACC (OP[0], tmp);
3036
3037 trace_output_40 (tmp);
3038 }
3039
3040 /* sub */
3041
3042 void
3043 OP_1003 (void)
3044 {
3045 int64 tmp;
3046
3047 trace_input ("sub", OP_ACCUM, OP_ACCUM, OP_VOID);
3048 tmp = SEXT40(ACC (OP[0])) - SEXT40(ACC (OP[1]));
3049 if (PSW_ST)
3050 {
3051 if (tmp > SEXT40(MAX32))
3052 tmp = (MAX32);
3053 else if (tmp < SEXT40(MIN32))
3054 tmp = (MIN32);
3055 else
3056 tmp = (tmp & MASK40);
3057 }
3058 else
3059 tmp = (tmp & MASK40);
3060 SET_ACC (OP[0], tmp);
3061
3062 trace_output_40 (tmp);
3063 }
3064
3065 /* sub2w */
3066 void
3067 OP_1000 (void)
3068 {
3069 uint32 tmp, a, b;
3070
3071 trace_input ("sub2w", OP_DREG, OP_DREG, OP_VOID);
3072 a = (uint32)((GPR (OP[0]) << 16) | GPR (OP[0] + 1));
3073 b = (uint32)((GPR (OP[1]) << 16) | GPR (OP[1] + 1));
3074 /* see ../common/sim-alu.h for a more extensive discussion on how to
3075 compute the carry/overflow bits */
3076 tmp = a - b;
3077 SET_PSW_C (a >= b);
3078 SET_GPR32 (OP[0], tmp);
3079 trace_output_32 (tmp);
3080 }
3081
3082 /* subac3 */
3083 void
3084 OP_17000000 (void)
3085 {
3086 int64 tmp;
3087
3088 trace_input ("subac3", OP_DREG_OUTPUT, OP_DREG, OP_ACCUM);
3089 tmp = SEXT40 ((GPR (OP[1]) << 16) | GPR (OP[1] + 1)) - SEXT40 (ACC (OP[2]));
3090 SET_GPR32 (OP[0], tmp);
3091 trace_output_32 (tmp);
3092 }
3093
3094 /* subac3 */
3095 void
3096 OP_17000002 (void)
3097 {
3098 int64 tmp;
3099
3100 trace_input ("subac3", OP_DREG_OUTPUT, OP_ACCUM, OP_ACCUM);
3101 tmp = SEXT40 (ACC (OP[1])) - SEXT40(ACC (OP[2]));
3102 SET_GPR32 (OP[0], tmp);
3103 trace_output_32 (tmp);
3104 }
3105
3106 /* subac3s */
3107 void
3108 OP_17001000 (void)
3109 {
3110 int64 tmp;
3111
3112 trace_input ("subac3s", OP_DREG_OUTPUT, OP_DREG, OP_ACCUM);
3113 SET_PSW_F1 (PSW_F0);
3114 tmp = SEXT40 ((GPR (OP[1]) << 16) | GPR (OP[1] + 1)) - SEXT40(ACC (OP[2]));
3115 if (tmp > SEXT40(MAX32))
3116 {
3117 tmp = (MAX32);
3118 SET_PSW_F0 (1);
3119 }
3120 else if (tmp < SEXT40(MIN32))
3121 {
3122 tmp = (MIN32);
3123 SET_PSW_F0 (1);
3124 }
3125 else
3126 {
3127 SET_PSW_F0 (0);
3128 }
3129 SET_GPR32 (OP[0], tmp);
3130 trace_output_32 (tmp);
3131 }
3132
3133 /* subac3s */
3134 void
3135 OP_17001002 (void)
3136 {
3137 int64 tmp;
3138
3139 trace_input ("subac3s", OP_DREG_OUTPUT, OP_ACCUM, OP_ACCUM);
3140 SET_PSW_F1 (PSW_F0);
3141 tmp = SEXT40(ACC (OP[1])) - SEXT40(ACC (OP[2]));
3142 if (tmp > SEXT40(MAX32))
3143 {
3144 tmp = (MAX32);
3145 SET_PSW_F0 (1);
3146 }
3147 else if (tmp < SEXT40(MIN32))
3148 {
3149 tmp = (MIN32);
3150 SET_PSW_F0 (1);
3151 }
3152 else
3153 {
3154 SET_PSW_F0 (0);
3155 }
3156 SET_GPR32 (OP[0], tmp);
3157 trace_output_32 (tmp);
3158 }
3159
3160 /* subi */
3161 void
3162 OP_1 (void)
3163 {
3164 unsigned tmp;
3165 if (OP[1] == 0)
3166 OP[1] = 16;
3167
3168 trace_input ("subi", OP_REG, OP_CONSTANT16, OP_VOID);
3169 /* see ../common/sim-alu.h for a more extensive discussion on how to
3170 compute the carry/overflow bits. */
3171 /* since OP[1] is never <= 0, -OP[1] == ~OP[1]+1 can never overflow */
3172 tmp = ((unsigned)(unsigned16) GPR (OP[0])
3173 + (unsigned)(unsigned16) ( - OP[1]));
3174 SET_PSW_C (tmp >= (1 << 16));
3175 SET_GPR (OP[0], tmp);
3176 trace_output_16 (tmp);
3177 }
3178
3179 /* trap */
3180 void
3181 OP_5F00 (void)
3182 {
3183 trace_input ("trap", OP_CONSTANT4, OP_VOID, OP_VOID);
3184 trace_output_void ();
3185
3186 switch (OP[0])
3187 {
3188 default:
3189 #if (DEBUG & DEBUG_TRAP) == 0
3190 {
3191 uint16 vec = OP[0] + TRAP_VECTOR_START;
3192 SET_BPC (PC + 1);
3193 SET_BPSW (PSW);
3194 SET_PSW (PSW & PSW_SM_BIT);
3195 JMP (vec);
3196 break;
3197 }
3198 #else /* if debugging use trap to print registers */
3199 {
3200 int i;
3201 static int first_time = 1;
3202
3203 if (first_time)
3204 {
3205 first_time = 0;
3206 (*d10v_callback->printf_filtered) (d10v_callback, "Trap # PC ");
3207 for (i = 0; i < 16; i++)
3208 (*d10v_callback->printf_filtered) (d10v_callback, " %sr%d", (i > 9) ? "" : " ", i);
3209 (*d10v_callback->printf_filtered) (d10v_callback, " a0 a1 f0 f1 c\n");
3210 }
3211
3212 (*d10v_callback->printf_filtered) (d10v_callback, "Trap %2d 0x%.4x:", (int)OP[0], (int)PC);
3213
3214 for (i = 0; i < 16; i++)
3215 (*d10v_callback->printf_filtered) (d10v_callback, " %.4x", (int) GPR (i));
3216
3217 for (i = 0; i < 2; i++)
3218 (*d10v_callback->printf_filtered) (d10v_callback, " %.2x%.8lx",
3219 ((int)(ACC (i) >> 32) & 0xff),
3220 ((unsigned long) ACC (i)) & 0xffffffff);
3221
3222 (*d10v_callback->printf_filtered) (d10v_callback, " %d %d %d\n",
3223 PSW_F0 != 0, PSW_F1 != 0, PSW_C != 0);
3224 (*d10v_callback->flush_stdout) (d10v_callback);
3225 break;
3226 }
3227 #endif
3228 case 15: /* new system call trap */
3229 /* Trap 15 is used for simulating low-level I/O */
3230 {
3231 unsigned32 result = 0;
3232 errno = 0;
3233
3234 /* Registers passed to trap 0 */
3235
3236 #define FUNC GPR (4) /* function number */
3237 #define PARM1 GPR (0) /* optional parm 1 */
3238 #define PARM2 GPR (1) /* optional parm 2 */
3239 #define PARM3 GPR (2) /* optional parm 3 */
3240 #define PARM4 GPR (3) /* optional parm 3 */
3241
3242 /* Registers set by trap 0 */
3243
3244 #define RETVAL(X) do { result = (X); SET_GPR (0, result); } while (0)
3245 #define RETVAL32(X) do { result = (X); SET_GPR (0, result >> 16); SET_GPR (1, result); } while (0)
3246 #define RETERR(X) SET_GPR (4, (X)) /* return error code */
3247
3248 /* Turn a pointer in a register into a pointer into real memory. */
3249
3250 #define MEMPTR(x) ((char *)(dmem_addr(x)))
3251
3252 switch (FUNC)
3253 {
3254 #if !defined(__GO32__) && !defined(_WIN32)
3255 case TARGET_SYS_fork:
3256 trace_input ("<fork>", OP_VOID, OP_VOID, OP_VOID);
3257 RETVAL (fork ());
3258 trace_output_16 (result);
3259 break;
3260
3261 #define getpid() 47
3262 case TARGET_SYS_getpid:
3263 trace_input ("<getpid>", OP_VOID, OP_VOID, OP_VOID);
3264 RETVAL (getpid ());
3265 trace_output_16 (result);
3266 break;
3267
3268 case TARGET_SYS_kill:
3269 trace_input ("<kill>", OP_R0, OP_R1, OP_VOID);
3270 if (PARM1 == getpid ())
3271 {
3272 trace_output_void ();
3273 State.exception = PARM2;
3274 }
3275 else
3276 {
3277 int os_sig = -1;
3278 switch (PARM2)
3279 {
3280 #ifdef SIGHUP
3281 case 1: os_sig = SIGHUP; break;
3282 #endif
3283 #ifdef SIGINT
3284 case 2: os_sig = SIGINT; break;
3285 #endif
3286 #ifdef SIGQUIT
3287 case 3: os_sig = SIGQUIT; break;
3288 #endif
3289 #ifdef SIGILL
3290 case 4: os_sig = SIGILL; break;
3291 #endif
3292 #ifdef SIGTRAP
3293 case 5: os_sig = SIGTRAP; break;
3294 #endif
3295 #ifdef SIGABRT
3296 case 6: os_sig = SIGABRT; break;
3297 #elif defined(SIGIOT)
3298 case 6: os_sig = SIGIOT; break;
3299 #endif
3300 #ifdef SIGEMT
3301 case 7: os_sig = SIGEMT; break;
3302 #endif
3303 #ifdef SIGFPE
3304 case 8: os_sig = SIGFPE; break;
3305 #endif
3306 #ifdef SIGKILL
3307 case 9: os_sig = SIGKILL; break;
3308 #endif
3309 #ifdef SIGBUS
3310 case 10: os_sig = SIGBUS; break;
3311 #endif
3312 #ifdef SIGSEGV
3313 case 11: os_sig = SIGSEGV; break;
3314 #endif
3315 #ifdef SIGSYS
3316 case 12: os_sig = SIGSYS; break;
3317 #endif
3318 #ifdef SIGPIPE
3319 case 13: os_sig = SIGPIPE; break;
3320 #endif
3321 #ifdef SIGALRM
3322 case 14: os_sig = SIGALRM; break;
3323 #endif
3324 #ifdef SIGTERM
3325 case 15: os_sig = SIGTERM; break;
3326 #endif
3327 #ifdef SIGURG
3328 case 16: os_sig = SIGURG; break;
3329 #endif
3330 #ifdef SIGSTOP
3331 case 17: os_sig = SIGSTOP; break;
3332 #endif
3333 #ifdef SIGTSTP
3334 case 18: os_sig = SIGTSTP; break;
3335 #endif
3336 #ifdef SIGCONT
3337 case 19: os_sig = SIGCONT; break;
3338 #endif
3339 #ifdef SIGCHLD
3340 case 20: os_sig = SIGCHLD; break;
3341 #elif defined(SIGCLD)
3342 case 20: os_sig = SIGCLD; break;
3343 #endif
3344 #ifdef SIGTTIN
3345 case 21: os_sig = SIGTTIN; break;
3346 #endif
3347 #ifdef SIGTTOU
3348 case 22: os_sig = SIGTTOU; break;
3349 #endif
3350 #ifdef SIGIO
3351 case 23: os_sig = SIGIO; break;
3352 #elif defined (SIGPOLL)
3353 case 23: os_sig = SIGPOLL; break;
3354 #endif
3355 #ifdef SIGXCPU
3356 case 24: os_sig = SIGXCPU; break;
3357 #endif
3358 #ifdef SIGXFSZ
3359 case 25: os_sig = SIGXFSZ; break;
3360 #endif
3361 #ifdef SIGVTALRM
3362 case 26: os_sig = SIGVTALRM; break;
3363 #endif
3364 #ifdef SIGPROF
3365 case 27: os_sig = SIGPROF; break;
3366 #endif
3367 #ifdef SIGWINCH
3368 case 28: os_sig = SIGWINCH; break;
3369 #endif
3370 #ifdef SIGLOST
3371 case 29: os_sig = SIGLOST; break;
3372 #endif
3373 #ifdef SIGUSR1
3374 case 30: os_sig = SIGUSR1; break;
3375 #endif
3376 #ifdef SIGUSR2
3377 case 31: os_sig = SIGUSR2; break;
3378 #endif
3379 }
3380
3381 if (os_sig == -1)
3382 {
3383 trace_output_void ();
3384 (*d10v_callback->printf_filtered) (d10v_callback, "Unknown signal %d\n", PARM2);
3385 (*d10v_callback->flush_stdout) (d10v_callback);
3386 State.exception = SIGILL;
3387 }
3388 else
3389 {
3390 RETVAL (kill (PARM1, PARM2));
3391 trace_output_16 (result);
3392 }
3393 }
3394 break;
3395
3396 case TARGET_SYS_execve:
3397 trace_input ("<execve>", OP_R0, OP_R1, OP_R2);
3398 RETVAL (execve (MEMPTR (PARM1), (char **) MEMPTR (PARM2),
3399 (char **)MEMPTR (PARM3)));
3400 trace_output_16 (result);
3401 break;
3402
3403 #ifdef TARGET_SYS_execv
3404 case TARGET_SYS_execv:
3405 trace_input ("<execv>", OP_R0, OP_R1, OP_VOID);
3406 RETVAL (execve (MEMPTR (PARM1), (char **) MEMPTR (PARM2), NULL));
3407 trace_output_16 (result);
3408 break;
3409 #endif
3410
3411 case TARGET_SYS_pipe:
3412 {
3413 reg_t buf;
3414 int host_fd[2];
3415
3416 trace_input ("<pipe>", OP_R0, OP_VOID, OP_VOID);
3417 buf = PARM1;
3418 RETVAL (pipe (host_fd));
3419 SW (buf, host_fd[0]);
3420 buf += sizeof(uint16);
3421 SW (buf, host_fd[1]);
3422 trace_output_16 (result);
3423 }
3424 break;
3425
3426 #if 0
3427 #ifdef TARGET_SYS_wait
3428 case TARGET_SYS_wait:
3429 {
3430 int status;
3431 trace_input ("<wait>", OP_R0, OP_VOID, OP_VOID);
3432 RETVAL (wait (&status));
3433 if (PARM1)
3434 SW (PARM1, status);
3435 trace_output_16 (result);
3436 }
3437 break;
3438 #endif
3439 #endif
3440 #else
3441 case TARGET_SYS_getpid:
3442 trace_input ("<getpid>", OP_VOID, OP_VOID, OP_VOID);
3443 RETVAL (1);
3444 trace_output_16 (result);
3445 break;
3446
3447 case TARGET_SYS_kill:
3448 trace_input ("<kill>", OP_REG, OP_REG, OP_VOID);
3449 trace_output_void ();
3450 State.exception = PARM2;
3451 break;
3452 #endif
3453
3454 case TARGET_SYS_read:
3455 trace_input ("<read>", OP_R0, OP_R1, OP_R2);
3456 RETVAL (d10v_callback->read (d10v_callback, PARM1, MEMPTR (PARM2),
3457 PARM3));
3458 trace_output_16 (result);
3459 break;
3460
3461 case TARGET_SYS_write:
3462 trace_input ("<write>", OP_R0, OP_R1, OP_R2);
3463 if (PARM1 == 1)
3464 RETVAL ((int)d10v_callback->write_stdout (d10v_callback,
3465 MEMPTR (PARM2), PARM3));
3466 else
3467 RETVAL ((int)d10v_callback->write (d10v_callback, PARM1,
3468 MEMPTR (PARM2), PARM3));
3469 trace_output_16 (result);
3470 break;
3471
3472 case TARGET_SYS_lseek:
3473 trace_input ("<lseek>", OP_R0, OP_R1, OP_R2);
3474 RETVAL32 (d10v_callback->lseek (d10v_callback, PARM1,
3475 ((((unsigned long) PARM2) << 16)
3476 || (unsigned long) PARM3),
3477 PARM4));
3478 trace_output_32 (result);
3479 break;
3480
3481 case TARGET_SYS_close:
3482 trace_input ("<close>", OP_R0, OP_VOID, OP_VOID);
3483 RETVAL (d10v_callback->close (d10v_callback, PARM1));
3484 trace_output_16 (result);
3485 break;
3486
3487 case TARGET_SYS_open:
3488 trace_input ("<open>", OP_R0, OP_R1, OP_R2);
3489 RETVAL (d10v_callback->open (d10v_callback, MEMPTR (PARM1), PARM2));
3490 trace_output_16 (result);
3491 break;
3492
3493 case TARGET_SYS_exit:
3494 trace_input ("<exit>", OP_R0, OP_VOID, OP_VOID);
3495 State.exception = SIG_D10V_EXIT;
3496 trace_output_void ();
3497 break;
3498
3499 #ifdef TARGET_SYS_stat
3500 case TARGET_SYS_stat:
3501 trace_input ("<stat>", OP_R0, OP_R1, OP_VOID);
3502 /* stat system call */
3503 {
3504 struct stat host_stat;
3505 reg_t buf;
3506
3507 RETVAL (stat (MEMPTR (PARM1), &host_stat));
3508
3509 buf = PARM2;
3510
3511 /* The hard-coded offsets and sizes were determined by using
3512 * the D10V compiler on a test program that used struct stat.
3513 */
3514 SW (buf, host_stat.st_dev);
3515 SW (buf+2, host_stat.st_ino);
3516 SW (buf+4, host_stat.st_mode);
3517 SW (buf+6, host_stat.st_nlink);
3518 SW (buf+8, host_stat.st_uid);
3519 SW (buf+10, host_stat.st_gid);
3520 SW (buf+12, host_stat.st_rdev);
3521 SLW (buf+16, host_stat.st_size);
3522 SLW (buf+20, host_stat.st_atime);
3523 SLW (buf+28, host_stat.st_mtime);
3524 SLW (buf+36, host_stat.st_ctime);
3525 }
3526 trace_output_16 (result);
3527 break;
3528 #endif
3529
3530 case TARGET_SYS_chown:
3531 trace_input ("<chown>", OP_R0, OP_R1, OP_R2);
3532 RETVAL (chown (MEMPTR (PARM1), PARM2, PARM3));
3533 trace_output_16 (result);
3534 break;
3535
3536 case TARGET_SYS_chmod:
3537 trace_input ("<chmod>", OP_R0, OP_R1, OP_R2);
3538 RETVAL (chmod (MEMPTR (PARM1), PARM2));
3539 trace_output_16 (result);
3540 break;
3541
3542 #if 0
3543 #ifdef TARGET_SYS_utime
3544 case TARGET_SYS_utime:
3545 trace_input ("<utime>", OP_R0, OP_R1, OP_R2);
3546 /* Cast the second argument to void *, to avoid type mismatch
3547 if a prototype is present. */
3548 RETVAL (utime (MEMPTR (PARM1), (void *) MEMPTR (PARM2)));
3549 trace_output_16 (result);
3550 break;
3551 #endif
3552 #endif
3553
3554 #if 0
3555 #ifdef TARGET_SYS_time
3556 case TARGET_SYS_time:
3557 trace_input ("<time>", OP_R0, OP_R1, OP_R2);
3558 RETVAL32 (time (PARM1 ? MEMPTR (PARM1) : NULL));
3559 trace_output_32 (result);
3560 break;
3561 #endif
3562 #endif
3563
3564 default:
3565 d10v_callback->error (d10v_callback, "Unknown syscall %d", FUNC);
3566 }
3567 if ((uint16) result == (uint16) -1)
3568 RETERR (d10v_callback->get_errno(d10v_callback));
3569 else
3570 RETERR (0);
3571 break;
3572 }
3573 }
3574 }
3575
3576 /* tst0i */
3577 void
3578 OP_7000000 (void)
3579 {
3580 trace_input ("tst0i", OP_REG, OP_CONSTANT16, OP_VOID);
3581 SET_PSW_F1 (PSW_F0);;
3582 SET_PSW_F0 ((GPR (OP[0]) & OP[1]) ? 1 : 0);
3583 trace_output_flag ();
3584 }
3585
3586 /* tst1i */
3587 void
3588 OP_F000000 (void)
3589 {
3590 trace_input ("tst1i", OP_REG, OP_CONSTANT16, OP_VOID);
3591 SET_PSW_F1 (PSW_F0);
3592 SET_PSW_F0 ((~(GPR (OP[0])) & OP[1]) ? 1 : 0);
3593 trace_output_flag ();
3594 }
3595
3596 /* wait */
3597 void
3598 OP_5F80 (void)
3599 {
3600 trace_input ("wait", OP_VOID, OP_VOID, OP_VOID);
3601 SET_PSW_IE (1);
3602 trace_output_void ();
3603 }
3604
3605 /* xor */
3606 void
3607 OP_A00 (void)
3608 {
3609 int16 tmp;
3610 trace_input ("xor", OP_REG, OP_REG, OP_VOID);
3611 tmp = (GPR (OP[0]) ^ GPR (OP[1]));
3612 SET_GPR (OP[0], tmp);
3613 trace_output_16 (tmp);
3614 }
3615
3616 /* xor3 */
3617 void
3618 OP_5000000 (void)
3619 {
3620 int16 tmp;
3621 trace_input ("xor3", OP_REG_OUTPUT, OP_REG, OP_CONSTANT16);
3622 tmp = (GPR (OP[1]) ^ OP[2]);
3623 SET_GPR (OP[0], tmp);
3624 trace_output_16 (tmp);
3625 }
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