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For "mulxu", store unsigned product in ACC.
[thirdparty/binutils-gdb.git] / sim / d10v / simops.c
1 #include "config.h"
2
3 #include <signal.h>
4 #include <errno.h>
5 #include <sys/types.h>
6 #include <sys/stat.h>
7 #ifdef HAVE_UNISTD_H
8 #include <unistd.h>
9 #endif
10
11 #include "d10v_sim.h"
12 #include "simops.h"
13 #include "sys/syscall.h"
14
15 extern char *strrchr ();
16
17 enum op_types {
18 OP_VOID,
19 OP_REG,
20 OP_REG_OUTPUT,
21 OP_DREG,
22 OP_DREG_OUTPUT,
23 OP_ACCUM,
24 OP_ACCUM_OUTPUT,
25 OP_ACCUM_REVERSE,
26 OP_CR,
27 OP_CR_OUTPUT,
28 OP_CR_REVERSE,
29 OP_FLAG,
30 OP_FLAG_OUTPUT,
31 OP_CONSTANT16,
32 OP_CONSTANT8,
33 OP_CONSTANT3,
34 OP_CONSTANT4,
35 OP_MEMREF,
36 OP_MEMREF2,
37 OP_POSTDEC,
38 OP_POSTINC,
39 OP_PREDEC,
40 OP_R2,
41 OP_R3,
42 OP_R4,
43 OP_R2R3
44 };
45
46 #ifdef DEBUG
47 static void trace_input_func PARAMS ((char *name,
48 enum op_types in1,
49 enum op_types in2,
50 enum op_types in3));
51
52 #define trace_input(name, in1, in2, in3) do { if (d10v_debug) trace_input_func (name, in1, in2, in3); } while (0)
53
54 static void trace_output_func PARAMS ((enum op_types result));
55
56 #define trace_output(result) do { if (d10v_debug) trace_output_func (result); } while (0)
57
58 #ifndef SIZE_INSTRUCTION
59 #define SIZE_INSTRUCTION 8
60 #endif
61
62 #ifndef SIZE_OPERANDS
63 #define SIZE_OPERANDS 18
64 #endif
65
66 #ifndef SIZE_VALUES
67 #define SIZE_VALUES 13
68 #endif
69
70 #ifndef SIZE_LOCATION
71 #define SIZE_LOCATION 20
72 #endif
73
74 #ifndef SIZE_PC
75 #define SIZE_PC 6
76 #endif
77
78 #ifndef SIZE_LINE_NUMBER
79 #define SIZE_LINE_NUMBER 4
80 #endif
81
82 static void
83 trace_input_func (name, in1, in2, in3)
84 char *name;
85 enum op_types in1;
86 enum op_types in2;
87 enum op_types in3;
88 {
89 char *comma;
90 enum op_types in[3];
91 int i;
92 char buf[1024];
93 char *p;
94 long tmp;
95 char *type;
96 const char *filename;
97 const char *functionname;
98 unsigned int linenumber;
99 bfd_vma byte_pc;
100
101 if ((d10v_debug & DEBUG_TRACE) == 0)
102 return;
103
104 switch (State.ins_type)
105 {
106 default:
107 case INS_UNKNOWN: type = " ?"; break;
108 case INS_LEFT: type = " L"; break;
109 case INS_RIGHT: type = " R"; break;
110 case INS_LEFT_PARALLEL: type = "*L"; break;
111 case INS_RIGHT_PARALLEL: type = "*R"; break;
112 case INS_LEFT_COND_TEST: type = "?L"; break;
113 case INS_RIGHT_COND_TEST: type = "?R"; break;
114 case INS_LEFT_COND_EXE: type = "&L"; break;
115 case INS_RIGHT_COND_EXE: type = "&R"; break;
116 case INS_LONG: type = " B"; break;
117 }
118
119 if ((d10v_debug & DEBUG_LINE_NUMBER) == 0)
120 (*d10v_callback->printf_filtered) (d10v_callback,
121 "0x%.*x %s: %-*s ",
122 SIZE_PC, (unsigned)PC,
123 type,
124 SIZE_INSTRUCTION, name);
125
126 else
127 {
128 buf[0] = '\0';
129 byte_pc = decode_pc ();
130 if (text && byte_pc >= text_start && byte_pc < text_end)
131 {
132 filename = (const char *)0;
133 functionname = (const char *)0;
134 linenumber = 0;
135 if (bfd_find_nearest_line (prog_bfd, text, (struct symbol_cache_entry **)0, byte_pc - text_start,
136 &filename, &functionname, &linenumber))
137 {
138 p = buf;
139 if (linenumber)
140 {
141 sprintf (p, "#%-*d ", SIZE_LINE_NUMBER, linenumber);
142 p += strlen (p);
143 }
144 else
145 {
146 sprintf (p, "%-*s ", SIZE_LINE_NUMBER+1, "---");
147 p += SIZE_LINE_NUMBER+2;
148 }
149
150 if (functionname)
151 {
152 sprintf (p, "%s ", functionname);
153 p += strlen (p);
154 }
155 else if (filename)
156 {
157 char *q = strrchr (filename, '/');
158 sprintf (p, "%s ", (q) ? q+1 : filename);
159 p += strlen (p);
160 }
161
162 if (*p == ' ')
163 *p = '\0';
164 }
165 }
166
167 (*d10v_callback->printf_filtered) (d10v_callback,
168 "0x%.*x %s: %-*.*s %-*s ",
169 SIZE_PC, (unsigned)PC,
170 type,
171 SIZE_LOCATION, SIZE_LOCATION, buf,
172 SIZE_INSTRUCTION, name);
173 }
174
175 in[0] = in1;
176 in[1] = in2;
177 in[2] = in3;
178 comma = "";
179 p = buf;
180 for (i = 0; i < 3; i++)
181 {
182 switch (in[i])
183 {
184 case OP_VOID:
185 case OP_R2:
186 case OP_R3:
187 case OP_R4:
188 case OP_R2R3:
189 break;
190
191 case OP_REG:
192 case OP_REG_OUTPUT:
193 case OP_DREG:
194 case OP_DREG_OUTPUT:
195 sprintf (p, "%sr%d", comma, OP[i]);
196 p += strlen (p);
197 comma = ",";
198 break;
199
200 case OP_CR:
201 case OP_CR_OUTPUT:
202 case OP_CR_REVERSE:
203 sprintf (p, "%scr%d", comma, OP[i]);
204 p += strlen (p);
205 comma = ",";
206 break;
207
208 case OP_ACCUM:
209 case OP_ACCUM_OUTPUT:
210 case OP_ACCUM_REVERSE:
211 sprintf (p, "%sa%d", comma, OP[i]);
212 p += strlen (p);
213 comma = ",";
214 break;
215
216 case OP_CONSTANT16:
217 sprintf (p, "%s%d", comma, OP[i]);
218 p += strlen (p);
219 comma = ",";
220 break;
221
222 case OP_CONSTANT8:
223 sprintf (p, "%s%d", comma, SEXT8(OP[i]));
224 p += strlen (p);
225 comma = ",";
226 break;
227
228 case OP_CONSTANT4:
229 sprintf (p, "%s%d", comma, SEXT4(OP[i]));
230 p += strlen (p);
231 comma = ",";
232 break;
233
234 case OP_CONSTANT3:
235 sprintf (p, "%s%d", comma, SEXT3(OP[i]));
236 p += strlen (p);
237 comma = ",";
238 break;
239
240 case OP_MEMREF:
241 sprintf (p, "%s@r%d", comma, OP[i]);
242 p += strlen (p);
243 comma = ",";
244 break;
245
246 case OP_MEMREF2:
247 sprintf (p, "%s@(%d,r%d)", comma, (int16)OP[i], OP[i+1]);
248 p += strlen (p);
249 comma = ",";
250 break;
251
252 case OP_POSTINC:
253 sprintf (p, "%s@r%d+", comma, OP[i]);
254 p += strlen (p);
255 comma = ",";
256 break;
257
258 case OP_POSTDEC:
259 sprintf (p, "%s@r%d-", comma, OP[i]);
260 p += strlen (p);
261 comma = ",";
262 break;
263
264 case OP_PREDEC:
265 sprintf (p, "%s@-r%d", comma, OP[i]);
266 p += strlen (p);
267 comma = ",";
268 break;
269
270 case OP_FLAG:
271 case OP_FLAG_OUTPUT:
272 if (OP[i] == 0)
273 sprintf (p, "%sf0", comma);
274
275 else if (OP[i] == 1)
276 sprintf (p, "%sf1", comma);
277
278 else
279 sprintf (p, "%sc", comma);
280
281 p += strlen (p);
282 comma = ",";
283 break;
284 }
285 }
286
287 if ((d10v_debug & DEBUG_VALUES) == 0)
288 {
289 *p++ = '\n';
290 *p = '\0';
291 (*d10v_callback->printf_filtered) (d10v_callback, "%s", buf);
292 }
293 else
294 {
295 *p = '\0';
296 (*d10v_callback->printf_filtered) (d10v_callback, "%-*s", SIZE_OPERANDS, buf);
297
298 p = buf;
299 for (i = 0; i < 3; i++)
300 {
301 buf[0] = '\0';
302 switch (in[i])
303 {
304 case OP_VOID:
305 (*d10v_callback->printf_filtered) (d10v_callback, "%*s", SIZE_VALUES, "");
306 break;
307
308 case OP_REG_OUTPUT:
309 case OP_DREG_OUTPUT:
310 case OP_CR_OUTPUT:
311 case OP_ACCUM_OUTPUT:
312 case OP_FLAG_OUTPUT:
313 (*d10v_callback->printf_filtered) (d10v_callback, "%*s", SIZE_VALUES, "---");
314 break;
315
316 case OP_REG:
317 case OP_MEMREF:
318 case OP_POSTDEC:
319 case OP_POSTINC:
320 case OP_PREDEC:
321 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
322 (uint16)State.regs[OP[i]]);
323 break;
324
325 case OP_DREG:
326 tmp = (long)((((uint32) State.regs[OP[i]]) << 16) | ((uint32) State.regs[OP[i]+1]));
327 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.8lx", SIZE_VALUES-10, "", tmp);
328 break;
329
330 case OP_CR:
331 case OP_CR_REVERSE:
332 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
333 (uint16)State.cregs[OP[i]]);
334 break;
335
336 case OP_ACCUM:
337 case OP_ACCUM_REVERSE:
338 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.2x%.8lx", SIZE_VALUES-12, "",
339 ((int)(State.a[OP[i]] >> 32) & 0xff),
340 ((unsigned long)State.a[OP[i]]) & 0xffffffff);
341 break;
342
343 case OP_CONSTANT16:
344 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
345 (uint16)OP[i]);
346 break;
347
348 case OP_CONSTANT4:
349 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
350 (uint16)SEXT4(OP[i]));
351 break;
352
353 case OP_CONSTANT8:
354 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
355 (uint16)SEXT8(OP[i]));
356 break;
357
358 case OP_CONSTANT3:
359 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
360 (uint16)SEXT3(OP[i]));
361 break;
362
363 case OP_FLAG:
364 if (OP[i] == 0)
365 (*d10v_callback->printf_filtered) (d10v_callback, "%*sF0 = %d", SIZE_VALUES-6, "",
366 State.F0 != 0);
367
368 else if (OP[i] == 1)
369 (*d10v_callback->printf_filtered) (d10v_callback, "%*sF1 = %d", SIZE_VALUES-6, "",
370 State.F1 != 0);
371
372 else
373 (*d10v_callback->printf_filtered) (d10v_callback, "%*sC = %d", SIZE_VALUES-5, "",
374 State.C != 0);
375
376 break;
377
378 case OP_MEMREF2:
379 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
380 (uint16)OP[i]);
381 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
382 (uint16)State.regs[OP[++i]]);
383 break;
384
385 case OP_R2:
386 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
387 (uint16)State.regs[2]);
388 break;
389
390 case OP_R3:
391 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
392 (uint16)State.regs[3]);
393 break;
394
395 case OP_R4:
396 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
397 (uint16)State.regs[4]);
398 break;
399
400 case OP_R2R3:
401 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
402 (uint16)State.regs[2]);
403 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
404 (uint16)State.regs[3]);
405 i++;
406 break;
407 }
408 }
409 }
410
411 (*d10v_callback->flush_stdout) (d10v_callback);
412 }
413
414 static void
415 trace_output_func (result)
416 enum op_types result;
417 {
418 if ((d10v_debug & (DEBUG_TRACE | DEBUG_VALUES)) == (DEBUG_TRACE | DEBUG_VALUES))
419 {
420 long tmp;
421
422 switch (result)
423 {
424 default:
425 putchar ('\n');
426 break;
427
428 case OP_REG:
429 case OP_REG_OUTPUT:
430 (*d10v_callback->printf_filtered) (d10v_callback, " :: %*s0x%.4x F0=%d F1=%d C=%d\n", SIZE_VALUES-6, "",
431 (uint16)State.regs[OP[0]],
432 State.F0 != 0, State.F1 != 0, State.C != 0);
433 break;
434
435 case OP_DREG:
436 case OP_DREG_OUTPUT:
437 tmp = (long)((((uint32) State.regs[OP[0]]) << 16) | ((uint32) State.regs[OP[0]+1]));
438 (*d10v_callback->printf_filtered) (d10v_callback, " :: %*s0x%.8lx F0=%d F1=%d C=%d\n", SIZE_VALUES-10, "", tmp,
439 State.F0 != 0, State.F1 != 0, State.C != 0);
440 break;
441
442 case OP_CR:
443 case OP_CR_OUTPUT:
444 (*d10v_callback->printf_filtered) (d10v_callback, " :: %*s0x%.4x F0=%d F1=%d C=%d\n", SIZE_VALUES-6, "",
445 (uint16)State.cregs[OP[0]],
446 State.F0 != 0, State.F1 != 0, State.C != 0);
447 break;
448
449 case OP_CR_REVERSE:
450 (*d10v_callback->printf_filtered) (d10v_callback, " :: %*s0x%.4x F0=%d F1=%d C=%d\n", SIZE_VALUES-6, "",
451 (uint16)State.cregs[OP[1]],
452 State.F0 != 0, State.F1 != 0, State.C != 0);
453 break;
454
455 case OP_ACCUM:
456 case OP_ACCUM_OUTPUT:
457 (*d10v_callback->printf_filtered) (d10v_callback, " :: %*s0x%.2x%.8lx F0=%d F1=%d C=%d\n", SIZE_VALUES-12, "",
458 ((int)(State.a[OP[0]] >> 32) & 0xff),
459 ((unsigned long)State.a[OP[0]]) & 0xffffffff,
460 State.F0 != 0, State.F1 != 0, State.C != 0);
461 break;
462
463 case OP_ACCUM_REVERSE:
464 (*d10v_callback->printf_filtered) (d10v_callback, " :: %*s0x%.2x%.8lx F0=%d F1=%d C=%d\n", SIZE_VALUES-12, "",
465 ((int)(State.a[OP[1]] >> 32) & 0xff),
466 ((unsigned long)State.a[OP[1]]) & 0xffffffff,
467 State.F0 != 0, State.F1 != 0, State.C != 0);
468 break;
469
470 case OP_FLAG:
471 case OP_FLAG_OUTPUT:
472 (*d10v_callback->printf_filtered) (d10v_callback, " :: %*s F0=%d F1=%d C=%d\n", SIZE_VALUES, "",
473 State.F0 != 0, State.F1 != 0, State.C != 0);
474 break;
475
476 case OP_R2:
477 (*d10v_callback->printf_filtered) (d10v_callback, " :: %*s0x%.4x F0=%d F1=%d C=%d\n", SIZE_VALUES-6, "",
478 (uint16)State.regs[2],
479 State.F0 != 0, State.F1 != 0, State.C != 0);
480 break;
481
482 case OP_R2R3:
483 (*d10v_callback->printf_filtered) (d10v_callback, " :: %*s0x%.4x%.4x F0=%d F1=%d C=%d\n", SIZE_VALUES-10, "",
484 (uint16)State.regs[2], (uint16)State.regs[3],
485 State.F0 != 0, State.F1 != 0, State.C != 0);
486 break;
487 }
488 }
489
490 (*d10v_callback->flush_stdout) (d10v_callback);
491 }
492
493 #else
494 #define trace_input(NAME, IN1, IN2, IN3)
495 #define trace_output(RESULT)
496 #endif
497
498 /* abs */
499 void
500 OP_4607 ()
501 {
502 trace_input ("abs", OP_REG, OP_VOID, OP_VOID);
503 State.F1 = State.F0;
504 if ((int16)(State.regs[OP[0]]) < 0)
505 {
506 State.regs[OP[0]] = -(int16)(State.regs[OP[0]]);
507 State.F0 = 1;
508 }
509 else
510 State.F0 = 0;
511 trace_output (OP_REG);
512 }
513
514 /* abs */
515 void
516 OP_5607 ()
517 {
518 int64 tmp;
519
520 trace_input ("abs", OP_ACCUM, OP_VOID, OP_VOID);
521 State.F1 = State.F0;
522 State.a[OP[0]] = SEXT40(State.a[OP[0]]);
523
524 if (State.a[OP[0]] < 0 )
525 {
526 tmp = -State.a[OP[0]];
527 if (State.ST)
528 {
529 if (tmp > MAX32)
530 State.a[OP[0]] = MAX32;
531 else if (tmp < MIN32)
532 State.a[OP[0]] = MIN32;
533 else
534 State.a[OP[0]] = tmp & MASK40;
535 }
536 else
537 State.a[OP[0]] = tmp & MASK40;
538 State.F0 = 1;
539 }
540 else
541 State.F0 = 0;
542 trace_output (OP_ACCUM);
543 }
544
545 /* add */
546 void
547 OP_200 ()
548 {
549 uint16 tmp = State.regs[OP[0]];
550 trace_input ("add", OP_REG, OP_REG, OP_VOID);
551 State.regs[OP[0]] += State.regs[OP[1]];
552 if ( tmp > State.regs[OP[0]])
553 State.C = 1;
554 else
555 State.C = 0;
556 trace_output (OP_REG);
557 }
558
559 /* add */
560 void
561 OP_1201 ()
562 {
563 int64 tmp;
564 tmp = SEXT40(State.a[OP[0]]) + (SEXT16 (State.regs[OP[1]]) << 16 | State.regs[OP[1]+1]);
565
566 trace_input ("add", OP_ACCUM, OP_REG, OP_VOID);
567 if (State.ST)
568 {
569 if ( tmp > MAX32)
570 State.a[OP[0]] = MAX32;
571 else if ( tmp < MIN32)
572 State.a[OP[0]] = MIN32;
573 else
574 State.a[OP[0]] = tmp & MASK40;
575 }
576 else
577 State.a[OP[0]] = tmp & MASK40;
578 trace_output (OP_ACCUM);
579 }
580
581 /* add */
582 void
583 OP_1203 ()
584 {
585 int64 tmp;
586 tmp = SEXT40(State.a[OP[0]]) + SEXT40(State.a[OP[1]]);
587
588 trace_input ("add", OP_ACCUM, OP_ACCUM, OP_VOID);
589 if (State.ST)
590 {
591 if (tmp > MAX32)
592 State.a[OP[0]] = MAX32;
593 else if ( tmp < MIN32)
594 State.a[OP[0]] = MIN32;
595 else
596 State.a[OP[0]] = tmp & MASK40;
597 }
598 else
599 State.a[OP[0]] = tmp & MASK40;
600 trace_output (OP_ACCUM);
601 }
602
603 /* add2w */
604 void
605 OP_1200 ()
606 {
607 uint32 tmp;
608 uint32 a = (State.regs[OP[0]]) << 16 | State.regs[OP[0]+1];
609 uint32 b = (State.regs[OP[1]]) << 16 | State.regs[OP[1]+1];
610
611 trace_input ("add2w", OP_DREG, OP_DREG, OP_VOID);
612 tmp = a + b;
613 State.C = (tmp < a);
614 State.regs[OP[0]] = tmp >> 16;
615 State.regs[OP[0]+1] = tmp & 0xFFFF;
616 trace_output (OP_DREG);
617 }
618
619 /* add3 */
620 void
621 OP_1000000 ()
622 {
623 uint16 tmp = State.regs[OP[1]];
624 State.regs[OP[0]] = tmp + OP[2];
625
626 trace_input ("add3", OP_REG_OUTPUT, OP_REG, OP_CONSTANT16);
627 State.C = (State.regs[OP[0]] < tmp);
628 trace_output (OP_REG);
629 }
630
631 /* addac3 */
632 void
633 OP_17000200 ()
634 {
635 int64 tmp;
636 tmp = SEXT40(State.a[OP[2]]) + SEXT40 ((State.regs[OP[1]] << 16) | State.regs[OP[1]+1]);
637
638 trace_input ("addac3", OP_DREG_OUTPUT, OP_DREG, OP_ACCUM);
639 State.regs[OP[0]] = (tmp >> 16) & 0xffff;
640 State.regs[OP[0]+1] = tmp & 0xffff;
641 trace_output (OP_DREG);
642 }
643
644 /* addac3 */
645 void
646 OP_17000202 ()
647 {
648 int64 tmp;
649 tmp = SEXT40(State.a[OP[1]]) + SEXT40(State.a[OP[2]]);
650
651 trace_input ("addac3", OP_DREG_OUTPUT, OP_ACCUM, OP_ACCUM);
652 State.regs[OP[0]] = (tmp >> 16) & 0xffff;
653 State.regs[OP[0]+1] = tmp & 0xffff;
654 trace_output (OP_DREG);
655 }
656
657 /* addac3s */
658 void
659 OP_17001200 ()
660 {
661 int64 tmp;
662 State.F1 = State.F0;
663
664 trace_input ("addac3s", OP_DREG_OUTPUT, OP_DREG, OP_ACCUM);
665 tmp = SEXT40(State.a[OP[2]]) + SEXT40 ((State.regs[OP[1]] << 16) | State.regs[OP[1]+1]);
666 if ( tmp > MAX32)
667 {
668 State.regs[OP[0]] = 0x7fff;
669 State.regs[OP[0]+1] = 0xffff;
670 State.F0 = 1;
671 }
672 else if (tmp < MIN32)
673 {
674 State.regs[OP[0]] = 0x8000;
675 State.regs[OP[0]+1] = 0;
676 State.F0 = 1;
677 }
678 else
679 {
680 State.regs[OP[0]] = (tmp >> 16) & 0xffff;
681 State.regs[OP[0]+1] = tmp & 0xffff;
682 State.F0 = 0;
683 }
684 trace_output (OP_DREG);
685 }
686
687 /* addac3s */
688 void
689 OP_17001202 ()
690 {
691 int64 tmp;
692 State.F1 = State.F0;
693
694 trace_input ("addac3s", OP_DREG_OUTPUT, OP_ACCUM, OP_ACCUM);
695 tmp = SEXT40(State.a[OP[1]]) + SEXT40(State.a[OP[2]]);
696 if ( tmp > MAX32)
697 {
698 State.regs[OP[0]] = 0x7fff;
699 State.regs[OP[0]+1] = 0xffff;
700 State.F0 = 1;
701 }
702 else if (tmp < MIN32)
703 {
704 State.regs[OP[0]] = 0x8000;
705 State.regs[OP[0]+1] = 0;
706 State.F0 = 1;
707 }
708 else
709 {
710 State.regs[OP[0]] = (tmp >> 16) & 0xffff;
711 State.regs[OP[0]+1] = tmp & 0xffff;
712 State.F0 = 0;
713 }
714 trace_output (OP_DREG);
715 }
716
717 /* addi */
718 void
719 OP_201 ()
720 {
721 uint tmp = State.regs[OP[0]];
722 if (OP[1] == 0)
723 OP[1] = 16;
724
725 trace_input ("addi", OP_REG, OP_CONSTANT16, OP_VOID);
726 State.regs[OP[0]] += OP[1];
727 State.C = (State.regs[OP[0]] < tmp);
728 trace_output (OP_REG);
729 }
730
731 /* and */
732 void
733 OP_C00 ()
734 {
735 trace_input ("and", OP_REG, OP_REG, OP_VOID);
736 State.regs[OP[0]] &= State.regs[OP[1]];
737 trace_output (OP_REG);
738 }
739
740 /* and3 */
741 void
742 OP_6000000 ()
743 {
744 trace_input ("and3", OP_REG_OUTPUT, OP_REG, OP_CONSTANT16);
745 State.regs[OP[0]] = State.regs[OP[1]] & OP[2];
746 trace_output (OP_REG);
747 }
748
749 /* bclri */
750 void
751 OP_C01 ()
752 {
753 trace_input ("bclri", OP_REG, OP_CONSTANT16, OP_VOID);
754 State.regs[OP[0]] &= ~(0x8000 >> OP[1]);
755 trace_output (OP_REG);
756 }
757
758 /* bl.s */
759 void
760 OP_4900 ()
761 {
762 trace_input ("bl.s", OP_CONSTANT8, OP_R2, OP_R3);
763 State.regs[13] = PC+1;
764 JMP( PC + SEXT8 (OP[0]));
765 trace_output (OP_VOID);
766 }
767
768 /* bl.l */
769 void
770 OP_24800000 ()
771 {
772 trace_input ("bl.l", OP_CONSTANT16, OP_R2, OP_R3);
773 State.regs[13] = PC+1;
774 JMP (PC + OP[0]);
775 trace_output (OP_VOID);
776 }
777
778 /* bnoti */
779 void
780 OP_A01 ()
781 {
782 trace_input ("bnoti", OP_REG, OP_CONSTANT16, OP_VOID);
783 State.regs[OP[0]] ^= 0x8000 >> OP[1];
784 trace_output (OP_REG);
785 }
786
787 /* bra.s */
788 void
789 OP_4800 ()
790 {
791 trace_input ("bra.s", OP_CONSTANT8, OP_VOID, OP_VOID);
792 JMP (PC + SEXT8 (OP[0]));
793 trace_output (OP_VOID);
794 }
795
796 /* bra.l */
797 void
798 OP_24000000 ()
799 {
800 trace_input ("bra.l", OP_CONSTANT16, OP_VOID, OP_VOID);
801 JMP (PC + OP[0]);
802 trace_output (OP_VOID);
803 }
804
805 /* brf0f.s */
806 void
807 OP_4A00 ()
808 {
809 trace_input ("brf0f.s", OP_CONSTANT8, OP_VOID, OP_VOID);
810 if (State.F0 == 0)
811 JMP (PC + SEXT8 (OP[0]));
812 trace_output (OP_FLAG);
813 }
814
815 /* brf0f.l */
816 void
817 OP_25000000 ()
818 {
819 trace_input ("brf0f.l", OP_CONSTANT16, OP_VOID, OP_VOID);
820 if (State.F0 == 0)
821 JMP (PC + OP[0]);
822 trace_output (OP_FLAG);
823 }
824
825 /* brf0t.s */
826 void
827 OP_4B00 ()
828 {
829 trace_input ("brf0t.s", OP_CONSTANT8, OP_VOID, OP_VOID);
830 if (State.F0)
831 JMP (PC + SEXT8 (OP[0]));
832 trace_output (OP_FLAG);
833 }
834
835 /* brf0t.l */
836 void
837 OP_25800000 ()
838 {
839 trace_input ("brf0t.l", OP_CONSTANT16, OP_VOID, OP_VOID);
840 if (State.F0)
841 JMP (PC + OP[0]);
842 trace_output (OP_FLAG);
843 }
844
845 /* bseti */
846 void
847 OP_801 ()
848 {
849 trace_input ("bseti", OP_REG, OP_CONSTANT16, OP_VOID);
850 State.regs[OP[0]] |= 0x8000 >> OP[1];
851 trace_output (OP_REG);
852 }
853
854 /* btsti */
855 void
856 OP_E01 ()
857 {
858 trace_input ("btsti", OP_REG, OP_CONSTANT16, OP_VOID);
859 State.F1 = State.F0;
860 State.F0 = (State.regs[OP[0]] & (0x8000 >> OP[1])) ? 1 : 0;
861 trace_output (OP_FLAG);
862 }
863
864 /* clrac */
865 void
866 OP_5601 ()
867 {
868 trace_input ("clrac", OP_ACCUM_OUTPUT, OP_VOID, OP_VOID);
869 State.a[OP[0]] = 0;
870 trace_output (OP_ACCUM);
871 }
872
873 /* cmp */
874 void
875 OP_600 ()
876 {
877 trace_input ("cmp", OP_REG, OP_REG, OP_VOID);
878 State.F1 = State.F0;
879 State.F0 = ((int16)(State.regs[OP[0]]) < (int16)(State.regs[OP[1]])) ? 1 : 0;
880 trace_output (OP_FLAG);
881 }
882
883 /* cmp */
884 void
885 OP_1603 ()
886 {
887 trace_input ("cmp", OP_ACCUM, OP_ACCUM, OP_VOID);
888 State.F1 = State.F0;
889 State.F0 = (SEXT40(State.a[OP[0]]) < SEXT40(State.a[OP[1]])) ? 1 : 0;
890 trace_output (OP_FLAG);
891 }
892
893 /* cmpeq */
894 void
895 OP_400 ()
896 {
897 trace_input ("cmpeq", OP_REG, OP_REG, OP_VOID);
898 State.F1 = State.F0;
899 State.F0 = (State.regs[OP[0]] == State.regs[OP[1]]) ? 1 : 0;
900 trace_output (OP_FLAG);
901 }
902
903 /* cmpeq */
904 void
905 OP_1403 ()
906 {
907 trace_input ("cmpeq", OP_ACCUM, OP_ACCUM, OP_VOID);
908 State.F1 = State.F0;
909 State.F0 = ((State.a[OP[0]] & MASK40) == (State.a[OP[1]] & MASK40)) ? 1 : 0;
910 trace_output (OP_FLAG);
911 }
912
913 /* cmpeqi.s */
914 void
915 OP_401 ()
916 {
917 trace_input ("cmpeqi.s", OP_REG, OP_CONSTANT4, OP_VOID);
918 State.F1 = State.F0;
919 State.F0 = (State.regs[OP[0]] == (reg_t)SEXT4(OP[1])) ? 1 : 0;
920 trace_output (OP_FLAG);
921 }
922
923 /* cmpeqi.l */
924 void
925 OP_2000000 ()
926 {
927 trace_input ("cmpeqi.l", OP_REG, OP_CONSTANT16, OP_VOID);
928 State.F1 = State.F0;
929 State.F0 = (State.regs[OP[0]] == (reg_t)OP[1]) ? 1 : 0;
930 trace_output (OP_FLAG);
931 }
932
933 /* cmpi.s */
934 void
935 OP_601 ()
936 {
937 trace_input ("cmpi.s", OP_REG, OP_CONSTANT4, OP_VOID);
938 State.F1 = State.F0;
939 State.F0 = ((int16)(State.regs[OP[0]]) < (int16)SEXT4(OP[1])) ? 1 : 0;
940 trace_output (OP_FLAG);
941 }
942
943 /* cmpi.l */
944 void
945 OP_3000000 ()
946 {
947 trace_input ("cmpi.l", OP_REG, OP_CONSTANT16, OP_VOID);
948 State.F1 = State.F0;
949 State.F0 = ((int16)(State.regs[OP[0]]) < (int16)(OP[1])) ? 1 : 0;
950 trace_output (OP_FLAG);
951 }
952
953 /* cmpu */
954 void
955 OP_4600 ()
956 {
957 trace_input ("cmpu", OP_REG, OP_REG, OP_VOID);
958 State.F1 = State.F0;
959 State.F0 = (State.regs[OP[0]] < State.regs[OP[1]]) ? 1 : 0;
960 trace_output (OP_FLAG);
961 }
962
963 /* cmpui */
964 void
965 OP_23000000 ()
966 {
967 trace_input ("cmpui", OP_REG, OP_CONSTANT16, OP_VOID);
968 State.F1 = State.F0;
969 State.F0 = (State.regs[OP[0]] < (reg_t)OP[1]) ? 1 : 0;
970 trace_output (OP_FLAG);
971 }
972
973 /* cpfg */
974 void
975 OP_4E09 ()
976 {
977 uint8 *src, *dst;
978
979 trace_input ("cpfg", OP_FLAG_OUTPUT, OP_FLAG, OP_VOID);
980 if (OP[0] == 0)
981 dst = &State.F0;
982 else
983 dst = &State.F1;
984
985 if (OP[1] == 0)
986 src = &State.F0;
987 else if (OP[1] == 1)
988 src = &State.F1;
989 else
990 src = &State.C;
991
992 *dst = *src;
993 trace_output (OP_FLAG);
994 }
995
996 /* dbt */
997 void
998 OP_5F20 ()
999 {
1000 /* d10v_callback->printf_filtered(d10v_callback, "***** DBT ***** PC=%x\n",PC); */
1001 State.exception = SIGTRAP;
1002 }
1003
1004 /* divs */
1005 void
1006 OP_14002800 ()
1007 {
1008 uint16 foo, tmp, tmpf;
1009
1010 trace_input ("divs", OP_DREG, OP_REG, OP_VOID);
1011 foo = (State.regs[OP[0]] << 1) | (State.regs[OP[0]+1] >> 15);
1012 tmp = (int16)foo - (int16)(State.regs[OP[1]]);
1013 tmpf = (foo >= State.regs[OP[1]]) ? 1 : 0;
1014 State.regs[OP[0]] = (tmpf == 1) ? tmp : foo;
1015 State.regs[OP[0]+1] = (State.regs[OP[0]+1] << 1) | tmpf;
1016 trace_output (OP_DREG);
1017 }
1018
1019 /* exef0f */
1020 void
1021 OP_4E04 ()
1022 {
1023 trace_input ("exef0f", OP_VOID, OP_VOID, OP_VOID);
1024 State.exe = (State.F0 == 0);
1025 trace_output (OP_FLAG);
1026 }
1027
1028 /* exef0t */
1029 void
1030 OP_4E24 ()
1031 {
1032 trace_input ("exef0t", OP_VOID, OP_VOID, OP_VOID);
1033 State.exe = (State.F0 != 0);
1034 trace_output (OP_FLAG);
1035 }
1036
1037 /* exef1f */
1038 void
1039 OP_4E40 ()
1040 {
1041 trace_input ("exef1f", OP_VOID, OP_VOID, OP_VOID);
1042 State.exe = (State.F1 == 0);
1043 trace_output (OP_FLAG);
1044 }
1045
1046 /* exef1t */
1047 void
1048 OP_4E42 ()
1049 {
1050 trace_input ("exef1t", OP_VOID, OP_VOID, OP_VOID);
1051 State.exe = (State.F1 != 0);
1052 trace_output (OP_FLAG);
1053 }
1054
1055 /* exefaf */
1056 void
1057 OP_4E00 ()
1058 {
1059 trace_input ("exefaf", OP_VOID, OP_VOID, OP_VOID);
1060 State.exe = (State.F0 == 0) & (State.F1 == 0);
1061 trace_output (OP_FLAG);
1062 }
1063
1064 /* exefat */
1065 void
1066 OP_4E02 ()
1067 {
1068 trace_input ("exefat", OP_VOID, OP_VOID, OP_VOID);
1069 State.exe = (State.F0 == 0) & (State.F1 != 0);
1070 trace_output (OP_FLAG);
1071 }
1072
1073 /* exetaf */
1074 void
1075 OP_4E20 ()
1076 {
1077 trace_input ("exetaf", OP_VOID, OP_VOID, OP_VOID);
1078 State.exe = (State.F0 != 0) & (State.F1 == 0);
1079 trace_output (OP_FLAG);
1080 }
1081
1082 /* exetat */
1083 void
1084 OP_4E22 ()
1085 {
1086 trace_input ("exetat", OP_VOID, OP_VOID, OP_VOID);
1087 State.exe = (State.F0 != 0) & (State.F1 != 0);
1088 trace_output (OP_FLAG);
1089 }
1090
1091 /* exp */
1092 void
1093 OP_15002A00 ()
1094 {
1095 uint32 tmp, foo;
1096 int i;
1097
1098 trace_input ("exp", OP_REG_OUTPUT, OP_DREG, OP_VOID);
1099 if (((int16)State.regs[OP[1]]) >= 0)
1100 tmp = (State.regs[OP[1]] << 16) | State.regs[OP[1]+1];
1101 else
1102 tmp = ~((State.regs[OP[1]] << 16) | State.regs[OP[1]+1]);
1103
1104 foo = 0x40000000;
1105 for (i=1;i<17;i++)
1106 {
1107 if (tmp & foo)
1108 {
1109 State.regs[OP[0]] = i-1;
1110 trace_output (OP_REG);
1111 return;
1112 }
1113 foo >>= 1;
1114 }
1115 State.regs[OP[0]] = 16;
1116 trace_output (OP_REG);
1117 }
1118
1119 /* exp */
1120 void
1121 OP_15002A02 ()
1122 {
1123 int64 tmp, foo;
1124 int i;
1125
1126 trace_input ("exp", OP_REG_OUTPUT, OP_ACCUM, OP_VOID);
1127 tmp = SEXT40(State.a[OP[1]]);
1128 if (tmp < 0)
1129 tmp = ~tmp & MASK40;
1130
1131 foo = 0x4000000000LL;
1132 for (i=1;i<25;i++)
1133 {
1134 if (tmp & foo)
1135 {
1136 State.regs[OP[0]] = i-9;
1137 trace_output (OP_REG);
1138 return;
1139 }
1140 foo >>= 1;
1141 }
1142 State.regs[OP[0]] = 16;
1143 trace_output (OP_REG);
1144 }
1145
1146 /* jl */
1147 void
1148 OP_4D00 ()
1149 {
1150 trace_input ("jl", OP_REG, OP_R2, OP_R3);
1151 State.regs[13] = PC+1;
1152 JMP (State.regs[OP[0]]);
1153 trace_output (OP_VOID);
1154 }
1155
1156 /* jmp */
1157 void
1158 OP_4C00 ()
1159 {
1160 trace_input ("jmp", OP_REG,
1161 (OP[0] == 13) ? OP_R2 : OP_VOID,
1162 (OP[0] == 13) ? OP_R3 : OP_VOID);
1163
1164 JMP (State.regs[OP[0]]);
1165 trace_output (OP_VOID);
1166 }
1167
1168 /* ld */
1169 void
1170 OP_30000000 ()
1171 {
1172 trace_input ("ld", OP_REG_OUTPUT, OP_MEMREF2, OP_VOID);
1173 State.regs[OP[0]] = RW (OP[1] + State.regs[OP[2]]);
1174 trace_output (OP_REG);
1175 }
1176
1177 /* ld */
1178 void
1179 OP_6401 ()
1180 {
1181 trace_input ("ld", OP_REG_OUTPUT, OP_POSTDEC, OP_VOID);
1182 State.regs[OP[0]] = RW (State.regs[OP[1]]);
1183 INC_ADDR(State.regs[OP[1]],-2);
1184 trace_output (OP_REG);
1185 }
1186
1187 /* ld */
1188 void
1189 OP_6001 ()
1190 {
1191 trace_input ("ld", OP_REG_OUTPUT, OP_POSTINC, OP_VOID);
1192 State.regs[OP[0]] = RW (State.regs[OP[1]]);
1193 INC_ADDR(State.regs[OP[1]],2);
1194 trace_output (OP_REG);
1195 }
1196
1197 /* ld */
1198 void
1199 OP_6000 ()
1200 {
1201 trace_input ("ld", OP_REG_OUTPUT, OP_MEMREF, OP_VOID);
1202 State.regs[OP[0]] = RW (State.regs[OP[1]]);
1203 trace_output (OP_REG);
1204 }
1205
1206 /* ld2w */
1207 void
1208 OP_31000000 ()
1209 {
1210 uint16 addr = State.regs[OP[2]];
1211 trace_input ("ld2w", OP_REG_OUTPUT, OP_MEMREF2, OP_VOID);
1212 State.regs[OP[0]] = RW (OP[1] + addr);
1213 State.regs[OP[0]+1] = RW (OP[1] + addr + 2);
1214 trace_output (OP_DREG);
1215 }
1216
1217 /* ld2w */
1218 void
1219 OP_6601 ()
1220 {
1221 uint16 addr = State.regs[OP[1]];
1222 trace_input ("ld2w", OP_REG_OUTPUT, OP_POSTDEC, OP_VOID);
1223 State.regs[OP[0]] = RW (addr);
1224 State.regs[OP[0]+1] = RW (addr+2);
1225 INC_ADDR(State.regs[OP[1]],-4);
1226 trace_output (OP_DREG);
1227 }
1228
1229 /* ld2w */
1230 void
1231 OP_6201 ()
1232 {
1233 uint16 addr = State.regs[OP[1]];
1234 trace_input ("ld2w", OP_REG_OUTPUT, OP_POSTINC, OP_VOID);
1235 State.regs[OP[0]] = RW (addr);
1236 State.regs[OP[0]+1] = RW (addr+2);
1237 INC_ADDR(State.regs[OP[1]],4);
1238 trace_output (OP_DREG);
1239 }
1240
1241 /* ld2w */
1242 void
1243 OP_6200 ()
1244 {
1245 uint16 addr = State.regs[OP[1]];
1246 trace_input ("ld2w", OP_REG_OUTPUT, OP_MEMREF, OP_VOID);
1247 State.regs[OP[0]] = RW (addr);
1248 State.regs[OP[0]+1] = RW (addr+2);
1249 trace_output (OP_DREG);
1250 }
1251
1252 /* ldb */
1253 void
1254 OP_38000000 ()
1255 {
1256 trace_input ("ldb", OP_REG_OUTPUT, OP_MEMREF2, OP_VOID);
1257 State.regs[OP[0]] = SEXT8 (RB (OP[1] + State.regs[OP[2]]));
1258 trace_output (OP_REG);
1259 }
1260
1261 /* ldb */
1262 void
1263 OP_7000 ()
1264 {
1265 trace_input ("ldb", OP_REG_OUTPUT, OP_MEMREF, OP_VOID);
1266 State.regs[OP[0]] = SEXT8 (RB (State.regs[OP[1]]));
1267 trace_output (OP_REG);
1268 }
1269
1270 /* ldi.s */
1271 void
1272 OP_4001 ()
1273 {
1274 trace_input ("ldi.s", OP_REG_OUTPUT, OP_CONSTANT4, OP_VOID);
1275 State.regs[OP[0]] = SEXT4(OP[1]);
1276 trace_output (OP_REG);
1277 }
1278
1279 /* ldi.l */
1280 void
1281 OP_20000000 ()
1282 {
1283 trace_input ("ldi.l", OP_REG_OUTPUT, OP_CONSTANT16, OP_VOID);
1284 State.regs[OP[0]] = OP[1];
1285 trace_output (OP_REG);
1286 }
1287
1288 /* ldub */
1289 void
1290 OP_39000000 ()
1291 {
1292 trace_input ("ldub", OP_REG_OUTPUT, OP_MEMREF2, OP_VOID);
1293 State.regs[OP[0]] = RB (OP[1] + State.regs[OP[2]]);
1294 trace_output (OP_REG);
1295 }
1296
1297 /* ldub */
1298 void
1299 OP_7200 ()
1300 {
1301 trace_input ("ldub", OP_REG_OUTPUT, OP_MEMREF, OP_VOID);
1302 State.regs[OP[0]] = RB (State.regs[OP[1]]);
1303 trace_output (OP_REG);
1304 }
1305
1306 /* mac */
1307 void
1308 OP_2A00 ()
1309 {
1310 int64 tmp;
1311
1312 trace_input ("mac", OP_ACCUM, OP_REG, OP_REG);
1313 tmp = SEXT40 ((int16)(State.regs[OP[1]]) * (int16)(State.regs[OP[2]]));
1314
1315 if (State.FX)
1316 tmp = SEXT40( (tmp << 1) & MASK40);
1317
1318 if (State.ST && tmp > MAX32)
1319 tmp = MAX32;
1320
1321 tmp += SEXT40(State.a[OP[0]]);
1322 if (State.ST)
1323 {
1324 if (tmp > MAX32)
1325 State.a[OP[0]] = MAX32;
1326 else if (tmp < MIN32)
1327 State.a[OP[0]] = MIN32;
1328 else
1329 State.a[OP[0]] = tmp & MASK40;
1330 }
1331 else
1332 State.a[OP[0]] = tmp & MASK40;
1333 trace_output (OP_ACCUM);
1334 }
1335
1336 /* macsu */
1337 void
1338 OP_1A00 ()
1339 {
1340 int64 tmp;
1341
1342 trace_input ("macsu", OP_ACCUM, OP_REG, OP_REG);
1343 tmp = SEXT40 ((int16)State.regs[OP[1]] * State.regs[OP[2]]);
1344 if (State.FX)
1345 tmp = SEXT40( (tmp << 1) & MASK40);
1346
1347 State.a[OP[0]] = (SEXT40 (State.a[OP[0]]) + tmp) & MASK40;
1348 trace_output (OP_ACCUM);
1349 }
1350
1351 /* macu */
1352 void
1353 OP_3A00 ()
1354 {
1355 uint64 tmp;
1356 uint32 src1;
1357 uint32 src2;
1358
1359 trace_input ("macu", OP_ACCUM, OP_REG, OP_REG);
1360 src1 = (uint16) State.regs[OP[1]];
1361 src2 = (uint16) State.regs[OP[2]];
1362 tmp = src1 * src2;
1363 if (State.FX)
1364 tmp = (tmp << 1);
1365 State.a[OP[0]] = (State.a[OP[0]] + tmp) & MASK40;
1366 trace_output (OP_ACCUM);
1367 }
1368
1369 /* max */
1370 void
1371 OP_2600 ()
1372 {
1373 trace_input ("max", OP_REG, OP_REG, OP_VOID);
1374 State.F1 = State.F0;
1375 if ((int16)State.regs[OP[1]] > (int16)State.regs[OP[0]])
1376 {
1377 State.regs[OP[0]] = State.regs[OP[1]];
1378 State.F0 = 1;
1379 }
1380 else
1381 State.F0 = 0;
1382 trace_output (OP_REG);
1383 }
1384
1385 /* max */
1386 void
1387 OP_3600 ()
1388 {
1389 int64 tmp;
1390
1391 trace_input ("max", OP_ACCUM, OP_DREG, OP_VOID);
1392 State.F1 = State.F0;
1393 tmp = SEXT16 (State.regs[OP[1]]) << 16 | State.regs[OP[1]+1];
1394 if (tmp > SEXT40(State.a[OP[0]]))
1395 {
1396 State.a[OP[0]] = tmp & MASK40;
1397 State.F0 = 1;
1398 }
1399 else
1400 State.F0 = 0;
1401 trace_output (OP_ACCUM);
1402 }
1403
1404 /* max */
1405 void
1406 OP_3602 ()
1407 {
1408 trace_input ("max", OP_ACCUM, OP_ACCUM, OP_VOID);
1409 State.F1 = State.F0;
1410 if (SEXT40(State.a[OP[1]]) > SEXT40(State.a[OP[0]]))
1411 {
1412 State.a[OP[0]] = State.a[OP[1]];
1413 State.F0 = 1;
1414 }
1415 else
1416 State.F0 = 0;
1417 trace_output (OP_ACCUM);
1418 }
1419
1420
1421 /* min */
1422 void
1423 OP_2601 ()
1424 {
1425 trace_input ("min", OP_REG, OP_REG, OP_VOID);
1426 State.F1 = State.F0;
1427 if ((int16)State.regs[OP[1]] < (int16)State.regs[OP[0]])
1428 {
1429 State.regs[OP[0]] = State.regs[OP[1]];
1430 State.F0 = 1;
1431 }
1432 else
1433 State.F0 = 0;
1434 trace_output (OP_REG);
1435 }
1436
1437 /* min */
1438 void
1439 OP_3601 ()
1440 {
1441 int64 tmp;
1442
1443 trace_input ("min", OP_ACCUM, OP_DREG, OP_VOID);
1444 State.F1 = State.F0;
1445 tmp = SEXT16 (State.regs[OP[1]]) << 16 | State.regs[OP[1]+1];
1446 if (tmp < SEXT40(State.a[OP[0]]))
1447 {
1448 State.a[OP[0]] = tmp & MASK40;
1449 State.F0 = 1;
1450 }
1451 else
1452 State.F0 = 0;
1453 trace_output (OP_ACCUM);
1454 }
1455
1456 /* min */
1457 void
1458 OP_3603 ()
1459 {
1460 trace_input ("min", OP_ACCUM, OP_ACCUM, OP_VOID);
1461 State.F1 = State.F0;
1462 if (SEXT40(State.a[OP[1]]) < SEXT40(State.a[OP[0]]))
1463 {
1464 State.a[OP[0]] = State.a[OP[1]];
1465 State.F0 = 1;
1466 }
1467 else
1468 State.F0 = 0;
1469 trace_output (OP_ACCUM);
1470 }
1471
1472 /* msb */
1473 void
1474 OP_2800 ()
1475 {
1476 int64 tmp;
1477
1478 trace_input ("msb", OP_ACCUM, OP_REG, OP_REG);
1479 tmp = SEXT40 ((int16)(State.regs[OP[1]]) * (int16)(State.regs[OP[2]]));
1480
1481 if (State.FX)
1482 tmp = SEXT40 ((tmp << 1) & MASK40);
1483
1484 if (State.ST && tmp > MAX32)
1485 tmp = MAX32;
1486
1487 tmp = SEXT40(State.a[OP[0]]) - tmp;
1488 if (State.ST)
1489 {
1490 if (tmp > MAX32)
1491 State.a[OP[0]] = MAX32;
1492 else if (tmp < MIN32)
1493 State.a[OP[0]] = MIN32;
1494 else
1495 State.a[OP[0]] = tmp & MASK40;
1496 }
1497 else
1498 State.a[OP[0]] = tmp & MASK40;
1499 trace_output (OP_ACCUM);
1500 }
1501
1502 /* msbsu */
1503 void
1504 OP_1800 ()
1505 {
1506 int64 tmp;
1507
1508 trace_input ("msbsu", OP_ACCUM, OP_REG, OP_REG);
1509 tmp = SEXT40 ((int16)State.regs[OP[1]] * State.regs[OP[2]]);
1510 if (State.FX)
1511 tmp = SEXT40( (tmp << 1) & MASK40);
1512
1513 State.a[OP[0]] = (SEXT40 (State.a[OP[0]]) - tmp) & MASK40;
1514 trace_output (OP_ACCUM);
1515 }
1516
1517 /* msbu */
1518 void
1519 OP_3800 ()
1520 {
1521 int64 tmp;
1522
1523 trace_input ("msbu", OP_ACCUM, OP_REG, OP_REG);
1524 tmp = SEXT40 (State.regs[OP[1]] * State.regs[OP[2]]);
1525 if (State.FX)
1526 tmp = SEXT40( (tmp << 1) & MASK40);
1527
1528 State.a[OP[0]] = (SEXT40 (State.a[OP[0]]) - tmp) & MASK40;
1529 trace_output (OP_ACCUM);
1530 }
1531
1532 /* mul */
1533 void
1534 OP_2E00 ()
1535 {
1536 trace_input ("mul", OP_REG, OP_REG, OP_VOID);
1537 State.regs[OP[0]] *= State.regs[OP[1]];
1538 trace_output (OP_REG);
1539 }
1540
1541 /* mulx */
1542 void
1543 OP_2C00 ()
1544 {
1545 int64 tmp;
1546
1547 trace_input ("mulx", OP_ACCUM_OUTPUT, OP_REG, OP_REG);
1548 tmp = SEXT40 ((int16)(State.regs[OP[1]]) * (int16)(State.regs[OP[2]]));
1549
1550 if (State.FX)
1551 tmp = SEXT40 ((tmp << 1) & MASK40);
1552
1553 if (State.ST && tmp > MAX32)
1554 State.a[OP[0]] = MAX32;
1555 else
1556 State.a[OP[0]] = tmp & MASK40;
1557 trace_output (OP_ACCUM);
1558 }
1559
1560 /* mulxsu */
1561 void
1562 OP_1C00 ()
1563 {
1564 int64 tmp;
1565
1566 trace_input ("mulxsu", OP_ACCUM_OUTPUT, OP_REG, OP_REG);
1567 tmp = SEXT40 ((int16)(State.regs[OP[1]]) * State.regs[OP[2]]);
1568
1569 if (State.FX)
1570 tmp <<= 1;
1571
1572 State.a[OP[0]] = tmp & MASK40;
1573 trace_output (OP_ACCUM);
1574 }
1575
1576 /* mulxu */
1577 void
1578 OP_3C00 ()
1579 {
1580 uint64 tmp;
1581 uint32 src1;
1582 uint32 src2;
1583
1584 trace_input ("mulxu", OP_ACCUM_OUTPUT, OP_REG, OP_REG);
1585 src1 = (uint16) State.regs[OP[1]];
1586 src2 = (uint16) State.regs[OP[2]];
1587 tmp = src1 * src2;
1588 if (State.FX)
1589 tmp <<= 1;
1590
1591 State.a[OP[0]] = tmp & MASK40;
1592 trace_output (OP_ACCUM);
1593 }
1594
1595 /* mv */
1596 void
1597 OP_4000 ()
1598 {
1599 trace_input ("mv", OP_REG_OUTPUT, OP_REG, OP_VOID);
1600 State.regs[OP[0]] = State.regs[OP[1]];
1601 trace_output (OP_REG);
1602 }
1603
1604 /* mv2w */
1605 void
1606 OP_5000 ()
1607 {
1608 trace_input ("mv2w", OP_DREG_OUTPUT, OP_DREG, OP_VOID);
1609 State.regs[OP[0]] = State.regs[OP[1]];
1610 State.regs[OP[0]+1] = State.regs[OP[1]+1];
1611 trace_output (OP_DREG);
1612 }
1613
1614 /* mv2wfac */
1615 void
1616 OP_3E00 ()
1617 {
1618 trace_input ("mv2wfac", OP_DREG_OUTPUT, OP_ACCUM, OP_VOID);
1619 State.regs[OP[0]] = (State.a[OP[1]] >> 16) & 0xffff;
1620 State.regs[OP[0]+1] = State.a[OP[1]] & 0xffff;
1621 trace_output (OP_DREG);
1622 }
1623
1624 /* mv2wtac */
1625 void
1626 OP_3E01 ()
1627 {
1628 trace_input ("mv2wtac", OP_DREG, OP_ACCUM_OUTPUT, OP_VOID);
1629 State.a[OP[1]] = (SEXT16 (State.regs[OP[0]]) << 16 | State.regs[OP[0]+1]) & MASK40;
1630 trace_output (OP_ACCUM_REVERSE);
1631 }
1632
1633 /* mvac */
1634 void
1635 OP_3E03 ()
1636 {
1637 trace_input ("mvac", OP_ACCUM_OUTPUT, OP_ACCUM, OP_VOID);
1638 State.a[OP[0]] = State.a[OP[1]];
1639 trace_output (OP_ACCUM);
1640 }
1641
1642 /* mvb */
1643 void
1644 OP_5400 ()
1645 {
1646 trace_input ("mvb", OP_REG_OUTPUT, OP_REG, OP_VOID);
1647 State.regs[OP[0]] = SEXT8 (State.regs[OP[1]] & 0xff);
1648 trace_output (OP_REG);
1649 }
1650
1651 /* mvf0f */
1652 void
1653 OP_4400 ()
1654 {
1655 trace_input ("mf0f", OP_REG_OUTPUT, OP_REG, OP_VOID);
1656 if (State.F0 == 0)
1657 State.regs[OP[0]] = State.regs[OP[1]];
1658 trace_output (OP_REG);
1659 }
1660
1661 /* mvf0t */
1662 void
1663 OP_4401 ()
1664 {
1665 trace_input ("mf0t", OP_REG_OUTPUT, OP_REG, OP_VOID);
1666 if (State.F0)
1667 State.regs[OP[0]] = State.regs[OP[1]];
1668 trace_output (OP_REG);
1669 }
1670
1671 /* mvfacg */
1672 void
1673 OP_1E04 ()
1674 {
1675 trace_input ("mvfacg", OP_REG_OUTPUT, OP_ACCUM, OP_VOID);
1676 State.regs[OP[0]] = (State.a[OP[1]] >> 32) & 0xff;
1677 trace_output (OP_ACCUM);
1678 }
1679
1680 /* mvfachi */
1681 void
1682 OP_1E00 ()
1683 {
1684 trace_input ("mvfachi", OP_REG_OUTPUT, OP_ACCUM, OP_VOID);
1685 State.regs[OP[0]] = (State.a[OP[1]] >> 16) & 0xffff;
1686 trace_output (OP_REG);
1687 }
1688
1689 /* mvfaclo */
1690 void
1691 OP_1E02 ()
1692 {
1693 trace_input ("mvfaclo", OP_REG_OUTPUT, OP_ACCUM, OP_VOID);
1694 State.regs[OP[0]] = State.a[OP[1]] & 0xffff;
1695 trace_output (OP_REG);
1696 }
1697
1698 /* mvfc */
1699 void
1700 OP_5200 ()
1701 {
1702 trace_input ("mvfc", OP_REG_OUTPUT, OP_CR, OP_VOID);
1703 if (OP[1] == 0)
1704 {
1705 /* PSW is treated specially */
1706 PSW = 0;
1707 if (State.SM) PSW |= 0x8000;
1708 if (State.EA) PSW |= 0x2000;
1709 if (State.DB) PSW |= 0x1000;
1710 if (State.IE) PSW |= 0x400;
1711 if (State.RP) PSW |= 0x200;
1712 if (State.MD) PSW |= 0x100;
1713 if (State.FX) PSW |= 0x80;
1714 if (State.ST) PSW |= 0x40;
1715 if (State.F0) PSW |= 8;
1716 if (State.F1) PSW |= 4;
1717 if (State.C) PSW |= 1;
1718 }
1719 State.regs[OP[0]] = State.cregs[OP[1]];
1720 trace_output (OP_REG);
1721 }
1722
1723 /* mvtacg */
1724 void
1725 OP_1E41 ()
1726 {
1727 trace_input ("mvtacg", OP_REG, OP_ACCUM, OP_VOID);
1728 State.a[OP[1]] &= MASK32;
1729 State.a[OP[1]] |= (int64)(State.regs[OP[0]] & 0xff) << 32;
1730 trace_output (OP_ACCUM_REVERSE);
1731 }
1732
1733 /* mvtachi */
1734 void
1735 OP_1E01 ()
1736 {
1737 uint16 tmp;
1738
1739 trace_input ("mvtachi", OP_REG, OP_ACCUM, OP_VOID);
1740 tmp = State.a[OP[1]] & 0xffff;
1741 State.a[OP[1]] = (SEXT16 (State.regs[OP[0]]) << 16 | tmp) & MASK40;
1742 trace_output (OP_ACCUM_REVERSE);
1743 }
1744
1745 /* mvtaclo */
1746 void
1747 OP_1E21 ()
1748 {
1749 trace_input ("mvtaclo", OP_REG, OP_ACCUM, OP_VOID);
1750 State.a[OP[1]] = (SEXT16 (State.regs[OP[0]])) & MASK40;
1751 trace_output (OP_ACCUM_REVERSE);
1752 }
1753
1754 /* mvtc */
1755 void
1756 OP_5600 ()
1757 {
1758 trace_input ("mvtc", OP_REG, OP_CR_OUTPUT, OP_VOID);
1759 State.cregs[OP[1]] = State.regs[OP[0]];
1760 if (OP[1] == 0)
1761 {
1762 /* PSW is treated specially */
1763 State.SM = (PSW & 0x8000) ? 1 : 0;
1764 State.EA = (PSW & 0x2000) ? 1 : 0;
1765 State.DB = (PSW & 0x1000) ? 1 : 0;
1766 State.IE = (PSW & 0x400) ? 1 : 0;
1767 State.RP = (PSW & 0x200) ? 1 : 0;
1768 State.MD = (PSW & 0x100) ? 1 : 0;
1769 State.FX = (PSW & 0x80) ? 1 : 0;
1770 State.ST = (PSW & 0x40) ? 1 : 0;
1771 State.F0 = (PSW & 8) ? 1 : 0;
1772 State.F1 = (PSW & 4) ? 1 : 0;
1773 State.C = PSW & 1;
1774 if (State.ST && !State.FX)
1775 {
1776 (*d10v_callback->printf_filtered) (d10v_callback,
1777 "ERROR at PC 0x%x: ST can only be set when FX is set.\n",
1778 PC<<2);
1779 State.exception = SIGILL;
1780 }
1781 }
1782 trace_output (OP_CR_REVERSE);
1783 }
1784
1785 /* mvub */
1786 void
1787 OP_5401 ()
1788 {
1789 trace_input ("mvub", OP_REG_OUTPUT, OP_REG, OP_VOID);
1790 State.regs[OP[0]] = State.regs[OP[1]] & 0xff;
1791 trace_output (OP_REG);
1792 }
1793
1794 /* neg */
1795 void
1796 OP_4605 ()
1797 {
1798 trace_input ("neg", OP_REG, OP_VOID, OP_VOID);
1799 State.regs[OP[0]] = 0 - State.regs[OP[0]];
1800 trace_output (OP_REG);
1801 }
1802
1803 /* neg */
1804 void
1805 OP_5605 ()
1806 {
1807 int64 tmp;
1808
1809 trace_input ("neg", OP_ACCUM, OP_VOID, OP_VOID);
1810 tmp = -SEXT40(State.a[OP[0]]);
1811 if (State.ST)
1812 {
1813 if ( tmp > MAX32)
1814 State.a[OP[0]] = MAX32;
1815 else if (tmp < MIN32)
1816 State.a[OP[0]] = MIN32;
1817 else
1818 State.a[OP[0]] = tmp & MASK40;
1819 }
1820 else
1821 State.a[OP[0]] = tmp & MASK40;
1822 trace_output (OP_ACCUM);
1823 }
1824
1825
1826 /* nop */
1827 void
1828 OP_5E00 ()
1829 {
1830 trace_input ("nop", OP_VOID, OP_VOID, OP_VOID);
1831
1832 ins_type_counters[ (int)State.ins_type ]--; /* don't count nops as normal instructions */
1833 switch (State.ins_type)
1834 {
1835 default:
1836 ins_type_counters[ (int)INS_UNKNOWN ]++;
1837 break;
1838
1839 case INS_LEFT_PARALLEL:
1840 /* Don't count a parallel op that includes a NOP as a true parallel op */
1841 ins_type_counters[ (int)INS_RIGHT_PARALLEL ]--;
1842 ins_type_counters[ (int)INS_RIGHT ]++;
1843 ins_type_counters[ (int)INS_LEFT_NOPS ]++;
1844 break;
1845
1846 case INS_LEFT:
1847 case INS_LEFT_COND_EXE:
1848 ins_type_counters[ (int)INS_LEFT_NOPS ]++;
1849 break;
1850
1851 case INS_RIGHT_PARALLEL:
1852 /* Don't count a parallel op that includes a NOP as a true parallel op */
1853 ins_type_counters[ (int)INS_LEFT_PARALLEL ]--;
1854 ins_type_counters[ (int)INS_LEFT ]++;
1855 ins_type_counters[ (int)INS_RIGHT_NOPS ]++;
1856 break;
1857
1858 case INS_RIGHT:
1859 case INS_RIGHT_COND_EXE:
1860 ins_type_counters[ (int)INS_RIGHT_NOPS ]++;
1861 break;
1862 }
1863
1864 trace_output (OP_VOID);
1865 }
1866
1867 /* not */
1868 void
1869 OP_4603 ()
1870 {
1871 trace_input ("not", OP_REG, OP_VOID, OP_VOID);
1872 State.regs[OP[0]] = ~(State.regs[OP[0]]);
1873 trace_output (OP_REG);
1874 }
1875
1876 /* or */
1877 void
1878 OP_800 ()
1879 {
1880 trace_input ("or", OP_REG, OP_REG, OP_VOID);
1881 State.regs[OP[0]] |= State.regs[OP[1]];
1882 trace_output (OP_REG);
1883 }
1884
1885 /* or3 */
1886 void
1887 OP_4000000 ()
1888 {
1889 trace_input ("or3", OP_REG_OUTPUT, OP_REG, OP_CONSTANT16);
1890 State.regs[OP[0]] = State.regs[OP[1]] | OP[2];
1891 trace_output (OP_REG);
1892 }
1893
1894 /* rac */
1895 void
1896 OP_5201 ()
1897 {
1898 int64 tmp;
1899 int shift = SEXT3 (OP[2]);
1900
1901 trace_input ("rac", OP_DREG_OUTPUT, OP_ACCUM, OP_CONSTANT3);
1902 if (OP[1] != 0)
1903 {
1904 (*d10v_callback->printf_filtered) (d10v_callback,
1905 "ERROR at PC 0x%x: instruction only valid for A0\n",
1906 PC<<2);
1907 State.exception = SIGILL;
1908 }
1909
1910 State.F1 = State.F0;
1911 if (shift >=0)
1912 tmp = ((State.a[0] << 16) | (State.a[1] & 0xffff)) << shift;
1913 else
1914 tmp = ((State.a[0] << 16) | (State.a[1] & 0xffff)) >> -shift;
1915 tmp = ( SEXT60(tmp) + 0x8000 ) >> 16;
1916 if (tmp > MAX32)
1917 {
1918 State.regs[OP[0]] = 0x7fff;
1919 State.regs[OP[0]+1] = 0xffff;
1920 State.F0 = 1;
1921 }
1922 else if (tmp < MIN32)
1923 {
1924 State.regs[OP[0]] = 0x8000;
1925 State.regs[OP[0]+1] = 0;
1926 State.F0 = 1;
1927 }
1928 else
1929 {
1930 State.regs[OP[0]] = (tmp >> 16) & 0xffff;
1931 State.regs[OP[0]+1] = tmp & 0xffff;
1932 State.F0 = 0;
1933 }
1934 trace_output (OP_DREG);
1935 }
1936
1937 /* rachi */
1938 void
1939 OP_4201 ()
1940 {
1941 signed64 tmp;
1942 int shift = SEXT3 (OP[2]);
1943
1944 trace_input ("rachi", OP_REG_OUTPUT, OP_ACCUM, OP_CONSTANT3);
1945 State.F1 = State.F0;
1946 if (shift >=0)
1947 tmp = SEXT40 (State.a[OP[1]]) << shift;
1948 else
1949 tmp = SEXT40 (State.a[OP[1]]) >> -shift;
1950 tmp += 0x8000;
1951
1952 if (tmp > SEXT44 (SIGNED64 (0x0007fffffff)))
1953 {
1954 State.regs[OP[0]] = 0x7fff;
1955 State.F0 = 1;
1956 }
1957 else if (tmp < SEXT44 (SIGNED64 (0xfff80000000)))
1958 {
1959 State.regs[OP[0]] = 0x8000;
1960 State.F0 = 1;
1961 }
1962 else
1963 {
1964 State.regs[OP[0]] = (tmp >> 16) & 0xffff;
1965 State.F0 = 0;
1966 }
1967 trace_output (OP_REG);
1968 }
1969
1970 /* rep */
1971 void
1972 OP_27000000 ()
1973 {
1974 trace_input ("rep", OP_REG, OP_CONSTANT16, OP_VOID);
1975 RPT_S = PC + 1;
1976 RPT_E = PC + OP[1];
1977 RPT_C = State.regs[OP[0]];
1978 State.RP = 1;
1979 if (RPT_C == 0)
1980 {
1981 (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: rep with count=0 is illegal.\n");
1982 State.exception = SIGILL;
1983 }
1984 if (OP[1] < 4)
1985 {
1986 (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: rep must include at least 4 instructions.\n");
1987 State.exception = SIGILL;
1988 }
1989 trace_output (OP_VOID);
1990 }
1991
1992 /* repi */
1993 void
1994 OP_2F000000 ()
1995 {
1996 trace_input ("repi", OP_CONSTANT16, OP_CONSTANT16, OP_VOID);
1997 RPT_S = PC + 1;
1998 RPT_E = PC + OP[1];
1999 RPT_C = OP[0];
2000 State.RP = 1;
2001 if (RPT_C == 0)
2002 {
2003 (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: repi with count=0 is illegal.\n");
2004 State.exception = SIGILL;
2005 }
2006 if (OP[1] < 4)
2007 {
2008 (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: repi must include at least 4 instructions.\n");
2009 State.exception = SIGILL;
2010 }
2011 trace_output (OP_VOID);
2012 }
2013
2014 /* rtd */
2015 void
2016 OP_5F60 ()
2017 {
2018 d10v_callback->printf_filtered(d10v_callback, "ERROR: rtd - NOT IMPLEMENTED\n");
2019 State.exception = SIGILL;
2020 }
2021
2022 /* rte */
2023 void
2024 OP_5F40 ()
2025 {
2026 trace_input ("rte", OP_VOID, OP_VOID, OP_VOID);
2027 PC = BPC;
2028 PSW = BPSW;
2029 trace_output (OP_VOID);
2030 }
2031
2032 /* sadd */
2033 void
2034 OP_1223 ()
2035 {
2036 int64 tmp;
2037
2038 trace_input ("sadd", OP_ACCUM, OP_ACCUM, OP_VOID);
2039 tmp = SEXT40(State.a[OP[0]]) + (SEXT40(State.a[OP[1]]) >> 16);
2040 if (State.ST)
2041 {
2042 if (tmp > MAX32)
2043 State.a[OP[0]] = MAX32;
2044 else if (tmp < MIN32)
2045 State.a[OP[0]] = MIN32;
2046 else
2047 State.a[OP[0]] = tmp & MASK40;
2048 }
2049 else
2050 State.a[OP[0]] = tmp & MASK40;
2051 trace_output (OP_ACCUM);
2052 }
2053
2054 /* setf0f */
2055 void
2056 OP_4611 ()
2057 {
2058 trace_input ("setf0f", OP_REG_OUTPUT, OP_VOID, OP_VOID);
2059 State.regs[OP[0]] = (State.F0 == 0) ? 1 : 0;
2060 trace_output (OP_REG);
2061 }
2062
2063 /* setf0t */
2064 void
2065 OP_4613 ()
2066 {
2067 trace_input ("setf0t", OP_REG_OUTPUT, OP_VOID, OP_VOID);
2068 State.regs[OP[0]] = (State.F0 == 1) ? 1 : 0;
2069 trace_output (OP_REG);
2070 }
2071
2072 /* sleep */
2073 void
2074 OP_5FC0 ()
2075 {
2076 trace_input ("sleep", OP_VOID, OP_VOID, OP_VOID);
2077 State.IE = 1;
2078 trace_output (OP_VOID);
2079 }
2080
2081 /* sll */
2082 void
2083 OP_2200 ()
2084 {
2085 trace_input ("sll", OP_REG, OP_REG, OP_VOID);
2086 State.regs[OP[0]] <<= (State.regs[OP[1]] & 0xf);
2087 trace_output (OP_REG);
2088 }
2089
2090 /* sll */
2091 void
2092 OP_3200 ()
2093 {
2094 int64 tmp;
2095 trace_input ("sll", OP_ACCUM, OP_REG, OP_VOID);
2096 if ((State.regs[OP[1]] & 31) <= 16)
2097 tmp = SEXT40 (State.a[OP[0]]) << (State.regs[OP[1]] & 31);
2098 else
2099 {
2100 (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: shift value %d too large.\n", State.regs[OP[1]] & 31);
2101 State.exception = SIGILL;
2102 return;
2103 }
2104
2105 if (State.ST)
2106 {
2107 if (tmp > MAX32)
2108 State.a[OP[0]] = MAX32;
2109 else if (tmp < 0xffffff80000000LL)
2110 State.a[OP[0]] = MIN32;
2111 else
2112 State.a[OP[0]] = tmp & MASK40;
2113 }
2114 else
2115 State.a[OP[0]] = tmp & MASK40;
2116 trace_output (OP_ACCUM);
2117 }
2118
2119 /* slli */
2120 void
2121 OP_2201 ()
2122 {
2123 trace_input ("slli", OP_REG, OP_CONSTANT16, OP_VOID);
2124 State.regs[OP[0]] <<= OP[1];
2125 trace_output (OP_REG);
2126 }
2127
2128 /* slli */
2129 void
2130 OP_3201 ()
2131 {
2132 int64 tmp;
2133
2134 if (OP[1] == 0)
2135 OP[1] = 16;
2136
2137 trace_input ("slli", OP_ACCUM, OP_CONSTANT16, OP_VOID);
2138 tmp = SEXT40(State.a[OP[0]]) << OP[1];
2139
2140 if (State.ST)
2141 {
2142 if (tmp > MAX32)
2143 State.a[OP[0]] = MAX32;
2144 else if (tmp < 0xffffff80000000LL)
2145 State.a[OP[0]] = MIN32;
2146 else
2147 State.a[OP[0]] = tmp & MASK40;
2148 }
2149 else
2150 State.a[OP[0]] = tmp & MASK40;
2151 trace_output (OP_ACCUM);
2152 }
2153
2154 /* slx */
2155 void
2156 OP_460B ()
2157 {
2158 trace_input ("slx", OP_REG, OP_FLAG, OP_VOID);
2159 State.regs[OP[0]] = (State.regs[OP[0]] << 1) | State.F0;
2160 trace_output (OP_REG);
2161 }
2162
2163 /* sra */
2164 void
2165 OP_2400 ()
2166 {
2167 trace_input ("sra", OP_REG, OP_REG, OP_VOID);
2168 State.regs[OP[0]] = ((int16)(State.regs[OP[0]])) >> (State.regs[OP[1]] & 0xf);
2169 trace_output (OP_REG);
2170 }
2171
2172 /* sra */
2173 void
2174 OP_3400 ()
2175 {
2176 trace_input ("sra", OP_ACCUM, OP_REG, OP_VOID);
2177 if ((State.regs[OP[1]] & 31) <= 16)
2178 State.a[OP[0]] = (SEXT40(State.a[OP[0]]) >> (State.regs[OP[1]] & 31)) & MASK40;
2179 else
2180 {
2181 (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: shift value %d too large.\n", State.regs[OP[1]] & 31);
2182 State.exception = SIGILL;
2183 return;
2184 }
2185
2186 trace_output (OP_ACCUM);
2187 }
2188
2189 /* srai */
2190 void
2191 OP_2401 ()
2192 {
2193 trace_input ("srai", OP_REG, OP_CONSTANT16, OP_VOID);
2194 State.regs[OP[0]] = ((int16)(State.regs[OP[0]])) >> OP[1];
2195 trace_output (OP_REG);
2196 }
2197
2198 /* srai */
2199 void
2200 OP_3401 ()
2201 {
2202 if (OP[1] == 0)
2203 OP[1] = 16;
2204
2205 trace_input ("srai", OP_ACCUM, OP_CONSTANT16, OP_VOID);
2206 State.a[OP[0]] = (SEXT40(State.a[OP[0]]) >> OP[1]) & MASK40;
2207 trace_output (OP_ACCUM);
2208 }
2209
2210 /* srl */
2211 void
2212 OP_2000 ()
2213 {
2214 trace_input ("srl", OP_REG, OP_REG, OP_VOID);
2215 State.regs[OP[0]] >>= (State.regs[OP[1]] & 0xf);
2216 trace_output (OP_REG);
2217 }
2218
2219 /* srl */
2220 void
2221 OP_3000 ()
2222 {
2223 trace_input ("srl", OP_ACCUM, OP_REG, OP_VOID);
2224 if ((State.regs[OP[1]] & 31) <= 16)
2225 State.a[OP[0]] = (uint64)((State.a[OP[0]] & MASK40) >> (State.regs[OP[1]] & 31));
2226 else
2227 {
2228 (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: shift value %d too large.\n", State.regs[OP[1]] & 31);
2229 State.exception = SIGILL;
2230 return;
2231 }
2232
2233 trace_output (OP_ACCUM);
2234 }
2235
2236 /* srli */
2237 void
2238 OP_2001 ()
2239 {
2240 trace_input ("srli", OP_REG, OP_CONSTANT16, OP_VOID);
2241 State.regs[OP[0]] >>= OP[1];
2242 trace_output (OP_REG);
2243 }
2244
2245 /* srli */
2246 void
2247 OP_3001 ()
2248 {
2249 if (OP[1] == 0)
2250 OP[1] = 16;
2251
2252 trace_input ("srli", OP_ACCUM, OP_CONSTANT16, OP_VOID);
2253 State.a[OP[0]] = (uint64)(State.a[OP[0]] & MASK40) >> OP[1];
2254 trace_output (OP_ACCUM);
2255 }
2256
2257 /* srx */
2258 void
2259 OP_4609 ()
2260 {
2261 uint16 tmp;
2262
2263 trace_input ("srx", OP_REG, OP_FLAG, OP_VOID);
2264 tmp = State.F0 << 15;
2265 State.regs[OP[0]] = (State.regs[OP[0]] >> 1) | tmp;
2266 trace_output (OP_REG);
2267 }
2268
2269 /* st */
2270 void
2271 OP_34000000 ()
2272 {
2273 trace_input ("st", OP_REG, OP_MEMREF2, OP_VOID);
2274 SW (OP[1] + State.regs[OP[2]], State.regs[OP[0]]);
2275 trace_output (OP_VOID);
2276 }
2277
2278 /* st */
2279 void
2280 OP_6800 ()
2281 {
2282 trace_input ("st", OP_REG, OP_MEMREF, OP_VOID);
2283 SW (State.regs[OP[1]], State.regs[OP[0]]);
2284 trace_output (OP_VOID);
2285 }
2286
2287 /* st */
2288 void
2289 OP_6C1F ()
2290 {
2291 trace_input ("st", OP_REG, OP_PREDEC, OP_VOID);
2292 if ( OP[1] != 15 )
2293 {
2294 (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: cannot pre-decrement any registers but r15 (SP).\n");
2295 State.exception = SIGILL;
2296 return;
2297 }
2298 State.regs[OP[1]] -= 2;
2299 SW (State.regs[OP[1]], State.regs[OP[0]]);
2300 trace_output (OP_VOID);
2301 }
2302
2303 /* st */
2304 void
2305 OP_6801 ()
2306 {
2307 trace_input ("st", OP_REG, OP_POSTINC, OP_VOID);
2308 SW (State.regs[OP[1]], State.regs[OP[0]]);
2309 INC_ADDR (State.regs[OP[1]],2);
2310 trace_output (OP_VOID);
2311 }
2312
2313 /* st */
2314 void
2315 OP_6C01 ()
2316 {
2317 trace_input ("st", OP_REG, OP_POSTDEC, OP_VOID);
2318 if ( OP[1] == 15 )
2319 {
2320 (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: cannot post-decrement register r15 (SP).\n");
2321 State.exception = SIGILL;
2322 return;
2323 }
2324 SW (State.regs[OP[1]], State.regs[OP[0]]);
2325 INC_ADDR (State.regs[OP[1]],-2);
2326 trace_output (OP_VOID);
2327 }
2328
2329 /* st2w */
2330 void
2331 OP_35000000 ()
2332 {
2333 trace_input ("st2w", OP_DREG, OP_MEMREF2, OP_VOID);
2334 SW (State.regs[OP[2]]+OP[1], State.regs[OP[0]]);
2335 SW (State.regs[OP[2]]+OP[1]+2, State.regs[OP[0]+1]);
2336 trace_output (OP_VOID);
2337 }
2338
2339 /* st2w */
2340 void
2341 OP_6A00 ()
2342 {
2343 trace_input ("st2w", OP_DREG, OP_MEMREF, OP_VOID);
2344 SW (State.regs[OP[1]], State.regs[OP[0]]);
2345 SW (State.regs[OP[1]]+2, State.regs[OP[0]+1]);
2346 trace_output (OP_VOID);
2347 }
2348
2349 /* st2w */
2350 void
2351 OP_6E1F ()
2352 {
2353 trace_input ("st2w", OP_DREG, OP_PREDEC, OP_VOID);
2354 if ( OP[1] != 15 )
2355 {
2356 (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: cannot pre-decrement any registers but r15 (SP).\n");
2357 State.exception = SIGILL;
2358 return;
2359 }
2360 State.regs[OP[1]] -= 4;
2361 SW (State.regs[OP[1]], State.regs[OP[0]]);
2362 SW (State.regs[OP[1]]+2, State.regs[OP[0]+1]);
2363 trace_output (OP_VOID);
2364 }
2365
2366 /* st2w */
2367 void
2368 OP_6A01 ()
2369 {
2370 trace_input ("st2w", OP_DREG, OP_POSTINC, OP_VOID);
2371 SW (State.regs[OP[1]], State.regs[OP[0]]);
2372 SW (State.regs[OP[1]]+2, State.regs[OP[0]+1]);
2373 INC_ADDR (State.regs[OP[1]],4);
2374 trace_output (OP_VOID);
2375 }
2376
2377 /* st2w */
2378 void
2379 OP_6E01 ()
2380 {
2381 trace_input ("st2w", OP_DREG, OP_POSTDEC, OP_VOID);
2382 if ( OP[1] == 15 )
2383 {
2384 (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: cannot post-decrement register r15 (SP).\n");
2385 State.exception = SIGILL;
2386 return;
2387 }
2388 SW (State.regs[OP[1]], State.regs[OP[0]]);
2389 SW (State.regs[OP[1]]+2, State.regs[OP[0]+1]);
2390 INC_ADDR (State.regs[OP[1]],-4);
2391 trace_output (OP_VOID);
2392 }
2393
2394 /* stb */
2395 void
2396 OP_3C000000 ()
2397 {
2398 trace_input ("stb", OP_REG, OP_MEMREF2, OP_VOID);
2399 SB (State.regs[OP[2]]+OP[1], State.regs[OP[0]]);
2400 trace_output (OP_VOID);
2401 }
2402
2403 /* stb */
2404 void
2405 OP_7800 ()
2406 {
2407 trace_input ("stb", OP_REG, OP_MEMREF, OP_VOID);
2408 SB (State.regs[OP[1]], State.regs[OP[0]]);
2409 trace_output (OP_VOID);
2410 }
2411
2412 /* stop */
2413 void
2414 OP_5FE0 ()
2415 {
2416 trace_input ("stop", OP_VOID, OP_VOID, OP_VOID);
2417 State.exception = SIG_D10V_STOP;
2418 trace_output (OP_VOID);
2419 }
2420
2421 /* sub */
2422 void
2423 OP_0 ()
2424 {
2425 uint16 tmp;
2426
2427 trace_input ("sub", OP_REG, OP_REG, OP_VOID);
2428 tmp = State.regs[OP[0]] - State.regs[OP[1]];
2429 State.C = (tmp > State.regs[OP[0]]);
2430 State.regs[OP[0]] = tmp;
2431 trace_output (OP_REG);
2432 }
2433
2434 /* sub */
2435 void
2436 OP_1001 ()
2437 {
2438 int64 tmp;
2439
2440 trace_input ("sub", OP_ACCUM, OP_DREG, OP_VOID);
2441 tmp = SEXT40(State.a[OP[0]]) - (SEXT16 (State.regs[OP[1]]) << 16 | State.regs[OP[1]+1]);
2442 if (State.ST)
2443 {
2444 if ( tmp > MAX32)
2445 State.a[OP[0]] = MAX32;
2446 else if ( tmp < MIN32)
2447 State.a[OP[0]] = MIN32;
2448 else
2449 State.a[OP[0]] = tmp & MASK40;
2450 }
2451 else
2452 State.a[OP[0]] = tmp & MASK40;
2453
2454 trace_output (OP_ACCUM);
2455 }
2456
2457 /* sub */
2458
2459 void
2460 OP_1003 ()
2461 {
2462 int64 tmp;
2463
2464 trace_input ("sub", OP_ACCUM, OP_ACCUM, OP_VOID);
2465 tmp = SEXT40(State.a[OP[0]]) - SEXT40(State.a[OP[1]]);
2466 if (State.ST)
2467 {
2468 if (tmp > MAX32)
2469 State.a[OP[0]] = MAX32;
2470 else if ( tmp < MIN32)
2471 State.a[OP[0]] = MIN32;
2472 else
2473 State.a[OP[0]] = tmp & MASK40;
2474 }
2475 else
2476 State.a[OP[0]] = tmp & MASK40;
2477
2478 trace_output (OP_ACCUM);
2479 }
2480
2481 /* sub2w */
2482 void
2483 OP_1000 ()
2484 {
2485 uint32 tmp,a,b;
2486
2487 trace_input ("sub2w", OP_DREG, OP_DREG, OP_VOID);
2488 a = (uint32)((State.regs[OP[0]] << 16) | State.regs[OP[0]+1]);
2489 b = (uint32)((State.regs[OP[1]] << 16) | State.regs[OP[1]+1]);
2490 /* see ../common/sim-alu.h for a more extensive discussion on how to
2491 compute the carry/overflow bits */
2492 tmp = a - b;
2493 State.C = (a >= b);
2494 State.regs[OP[0]] = (tmp >> 16) & 0xffff;
2495 State.regs[OP[0]+1] = tmp & 0xffff;
2496 trace_output (OP_DREG);
2497 }
2498
2499 /* subac3 */
2500 void
2501 OP_17000000 ()
2502 {
2503 int64 tmp;
2504
2505 trace_input ("subac3", OP_DREG_OUTPUT, OP_DREG, OP_ACCUM);
2506 tmp = SEXT40 ((State.regs[OP[1]] << 16) | State.regs[OP[1]+1]) - SEXT40 (State.a[OP[2]]);
2507 State.regs[OP[0]] = (tmp >> 16) & 0xffff;
2508 State.regs[OP[0]+1] = tmp & 0xffff;
2509 trace_output (OP_DREG);
2510 }
2511
2512 /* subac3 */
2513 void
2514 OP_17000002 ()
2515 {
2516 int64 tmp;
2517
2518 trace_input ("subac3", OP_DREG_OUTPUT, OP_ACCUM, OP_ACCUM);
2519 tmp = SEXT40(State.a[OP[1]]) - SEXT40(State.a[OP[2]]);
2520 State.regs[OP[0]] = (tmp >> 16) & 0xffff;
2521 State.regs[OP[0]+1] = tmp & 0xffff;
2522 trace_output (OP_DREG);
2523 }
2524
2525 /* subac3s */
2526 void
2527 OP_17001000 ()
2528 {
2529 int64 tmp;
2530
2531 trace_input ("subac3s", OP_DREG_OUTPUT, OP_DREG, OP_ACCUM);
2532 State.F1 = State.F0;
2533 tmp = SEXT40 ((State.regs[OP[1]] << 16) | State.regs[OP[1]+1]) - SEXT40(State.a[OP[2]]);
2534 if ( tmp > MAX32)
2535 {
2536 State.regs[OP[0]] = 0x7fff;
2537 State.regs[OP[0]+1] = 0xffff;
2538 State.F0 = 1;
2539 }
2540 else if (tmp < MIN32)
2541 {
2542 State.regs[OP[0]] = 0x8000;
2543 State.regs[OP[0]+1] = 0;
2544 State.F0 = 1;
2545 }
2546 else
2547 {
2548 State.regs[OP[0]] = (tmp >> 16) & 0xffff;
2549 State.regs[OP[0]+1] = tmp & 0xffff;
2550 State.F0 = 0;
2551 }
2552 trace_output (OP_DREG);
2553 }
2554
2555 /* subac3s */
2556 void
2557 OP_17001002 ()
2558 {
2559 int64 tmp;
2560
2561 trace_input ("subac3s", OP_DREG_OUTPUT, OP_ACCUM, OP_ACCUM);
2562 State.F1 = State.F0;
2563 tmp = SEXT40(State.a[OP[1]]) - SEXT40(State.a[OP[2]]);
2564 if ( tmp > MAX32)
2565 {
2566 State.regs[OP[0]] = 0x7fff;
2567 State.regs[OP[0]+1] = 0xffff;
2568 State.F0 = 1;
2569 }
2570 else if (tmp < MIN32)
2571 {
2572 State.regs[OP[0]] = 0x8000;
2573 State.regs[OP[0]+1] = 0;
2574 State.F0 = 1;
2575 }
2576 else
2577 {
2578 State.regs[OP[0]] = (tmp >> 16) & 0xffff;
2579 State.regs[OP[0]+1] = tmp & 0xffff;
2580 State.F0 = 0;
2581 }
2582 trace_output (OP_DREG);
2583 }
2584
2585 /* subi */
2586 void
2587 OP_1 ()
2588 {
2589 unsigned tmp;
2590 if (OP[1] == 0)
2591 OP[1] = 16;
2592
2593 trace_input ("subi", OP_REG, OP_CONSTANT16, OP_VOID);
2594 /* see ../common/sim-alu.h for a more extensive discussion on how to
2595 compute the carry/overflow bits. */
2596 /* since OP[1] is never <= 0, -OP[1] == ~OP[1]+1 can never overflow */
2597 tmp = ((unsigned)(unsigned16) State.regs[OP[0]]
2598 + (unsigned)(unsigned16) ( - OP[1]));
2599 State.C = (tmp >= (1 << 16));
2600 State.regs[OP[0]] = tmp;
2601 trace_output (OP_REG);
2602 }
2603
2604 /* trap */
2605 void
2606 OP_5F00 ()
2607 {
2608 trace_input ("trap", OP_CONSTANT4, OP_VOID, OP_VOID);
2609 trace_output (OP_VOID);
2610
2611 switch (OP[0])
2612 {
2613 default:
2614 #if 0
2615 (*d10v_callback->printf_filtered) (d10v_callback, "Unknown trap code %d\n", OP[0]);
2616 State.exception = SIGILL;
2617 #else
2618 /* Use any other traps for batch debugging. */
2619 {
2620 int i;
2621 static int first_time = 1;
2622
2623 if (first_time)
2624 {
2625 first_time = 0;
2626 (*d10v_callback->printf_filtered) (d10v_callback, "Trap # PC ");
2627 for (i = 0; i < 16; i++)
2628 (*d10v_callback->printf_filtered) (d10v_callback, " %sr%d", (i > 9) ? "" : " ", i);
2629 (*d10v_callback->printf_filtered) (d10v_callback, " a0 a1 f0 f1 c\n");
2630 }
2631
2632 (*d10v_callback->printf_filtered) (d10v_callback, "Trap %2d 0x%.4x:", (int)OP[0], (int)PC);
2633
2634 for (i = 0; i < 16; i++)
2635 (*d10v_callback->printf_filtered) (d10v_callback, " %.4x", (int) State.regs[i]);
2636
2637 for (i = 0; i < 2; i++)
2638 (*d10v_callback->printf_filtered) (d10v_callback, " %.2x%.8lx",
2639 ((int)(State.a[i] >> 32) & 0xff),
2640 ((unsigned long)State.a[i]) & 0xffffffff);
2641
2642 (*d10v_callback->printf_filtered) (d10v_callback, " %d %d %d\n",
2643 State.F0 != 0, State.F1 != 0, State.C != 0);
2644 (*d10v_callback->flush_stdout) (d10v_callback);
2645 break;
2646 }
2647 #endif
2648
2649 case 0: /* old system call trap, to be deleted */
2650 case 15: /* new system call trap */
2651 /* Trap 15 is used for simulating low-level I/O */
2652 {
2653 errno = 0;
2654
2655 /* Registers passed to trap 0 */
2656
2657 #define FUNC State.regs[6] /* function number */
2658 #define PARM1 State.regs[2] /* optional parm 1 */
2659 #define PARM2 State.regs[3] /* optional parm 2 */
2660 #define PARM3 State.regs[4] /* optional parm 3 */
2661 #define PARM4 State.regs[5] /* optional parm 3 */
2662
2663 /* Registers set by trap 0 */
2664
2665 #define RETVAL State.regs[2] /* return value */
2666 #define RETVAL_HIGH State.regs[2] /* return value */
2667 #define RETVAL_LOW State.regs[3] /* return value */
2668 #define RETERR State.regs[4] /* return error code */
2669
2670 /* Turn a pointer in a register into a pointer into real memory. */
2671
2672 #define MEMPTR(x) ((char *)(dmem_addr(x)))
2673
2674 switch (FUNC)
2675 {
2676 #if !defined(__GO32__) && !defined(_WIN32)
2677 case SYS_fork:
2678 RETVAL = fork ();
2679 trace_input ("<fork>", OP_VOID, OP_VOID, OP_VOID);
2680 trace_output (OP_R2);
2681 break;
2682
2683 case SYS_getpid:
2684 trace_input ("<getpid>", OP_VOID, OP_VOID, OP_VOID);
2685 RETVAL = getpid ();
2686 trace_output (OP_R2);
2687 break;
2688
2689 case SYS_kill:
2690 trace_input ("<kill>", OP_REG, OP_REG, OP_VOID);
2691 if (PARM1 == getpid ())
2692 {
2693 trace_output (OP_VOID);
2694 State.exception = PARM2;
2695 }
2696 else
2697 {
2698 int os_sig = -1;
2699 switch (PARM2)
2700 {
2701 #ifdef SIGHUP
2702 case 1: os_sig = SIGHUP; break;
2703 #endif
2704 #ifdef SIGINT
2705 case 2: os_sig = SIGINT; break;
2706 #endif
2707 #ifdef SIGQUIT
2708 case 3: os_sig = SIGQUIT; break;
2709 #endif
2710 #ifdef SIGILL
2711 case 4: os_sig = SIGILL; break;
2712 #endif
2713 #ifdef SIGTRAP
2714 case 5: os_sig = SIGTRAP; break;
2715 #endif
2716 #ifdef SIGABRT
2717 case 6: os_sig = SIGABRT; break;
2718 #elif defined(SIGIOT)
2719 case 6: os_sig = SIGIOT; break;
2720 #endif
2721 #ifdef SIGEMT
2722 case 7: os_sig = SIGEMT; break;
2723 #endif
2724 #ifdef SIGFPE
2725 case 8: os_sig = SIGFPE; break;
2726 #endif
2727 #ifdef SIGKILL
2728 case 9: os_sig = SIGKILL; break;
2729 #endif
2730 #ifdef SIGBUS
2731 case 10: os_sig = SIGBUS; break;
2732 #endif
2733 #ifdef SIGSEGV
2734 case 11: os_sig = SIGSEGV; break;
2735 #endif
2736 #ifdef SIGSYS
2737 case 12: os_sig = SIGSYS; break;
2738 #endif
2739 #ifdef SIGPIPE
2740 case 13: os_sig = SIGPIPE; break;
2741 #endif
2742 #ifdef SIGALRM
2743 case 14: os_sig = SIGALRM; break;
2744 #endif
2745 #ifdef SIGTERM
2746 case 15: os_sig = SIGTERM; break;
2747 #endif
2748 #ifdef SIGURG
2749 case 16: os_sig = SIGURG; break;
2750 #endif
2751 #ifdef SIGSTOP
2752 case 17: os_sig = SIGSTOP; break;
2753 #endif
2754 #ifdef SIGTSTP
2755 case 18: os_sig = SIGTSTP; break;
2756 #endif
2757 #ifdef SIGCONT
2758 case 19: os_sig = SIGCONT; break;
2759 #endif
2760 #ifdef SIGCHLD
2761 case 20: os_sig = SIGCHLD; break;
2762 #elif defined(SIGCLD)
2763 case 20: os_sig = SIGCLD; break;
2764 #endif
2765 #ifdef SIGTTIN
2766 case 21: os_sig = SIGTTIN; break;
2767 #endif
2768 #ifdef SIGTTOU
2769 case 22: os_sig = SIGTTOU; break;
2770 #endif
2771 #ifdef SIGIO
2772 case 23: os_sig = SIGIO; break;
2773 #elif defined (SIGPOLL)
2774 case 23: os_sig = SIGPOLL; break;
2775 #endif
2776 #ifdef SIGXCPU
2777 case 24: os_sig = SIGXCPU; break;
2778 #endif
2779 #ifdef SIGXFSZ
2780 case 25: os_sig = SIGXFSZ; break;
2781 #endif
2782 #ifdef SIGVTALRM
2783 case 26: os_sig = SIGVTALRM; break;
2784 #endif
2785 #ifdef SIGPROF
2786 case 27: os_sig = SIGPROF; break;
2787 #endif
2788 #ifdef SIGWINCH
2789 case 28: os_sig = SIGWINCH; break;
2790 #endif
2791 #ifdef SIGLOST
2792 case 29: os_sig = SIGLOST; break;
2793 #endif
2794 #ifdef SIGUSR1
2795 case 30: os_sig = SIGUSR1; break;
2796 #endif
2797 #ifdef SIGUSR2
2798 case 31: os_sig = SIGUSR2; break;
2799 #endif
2800 }
2801
2802 if (os_sig == -1)
2803 {
2804 trace_output (OP_VOID);
2805 (*d10v_callback->printf_filtered) (d10v_callback, "Unknown signal %d\n", PARM2);
2806 (*d10v_callback->flush_stdout) (d10v_callback);
2807 State.exception = SIGILL;
2808 }
2809 else
2810 {
2811 RETVAL = kill (PARM1, PARM2);
2812 trace_output (OP_R2);
2813 }
2814 }
2815 break;
2816
2817 case SYS_execve:
2818 RETVAL = execve (MEMPTR (PARM1), (char **) MEMPTR (PARM2),
2819 (char **)MEMPTR (PARM3));
2820 trace_input ("<execve>", OP_R2, OP_R3, OP_R4);
2821 trace_output (OP_R2);
2822 break;
2823
2824 #ifdef SYS_execv
2825 case SYS_execv:
2826 RETVAL = execve (MEMPTR (PARM1), (char **) MEMPTR (PARM2), NULL);
2827 trace_input ("<execv>", OP_R2, OP_R3, OP_VOID);
2828 trace_output (OP_R2);
2829 break;
2830 #endif
2831
2832 case SYS_pipe:
2833 {
2834 reg_t buf;
2835 int host_fd[2];
2836
2837 buf = PARM1;
2838 RETVAL = pipe (host_fd);
2839 SW (buf, host_fd[0]);
2840 buf += sizeof(uint16);
2841 SW (buf, host_fd[1]);
2842 trace_input ("<pipe>", OP_R2, OP_VOID, OP_VOID);
2843 trace_output (OP_R2);
2844 }
2845 break;
2846
2847 #ifdef SYS_wait
2848 case SYS_wait:
2849 {
2850 int status;
2851
2852 RETVAL = wait (&status);
2853 if (PARM1)
2854 SW (PARM1, status);
2855 trace_input ("<wait>", OP_R2, OP_VOID, OP_VOID);
2856 trace_output (OP_R2);
2857 }
2858 break;
2859 #endif
2860 #else
2861 case SYS_getpid:
2862 trace_input ("<getpid>", OP_VOID, OP_VOID, OP_VOID);
2863 RETVAL = 1;
2864 trace_output (OP_R2);
2865 break;
2866
2867 case SYS_kill:
2868 trace_input ("<kill>", OP_REG, OP_REG, OP_VOID);
2869 trace_output (OP_VOID);
2870 State.exception = PARM2;
2871 break;
2872 #endif
2873
2874 case SYS_read:
2875 RETVAL = d10v_callback->read (d10v_callback, PARM1, MEMPTR (PARM2),
2876 PARM3);
2877 trace_input ("<read>", OP_R2, OP_R3, OP_R4);
2878 trace_output (OP_R2);
2879 break;
2880
2881 case SYS_write:
2882 if (PARM1 == 1)
2883 RETVAL = (int)d10v_callback->write_stdout (d10v_callback,
2884 MEMPTR (PARM2), PARM3);
2885 else
2886 RETVAL = (int)d10v_callback->write (d10v_callback, PARM1,
2887 MEMPTR (PARM2), PARM3);
2888 trace_input ("<write>", OP_R2, OP_R3, OP_R4);
2889 trace_output (OP_R2);
2890 break;
2891
2892 case SYS_lseek:
2893 {
2894 unsigned long ret = d10v_callback->lseek (d10v_callback, PARM1,
2895 (((unsigned long)PARM2) << 16) || (unsigned long)PARM3,
2896 PARM4);
2897 RETVAL_HIGH = ret >> 16;
2898 RETVAL_LOW = ret & 0xffff;
2899 }
2900 trace_input ("<lseek>", OP_R2, OP_R3, OP_R4);
2901 trace_output (OP_R2R3);
2902 break;
2903
2904 case SYS_close:
2905 RETVAL = d10v_callback->close (d10v_callback, PARM1);
2906 trace_input ("<close>", OP_R2, OP_VOID, OP_VOID);
2907 trace_output (OP_R2);
2908 break;
2909
2910 case SYS_open:
2911 RETVAL = d10v_callback->open (d10v_callback, MEMPTR (PARM1), PARM2);
2912 trace_input ("<open>", OP_R2, OP_R3, OP_R4);
2913 trace_output (OP_R2);
2914 trace_input ("<open>", OP_R2, OP_R3, OP_R4);
2915 trace_output (OP_R2);
2916 break;
2917
2918 case SYS_exit:
2919 State.exception = SIG_D10V_EXIT;
2920 trace_input ("<exit>", OP_R2, OP_VOID, OP_VOID);
2921 trace_output (OP_VOID);
2922 break;
2923
2924 case SYS_stat:
2925 /* stat system call */
2926 {
2927 struct stat host_stat;
2928 reg_t buf;
2929
2930 RETVAL = stat (MEMPTR (PARM1), &host_stat);
2931
2932 buf = PARM2;
2933
2934 /* The hard-coded offsets and sizes were determined by using
2935 * the D10V compiler on a test program that used struct stat.
2936 */
2937 SW (buf, host_stat.st_dev);
2938 SW (buf+2, host_stat.st_ino);
2939 SW (buf+4, host_stat.st_mode);
2940 SW (buf+6, host_stat.st_nlink);
2941 SW (buf+8, host_stat.st_uid);
2942 SW (buf+10, host_stat.st_gid);
2943 SW (buf+12, host_stat.st_rdev);
2944 SLW (buf+16, host_stat.st_size);
2945 SLW (buf+20, host_stat.st_atime);
2946 SLW (buf+28, host_stat.st_mtime);
2947 SLW (buf+36, host_stat.st_ctime);
2948 }
2949 trace_input ("<stat>", OP_R2, OP_R3, OP_VOID);
2950 trace_output (OP_R2);
2951 break;
2952
2953 case SYS_chown:
2954 RETVAL = chown (MEMPTR (PARM1), PARM2, PARM3);
2955 trace_input ("<chown>", OP_R2, OP_R3, OP_R4);
2956 trace_output (OP_R2);
2957 break;
2958
2959 case SYS_chmod:
2960 RETVAL = chmod (MEMPTR (PARM1), PARM2);
2961 trace_input ("<chmod>", OP_R2, OP_R3, OP_R4);
2962 trace_output (OP_R2);
2963 break;
2964
2965 #ifdef SYS_utime
2966 case SYS_utime:
2967 /* Cast the second argument to void *, to avoid type mismatch
2968 if a prototype is present. */
2969 RETVAL = utime (MEMPTR (PARM1), (void *) MEMPTR (PARM2));
2970 trace_input ("<utime>", OP_R2, OP_R3, OP_R4);
2971 trace_output (OP_R2);
2972 break;
2973 #endif
2974
2975 #ifdef SYS_time
2976 case SYS_time:
2977 {
2978 unsigned long ret = time (PARM1 ? MEMPTR (PARM1) : NULL);
2979 RETVAL_HIGH = ret >> 16;
2980 RETVAL_LOW = ret & 0xffff;
2981 }
2982 trace_input ("<time>", OP_R2, OP_R3, OP_R4);
2983 trace_output (OP_R2R3);
2984 break;
2985 #endif
2986
2987 default:
2988 abort ();
2989 }
2990 RETERR = (RETVAL == (uint16) -1) ? d10v_callback->get_errno(d10v_callback) : 0;
2991 break;
2992 }
2993 }
2994 }
2995
2996 /* tst0i */
2997 void
2998 OP_7000000 ()
2999 {
3000 trace_input ("tst0i", OP_REG, OP_CONSTANT16, OP_VOID);
3001 State.F1 = State.F0;
3002 State.F0 = (State.regs[OP[0]] & OP[1]) ? 1 : 0;
3003 trace_output (OP_FLAG);
3004 }
3005
3006 /* tst1i */
3007 void
3008 OP_F000000 ()
3009 {
3010 trace_input ("tst1i", OP_REG, OP_CONSTANT16, OP_VOID);
3011 State.F1 = State.F0;
3012 State.F0 = (~(State.regs[OP[0]]) & OP[1]) ? 1 : 0;
3013 trace_output (OP_FLAG);
3014 }
3015
3016 /* wait */
3017 void
3018 OP_5F80 ()
3019 {
3020 trace_input ("wait", OP_VOID, OP_VOID, OP_VOID);
3021 State.IE = 1;
3022 trace_output (OP_VOID);
3023 }
3024
3025 /* xor */
3026 void
3027 OP_A00 ()
3028 {
3029 trace_input ("xor", OP_REG, OP_REG, OP_VOID);
3030 State.regs[OP[0]] ^= State.regs[OP[1]];
3031 trace_output (OP_REG);
3032 }
3033
3034 /* xor3 */
3035 void
3036 OP_5000000 ()
3037 {
3038 trace_input ("xor3", OP_REG_OUTPUT, OP_REG, OP_CONSTANT16);
3039 State.regs[OP[0]] = State.regs[OP[1]] ^ OP[2];
3040 trace_output (OP_REG);
3041 }
3042
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