sim/d30v/d30v-insns

   1 //  -*- C -*-
   2 //  Mitsubishi Electric Corp. D30V Simulator.
   3 //  Copyright (C) 1997, Free Software Foundation, Inc.
   4 //  Contributed by Cygnus Solutions Inc.
   5 //
   6 //  This file is part of GDB, the GNU debugger.
   7 //
   8 //  This program is free software; you can redistribute it and/or modify
   9 //  it under the terms of the GNU General Public License as published by
  10 //  the Free Software Foundation; either version 2 of the License, or
  11 //  (at your option) any later version.
  12 //
  13 //  This program is distributed in the hope that it will be useful,
  14 //  but WITHOUT ANY WARRANTY; without even the implied warranty of
  15 //  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16 //  GNU General Public License for more details.
  17 //
  18 //  You should have received a copy of the GNU General Public License
  19 //  along with this program; if not, write to the Free Software
  20 //  Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  21 //
  22
  23
  24 define( _BRA,  `1.*,CCC,000')
  25 define( _LOGIC, `1.*,CCC,001')
  26 define( _IMEM, `1.*,CCC,010')
  27 define( _IALU1, `1.*,CCC,100')
  28 define(_IALU2, `1.*,CCC,101')
  29
  30
  31
  32 define(_IMM6, `6.IMM_6S')
  33 define(_IMM12, `12.IMM_12S')
  34 define(_IMM18, `18.IMM_18S')
  35 define(_IMM32, `6.IMM_6L,*,000,8.IMM_8L,00,18.IMM_18L')
  36
  37
  38
  39 // The following is called when ever an illegal instruction is
  40 // encountered
  41 ::internal::illegal
  42         sim_io_eprintf (sd, "illegal instruction at 0x%lx\n", cia);
  43         sim_engine_halt (SD, CPU, NULL, cia, sim_signalled, SIM_SIGILL);
  44
  45 // The following is called when ever an instruction in the wrong
  46 // slot is encountered.
  47 ::internal::wrong_slot
  48         sim_io_eprintf (sd, "wrong slot at 0x%lx\n", cia);
  49         sim_engine_halt (SD, CPU, NULL, cia, sim_signalled, SIM_SIGILL);
  50
  51
  52
  53 // Something illegal that can be used to contact the simulator emul
  54 // library.
  55 define(_EMUL, `1.*,CCC,111')
  56
  57 void::function::do_emul:int imm
  58         /* temp hack - later replace with real interface */
  59         enum {
  60           param1 = 2, param2, param3, param4
  61         };
  62         switch (imm) {
  63         case 0:
  64           {
  65             sim_engine_abort (SD, CPU, cia, "UNIX call emulation unsupported");
  66             break;
  67           }
  68         case 1:
  69           /* Trap 1 - prints a string */
  70           {
  71             address_word str = GPR[param1];
  72             char chr;
  73             while (1) {
  74               chr = MEM (unsigned, str, 1);
  75             if (chr == '\0') break;
  76               sim_io_write_stdout (sd, &chr, sizeof chr);
  77               str++;
  78             }
  79             break;
  80           }
  81         case 3:
  82           /* Trap 3 - writes a character */
  83           {
  84             char chr = GPR[param1];
  85             sim_io_write_stdout (sd, &chr, sizeof chr);
  86             break;
  87           }
  88         case 4:
  89           /* Trap 4 exits with status in [param1] */
  90           {
  91             sim_engine_halt (SD, CPU, NULL, cia, sim_exited, GPR[param1]);
  92             break;
  93           }
  94         case 5:
  95           /* Trap 5 breakpoints.  If the breakpoint system knows about this, it
  96              won't return.  Otherwise, we fall through to treat this as an
  97              unknown instruction.  */
  98           {
  99             sim_handle_breakpoint (SD, CPU, cia);
 100           /* Fall through to default case.*/
 101           }
 102         default:
 103           sim_engine_abort (SD, CPU, cia, "Unknown monitor call %d", imm);
 104         }
 105
 106 _EMUL,00000,00,6.*,6.*,IMM_6S:EMUL:short,emul:iu,mu:EMUL
 107 "syscall <imm>"
 108         do_emul (_SD, imm);
 109 _BRA,00000,00,6.**,6.**,_IMM32:BRA:long:iu,mu:EMUL long
 110 "syscall <imm>"
 111         do_emul (_SD, imm);
 112
 113 // ABS
 114
 115 _IALU1,01000,00,6.RA,6.RB,6.**:IALU1:short:iu,mu:ABS
 116 "abs r<RA>, r<RB>"
 117         WRITE32_QUEUE (Ra, abs(Rb));
 118
 119
 120
 121 // ADD
 122
 123 void::function::do_add:unsigned32 *ra, unsigned32 rb, unsigned32 imm
 124         ALU_BEGIN(rb);
 125         ALU_ADDC(imm);
 126         ALU_END(ra);
 127
 128 _IALU1,00000,00,6.RA,6.RB,6.RC:IALU1:short:iu,mu:ADD
 129 "add r<RA>, r<RB>, r<RC>"
 130         do_add (_SD, Ra, Rb, Rc);
 131 _IALU1,00000,10,6.RA,6.RB,_IMM6:IALU1:short:iu,mu:ADD imm
 132 "add r<RA>, r<RB>, <imm>"
 133         do_add (_SD, Ra, Rb, imm);
 134 _IALU1,00000,10,6.RA,6.RB,_IMM32:IALU1:long:iu,mu:ADD imm long
 135 "add r<RA>, r<RB>, <imm>"
 136         do_add (_SD, Ra, Rb, imm);
 137
 138
 139
 140 // ADD2H
 141
 142 void::function::do_add2h:signed32 *ra, signed32 rb, signed32 imm
 143         unsigned16 ah2 = VH2_4(rb) + VH2_4(imm);
 144         unsigned16 al2 = VL2_4(rb) + VL2_4(imm);
 145         WRITE32_QUEUE (ra, (ah2 << 16) | al2);
 146
 147 _IALU1,00001,00,6.RA,6.RB,6.RC:IALU1:short:iu,mu:ADD2H
 148 "add2h r<RA>, r<RB>, r<RC>"
 149         do_add2h (_SD, Ra, Rb, Rc);
 150 _IALU1,00001,10,6.RA,6.RB,_IMM6:IALU1:short:iu,mu:ADD2H imm
 151 "add2h r<RA>, r<RB>, <imm>"
 152         do_add2h (_SD, Ra, Rb, immHL);
 153 _IALU1,00001,10,6.RA,6.RB,_IMM32:IALU1:long:iu,mu:ADD2H imm long
 154 "add2h r<RA>, r<RB>, <imm>"
 155         do_add2h (_SD, Ra, Rb, imm);
 156
 157
 158
 159 // ADDC
 160
 161 void::function::do_addc:unsigned32 *ra, unsigned32 rb, unsigned32 imm
 162         ALU_BEGIN(rb);
 163         ALU_ADDC_C(imm, ALU_CARRY);
 164         ALU_END(ra);
 165
 166 _IALU1,00100,00,6.RA,6.RB,6.RC:IALU1:short:iu,mu:ADDC
 167 "addc r<RA>, r<RB>, r<RC>"
 168         do_addc (_SD, Ra, Rb, Rc);
 169 _IALU1,00100,10,6.RA,6.RB,_IMM6:IALU1:short:iu,mu:ADDC imm
 170 "addc r<RA>, r<RB>, <imm>"
 171         do_addc (_SD, Ra, Rb, imm);
 172 _IALU1,00100,10,6.RA,6.RB,_IMM32:IALU1:long:iu,mu:ADDC imm long
 173 "addc r<RA>, r<RB>, <imm>"
 174         do_addc (_SD, Ra, Rb, imm);
 175
 176
 177
 178 // ADDHppp
 179
 180 void::function::do_addh_ppp:int ppp, unsigned32 *ra, unsigned32 rb, unsigned32 src
 181         switch (ppp) {
 182         case 0x0: /* LLL */
 183           {
 184           ALU16_BEGIN(VL2_4(rb));
 185           ALU16_ADDC(VL2_4(src));
 186           ALU16_END(ra, 0);
 187           }
 188           break;
 189         case 0x1: /* LLH */
 190           {
 191           ALU16_BEGIN(VL2_4(rb));
 192           ALU16_ADDC(VH2_4(src));
 193           ALU16_END(ra, 0);
 194           }
 195           break;
 196         case 0x2: /* LHL */
 197           {
 198           ALU16_BEGIN(VH2_4(rb));
 199           ALU16_ADDC(VL2_4(src));
 200           ALU16_END(ra, 0);
 201           }
 202           break;
 203         case 0x3: /* LHH */
 204           {
 205           ALU16_BEGIN(VH2_4(rb));
 206           ALU16_ADDC(VH2_4(src));
 207           ALU16_END(ra, 0);
 208           }
 209           break;
 210         case 0x4: /* HLL */
 211           {
 212           ALU16_BEGIN(VL2_4(rb));
 213           ALU16_ADDC(VL2_4(src));
 214           ALU16_END(ra, 1);
 215           }
 216           break;
 217         case 0x5: /* HLH */
 218           {
 219           ALU16_BEGIN(VL2_4(rb));
 220           ALU16_ADDC(VH2_4(src));
 221           ALU16_END(ra, 1);
 222           }
 223           break;
 224         case 0x6: /* HHL */
 225           {
 226           ALU16_BEGIN(VH2_4(rb));
 227           ALU16_ADDC(VL2_4(src));
 228           ALU16_END(ra, 1);
 229           }
 230           break;
 231         case 0x7: /* HHH */
 232           {
 233           ALU16_BEGIN(VH2_4(rb));
 234           ALU16_ADDC(VH2_4(src));
 235           ALU16_END(ra, 1);
 236           }
 237           break;
 238         default:
 239           sim_engine_abort (SD, CPU, cia, "do_addh_ppp - internal error - bad switch");
 240         }
 241 ::%s::ppp:int ppp
 242         switch (ppp)
 243           {
 244           case 0x0: return "lll";
 245           case 0x1: return "llh";
 246           case 0x2: return "lhl";
 247           case 0x3: return "lhh";
 248           case 0x4: return "hll";
 249           case 0x5: return "hlh";
 250           case 0x6: return "hhl";
 251           case 0x7: return "hhh";
 252           default: return "?";
 253           }
 254
 255 _IALU1,10,ppp,00,6.RA,6.RB,6.RC:IALU1:short:iu,mu:ADDHppp
 256 "addh%s<ppp> r<RA>, r<RB>, r<RC>"
 257         do_addh_ppp(_SD, ppp, Ra, Rb, Rc);
 258 _IALU1,10,ppp,10,6.RA,6.RB,_IMM6:IALU1:short:iu,mu:ADDHppp imm
 259 "addh%s<ppp> r<RA>, r<RB>, <imm>"
 260         do_addh_ppp(_SD, ppp, Ra, Rb, immHL);
 261 _IALU1,10,ppp,10,6.RA,6.RB,_IMM32:IALU1:long:iu,mu:ADDHppp imm long
 262 "addh%s<ppp> r<RA>, r<RB>, <imm>"
 263         do_addh_ppp(_SD, ppp, Ra, Rb, imm);
 264
 265
 266
 267 // ADDS
 268
 269 void::function::do_adds:unsigned32 *ra, unsigned32 rb, unsigned32 imm
 270         ALU_BEGIN(rb);
 271         ALU_ADDC(EXTRACTED32(imm, 0, 0));
 272         ALU_END(ra);
 273
 274 _IALU1,00110,00,6.RA,6.RB,6.RC:IALU1:short:iu,mu:ADDS
 275 "adds r<RA>, r<RB>, r<RC>"
 276         do_adds (_SD, Ra, Rb, Rc);
 277 _IALU1,00110,10,6.RA,6.RB,_IMM6:IALU1:short:iu,mu:ADDS imm
 278 "adds r<RA>, r<RB>, <imm>"
 279         do_adds (_SD, Ra, Rb, imm);
 280 _IALU1,00110,10,6.RA,6.RB,_IMM32:IALU1:long:iu,mu:ADDS imm long
 281 "adds r<RA>, r<RB>, <imm>"
 282         do_adds (_SD, Ra, Rb, imm);
 283
 284
 285
 286 // ADDS2H
 287
 288 void::function::do_adds2h:unsigned32 *ra, unsigned32 rb, unsigned32 immHL
 289         unsigned16 high = VH2_4(rb) + EXTRACTED32(immHL, 0, 0);
 290         unsigned16 low = VL2_4(rb) + EXTRACTED32(immHL, 16, 16);
 291         WRITE32_QUEUE (ra, (high << 16) | low);
 292
 293 _IALU1,00111,00,6.RA,6.RB,6.RC:IALU1:short:iu,mu:ADDS2H
 294 "adds2h r<RA>, r<RB>, r<RC>"
 295         do_adds2h (_SD, Ra, Rb, Rc);
 296 _IALU1,00111,10,6.RA,6.RB,_IMM6:IALU1:short:iu,mu:ADDS2H imm
 297 "adds2h r<RA>, r<RB>, <imm>"
 298         do_adds2h (_SD, Ra, Rb, immHL);
 299 _IALU1,00111,10,6.RA,6.RB,_IMM32:IALU1:long:iu,mu:ADDS2H imm long
 300 "adds2h r<RA>, r<RB>, <imm>"
 301         do_adds2h (_SD, Ra, Rb, imm);
 302
 303
 304
 305 // AND
 306
 307 _LOGIC,11000,00,6.RA,6.RB,6.RC:LOGIC:short:iu,mu:AND
 308 "and r<RA>, r<RB>, r<RC>"
 309         WRITE32_QUEUE (Ra, Rb & Rc);
 310 _LOGIC,11000,10,6.RA,6.RB,_IMM6:LOGIC:short:iu,mu:AND imm
 311 "and r<RA>, r<RB>, <imm>"
 312         WRITE32_QUEUE (Ra, Rb & imm);
 313 _LOGIC,11000,10,6.RA,6.RB,_IMM32:LOGIC:long:iu,mu:AND imm long
 314 "and r<RA>, r<RB>, <imm>"
 315         WRITE32_QUEUE (Ra, Rb & imm);
 316
 317
 318 // ANDFG
 319
 320 _LOGIC,01000,00,***,3.FA,***,3.FB,***,3.FC:LOGIC:short:iu,mu:Logical AND Flags
 321 "andfg f<FA>, f<FB>, f<FC>"
 322         PSW_FLAG_SET_QUEUE(FA, PSW_FLAG_VAL(FB) & PSW_FLAG_VAL(FC));
 323 _LOGIC,01000,10,***,3.FA,***,3.FB,_IMM6:LOGIC:short:iu,mu:Logical AND Flags imm
 324 "andfg f<FA>, f<FB>, <imm_6>"
 325         PSW_FLAG_SET_QUEUE(FA, PSW_FLAG_VAL(FB) & (imm_6 & 1));
 326
 327
 328
 329 // AVG
 330
 331 void::function::do_avg:unsigned32 *ra, unsigned32 rb, unsigned32 imm
 332         WRITE32_QUEUE (ra, ((signed64)(signed32)rb + (signed64)(signed32)imm + 1) >> 1);
 333
 334 _IALU1,01010,00,6.RA,6.RB,6.RC:IALU1:short:iu,mu:AVG
 335 "avg r<RA>, r<RB>, r<RC>"
 336         do_avg (_SD, Ra, Rb, Rc);
 337 _IALU1,01010,10,6.RA,6.RB,_IMM6:IALU1:short:iu,mu:AVG imm
 338 "avg r<RA>, r<RB>, <imm>"
 339         do_avg (_SD, Ra, Rb, imm);
 340 _IALU1,01010,10,6.RA,6.RB,_IMM32:IALU1:long:iu,mu:AVG imm long
 341 "avg r<RA>, r<RB>, <imm>"
 342         do_avg (_SD, Ra, Rb, imm);
 343
 344
 345
 346 // AVG2H
 347
 348 void::function::do_avg2h:unsigned32 *ra, unsigned32 rb, unsigned32 imm
 349         unsigned16 high = ((signed32)(signed16)VH2_4(rb) + (signed32)(signed16)VH2_4(imm) + 1) >> 1;
 350         unsigned16 low  = ((signed32)(signed16)VL2_4(rb) + (signed32)(signed16)VL2_4(imm) + 1) >> 1;
 351         WRITE32_QUEUE (ra, (high << 16) | low);
 352
 353 _IALU1,01011,00,6.RA,6.RB,6.RC:IALU1:short:iu,mu:AVG2H
 354 "avg2h r<RA>, r<RB>, r<RC>"
 355         do_avg2h (_SD, Ra, Rb, Rc);
 356 _IALU1,01011,10,6.RA,6.RB,_IMM6:IALU1:short:iu,mu:AVG2H imm
 357 "avg2h r<RA>, r<RB>, <imm>"
 358         do_avg2h (_SD, Ra, Rb, immHL);
 359 _IALU1,01011,10,6.RA,6.RB,_IMM32:IALU1:long:iu,mu:AVG2H imm long
 360 "avg2h r<RA>, r<RB>, <imm>"
 361         do_avg2h (_SD, Ra, Rb, imm);
 362
 363
 364
 365 // BCLR
 366
 367 _LOGIC,00011,00,6.RA,6.RB,6.RC:LOGIC:short:iu,mu:BCLR
 368 "bclr r<RA>, r<RB>, r<RC>"
 369         WRITE32_QUEUE(Ra, Rb & ~BIT32((Rc) % 32));
 370 _LOGIC,00011,10,6.RA,6.RB,_IMM6:LOGIC:short:iu,mu:BCLR imm
 371 "bclr r<RA>, r<RB>, <imm>"
 372         WRITE32_QUEUE(Ra, Rb & ~BIT32((imm) % 32));
 373
 374
 375
 376 // BNOT
 377
 378 _LOGIC,00001,00,6.RA,6.RB,6.RC:LOGIC:short:iu,mu:BNOT
 379 "bnot r<RA>, r<RB>, r<RC>"
 380         WRITE32_QUEUE (Ra, Rb ^ BIT32((Rc) % 32));
 381 _LOGIC,00001,10,6.RA,6.RB,_IMM6:LOGIC:short:iu,mu:BNOT imm
 382 "bnot r<RA>, r<RB>, <imm>"
 383         WRITE32_QUEUE (Ra, Rb ^ BIT32((imm) % 32));
 384
 385
 386
 387 // BRA
 388
 389 _BRA,00000,00,6.**,6.**,6.RC:BRA:short:mu:BRA
 390 "bra r<RC>"
 391         nia = cia + pcdisp;
 392 _BRA,00000,10,_IMM18:BRA:short:mu:BRA imm
 393 "bra <pcdisp>"
 394         nia = cia + pcdisp;
 395 _BRA,00000,10,6.**,6.**,_IMM32:BRA:long:mu:BRA imm long
 396 "bra <pcdisp>"
 397         nia = cia + pcdisp;
 398
 399
 400
 401 // BRATNZ
 402
 403 _BRA,00100,01,6.RA,6.**,6.RC:BRA:short:mu:BRATNZ
 404 "bratnz r<RC>"
 405         if (*Ra != 0)
 406           nia = cia + pcdisp;
 407 _BRA,00100,11,6.RA,_IMM12:BRA:short:mu:BRATNZ imm
 408 "bratnz <pcdisp>"
 409         if (*Ra != 0)
 410           nia = cia + pcdisp;
 411 _BRA,00100,11,6.RA,6.**,_IMM32:BRA:long:mu:BRATNZ imm long
 412 "bratnz <pcdisp>"
 413         if (*Ra != 0)
 414           nia = cia + pcdisp;
 415
 416
 417
 418 // BRATZR
 419
 420 _BRA,00100,00,6.RA,6.**,6.RC:BRA:short:mu:BRATZR
 421 "bratzr r<RC>"
 422         if (val_Ra == 0)
 423           nia = cia + pcdisp;
 424 _BRA,00100,10,6.RA,_IMM12:BRA:short:mu:BRATZR imm
 425 "bratzr <pcdisp>"
 426         if (val_Ra == 0)
 427           nia = cia + pcdisp;
 428 _BRA,00100,10,6.RA,6.**,_IMM32:BRA:long:mu:BRATZR imm long
 429 "bratzr <pcdisp>"
 430         if (val_Ra == 0)
 431           nia = cia + pcdisp;
 432
 433
 434
 435 // BSET
 436
 437 _LOGIC,00010,00,6.RA,6.RB,6.RC:LOGIC:short:iu,mu:BSET
 438 "bset r<RA>, r<RB>, r<RC>"
 439         WRITE32_QUEUE (Ra, Rb | BIT32((Rc) % 32));
 440 _LOGIC,00010,10,6.RA,6.RB,_IMM6:LOGIC:short:iu,mu:BSET imm
 441 "bset r<RA>, r<RB>, <imm>"
 442         WRITE32_QUEUE (Ra, Rb | BIT32((imm) % 32));
 443
 444
 445
 446 // BSR
 447
 448 _BRA,00010,00,6.**,6.**,6.RC:BRA:short:mu:BSR
 449 "bsr r<RC>"
 450         if (cia == RPT_E && PSW_VAL (PSW_RP))
 451           WRITE32_QUEUE (&GPR[62], RPT_S);
 452         else
 453           WRITE32_QUEUE (&GPR[62], cia + 8);
 454         nia = cia + pcdisp;
 455         if (TRACE_CALL_P)
 456           TRACE_ACTION |= TRACE_ACTION_CALL;
 457 _BRA,00010,10,_IMM18:BRA:short:mu:BSR imm
 458 "bsr <pcdisp>"
 459         if (cia == RPT_E && PSW_VAL (PSW_RP))
 460           WRITE32_QUEUE (&GPR[62], RPT_S);
 461         else
 462           WRITE32_QUEUE (&GPR[62], cia + 8);
 463         nia = cia + pcdisp;
 464         if (TRACE_CALL_P)
 465           TRACE_ACTION |= TRACE_ACTION_CALL;
 466 _BRA,00010,10,6.**,6.**,_IMM32:BRA:long:mu:BSR imm long
 467 "bsr <pcdisp>"
 468         if (cia == RPT_E && PSW_VAL (PSW_RP))
 469           WRITE32_QUEUE (&GPR[62], RPT_S);
 470         else
 471           WRITE32_QUEUE (&GPR[62], cia + 8);
 472         nia = cia + pcdisp;
 473         if (TRACE_CALL_P)
 474           TRACE_ACTION |= TRACE_ACTION_CALL;
 475
 476
 477 // BSRTNZ
 478
 479 _BRA,00110,01,6.RA,6.**,6.RC:BRA:short:mu:BSRTNZ
 480 "bsrtnz r<RC>"
 481         if (val_Ra != 0) {
 482           if (cia == RPT_E && PSW_VAL (PSW_RP))
 483             WRITE32_QUEUE (&GPR[62], RPT_S);
 484           else
 485             WRITE32_QUEUE (&GPR[62], cia + 8);
 486           nia = cia + pcdisp;
 487           if (TRACE_CALL_P)
 488             TRACE_ACTION |= TRACE_ACTION_CALL;
 489         }
 490
 491 _BRA,00110,11,6.RA,_IMM12:BRA:short:mu:BSRTNZ imm
 492 "bsrtnz <pcdisp>"
 493         if (val_Ra != 0) {
 494           if (cia == RPT_E && PSW_VAL (PSW_RP))
 495             WRITE32_QUEUE (&GPR[62], RPT_S);
 496           else
 497             WRITE32_QUEUE (&GPR[62], cia + 8);
 498           nia = cia + pcdisp;
 499           if (TRACE_CALL_P)
 500             TRACE_ACTION |= TRACE_ACTION_CALL;
 501         }
 502
 503 _BRA,00110,11,6.RA,6.**,_IMM32:BRA:long:mu:BSRTNZ imm long
 504 "bsrtnz <pcdisp>"
 505         if (val_Ra != 0) {
 506           if (cia == RPT_E && PSW_VAL (PSW_RP))
 507             WRITE32_QUEUE (&GPR[62], RPT_S);
 508           else
 509             WRITE32_QUEUE (&GPR[62], cia + 8);
 510           nia = cia + pcdisp;
 511           if (TRACE_CALL_P)
 512             TRACE_ACTION |= TRACE_ACTION_CALL;
 513         }
 514
 515
 516 // BSRTZR
 517
 518 _BRA,00110,00,6.RA,6.**,6.RC:BRA:short:mu:BSRTZR
 519 "bsrtzr r<RC>"
 520         if (val_Ra == 0) {
 521           if (cia == RPT_E && PSW_VAL (PSW_RP))
 522             WRITE32_QUEUE (&GPR[62], RPT_S);
 523           else
 524             WRITE32_QUEUE (&GPR[62], cia + 8);
 525           nia = cia + pcdisp;
 526           if (TRACE_CALL_P)
 527             TRACE_ACTION |= TRACE_ACTION_CALL;
 528         }
 529
 530 _BRA,00110,10,6.RA,_IMM12:BRA:short:mu:BSRTZR imm
 531 "bsrtzr <pcdisp>"
 532         if (val_Ra == 0) {
 533           if (cia == RPT_E && PSW_VAL (PSW_RP))
 534             WRITE32_QUEUE (&GPR[62], RPT_S);
 535           else
 536             WRITE32_QUEUE (&GPR[62], cia + 8);
 537           nia = cia + pcdisp;
 538           if (TRACE_CALL_P)
 539             TRACE_ACTION |= TRACE_ACTION_CALL;
 540         }
 541
 542 _BRA,00110,10,6.RA,6.**,_IMM32:BRA:long:mu:BSRTZR imm long
 543 "bsrtzr <pcdisp>"
 544         if (val_Ra == 0) {
 545           if (cia == RPT_E && PSW_VAL (PSW_RP))
 546             WRITE32_QUEUE (&GPR[62], RPT_S);
 547           else
 548             WRITE32_QUEUE (&GPR[62], cia + 8);
 549           nia = cia + pcdisp;
 550           if (TRACE_CALL_P)
 551             TRACE_ACTION |= TRACE_ACTION_CALL;
 552         }
 553
 554
 555 // BTST
 556
 557 _LOGIC,00000,00,***,3.FA,6.RB,6.RC:LOGIC:short:iu,mu:BTST
 558 "btst f<FA>, r<RB>, r<RC>"
 559         int bit = (Rc) % 32;
 560         PSW_FLAG_SET_QUEUE(FA, MASKED32(Rb, bit, bit));
 561 _LOGIC,00000,10,***,3.FA,6.RB,_IMM6:LOGIC:short:iu,mu:BTST imm
 562 "btst f<FA>, r<RB>, <imm>"
 563         int bit = imm % 32;
 564         PSW_FLAG_SET_QUEUE(FA, MASKED32(Rb, bit, bit));
 565
 566
 567
 568 // CMPcc
 569
 570 void::function::do_cmp_cc:int cc, int fa, signed32 rb, signed32 rc
 571         int value = 0;
 572         switch (cc) {
 573         case 0: /* EQ */
 574           value = (rb == rc);
 575           break;
 576         case 1: /* NE */
 577           value = (rb != rc);
 578           break;
 579         case 2: /* GT */
 580           value = (rb > rc);
 581           break;
 582         case 3: /* GE */
 583           value = (rb >= rc);
 584           break;
 585         case 4: /* LT */
 586           value = (rb < rc);
 587           break;
 588         case 5: /* LE */
 589           value = (rb <= rc);
 590           break;
 591         case 6: /* PS */
 592           value = ((rb >= 0) && (rc >= 0));
 593           break;
 594         case 7: /* NG */
 595           value = ((rb < 0) && (rc < 0));
 596           break;
 597         default:
 598           sim_engine_abort (SD, CPU, cia, "do_cmp_cc - internal error - bad switch (%d)", cc);
 599         }
 600         PSW_FLAG_SET_QUEUE(fa, value);
 601
 602 ::%s::ccc:int ccc
 603         switch (ccc)
 604           {
 605           case 0: return "eq";
 606           case 1: return "ne";
 607           case 2: return "gt";
 608           case 3: return "ge";
 609           case 4: return "lt";
 610           case 5: return "le";
 611           case 6: return "ps";
 612           case 7: return "ng";
 613           default: return "?";
 614           }
 615
 616 _LOGIC,01100,00,ccc,3.FA,6.RB,6.RC:LOGIC:short:iu,mu:CMPcc
 617 "cmp%s<ccc> f<FA>, r<RB>, r<RC>"
 618         do_cmp_cc(_SD, ccc, FA, Rb, Rc);
 619 _LOGIC,01100,10,ccc,3.FA,6.RB,_IMM6:LOGIC:short:iu,mu:CMPcc imm
 620 "cmp%s<ccc> f<FA>, r<RB>, <imm>"
 621         do_cmp_cc(_SD, ccc, FA, Rb, imm);
 622 _LOGIC,01100,10,ccc,3.FA,6.RB,_IMM32:LOGIC:long:iu,mu:CMPcc imm long
 623 "cmp%s<ccc> f<FA>, r<RB>, <imm>"
 624         do_cmp_cc(_SD, ccc, FA, Rb, imm);
 625
 626
 627
 628 // CMPUcc
 629
 630 void::function::do_cmpu_cc:int cc, int fa, unsigned32 rb, unsigned32 rc
 631         int value = 0;
 632         switch (cc) {
 633         case 2: /* GT */
 634           value = (rb > rc);
 635           break;
 636         case 3: /* GE */
 637           value = (rb >= rc);
 638           break;
 639         case 4: /* LT */
 640           value = (rb < rc);
 641           break;
 642         case 5: /* LE */
 643           value = (rb <= rc);
 644           break;
 645         default:
 646           sim_engine_abort (SD, CPU, cia, "do_cmpu_cc - internal error - bad switch (%d)", cc);
 647         }
 648         PSW_FLAG_SET_QUEUE(fa, value);
 649
 650 _LOGIC,01101,00,ccc,3.FA,6.RB,6.RC:LOGIC:short:iu,mu:CMPUcc
 651 "cmpu%s<ccc> f<FA>, r<RB>, r<RC>"
 652         do_cmpu_cc(_SD, ccc, FA, Rb, Rc);
 653 _LOGIC,01101,10,ccc,3.FA,6.RB,_IMM6:LOGIC:short:iu,mu:CMPUcc imm
 654 "cmpu%s<ccc> f<FA>, r<RB>, <imm>"
 655         do_cmpu_cc(_SD, ccc, FA, Rb, imm_6u);
 656 _LOGIC,01101,10,ccc,3.FA,6.RB,_IMM32:LOGIC:long:iu,mu:CMPUcc imm long
 657 "cmpu%s<ccc> f<FA>, r<RB>, <imm>"
 658         do_cmpu_cc(_SD, ccc, FA, Rb, imm);
 659
 660
 661
 662 // DBRA
 663
 664 void::function::do_dbra:address_word pcdisp, unsigned32 ra
 665         PSW_SET_QUEUE (PSW_RP, 1);
 666         WRITE32_QUEUE (&RPT_C, 1);
 667         WRITE32_QUEUE (&RPT_S, cia + pcdisp);
 668         WRITE32_QUEUE (&RPT_E, cia + (ra & ~0x7));
 669
 670 _BRA,10000,00,6.RA,6.**,6.RC:BRA:short:mu:DBRA
 671 "dbra r<RA>, r<RC>"
 672         do_dbra(_SD, pcdisp, val_Ra);
 673 _BRA,10000,10,6.RA,_IMM12:BRA:short:mu:DBRA imm
 674 "dbra r<RA>, <pcdisp>"
 675         do_dbra(_SD, pcdisp, val_Ra);
 676 _BRA,10000,10,6.RA,6.**,_IMM32:BRA:long:mu:DBRA imm long
 677 "dbra r<RA>, <pcdisp>"
 678         do_dbra(_SD, pcdisp, val_Ra);
 679
 680
 681
 682 // DBRAI
 683
 684 void::function::do_dbrai:address_word pcdisp, unsigned32 imm
 685         PSW_SET_QUEUE (PSW_RP, 1);
 686         WRITE32_QUEUE (&RPT_C, 1);
 687         WRITE32_QUEUE (&RPT_S, cia + pcdisp);
 688         WRITE32_QUEUE (&RPT_E, cia + (imm << 3));
 689
 690 _BRA,10100,00,6.IMM_6,6.**,6.RC:BRA:short:mu:DBRAI
 691 "dbrai <IMM_6>, r<RC>"
 692         do_dbrai(_SD, pcdisp, IMM_6);
 693 _BRA,10100,10,6.IMM_6,_IMM12:BRA:short:mu:DBRAI imm
 694 "dbrai <IMM_6>, <pcdisp>"
 695         do_dbrai(_SD, pcdisp, IMM_6);
 696 _BRA,10100,10,6.IMM_6,6.**,_IMM32:BRA:long:mu:DBRAI imm long
 697 "dbrai <IMM_6>, <pcdisp>"
 698         do_dbrai(_SD, pcdisp, IMM_6);
 699
 700
 701
 702 // DBSR
 703
 704 void::function::do_dbsr:address_word pcdisp, unsigned32 ra
 705         PSW_SET_QUEUE (PSW_RP, 1);
 706         WRITE32_QUEUE (&RPT_C, 1);
 707         WRITE32_QUEUE (&RPT_S, cia + pcdisp);
 708         WRITE32_QUEUE (&RPT_E, cia + ra);
 709         WRITE32_QUEUE (&GPR[62], cia + ra + 8);
 710
 711 _BRA,10010,00,6.RA,6.**,6.RC:BRA:short:mu:DBSR
 712 "dbsr r<RA>, r<RC>"
 713         do_dbsr(_SD, pcdisp, val_Ra);
 714 _BRA,10010,10,6.RA,_IMM12:BRA:short:mu:DBSR imm
 715 "dbsr r<RA>, <pcdisp>"
 716         do_dbsr(_SD, pcdisp, val_Ra);
 717 _BRA,10010,10,6.RA,6.**,_IMM32:BRA:long:mu:DBSR imm long
 718 "dbsr r<RA>, <pcdisp>"
 719         do_dbsr(_SD, pcdisp, val_Ra);
 720
 721
 722
 723 // DBSRI
 724
 725 void::function::do_dbsri:address_word pcdisp, unsigned32 imm
 726         PSW_SET_QUEUE (PSW_RP, 1);
 727         WRITE32_QUEUE (&RPT_C, 1);
 728         WRITE32_QUEUE (&RPT_S, cia + pcdisp);
 729         WRITE32_QUEUE (&RPT_E, cia + (imm << 3));
 730         WRITE32_QUEUE (&GPR[62], cia + (imm << 3) + 8);
 731
 732 _BRA,10110,00,6.IMM_6,6.**,6.RC:BRA:short:mu:DBSRI
 733 "dbsri <IMM_6>, r<RC>"
 734         do_dbsri(_SD, pcdisp, IMM_6);
 735 _BRA,10110,10,6.IMM_6,_IMM12:BRA:short:mu:DBSRI imm
 736 "dbsri <IMM_6>, <pcdisp>"
 737         do_dbsri(_SD, pcdisp, IMM_6);
 738 _BRA,10110,10,6.IMM_6,6.**,_IMM32:BRA:long:mu:DBSRI imm long
 739 "dbsri <IMM_6>, <pcdisp>"
 740         do_dbsri(_SD, pcdisp, IMM_6);
 741
 742
 743
 744 // DBT
 745
 746
 747 _BRA,01011,00,6.**,6.**,6.**:BRA:short:mu:DBT
 748 "dbt"
 749         if (cia == RPT_E && PSW_VAL (PSW_RP))
 750           {
 751             WRITE32_QUEUE (&DPC, RPT_S);
 752             if (RPT_C == 0)
 753               PSW_SET (PSW_RP, 0);
 754           }
 755         else
 756           WRITE32_QUEUE (&DPC, cia + 8);
 757         DID_TRAP = 2;
 758         nia = 0xfffff120; /* debug_trap_address */
 759
 760 // DJMP
 761
 762 void::function::do_djmp:address_word pcdisp, unsigned32 ra
 763         PSW_SET_QUEUE (PSW_RP, 1);
 764         WRITE32_QUEUE (&RPT_C, 1);
 765         WRITE32_QUEUE (&RPT_S, pcdisp);
 766         WRITE32_QUEUE (&RPT_E, cia + (ra & ~0x7));
 767
 768 _BRA,10001,00,6.RA,6.**,6.RC:BRA:short:mu:DJMP
 769 "djmp r<RA>, r<RC>"
 770         do_djmp(_SD, pcdisp, val_Ra);
 771 _BRA,10001,10,6.RA,_IMM12:BRA:short:mu:DJMP imm
 772 "djmp r<RA>, <pcdisp>"
 773         do_djmp(_SD, pcdisp, val_Ra);
 774 _BRA,10001,10,6.RA,6.**,_IMM32:BRA:long:mu:DJMP imm long
 775 "djmp r<RA>, <pcdisp>"
 776         do_djmp(_SD, pcdisp, val_Ra);
 777
 778
 779
 780 // DJMPI
 781
 782 void::function::do_djmpi:address_word pcdisp, unsigned32 imm
 783         PSW_SET_QUEUE (PSW_RP, 1);
 784         WRITE32_QUEUE (&RPT_C, 1);
 785         WRITE32_QUEUE (&RPT_S, pcdisp);
 786         WRITE32_QUEUE (&RPT_E, cia + (imm << 3));
 787
 788 _BRA,10101,00,6.IMM_6,6.**,6.RC:BRA:short:mu:DJMPI
 789 "djmpi <IMM_6>, r<RC>"
 790         do_djmpi(_SD, pcdisp, IMM_6);
 791 _BRA,10101,10,6.IMM_6,_IMM12:BRA:short:mu:DJMPI imm
 792 "djmpi <IMM_6>, <pcdisp>"
 793         do_djmpi(_SD, pcdisp, IMM_6);
 794 _BRA,10101,10,6.IMM_6,6.**,_IMM32:BRA:long:mu:DJMPI imm long
 795 "djmpi <IMM_6>, <pcdisp>"
 796         do_djmpi(_SD, pcdisp, IMM_6);
 797
 798
 799
 800 // DJSR
 801
 802 void::function::do_djsr:address_word pcdisp, unsigned32 ra
 803         PSW_SET_QUEUE (PSW_RP, 1);
 804         WRITE32_QUEUE (&RPT_C, 1);
 805         WRITE32_QUEUE (&RPT_S, pcdisp);
 806         WRITE32_QUEUE (&RPT_E, cia + (ra & ~0x7));
 807         WRITE32_QUEUE (&GPR[62], cia + (ra & ~0x7) + 8);
 808
 809 _BRA,10011,00,6.RA,6.**,6.RC:BRA:short:mu:DJSR
 810 "djsr r<RA>, r<RC>"
 811         do_djsr(_SD, pcdisp, val_Ra);
 812 _BRA,10011,10,6.RA,_IMM12:BRA:short:mu:DJSR imm
 813 "djsr r<RA>, <pcdisp>"
 814         do_djsr(_SD, pcdisp, val_Ra);
 815 _BRA,10011,10,6.RA,6.**,_IMM32:BRA:long:mu:DJSR imm long
 816 "djsr r<RA>, <pcdisp>"
 817         do_djsr(_SD, pcdisp, val_Ra);
 818
 819
 820
 821 // DJSRI
 822
 823 void::function::do_djsri:address_word pcdisp, unsigned32 imm
 824         PSW_SET_QUEUE (PSW_RP, 1);
 825         WRITE32_QUEUE (&RPT_C, 1);
 826         WRITE32_QUEUE (&RPT_S, pcdisp);
 827         WRITE32_QUEUE (&RPT_E, cia + (imm << 3));
 828         WRITE32_QUEUE (&GPR[62], cia + (imm << 3) + 8);
 829
 830 _BRA,10111,00,6.IMM_6,6.**,6.RC:BRA:short:mu:DJSRI
 831 "djsri <IMM_6>, r<RC>"
 832         do_djsri(_SD, pcdisp, IMM_6);
 833 _BRA,10111,10,6.IMM_6,_IMM12:BRA:short:mu:DJSRI imm
 834 "djsri <IMM_6>, <pcdisp>"
 835         do_djsri(_SD, pcdisp, IMM_6);
 836 _BRA,10111,10,6.IMM_6,6.**,_IMM32:BRA:long:mu:DJSRI imm long
 837 "djsri <IMM_6>, <pcdisp>"
 838         do_djsri(_SD, pcdisp, IMM_6);
 839
 840
 841
 842 // JMP
 843
 844 _BRA,00001,00,6.**,6.**,6.RC:BRA:short:mu:JMP
 845 "jmp r<RC>"
 846         nia = pcaddr;
 847         if (RC == 62 && TRACE_CALL_P)
 848           TRACE_ACTION |= TRACE_ACTION_RETURN;
 849 _BRA,00001,10,_IMM18:BRA:short:mu:JMP imm
 850 "jmp <pcdisp>"
 851         nia = pcaddr;
 852 _BRA,00001,10,6.**,6.**,_IMM32:BRA:long:mu:JMP imm long
 853 "jmp <pcdisp>"
 854         nia = pcaddr;
 855
 856
 857
 858 // JMPTNZ
 859
 860 _BRA,00101,01,6.RA,6.**,6.RC:BRA:short:mu:JMPTNZ
 861 "jmptnz r<RC>"
 862         if (val_Ra != 0)
 863           nia = pcaddr;
 864 _BRA,00101,11,6.RA,_IMM12:BRA:short:mu:JMPTNZ imm
 865 "jmptnz <pcdisp>"
 866         if (val_Ra != 0)
 867           nia = pcaddr;
 868 _BRA,00101,11,6.RA,6.**,_IMM32:BRA:long:mu:JMPTNZ imm long
 869 "jmptnz <pcdisp>"
 870         if (val_Ra != 0)
 871           nia = pcaddr;
 872
 873
 874
 875 // JMPTZR
 876
 877 _BRA,00101,00,6.RA,6.**,6.RC:BRA:short:mu:JMPTZR
 878 "jmptzr r<RC>"
 879         if (val_Ra == 0)
 880           nia = pcaddr;
 881 _BRA,00101,10,6.RA,_IMM12:BRA:short:mu:JMPTZR imm
 882 "jmptzr <pcdisp>"
 883         if (val_Ra == 0)
 884           nia = pcaddr;
 885 _BRA,00101,10,6.RA,6.**,_IMM32:BRA:long:mu:JMPTZR imm long
 886 "jmptzr <pcdisp>"
 887         if (val_Ra == 0)
 888           nia = pcaddr;
 889
 890
 891
 892 // JOINpp
 893
 894 void::function::do_join_pp:int pp, unsigned32 *ra, unsigned32 rb, unsigned32 src
 895         switch (pp) {
 896         case 0x0: /* LL */
 897           WRITE32_QUEUE (ra, ((unsigned32)VL2_4(rb) << 16) | VL2_4(src));
 898           break;
 899         case 0x1: /* LH */
 900           WRITE32_QUEUE (ra, ((unsigned32)VL2_4(rb) << 16) | VH2_4(src));
 901           break;
 902         case 0x2: /* HL */
 903           WRITE32_QUEUE (ra, ((unsigned32)VH2_4(rb) << 16) | VL2_4(src));
 904           break;
 905         case 0x3: /* HH */
 906           WRITE32_QUEUE (ra, ((unsigned32)VH2_4(rb) << 16) | VH2_4(src));
 907           break;
 908         }
 909
 910 ::%s::pp:int pp
 911         switch (pp)
 912           {
 913           case 0x0: return "ll";
 914           case 0x1: return "lh";
 915           case 0x2: return "hl";
 916           case 0x3: return "hh";
 917           default: return "?";
 918           }
 919
 920 _IALU1,011,pp,00,6.RA,6.RB,6.RC:IALU1:short:iu,mu:JOINpp
 921 "join%s<pp> r<RA>, r<RB>, r<RC>"
 922         do_join_pp(_SD, pp, Ra, Rb, Rc);
 923 _IALU1,011,pp,10,6.RA,6.RB,_IMM6:IALU1:short:iu,mu:JOINpp imm
 924 "join%s<pp> r<RA>, r<RB>, <imm>"
 925         do_join_pp(_SD, pp, Ra, Rb, immHL);
 926 _IALU1,011,pp,10,6.RA,6.RB,_IMM32:IALU1:long:iu,mu:JOINpp imm long
 927 "join%s<pp> r<RA>, r<RB>, <imm>"
 928         do_join_pp(_SD, pp, Ra, Rb, immHL);
 929
 930
 931
 932 // JSR
 933
 934 _BRA,00011,00,6.**,6.**,6.RC:BRA:short:mu:JSR
 935 "jsr r<RC>"
 936         if (cia == RPT_E && PSW_VAL (PSW_RP))
 937           WRITE32_QUEUE (&GPR[62], RPT_S);
 938         else
 939           WRITE32_QUEUE (&GPR[62], cia + 8);
 940         if (TRACE_CALL_P)
 941           TRACE_ACTION |= TRACE_ACTION_CALL;
 942         return pcaddr;
 943 _BRA,00011,10,_IMM18:BRA:short:mu:JSR imm
 944 "jsr <pcdisp>"
 945         if (cia == RPT_E && PSW_VAL (PSW_RP))
 946           WRITE32_QUEUE (&GPR[62], RPT_S);
 947         else
 948           WRITE32_QUEUE (&GPR[62], cia + 8);
 949         if (TRACE_CALL_P)
 950           TRACE_ACTION |= TRACE_ACTION_CALL;
 951         return pcaddr;
 952 _BRA,00011,10,6.**,6.**,_IMM32:BRA:long:mu:JSR imm long
 953 "jsr <pcdisp>"
 954         if (cia == RPT_E && PSW_VAL (PSW_RP))
 955           WRITE32_QUEUE (&GPR[62], RPT_S);
 956         else
 957           WRITE32_QUEUE (&GPR[62], cia + 8);
 958         if (TRACE_CALL_P)
 959           TRACE_ACTION |= TRACE_ACTION_CALL;
 960         return pcaddr;
 961
 962
 963 // JSRTNZ
 964
 965 _BRA,00111,01,6.RA,6.**,6.RC:BRA:short:mu:JSRTNZ
 966 "jsrtnz r<RC>"
 967         if (val_Ra != 0) {
 968           if (cia == RPT_E && PSW_VAL (PSW_RP))
 969             WRITE32_QUEUE (&GPR[62], RPT_S);
 970           else
 971             WRITE32_QUEUE (&GPR[62], cia + 8);
 972           nia = pcaddr;
 973           if (TRACE_CALL_P)
 974             TRACE_ACTION |= TRACE_ACTION_CALL;
 975         }
 976 _BRA,00111,11,6.RA,_IMM12:BRA:short:mu:JSRTNZ imm
 977 "jsrtnz <pcdisp>"
 978         if (val_Ra != 0) {
 979           if (cia == RPT_E && PSW_VAL (PSW_RP))
 980             WRITE32_QUEUE (&GPR[62], RPT_S);
 981           else
 982             WRITE32_QUEUE (&GPR[62], cia + 8);
 983           nia = pcaddr;
 984           if (TRACE_CALL_P)
 985             TRACE_ACTION |= TRACE_ACTION_CALL;
 986         }
 987 _BRA,00111,11,6.RA,6.**,_IMM32:BRA:long:mu:JSRTNZ imm long
 988 "jsrtnz <pcdisp>"
 989         if (val_Ra != 0) {
 990           if (cia == RPT_E && PSW_VAL (PSW_RP))
 991             WRITE32_QUEUE (&GPR[62], RPT_S);
 992           else
 993             WRITE32_QUEUE (&GPR[62], cia + 8);
 994           nia = pcaddr;
 995           if (TRACE_CALL_P)
 996             TRACE_ACTION |= TRACE_ACTION_CALL;
 997         }
 998
 999
1000
1001 // JSRTZR
1002
1003 _BRA,00111,00,6.RA,6.**,6.RC:BRA:short:mu:JSRTZR
1004 "jsrtzr r<RC>"
1005         if (val_Ra == 0) {
1006           if (cia == RPT_E && PSW_VAL (PSW_RP))
1007             WRITE32_QUEUE (&GPR[62], RPT_S);
1008           else
1009             WRITE32_QUEUE (&GPR[62], cia + 8);
1010           nia = pcaddr;
1011           if (TRACE_CALL_P)
1012             TRACE_ACTION |= TRACE_ACTION_CALL;
1013         }
1014 _BRA,00111,10,6.RA,_IMM12:BRA:short:mu:JSRTZR imm
1015 "jsrtzr <pcdisp>"
1016         if (val_Ra == 0) {
1017           if (cia == RPT_E && PSW_VAL (PSW_RP))
1018             WRITE32_QUEUE (&GPR[62], RPT_S);
1019           else
1020             WRITE32_QUEUE (&GPR[62], cia + 8);
1021           nia = pcaddr;
1022           if (TRACE_CALL_P)
1023             TRACE_ACTION |= TRACE_ACTION_CALL;
1024         }
1025 _BRA,00111,10,6.RA,6.**,_IMM32:BRA:long:mu:JSRTZR imm long
1026 "jsrtzr <pcdisp>"
1027         if (val_Ra == 0) {
1028           if (cia == RPT_E && PSW_VAL (PSW_RP))
1029             WRITE32_QUEUE (&GPR[62], RPT_S);
1030           else
1031             WRITE32_QUEUE (&GPR[62], cia + 8);
1032           nia = pcaddr;
1033           if (TRACE_CALL_P)
1034             TRACE_ACTION |= TRACE_ACTION_CALL;
1035         }
1036
1037
1038
1039 // Post increment
1040
1041 void::function::do_incr:int x, unsigned32 *rb, int delta
1042         unsigned32 next_rb;
1043         if (x == 1)
1044           next_rb = *rb + delta;
1045         else if (x == 3)
1046           next_rb = *rb - delta;
1047         else
1048           next_rb = *rb; /* value not used */
1049         /* HW erratum: check value after incrementing */
1050         if (next_rb == MOD_E
1051             && (x == 1 || x == 3)
1052             && (PSW_VAL(PSW_MD))) {
1053           WRITE32_QUEUE (rb, MOD_S);
1054         }
1055         else if (x == 1 || x == 3)
1056           WRITE32_QUEUE (rb, next_rb);
1057
1058 // LD2H
1059
1060 int::function::make_even_reg:int reg, const char *name
1061         if (reg & 1)
1062           sim_engine_abort (SD, CPU, cia,
1063                             "0x%lx:%s odd register (r%d) used in multi-word load/mulx2h",
1064                             cia, name, reg);
1065         return reg;
1066
1067 void::function::do_ld2h:int ra, unsigned32 rb, unsigned32 src
1068         signed32 mem;
1069         ra = make_even_reg(_SD, ra, "LD2H");
1070         mem = MEM(signed, rb + src, 4);
1071         if (ra != 0)
1072         {
1073           WRITE32_QUEUE (&GPR[ra + 0], SEXT32(EXTRACTED32(mem, 0, 15), 16));
1074           WRITE32_QUEUE (&GPR[ra + 1], SEXT32(EXTRACTED32(mem, 16, 31), 16));
1075         }
1076
1077 ::%s::XX:int XX
1078         switch (XX)
1079           {
1080           case 0: return "";
1081           case 1: return "+";
1082           case 3: return "-";
1083           default: return "?";
1084           }
1085
1086 _IMEM,00011,XX,6.RA,6.RB,6.SRC_6:IMEM:short:mu:LD2H
1087 "ld2h r<RA>, @(r<RB>, <SRC_6>)":XX == 0
1088 "ld2h r<RA>, @(r<RB>%s<XX>, r<SRC_6>)"
1089         do_ld2h(_SD, RA, Rb, src);
1090         do_incr(_SD, XX, &GPR[RB], 4);
1091 _IMEM,00011,10,6.RA,6.RB,_IMM32:IMEM:long:mu:LD2H long
1092 "ld2h r<RA>, @(r<RB>, <imm>)"
1093         do_ld2h(_SD, RA, Rb, imm);
1094
1095
1096
1097 // LD2W
1098
1099 void::function::do_ld2w:int ra, unsigned32 rb, unsigned32 src
1100         unsigned64 mem;
1101         ra = make_even_reg(_SD, ra, "LD2W");
1102         mem = MEM(unsigned, rb + src, 8);
1103         if (ra != 0)
1104         {
1105           WRITE32_QUEUE (&GPR[ra + 0], EXTRACTED64 (mem, 0, 31));
1106           WRITE32_QUEUE (&GPR[ra + 1], EXTRACTED64 (mem, 32, 63));
1107         }
1108
1109 _IMEM,00110,XX,6.RA,6.RB,6.SRC_6:IMEM:short:mu:L2W
1110 "ld2w r<RA>, @(r<RB>, <SRC_6>)":XX == 0
1111 "ld2w r<RA>, @(r<RB>%s<XX>, r<SRC_6>)"
1112         do_ld2w(_SD, RA, Rb, src);
1113         do_incr(_SD, XX, &GPR[RB], 8);
1114 _IMEM,00110,10,6.RA,6.RB,_IMM32:IMEM:long:mu:L2W long
1115 "ld2w r<RA>, @(r<RB>, <imm>)"
1116         do_ld2w(_SD, RA, Rb, imm);
1117
1118
1119
1120 // LD4BH
1121
1122 void::function::do_ld4bh:unsigned32 ra, unsigned32 rb, unsigned32 src
1123         unsigned16 l1, l2, h1, h2;
1124         unsigned32 mem;
1125         ra = make_even_reg(_SD, ra, "LD4BH");
1126         mem = MEM(unsigned, rb + src, 4);
1127         h1 = SEXT16(EXTRACTED32(mem, 0, 7), 8);
1128         l1 = SEXT16(EXTRACTED32(mem, 8, 15), 8);
1129         h2 = SEXT16(EXTRACTED32(mem, 16, 23), 8);
1130         l2 = SEXT16(EXTRACTED32(mem, 24, 31), 8);
1131         if (ra != 0)
1132         {
1133           WRITE32_QUEUE (&GPR[ra + 0], (h1 << 16) | l1);
1134           WRITE32_QUEUE (&GPR[ra + 1], (h2 << 16) | l2);
1135         }
1136
1137 _IMEM,00101,XX,6.RA,6.RB,6.SRC_6:IMEM:short:mu:LD4BH
1138 "ld4bh r<RA>, @(r<RB>, <SRC_6>)":XX == 0
1139 "ld4bh r<RA>, @(r<RB>%s<XX>, r<SRC_6>)"
1140         do_ld4bh(_SD, RA, Rb, src);
1141         do_incr(_SD, XX, &GPR[RB], 4);
1142 _IMEM,00101,10,6.RA,6.RB,_IMM32:IMEM:long:mu:LD4BH long
1143 "ld4bh r<RA>, @(r<RB>, <imm>)"
1144         do_ld4bh(_SD, RA, Rb, imm);
1145
1146
1147
1148 // LD4BHU
1149
1150 void::function::do_ld4bhu:unsigned32 ra, unsigned32 rb, unsigned32 src
1151         unsigned16 l1, l2, h1, h2;
1152         unsigned32 mem;
1153         ra = make_even_reg(_SD, ra, "LD4BH");
1154         mem = MEM(signed, rb + src, 4);
1155         h1 = EXTRACTED32(mem, 0, 7);
1156         l1 = EXTRACTED32(mem, 8, 15);
1157         h2 = EXTRACTED32(mem, 16, 23);
1158         l2 = EXTRACTED32(mem, 24, 31);
1159         if (ra != 0)
1160         {
1161           WRITE32_QUEUE (&GPR[ra + 0], (h1 << 16) | l1);
1162           WRITE32_QUEUE (&GPR[ra + 1], (h2 << 16) | l2);
1163         }
1164
1165 _IMEM,01101,XX,6.RA,6.RB,6.SRC_6:IMEM:short:mu:LD4BHU
1166 "ld4hbu r<RA>, @(r<RB>, <SRC_6>)":XX == 0
1167 "ld4hbu r<RA>, @(r<RB>%s<XX>, r<SRC_6>)"
1168         do_ld4bhu(_SD, RA, Rb, src);
1169         do_incr(_SD, XX, &GPR[RB], 4);
1170 _IMEM,01101,10,6.RA,6.RB,_IMM32:IMEM:long:mu:LD4BHU long
1171 "ld4hbu r<RA>, @(r<RB>, <imm>)"
1172         do_ld4bhu(_SD, RA, Rb, imm);
1173
1174
1175
1176 // LDB
1177
1178 void::function::do_ldb:unsigned32 *ra, unsigned32 rb, unsigned32 src
1179         WRITE32_QUEUE (ra, MEM(signed, rb + src, 1));
1180
1181 _IMEM,00000,XX,6.RA,6.RB,6.SRC_6:IMEM:short:mu:LDB
1182 "ldb r<RA>, @(r<RB>, <SRC_6>)":XX == 0
1183 "ldb r<RA>, @(r<RB>%s<XX>, r<SRC_6>)"
1184         do_ldb(_SD, Ra, Rb, src);
1185         do_incr(_SD, XX, &GPR[RB], 1);
1186 _IMEM,00000,10,6.RA,6.RB,_IMM32:IMEM:long:mu:LDB long
1187 "ldb r<RA>, @(r<RB>, <imm>)"
1188         do_ldb(_SD, Ra, Rb, imm);
1189
1190
1191
1192 // LDBU
1193
1194 void::function::do_ldbu:unsigned32 *ra, unsigned32 rb, unsigned32 src
1195         WRITE32_QUEUE (ra, MEM(unsigned, rb + src, 1));
1196
1197 _IMEM,01001,XX,6.RA,6.RB,6.SRC_6:IMEM:short:mu:LDBU
1198 "ldbu r<RA>, @(r<RB>, <SRC_6>)":XX == 0
1199 "ldbu r<RA>, @(r<RB>%s<XX>, r<SRC_6>)"
1200         do_ldbu(_SD, Ra, Rb, src);
1201         do_incr(_SD, XX, &GPR[RB], 1);
1202 _IMEM,01001,10,6.RA,6.RB,_IMM32:IMEM:long:mu:LDBU long
1203 "ldbu r<RA>, @(r<RB>, <imm>)"
1204         do_ldbu(_SD, Ra, Rb, imm);
1205
1206
1207
1208 // LDH
1209
1210 void::function::do_ldh:unsigned32 *ra, unsigned32 rb, unsigned32 src
1211         WRITE32_QUEUE (ra, MEM(signed, rb + src, 2));
1212
1213 _IMEM,00010,XX,6.RA,6.RB,6.SRC_6:IMEM:short:mu:LDH
1214 "ldh r<RA>, @(r<RB>, <SRC_6>)":XX == 0
1215 "ldh r<RA>, @(r<RB>%s<XX>, r<SRC_6>)"
1216         do_ldh(_SD, Ra, Rb, src);
1217         do_incr(_SD, XX, &GPR[RB], 2);
1218 _IMEM,00010,10,6.RA,6.RB,_IMM32:IMEM:long:mu:LDH long
1219 "ldh r<RA>, @(r<RB>, <imm>)"
1220         do_ldh(_SD, Ra, Rb, imm);
1221
1222
1223
1224 // LDHH
1225
1226 void::function::do_ldhh:unsigned32 *ra, unsigned32 rb, unsigned32 src
1227         WRITE32_QUEUE (ra, MEM(signed, rb + src, 2) << 16);
1228
1229 _IMEM,00001,XX,6.RA,6.RB,6.SRC_6:IMEM:short:mu:LDHH
1230 "ldhh r<RA>, @(r<RB>, <SRC_6>)":XX == 0
1231 "ldhh r<RA>, @(r<RB>%s<XX>, r<SRC_6>)"
1232         do_ldhh(_SD, Ra, Rb, src);
1233         do_incr(_SD, XX, &GPR[RB], 2);
1234 _IMEM,00001,10,6.RA,6.RB,_IMM32:IMEM:long:mu:LDHH long
1235 "ldhh r<RA>, @(r<RB>, <imm>)"
1236         do_ldhh(_SD, Ra, Rb, imm);
1237
1238
1239
1240 // LDHU
1241
1242 void::function::do_ldhu:unsigned32 *ra, unsigned32 rb, unsigned32 src
1243         WRITE32_QUEUE (ra, MEM(unsigned, rb + src, 2));
1244
1245 _IMEM,01010,XX,6.RA,6.RB,6.SRC_6:IMEM:short:mu:LDHU
1246 "ldhu r<RA>, @(r<RB>, <SRC_6>)":XX == 0
1247 "ldhu r<RA>, @(r<RB>%s<XX>, r<SRC_6>)"
1248         do_ldhu(_SD, Ra, Rb, src);
1249         do_incr(_SD, XX, &GPR[RB], 2);
1250 _IMEM,01010,10,6.RA,6.RB,_IMM32:IMEM:long:mu:LDHU long
1251 "ldhu r<RA>, @(r<RB>, <imm>)"
1252         do_ldhu(_SD, Ra, Rb, imm);
1253
1254
1255
1256 // LDW
1257
1258 void::function::do_ldw:unsigned32 *ra, unsigned32 rb, unsigned32 src
1259         WRITE32_QUEUE (ra, MEM(signed, rb + src, 4));
1260
1261 _IMEM,00100,XX,6.RA,6.RB,6.SRC_6:IMEM:short:mu:LDW
1262 "ldw r<RA>, @(r<RB>, <SRC_6>)":XX == 0
1263 "ldw r<RA>, @(r<RB>%s<XX>, r<SRC_6>)"
1264         do_ldw(_SD, Ra, Rb, src);
1265         do_incr(_SD, XX, &GPR[RB], 4);
1266 _IMEM,00100,10,6.RA,6.RB,_IMM32:IMEM:long:mu:LDW long
1267 "ldw r<RA>, @(r<RB>, <imm>)"
1268         do_ldw(_SD, Ra, Rb, imm);
1269
1270
1271
1272 // MACa
1273
1274 void::function::do_mac:unsigned64 *aa, unsigned32 *ra, signed32 rb, signed32 src
1275         unsigned64 accum = *aa;
1276         accum += (signed64) (rb) * (signed64) (src);
1277         WRITE64_QUEUE (aa, accum);
1278         WRITE32_QUEUE (ra, EXTRACTED64(accum, 32, 63));
1279
1280 _IALU2,10100,0,1.AA,6.RA,6.RB,6.RC:IALU2:short:iu:MACa
1281 "mac<AA> r<RA>, r<RB>, r<RC>"
1282         do_mac(_SD, Aa, Ra, Rb, Rc);
1283 _IALU2,10100,1,1.AA,6.RA,6.RB,_IMM6:IALU2:short:iu:MACa imm
1284 "mac<AA> r<RA>, r<RB>, <imm>"
1285         do_mac(_SD, Aa, Ra, Rb, imm);
1286
1287
1288
1289 // MACSa
1290
1291 void::function::do_macs:unsigned64 *aa, unsigned32 *ra, signed32 rb, signed32 src
1292         unsigned64 accum = *aa;
1293         accum += ((signed64) (rb) * (signed64) (src)) << 1;
1294         WRITE64_QUEUE (aa, accum);
1295         WRITE32_QUEUE (ra, EXTRACTED64(accum, 0, 31));
1296
1297 _IALU2,10101,0,1.AA,6.RA,6.RB,6.RC:IALU2:short:iu:MACSa
1298 "macs<AA> r<RA>, r<RB>, r<RC>"
1299         do_macs(_SD, Aa, Ra, Rb, Rc);
1300 _IALU2,10101,1,1.AA,6.RA,6.RB,_IMM6:IALU2:short:iu:MACSa imm
1301 "macs<AA> r<RA>, r<RB>, <imm>"
1302         do_macs(_SD, Aa, Ra, Rb, imm);
1303
1304
1305
1306 // MODDEC | MODINC
1307
1308 _IMEM,00111,11,6.**,6.RB,_IMM6:IMEM:short:mu:MODDEC
1309 "moddec r<RB>, <imm>"
1310         do_incr(_SD, 3/*0b11*/, &GPR[RB], imm_5);
1311 _IMEM,00111,01,6.**,6.RB,_IMM6:IMEM:short:mu:MODINC
1312 "modinc r<RB>, <imm>"
1313         do_incr(_SD, 1/*0b01*/, &GPR[RB], imm_5);
1314
1315
1316
1317 // MSUBa
1318
1319 void::function::do_msub:unsigned64 *aa, unsigned32 *ra, signed32 rb, signed32 src
1320         unsigned64 accum = *aa;
1321         accum -= (signed64) (rb) * (signed64) (src);
1322         WRITE64_QUEUE (aa, accum);
1323         WRITE32_QUEUE (ra, EXTRACTED64(accum, 32, 63));
1324
1325 _IALU2,10110,0,1.AA,6.RA,6.RB,6.RC:IALU2:short:iu:MSUBa
1326 "msub<AA> r<RA>, r<RB>, r<RC>"
1327         do_msub(_SD, Aa, Ra, Rb, Rc);
1328 _IALU2,10110,1,1.AA,6.RA,6.RB,_IMM6:IALU2:short:iu:MSUBa imm
1329 "msub<AA> r<RA>, r<RB>, <imm>"
1330         do_msub(_SD, Aa, Ra, Rb, imm);
1331
1332
1333
1334 // MSUBSa
1335
1336 void::function::do_msubs:unsigned64 *aa, unsigned32 *ra, signed32 rb, signed32 src
1337         unsigned64 accum = *aa;
1338         accum -= ((signed64) (rb) * (signed64) (src)) << 1;
1339         WRITE64_QUEUE (aa, accum);
1340         WRITE32_QUEUE (ra, EXTRACTED64(accum, 0, 31));
1341
1342 _IALU2,10111,0,1.AA,6.RA,6.RB,6.RC:IALU2:short:iu:MSUBSa
1343 "msubs<AA> r<RA>, r<RB>, r<RC>"
1344         do_msubs(_SD, Aa, Ra, Rb, Rc);
1345 _IALU2,10111,1,1.AA,6.RA,6.RB,_IMM6:IALU2:short:iu:MSUBSa imm
1346 "msubs<AA> r<RA>, r<RB>, <imm>"
1347         do_msubs(_SD, Aa, Ra, Rb, imm);
1348
1349
1350
1351 // MUL
1352
1353 void::function::do_mul:unsigned32 *ra, unsigned32 rb, unsigned32 src
1354         WRITE32_QUEUE (ra, rb * src);
1355
1356 _IALU2,10000,00,6.RA,6.RB,6.RC:IALU2:short:iu:MUL
1357 "mul r<RA>, r<RB>, r<RC>"
1358         do_mul(_SD, Ra, Rb, Rc);
1359 _IALU2,10000,10,6.RA,6.RB,_IMM6:IALU2:short:iu:MUL imm
1360 "mul r<RA>, r<RB>, <imm>"
1361         do_mul(_SD, Ra, Rb, imm);
1362
1363
1364
1365 // MUL2H
1366
1367 void::function::do_mul2h:unsigned32 *ra, unsigned32 rb, unsigned32 src
1368         unsigned16 high = VH2_4(rb) * VH2_4(src);
1369         unsigned16 low  = VL2_4(rb) * VL2_4(src);
1370         WRITE32_QUEUE (ra, (high << 16) | low);
1371
1372 _IALU2,00000,00,6.RA,6.RB,6.RC:IALU2:short:iu:MUL2H
1373 "mul2h r<RA>, r<RB>, r<RC>"
1374         do_mul2h(_SD, Ra, Rb, Rc);
1375 _IALU2,00000,10,6.RA,6.RB,_IMM6:IALU2:short:iu:MUL2H imm
1376 "mul2h r<RA>, r<RB>, <imm>"
1377         do_mul2h(_SD, Ra, Rb, immHL);
1378
1379
1380
1381 // MULX
1382
1383 void::function::do_mulx:unsigned64 *aa, signed32 rb, signed32 src
1384         WRITE64_QUEUE (aa, (signed64) (rb) * (signed64) (src));
1385
1386 _IALU2,11000,00,5.*,1.AA,6.RB,6.RC:IALU2:short:iu:MULX
1387 "mulx a<AA>, r<RB>, r<RC>"
1388         do_mulx(_SD, Aa, Rb, Rc);
1389 _IALU2,11000,10,5.*,1.AA,6.RB,_IMM6:IALU2:short:iu:MULX imm
1390 "mulx a<AA>, r<RB>, <imm>"
1391         do_mulx(_SD, Aa, Rb, imm);
1392
1393
1394 // MULX2H
1395
1396 void::function::do_mulx2h:int ra, signed32 rb, signed32 src, int high
1397         signed32 result = rb * src;
1398         if (!high)
1399           {
1400             ra = make_even_reg(_SD, ra, "MULX2H");
1401             if (ra != 0)
1402               WRITE32_QUEUE (&GPR[ra+1], result);
1403           }
1404         else if (ra != 0)
1405           {
1406               WRITE32_QUEUE (&GPR[ra+0], result);
1407           }
1408
1409 _IALU2,00001,00,6.RA,6.RB,6.RC:IALU2:short:iu:MULX2H
1410 "mul2h r<RA>, r<RB>, r<RC>"
1411         do_mulx2h(_SD, RA, RbH, RcH, 1);
1412         do_mulx2h(_SD, RA, RbL, RcL, 0);
1413 _IALU2,00001,10,6.RA,6.RB,_IMM6:IALU2:short:iu:MULX2H imm
1414 "mul2h r<RA>, r<RB>, <imm>"
1415         do_mulx2h(_SD, RA, RbH, imm, 1);
1416         do_mulx2h(_SD, RA, RbL, imm, 0);
1417
1418 // MULHXpp
1419
1420 void::function::do_mulhx:int pp, unsigned32 *ra, unsigned32 rb, unsigned32 src
1421         signed32 value = 0;
1422         switch (pp) {
1423         case 0: /* LL */
1424           value = SEXT32(VL2_4(rb), 16) * SEXT32(VL2_4(src), 16);
1425           break;
1426         case 1: /* LH */
1427           value = SEXT32(VL2_4(rb), 16) * SEXT32(VH2_4(src), 16);
1428           break;
1429         case 2: /* HL */
1430           value = SEXT32(VH2_4(rb), 16) * SEXT32(VL2_4(src), 16);
1431           break;
1432         case 3: /* HH */
1433           value = SEXT32(VH2_4(rb), 16) * SEXT32(VH2_4(src), 16);
1434           break;
1435         default:
1436           sim_engine_abort (SD, CPU, cia, "do_mulhx - internal error - bad switch");
1437         }
1438         WRITE32_QUEUE (ra, value);
1439
1440 _IALU2,001,pp,00,6.RA,6.RB,6.RC:IALU2:short:iu:MULHXpp
1441 "mulhx%s<pp> r<RA>, r<RB>, r<RC>"
1442         do_mulhx(_SD, pp, Ra, Rb, Rc);
1443 _IALU2,001,pp,10,6.RA,6.RB,_IMM6:IALU2:short:iu:MULHXpp imm
1444 "mulhx%s<pp> r<RA>, r<RB>, <imm>"
1445         do_mulhx(_SD, pp, Ra, Rb, immHL);
1446
1447
1448
1449 // MULXS
1450
1451 void::function::do_mulxs:unsigned64 *aa, signed32 rb, signed32 src
1452         WRITE64_QUEUE (aa, ((signed64) (rb) * (signed64) (src)) << 1);
1453
1454 _IALU2,11001,00,5.*,1.AA,6.RB,6.RC:IALU2:short:iu:MULXS
1455 "mulxs a<AA>, r<RB>, r<RC>"
1456         do_mulxs(_SD, Aa, Rb, Rc);
1457 _IALU2,11001,10,5.*,1.AA,6.RB,_IMM6:IALU2:short:iu:MULXS imm
1458 "mulxs a<AA>, r<RB>, <imm>"
1459         do_mulxs(_SD, Aa, Rb, imm);
1460
1461
1462
1463 // MVFACC
1464
1465 void::function::do_mvfacc:unsigned32 *ra, unsigned64 ab, unsigned32 src
1466         while (src > 63) src -= 64;
1467         WRITE32_QUEUE (ra, ((signed64)ab) >> src);
1468
1469 _IALU2,11111,00,6.RA,5.*,1.AB,6.RC:IALU2:short:iu:MVFACC
1470 "mvfacc r<RA>, a<AB>, r<RC>"
1471         do_mvfacc(_SD, Ra, *Ab, Rc);
1472 _IALU2,11111,10,6.RA,5.*,1.AB,_IMM6:IALU2:short:iu:MVFACC imm
1473 "mvfacc r<RA>, a<AB>, <imm>"
1474         do_mvfacc(_SD, Ra, *Ab, imm_6u);
1475
1476
1477
1478 // MVFSYS
1479
1480 _BRA,11110,00,6.RA,6.CR,6.ID:BRA:short:mu:MVFSYS
1481 "mvfsys r<RA>, cr<CR>"
1482         switch (ID) {
1483         case 0:
1484           if (CR >= NR_CONTROL_REGISTERS)
1485             sim_engine_abort (SD, CPU, cia, "FIXME - illegal CR");
1486           else
1487             WRITE32_QUEUE (Ra, (CPU)->regs.control[CR]);
1488           break;
1489         case 1:
1490           WRITE32_QUEUE (Ra, PSWL);
1491           break;
1492         case 2:
1493           WRITE32_QUEUE (Ra, EXTRACTED32(PSWH, 16, 31));
1494           break;
1495         case 3:
1496           WRITE32_QUEUE (Ra, PSW_FLAG_VAL(CR));
1497           break;
1498         default:
1499           sim_engine_abort (SD, CPU, cia, "FIXME - illegal ID");
1500         }
1501
1502
1503
1504 // MVTACC
1505
1506 _IALU2,01111,00,5.*,1.AA,6.RB,6.RC:IALU2:short:iu:MVTACC
1507 "mvtacc a<AA>, r<RB>, r<RC>"
1508         WRITE64_QUEUE (Aa, INSERTED64(RbU, 0, 31) | (RcU));
1509
1510
1511
1512 // MVTSYS
1513
1514 _BRA,01110,00,6.CR,6.RB,6.ID:BRA:short:mu:MVTSYS
1515 "mvtsys cr<CR>, r<RB>"
1516         switch (ID) {
1517         case 0:                 /* control register */
1518           if (CR >= NR_CONTROL_REGISTERS)
1519             sim_engine_abort (SD, CPU, cia, "FIXME - illegal CR");
1520           else
1521             {
1522               unsigned32 value = Rb;
1523               if (CR == processor_status_word_cr)
1524                 {
1525                   unsigned32 ds = PSW & BIT32 (PSW_DS); /* preserve ds */
1526                   value = ds | (value & PSW_VALID);
1527                   CPU->left_kills_right_p = 1;
1528                 }
1529               else if (CR == backup_processor_status_word_cr
1530                        || CR == debug_backup_processor_status_word_cr)
1531                 value &= DPSW_VALID;
1532               else if (CR == eit_vector_base_cr)
1533                 value &= EIT_VALID;
1534               WRITE32_QUEUE (&(CPU)->regs.control[CR], value);
1535             }
1536           break;
1537         case 1:                 /* PSWL */
1538           WRITE32_QUEUE_MASK (&PSW, EXTRACTED32(Rb, 16, 31),
1539                               PSW_VALID & 0x0000ffff);
1540           CPU->left_kills_right_p = 1;
1541           break;
1542         case 2:                 /* PSWH */
1543           {
1544             unsigned32 ds = PSW & BIT32 (PSW_DS);       /* preserve ds */
1545             WRITE32_QUEUE_MASK (&PSW, (EXTRACTED32(Rb, 16, 31) << 16) | ds,
1546                                 (PSW_VALID | ds) & 0xffff0000);
1547             CPU->left_kills_right_p = 1;
1548           }
1549           break;
1550         case 3:                 /* FLAG */
1551           PSW_FLAG_SET_QUEUE(CR, Rb & 1);
1552           CPU->left_kills_right_p = 1;
1553           break;
1554         default:
1555           sim_engine_abort (SD, CPU, cia, "FIXME - illegal ID");
1556         }
1557
1558
1559
1560 // NOP
1561
1562 _BRA,01111,00,6.**,6.**,6.**:BRA:short:iu,mu:NOP
1563 "nop"
1564         /* NOP */;
1565
1566
1567 // NOT
1568
1569 _LOGIC,11001,00,6.RA,6.RB,6.*:LOGIC:short:iu,mu:NOT
1570 "not r<RA>, r<RB>"
1571         WRITE32_QUEUE (Ra, ~Rb);
1572
1573
1574
1575 // NOTFG
1576
1577 _LOGIC,01001,00,***,3.FA,***,3.FB,***,3.FC:LOGIC:short:iu,mu:NOTFG
1578 "notfg f<FA>, f<FB>"
1579         PSW_FLAG_SET_QUEUE(FA, !PSW_FLAG_VAL(FB));
1580
1581
1582 // OR
1583
1584 _LOGIC,11010,00,6.RA,6.RB,6.RC:LOGIC:short:iu,mu:OR
1585 "or r<RA>, r<RB>, r<RC>"
1586         WRITE32_QUEUE (Ra, Rb | Rc);
1587 _LOGIC,11010,10,6.RA,6.RB,_IMM6:LOGIC:short:iu,mu:OR imm
1588 "or r<RA>, r<RB>, <imm>"
1589         WRITE32_QUEUE (Ra, Rb | imm);
1590 _LOGIC,11010,10,6.RA,6.RB,_IMM32:LOGIC:long:iu,mu:OR imm long
1591 "or r<RA>, r<RB>, <imm>"
1592         WRITE32_QUEUE (Ra, Rb | imm);
1593
1594
1595
1596 // ORFG
1597
1598 _LOGIC,01010,00,***,3.FA,***,3.FB,***,3.FC:LOGIC:short:iu,mu:ORFG
1599 "orfg f<FA>, f<FB>, f<FC>"
1600         PSW_FLAG_SET_QUEUE(FA, PSW_FLAG_VAL(FB) | PSW_FLAG_VAL(FC));
1601 _LOGIC,01010,10,***,3.FA,***,3.FB,_IMM6:LOGIC:short:iu,mu:ORFG imm
1602 "orfg f<FA>, f<FB>, <imm>"
1603         PSW_FLAG_SET_QUEUE(FA, PSW_FLAG_VAL(FB) | (imm_6 & 1));
1604
1605
1606
1607 // REIT
1608
1609 _BRA,01000,00,6.**,6.**,6.**:BRA:short:mu:REIT
1610 "reit"
1611         WRITE32_QUEUE (&PSW, bPSW);
1612         nia = bPC;
1613
1614
1615
1616
1617 // REPEAT
1618
1619 void::function::do_repeat:unsigned32 count, address_word pcaddr
1620         if (count == 0)
1621           sim_engine_abort (SD, CPU, cia, "REPEAT with ra=0 and REPEATI with imm = 0 is forbidden.");
1622         if (count > 1)
1623           PSW_SET_QUEUE (PSW_RP, 1);
1624         WRITE32_QUEUE (&RPT_C, count - 1);
1625         WRITE32_QUEUE (&RPT_S, cia + 8);
1626         WRITE32_QUEUE (&RPT_E, cia + pcaddr);
1627
1628 _BRA,11000,00,6.RA,6.**,6.RC:BRA:short:mu:REPEAT
1629 "repeat r<RA>, r<RC>"
1630         do_repeat(_SD, val_Ra, pcaddr);
1631 _BRA,11000,10,6.RA,_IMM12:BRA:short:mu:REPEAT imm
1632 "repeat r<RA>, <pcaddr>"
1633         do_repeat(_SD, val_Ra, pcaddr);
1634 _BRA,11000,10,6.RA,6.**,_IMM32:BRA:long:mu:REPEAT imm long
1635 "repeat r<RA>, <pcaddr>"
1636         do_repeat(_SD, val_Ra, pcaddr);
1637
1638
1639
1640
1641 // REPEATI
1642
1643 _BRA,11010,00,6.IMM_6,6.**,6.RC:BRA:short:mu:REPEATI
1644 "repeati <IMM_6>, r<RC>"
1645         do_repeat(_SD, IMM_6, pcaddr);
1646 _BRA,11010,10,6.IMM_6,_IMM12:BRA:short:mu:REPEATI imm
1647 "repeati <IMM_6>, <pcaddr>"
1648         do_repeat(_SD, IMM_6, pcaddr);
1649 _BRA,11010,10,6.IMM_6,6.**,_IMM32:BRA:long:mu:REPEATI imm long
1650 "repeati <IMM_6>, <pcaddr>"
1651         do_repeat(_SD, IMM_6, pcaddr);
1652
1653
1654
1655
1656 // RTD
1657
1658 _BRA,01010,00,6.*,6.*,6.*:BRA:short:mu:RTD
1659 "rtd"
1660         WRITE32_QUEUE (&PSW, DPSW);
1661         nia = DPC;
1662
1663
1664
1665
1666 // ROT
1667
1668 _LOGIC,10100,00,6.RA,6.RB,6.RC:LOGIC:short:iu,mu:ROT
1669 "rot r<RA>, r<RB>, r<RC>"
1670         WRITE32_QUEUE (Ra, ROT32(Rb, Rc & 0x1f));
1671 _LOGIC,10100,10,6.RA,6.RB,_IMM6:LOGIC:short:iu,mu:ROT imm
1672 "rot r<RA>, r<RB>, <imm>"
1673         WRITE32_QUEUE (Ra, ROT32(Rb, imm & 0x1f));
1674
1675
1676
1677
1678 // ROT2H
1679
1680 void::function::do_rot2h:unsigned32 *ra, unsigned32 rb, signed32 src
1681         unsigned16 high = ROTR16(VH2_4(rb), VH2_4(src) & 0xf);
1682         unsigned16 low  = ROTR16(VL2_4(rb), VL2_4(src) & 0xf);
1683         WRITE32_QUEUE (ra, (high << 16) | low);
1684
1685 _LOGIC,10101,00,6.RA,6.RB,6.RC:LOGIC:short:iu,mu:ROT2H
1686 "rot2h r<RA>, r<RB>, r<RC>"
1687         do_rot2h(_SD, Ra, Rb, Rc);
1688 _LOGIC,10101,10,6.RA,6.RB,_IMM6:LOGIC:short:iu,mu:ROT2H imm
1689 "rot2h r<RA>, r<RB>, <imm>"
1690         do_rot2h(_SD, Ra, Rb, immHL);
1691
1692
1693
1694
1695 // SAT
1696
1697 void::function::do_sat:signed32 *ra, signed32 rb, signed32 src
1698         int bits = LSMASKED32(src, 4, 0); /* 5 */
1699         signed32 sat = LSMASK32(bits, 0) >> 2;
1700         signed32 nsat = ~sat;
1701         signed32 value;
1702         if (bits != src)
1703           sim_io_eprintf (sd, "warning: 0x%lx:SAT bit overflow\n", cia);
1704         if (bits == 0)
1705           value = rb;
1706         else if (rb >= sat)
1707           value = sat;
1708         else if (rb <= nsat)
1709           value = nsat;
1710         else
1711           value = rb;
1712         WRITE32_QUEUE (ra, value);
1713
1714 _IALU2,01000,00,6.RA,6.RB,6.RC:IALU2:short:iu:SAT
1715 "sat r<RA>, r<RB>, r<RC>"
1716         do_sat(_SD, Ra, Rb, Rc);
1717 _IALU2,01000,10,6.RA,6.RB,_IMM6:IALU2:short:iu:SAT imm
1718 "sat r<RA>, r<RB>, <imm>"
1719         do_sat(_SD, Ra, Rb, imm_5);
1720
1721
1722
1723
1724 // SAT2H
1725
1726 void::function::do_sath:signed32 *ra, signed32 rb, signed32 src, int high, int updates_f4
1727         int bits = LSMASKED32(src, 4, 0); /* 5 */
1728         signed32 sat = LSMASK32(bits, 0) >> 2;
1729         signed32 nsat = ~sat;
1730         signed32 value;
1731         if (bits != src)
1732           sim_io_eprintf (sd, "warning: 0x%lx:SAT bit overflow\n", cia);
1733         if (bits == 0)
1734           value = rb;
1735         else if (rb >= sat)
1736           value = sat;
1737         else if (rb <= nsat)
1738           value = nsat;
1739         else
1740           value = rb;
1741         if (high)
1742           WRITE32_QUEUE_MASK (ra, value << 16, 0xffff0000);
1743         else
1744           WRITE32_QUEUE_MASK (ra, value, 0x0000ffff);
1745         if (updates_f4)
1746           {
1747             /* if MU instruction was a MVTSYS (lkr), unqueue register writes now */
1748             if(STATE_CPU (sd, 0)->left_kills_right_p)
1749               unqueue_writes (sd, STATE_CPU (sd, 0), cia);
1750             PSW_FLAG_SET_QUEUE(PSW_S_FLAG, PSW_FLAG_VAL(PSW_S_FLAG) ^ (value & 1));
1751           }
1752
1753 _IALU2,01001,00,6.RA,6.RB,6.RC:IALU2:short:iu:SAT2H
1754 "sat2h r<RA>, r<RB>, r<RC>"
1755         do_sath(_SD, Ra, RbH, RcH, 1, 0);
1756         do_sath(_SD, Ra, RbL, RcL, 0, 0);
1757 _IALU2,01001,10,6.RA,6.RB,_IMM6:IALU2:short:iu:SAT2H imm
1758 "sat2h r<RA>, r<RB>, <imm>"
1759         do_sath(_SD, Ra, RbH, imm_5, 1, 0);
1760         do_sath(_SD, Ra, RbL, imm_5, 0, 0);
1761
1762
1763
1764
1765 // SATHp
1766
1767 ::%s::p:int p
1768         switch (p)
1769           {
1770           case 0: return "l";
1771           case 1: return "h";
1772           default: return "?";
1773           }
1774
1775 _IALU2,1110,p,00,6.RA,6.RB,6.RC:IALU2:short:iu:SATHP
1776 "sath%s<p> r<RA>, r<RB>, r<RC>"
1777         do_sath(_SD, Ra, Rb, Rc, p, 1);
1778 _IALU2,1110,p,10,6.RA,6.RB,_IMM6:IALU2:short:iu:SATHP imm
1779 "sath%s<p> r<RA>, r<RB>, <imm>"
1780         do_sath(_SD, Ra, Rb, imm_5, p, 1);
1781
1782
1783
1784 // SATZ
1785
1786 void::function::do_satz:signed32 *ra, signed32 rb, signed32 src
1787         if (rb < 0)
1788           WRITE32_QUEUE (ra, 0);
1789         else
1790           do_sat (_SD, ra, rb, src);
1791
1792 _IALU2,01010,00,6.RA,6.RB,6.RC:IALU2:short:iu:SATZ
1793 "satz r<RA>, r<RB>, r<RC>"
1794         do_satz(_SD, Ra, Rb, Rc);
1795 _IALU2,01010,10,6.RA,6.RB,_IMM6:IALU2:short:iu:SATZ imm
1796 "satz r<RA>, r<RB>, <imm>"
1797         do_satz(_SD, Ra, Rb, imm_5);
1798
1799
1800
1801
1802 // SATZ2H
1803
1804 void::function::do_satzh:signed32 *ra, signed16 rb, signed32 src, int high
1805         int bits = LSMASKED32(src, 3, 0); /*4*/
1806         signed16 sat = LSMASK16(bits, 0) >> 2;
1807         signed16 nsat = 0;
1808         signed16 value;
1809         if (bits != src)
1810           sim_io_eprintf (sd, "warning: 0x%lx:SATZ2H bit overflow\n", cia);
1811         if (bits == 0 && rb > sat)
1812           value = rb;
1813         else if (rb > sat)
1814           value = sat;
1815         else if (rb < nsat)
1816           value = nsat;
1817         else
1818           value = rb;
1819         if (high)
1820           WRITE32_QUEUE_MASK (ra, value << 16, 0xffff0000);
1821         else
1822           WRITE32_QUEUE_MASK (ra, value, 0x0000ffff);
1823
1824
1825 _IALU2,01011,00,6.RA,6.RB,6.RC:IALU2:short:iu:SATZ2H
1826 "satz2h r<RA>, r<RB>, r<RC>"
1827         do_satzh(_SD, Ra, RbH, RcH, 1);
1828         do_satzh(_SD, Ra, RbL, RcL, 0);
1829 _IALU2,01011,10,6.RA,6.RB,_IMM6:IALU2:short:iu:SATZ2H imm
1830 "satz2h r<RA>, r<RB>, <imm>"
1831         do_satzh(_SD, Ra, RbH, imm, 1);
1832         do_satzh(_SD, Ra, RbL, imm, 0);
1833
1834
1835
1836
1837 // SRA
1838
1839 void::function::do_sra:unsigned32 *ra, unsigned32 rb, signed32 src
1840         unsigned32 value;
1841         while (src > 31) src -= 32;
1842         while (src < -32) src += 32;
1843         if (src >= 0)
1844           value = (signed32)rb >> src;
1845         else if (src == -32)
1846           value = 0;
1847         else
1848           value = rb << -src;
1849         WRITE32_QUEUE (ra, value);
1850
1851 _LOGIC,10000,00,6.RA,6.RB,6.RC:LOGIC:short:iu,mu:SRA
1852 "sra r<RA>, r<RB>, r<RC>"
1853         do_sra(_SD, Ra, Rb, Rc);
1854 _LOGIC,10000,10,6.RA,6.RB,_IMM6:LOGIC:short:iu,mu:SRA imm
1855 "sra r<RA>, r<RB>, <imm>"
1856         do_sra(_SD, Ra, Rb, imm);
1857
1858
1859
1860
1861 // SRAHp
1862
1863 void::function::do_srah:unsigned32 *ra, unsigned32 rb, int src, int high
1864         unsigned32 value;
1865         while (src > 31) src -= 32;
1866         while (src < -32) src += 32;
1867         if (src >= 0)
1868           value = (signed32)rb >> src;
1869         else if (src == -32)
1870           value = 0;
1871         else
1872           value = rb << -src;
1873         if (high)
1874           WRITE32_QUEUE_MASK (ra, value << 16, 0xffff0000);
1875         else
1876           WRITE32_QUEUE_MASK (ra, value, 0x0000ffff);
1877
1878 _LOGIC,0010,p,00,6.RA,6.RB,6.RC:LOGIC:short:iu,mu:SRAHP
1879 "srah%s<p> r<RA>, r<RB>, r<RC>"
1880         do_srah(_SD, Ra, Rb, Rc, p);
1881 _LOGIC,0010,p,10,6.RA,6.RB,_IMM6:LOGIC:short:iu,mu:SRAHP imm
1882 "srah%s<p> r<RA>, r<RB>, <imm>"
1883         do_srah(_SD, Ra, Rb, imm, p);
1884
1885
1886
1887
1888 // SRA2H
1889
1890 _LOGIC,10001,00,6.RA,6.RB,6.RC:LOGIC:short:iu,mu:SRA2H
1891 "sra2h r<RA>, r<RB>, r<RC>"
1892         signed32 srcH = RcH;
1893         signed32 srcL = RcL;
1894         while (srcH > 15) srcH -= 16;
1895         while (srcH < -16) srcH += 16;
1896         while (srcL > 15) srcL -= 16;
1897         while (srcL < -16) srcL += 16;
1898         do_srah(_SD, Ra, RbH, srcH, 1);
1899         do_srah(_SD, Ra, RbL, srcL, 0);
1900 _LOGIC,10001,10,6.RA,6.RB,_IMM6:LOGIC:short:iu,mu:SRA2H imm
1901 "sra2h r<RA>, r<RB>, <imm>"
1902         signed32 src = imm;
1903         while (src > 15) src -= 16;
1904         while (src < -16) src += 16;
1905         do_srah(_SD, Ra, RbH, src, 1);
1906         do_srah(_SD, Ra, RbL, src, 0);
1907
1908
1909
1910
1911 // SRC
1912
1913 void::function::do_src:unsigned32 *ra, unsigned32 rb, int src
1914         unsigned32 value;
1915         unsigned64 operand;
1916         unsigned64 shifted;
1917         while (src > 31) src -= 32;
1918         while (src < -32) src += 32;
1919         if (src >= 0)
1920           {
1921             operand = (INSERTED64(rb, 0, 31) | INSERTED64(*ra, 32, 63));
1922             shifted = operand >> src;
1923             value = EXTRACTED64(shifted, 32, 63);
1924           }
1925         else
1926           {
1927             operand = (INSERTED64(*ra, 0, 31) | INSERTED64(rb, 32, 63));
1928             shifted = operand << -src;
1929             value = EXTRACTED64(shifted, 0, 31);
1930           }
1931         WRITE32_QUEUE (ra, value);
1932
1933 _LOGIC,10110,00,6.RA,6.RB,6.RC:LOGIC:short:iu,mu:SRC
1934 "src r<RA>, r<RB>, r<RC>"
1935         do_src(_SD, Ra, Rb, Rc);
1936 _LOGIC,10110,10,6.RA,6.RB,_IMM6:LOGIC:short:iu,mu:SRC imm
1937 "src r<RA>, r<RB>, <imm>"
1938         do_src(_SD, Ra, Rb, imm);
1939
1940
1941
1942
1943 // SRL
1944
1945 void::function::do_srl:unsigned32 *ra, unsigned32 rb, int src
1946         unsigned32 value;
1947         while (src > 31) src -= 32;
1948         while (src < -32) src += 32;
1949         if (src >= 0)
1950           value = (unsigned32)rb >> src;
1951         else if (src == -32)
1952           value = 0;
1953         else
1954           value = (unsigned32)rb << -src;
1955         WRITE32_QUEUE (ra, value);
1956
1957 _LOGIC,10010,00,6.RA,6.RB,6.RC:LOGIC:short:iu,mu:SRL
1958 "srl r<RA>, r<RB>, r<RC>"
1959         do_srl(_SD, Ra, Rb, Rc);
1960 _LOGIC,10010,10,6.RA,6.RB,_IMM6:LOGIC:short:iu,mu:SRL imm
1961 "srl r<RA>, r<RB>, <imm>"
1962         do_srl(_SD, Ra, Rb, imm);
1963
1964
1965
1966
1967 // SRLHp
1968
1969 void::function::do_srlh:unsigned32 *ra, unsigned32 rb, int src, int high
1970         unsigned32 value;
1971         while (src > 31) src -= 32;
1972         while (src < -32) src += 32;
1973         if (src >= 0)
1974           value = rb >> src;
1975         else if (src == -32)
1976           value = 0;
1977         else
1978           value = rb << -src;
1979         if (high)
1980           WRITE32_QUEUE_MASK (ra, value << 16, 0xffff0000);
1981         else
1982           WRITE32_QUEUE_MASK (ra, value, 0x0000ffff);
1983
1984 _LOGIC,0011,p,00,6.RA,6.RB,6.RC:LOGIC:short:iu,mu:SRLHP
1985 "srlh%s<p> r<RA>, r<RB>, r<RC>"
1986         do_srlh(_SD, Ra, Rb, Rc, p);
1987 _LOGIC,0011,p,10,6.RA,6.RB,_IMM6:LOGIC:short:iu,mu:SRLHP imm
1988 "srlh%s<p> r<RA>, r<RB>, <imm>"
1989         do_srlh(_SD, Ra, Rb, imm, p);
1990
1991
1992 // SRL2H
1993
1994 _LOGIC,10011,00,6.RA,6.RB,6.RC:LOGIC:short:iu,mu:SRL2H
1995 "srl2h r<RA>, r<RB>, r<RC>"
1996         signed32 srcH = RcH;
1997         signed32 srcL = RcL;
1998         while (srcH > 15) srcH -= 16;
1999         while (srcH < -16) srcH += 16;
2000         while (srcL > 15) srcL -= 16;
2001         while (srcL < -16) srcL += 16;
2002         do_srlh(_SD, Ra, RbHU, srcH, 1);
2003         do_srlh(_SD, Ra, RbLU, srcL, 0);
2004 _LOGIC,10011,10,6.RA,6.RB,_IMM6:LOGIC:short:iu,mu:SRL2H imm
2005 "srl2h r<RA>, r<RB>, <imm>"
2006         signed32 src = imm;
2007         while (src > 15) src -= 16;
2008         while (src < -16) src += 16;
2009         do_srlh(_SD, Ra, RbHU, src, 1);
2010         do_srlh(_SD, Ra, RbLU, src, 0);
2011
2012
2013
2014
2015 // ST2H
2016
2017 void::function::get_even_reg:int *reg, unsigned32 *r0, const char *name
2018         if (*reg & 1)
2019           sim_engine_abort (SD, CPU, cia,
2020                             "0x%lx:%s odd register (r%d) used in multi-word store",
2021                             (long) cia, name, *reg);
2022         if (*reg == 0)
2023           *r0 = 0;
2024         else
2025           *r0 = GPR[*reg];
2026
2027 void::function::do_st2h:int ra, unsigned32 rb, unsigned32 src
2028         unsigned32 val_ra;
2029         unsigned32 mem;
2030         get_even_reg(_SD, &ra, &val_ra, "ST2H");
2031         mem = INSERTED32(val_ra, 0, 15) |
2032               INSERTED32(GPR[ra + 1], 16, 31);
2033         STORE(rb + src, 4, mem);
2034
2035 _IMEM,10011,XX,6.RA,6.RB,6.SRC_6:IMEM:short:mu:ST2H
2036 "st2h r<RA>, @(r<RB>, <SRC_6>)":XX == 0
2037 "st2h r<RA>, @(r<RB>%s<XX>, r<SRC_6>)"
2038         do_st2h(_SD, RA, Rb, src);
2039         do_incr(_SD, XX, &GPR[RB], 4);
2040 _IMEM,10011,10,6.RA,6.RB,_IMM32:IMEM:long:mu:ST2H long
2041 "st2h r<RA>, @(r<RB>, <imm>)"
2042         do_st2h(_SD, RA, Rb, imm);
2043
2044
2045
2046 // ST2W
2047
2048 void::function::do_st2w:int ra, unsigned32 rb, unsigned32 src
2049         unsigned32 val_ra;
2050         unsigned64 mem;
2051         get_even_reg(_SD, &ra, &val_ra, "ST2W");
2052         mem = INSERTED64(val_ra, 0, 31) | INSERTED64(GPR[ra + 1], 32, 63);
2053         STORE(rb + src, 8, mem);
2054
2055 _IMEM,10110,XX,6.RA,6.RB,6.SRC_6:IMEM:short:mu:ST2W
2056 "st2w r<RA>, @(r<RB>, <SRC_6>)":XX == 0
2057 "st2w r<RA>, @(r<RB>%s<XX>, r<SRC_6>)"
2058         do_st2w(_SD, RA, Rb, src);
2059         do_incr(_SD, XX, &GPR[RB], 8);
2060 _IMEM,10110,10,6.RA,6.RB,_IMM32:IMEM:long:mu:ST2W long
2061 "st2w r<RA>, @(r<RB>, <imm>)"
2062         do_st2w(_SD, RA, Rb, imm);
2063
2064
2065
2066 // ST4HB
2067
2068 void::function::do_st4hb:int ra, unsigned32 rb, unsigned32 src
2069         unsigned32 val_ra;
2070         unsigned32 mem;
2071         get_even_reg(_SD, &ra, &val_ra, "ST4HB");
2072         mem = INSERTED32(EXTRACTED32(val_ra, 8, 15), 0, 7) |
2073               INSERTED32(EXTRACTED32(val_ra, 24, 31), 8, 15) |
2074               INSERTED32(EXTRACTED32(GPR[ra + 1], 8, 15), 16, 23) |
2075               INSERTED32(EXTRACTED32(GPR[ra + 1], 24, 31), 24, 31);
2076         STORE(rb + src, 4, mem);
2077
2078 _IMEM,10101,XX,6.RA,6.RB,6.SRC_6:IMEM:short:mu:ST4HB
2079 "st4hb r<RA>, @(r<RB>, <SRC_6>)":XX == 0
2080 "st4hb r<RA>, @(r<RB>%s<XX>, r<SRC_6>)"
2081         do_st4hb(_SD, RA, Rb, src);
2082         do_incr(_SD, XX, &GPR[RB], 4);
2083 _IMEM,10101,10,6.RA,6.RB,_IMM32:IMEM:long:mu:ST4HB long
2084 "st4hb r<RA>, @(r<RB>, <imm>)"
2085         do_st4hb(_SD, RA, Rb, imm);
2086
2087
2088
2089 // STB
2090
2091 void::function::do_stb:unsigned32 ra, unsigned32 rb, unsigned32 src
2092         STORE(rb + src, 1, EXTRACTED32(ra, 24, 31));
2093
2094 _IMEM,10000,XX,6.RA,6.RB,6.SRC_6:IMEM:short:mu:STB
2095 "stb r<RA>, @(r<RB>, <SRC_6>)":XX == 0
2096 "stb r<RA>, @(r<RB>%s<XX>, r<SRC_6>)"
2097         do_stb(_SD, val_Ra, Rb, src);
2098         do_incr(_SD, XX, &GPR[RB], 1);
2099 _IMEM,10000,10,6.RA,6.RB,_IMM32:IMEM:long:mu:STB long
2100 "stb r<RA>, @(r<RB>, <imm>)"
2101         do_stb(_SD, val_Ra, Rb, imm);
2102
2103
2104
2105 // STH
2106
2107 void::function::do_sth:unsigned32 ra, unsigned32 rb, unsigned32 src
2108         STORE(rb + src, 2, EXTRACTED32(ra, 16, 31));
2109
2110 _IMEM,10010,XX,6.RA,6.RB,6.SRC_6:IMEM:short:mu:STH
2111 "sth r<RA>, @(r<RB>, <SRC_6>)":XX == 0
2112 "sth r<RA>, @(r<RB>%s<XX>, r<SRC_6>)"
2113         do_sth(_SD, val_Ra, Rb, src);
2114         do_incr(_SD, XX, &GPR[RB], 2);
2115 _IMEM,10010,10,6.RA,6.RB,_IMM32:IMEM:long:mu:STH long
2116 "sth r<RA>, @(r<RB>, <imm>)"
2117         do_sth(_SD, val_Ra, Rb, imm);
2118
2119
2120
2121 // STHH
2122
2123 void::function::do_sthh:unsigned32 ra, unsigned32 rb, unsigned32 src
2124         STORE(rb + src, 2, EXTRACTED32(ra, 0, 15));
2125
2126 _IMEM,10001,XX,6.RA,6.RB,6.SRC_6:IMEM:short:mu:STHH
2127 "sthh r<RA>, @(r<RB>, <SRC_6>)":XX == 0
2128 "sthh r<RA>, @(r<RB>%s<XX>, r<SRC_6>)"
2129         do_sthh(_SD, val_Ra, Rb, src);
2130         do_incr(_SD, XX, &GPR[RB], 2);
2131 _IMEM,10001,10,6.RA,6.RB,_IMM32:IMEM:long:mu:STHH long
2132 "sthh r<RA>, @(r<RB>, <imm>)"
2133         do_sthh(_SD, val_Ra, Rb, imm);
2134
2135
2136
2137 // STW
2138
2139 void::function::do_stw:unsigned32 ra, unsigned32 rb, unsigned32 src
2140         STORE(rb + src, 4, ra);
2141
2142 _IMEM,10100,XX,6.RA,6.RB,6.SRC_6:IMEM:short:mu:STW
2143 "stw r<RA>, @(r<RB>, <SRC_6>)":XX == 0
2144 "stw r<RA>, @(r<RB>%s<XX>, r<SRC_6>)"
2145         do_stw(_SD, val_Ra, Rb, src);
2146         do_incr(_SD, XX, &GPR[RB], 4);
2147 _IMEM,10100,10,6.RA,6.RB,_IMM32:IMEM:long:mu:STW long
2148 "stw r<RA>, @(r<RB>, <imm>)"
2149         do_stw(_SD, val_Ra, Rb, imm);
2150
2151
2152
2153 // SUB
2154
2155 void::function::do_sub:unsigned32 *ra, unsigned32 rb, unsigned32 imm
2156         ALU_BEGIN(rb);
2157         ALU_SUBB(imm);
2158         ALU_END(ra);
2159
2160 _IALU1,00010,00,6.RA,6.RB,6.RC:IALU1:short:iu,mu:SUB
2161 "sub r<RA>, r<RB>, r<RC>"
2162         do_sub (_SD, Ra, Rb, Rc);
2163 _IALU1,00010,10,6.RA,6.RB,_IMM6:IALU1:short:iu,mu:SUB imm
2164 "sub r<RA>, r<RB>, <imm>"
2165         do_sub (_SD, Ra, Rb, imm);
2166 _IALU1,00010,10,6.RA,6.RB,_IMM32:IALU1:long:iu,mu:SUB imm long
2167 "sub r<RA>, r<RB>, <imm>"
2168         do_sub (_SD, Ra, Rb, imm);
2169
2170
2171
2172 // SUB2H
2173
2174 void::function::do_sub2h:unsigned32 *ra, unsigned32 rb, unsigned32 imm
2175         unsigned16 high = VH2_4(rb) - VH2_4(imm);
2176         unsigned16 low  = VL2_4(rb) - VL2_4(imm);
2177         WRITE32_QUEUE (ra, (high << 16) | low);
2178
2179 _IALU1,00011,00,6.RA,6.RB,6.RC:IALU1:short:iu,mu:SUB2H
2180 "sub2h r<RA>, r<RB>, r<RC>"
2181         do_sub2h (_SD, Ra, Rb, Rc);
2182 _IALU1,00011,10,6.RA,6.RB,_IMM6:IALU1:short:iu,mu:SUB2H imm
2183 "sub2h r<RA>, r<RB>, <imm>"
2184         do_sub2h (_SD, Ra, Rb, immHL);
2185 _IALU1,00011,10,6.RA,6.RB,_IMM32:IALU1:long:iu,mu:SUB2H imm long
2186 "sub2h r<RA>, r<RB>, <imm>"
2187         do_sub2h (_SD, Ra, Rb, imm);
2188
2189
2190
2191 // SUBB
2192
2193 void::function::do_subb:unsigned32 *ra, unsigned32 rb, unsigned32 imm
2194         ALU_BEGIN(rb);
2195         ALU_SUBB_B(imm, ALU_CARRY);
2196         ALU_END(ra);
2197
2198 _IALU1,00101,00,6.RA,6.RB,6.RC:IALU1:short:iu,mu:SUBB
2199 "subb r<RA>, r<RB>, r<RC>"
2200         do_subb (_SD, Ra, Rb, Rc);
2201 _IALU1,00101,10,6.RA,6.RB,_IMM6:IALU1:short:iu,mu:SUBB imm
2202 "subb r<RA>, r<RB>, <imm>"
2203         do_subb (_SD, Ra, Rb, imm);
2204 _IALU1,00101,10,6.RA,6.RB,_IMM32:IALU1:long:iu,mu:SUBB imm long
2205 "subb r<RA>, r<RB>, <imm>"
2206         do_subb (_SD, Ra, Rb, imm);
2207
2208
2209
2210 // SUBHppp
2211
2212 void::function::do_subh_ppp:int ppp, unsigned32 *ra, unsigned32 rb, unsigned32 src
2213         switch (ppp) {
2214         case 0x0: /* LLL */
2215           {
2216           ALU16_BEGIN(VL2_4(rb));
2217           ALU16_SUBB(VL2_4(src));
2218           ALU16_END(ra, 0);
2219           }
2220           break;
2221         case 0x1: /* LLH */
2222           {
2223           ALU16_BEGIN(VL2_4(rb));
2224           ALU16_SUBB(VH2_4(src));
2225           ALU16_END(ra, 0);
2226           }
2227           break;
2228         case 0x2: /* LHL */
2229           {
2230           ALU16_BEGIN(VH2_4(rb));
2231           ALU16_SUBB(VL2_4(src));
2232           ALU16_END(ra, 0);
2233           }
2234           break;
2235         case 0x3: /* LHH */
2236           {
2237           ALU16_BEGIN(VH2_4(rb));
2238           ALU16_SUBB(VH2_4(src));
2239           ALU16_END(ra, 0);
2240           }
2241           break;
2242         case 0x4: /* HLL */
2243           {
2244           ALU16_BEGIN(VL2_4(rb));
2245           ALU16_SUBB(VL2_4(src));
2246           ALU16_END(ra, 1);
2247           }
2248           break;
2249         case 0x5: /* HLH */
2250           {
2251           ALU16_BEGIN(VL2_4(rb));
2252           ALU16_SUBB(VH2_4(src));
2253           ALU16_END(ra, 1);
2254           }
2255           break;
2256         case 0x6: /* HHL */
2257           {
2258           ALU16_BEGIN(VH2_4(rb));
2259           ALU16_SUBB(VL2_4(src));
2260           ALU16_END(ra, 1);
2261           }
2262           break;
2263         case 0x7: /* HHH */
2264           {
2265           ALU16_BEGIN(VH2_4(rb));
2266           ALU16_SUBB(VH2_4(src));
2267           ALU16_END(ra, 1);
2268           }
2269           break;
2270         default:
2271           sim_engine_abort (SD, CPU, cia, "do_subh_ppp - internal error - bad switch");
2272         }
2273
2274 _IALU1,11,ppp,00,6.RA,6.RB,6.RC:IALU1:short:iu,mu:SUBHppp
2275 "subh%s<ppp> r<RA>, r<RB>, r<RC>"
2276         do_subh_ppp(_SD, ppp, Ra, Rb, Rc);
2277 _IALU1,11,ppp,10,6.RA,6.RB,_IMM6:IALU1:short:iu,mu:SUBHppp imm
2278 "subh%s<ppp> r<RA>, r<RB>, <imm>"
2279         do_subh_ppp(_SD, ppp, Ra, Rb, immHL);
2280 _IALU1,11,ppp,10,6.RA,6.RB,_IMM32:IALU1:long:iu,mu:SUBHppp imm long
2281 "subh%s<ppp> r<RA>, r<RB>, <imm>"
2282         do_subh_ppp(_SD, ppp, Ra, Rb, imm);
2283
2284
2285
2286 // TRAP
2287
2288 address_word::function::do_trap:address_word trap_vector, address_word nia
2289         /* Steal trap 31 for doing system calls */
2290         /* System calls are defined in libgloss/d30v/syscall.h.  */
2291         if (trap_vector == EIT_VB + 0x20 + (31 << 3))
2292           {
2293             enum { PARM1 = 2, PARM2, PARM3, PARM4, FUNC };
2294             if (GPR[FUNC] == 1)         /* exit */
2295               {
2296                 sim_engine_halt (sd, STATE_CPU (sd, 0), NULL, cia, sim_exited,
2297                                  GPR[PARM1]);
2298                 return -1; /* dummy */
2299               }
2300             else
2301               {
2302                 CB_SYSCALL syscall;
2303
2304                 CB_SYSCALL_INIT (&syscall);
2305                 syscall.arg1 = GPR[PARM1];
2306                 syscall.arg2 = GPR[PARM2];
2307                 syscall.arg3 = GPR[PARM3];
2308                 syscall.arg4 = GPR[PARM4];
2309                 syscall.func = GPR[FUNC];
2310                 syscall.p1 = (PTR) SD;
2311                 syscall.read_mem = d30v_read_mem;
2312                 syscall.write_mem = d30v_write_mem;
2313
2314                 WRITE32_QUEUE (&GPR[PARM1],
2315                                ((cb_syscall (STATE_CALLBACK (SD), &syscall)
2316                                  == CB_RC_OK)
2317                                 ? syscall.result
2318                                 : -syscall.errcode));
2319                 return nia;
2320               }
2321           }
2322         else if (TRACE_TRAP_P)
2323           {
2324             int reg, i;
2325             sim_io_eprintf (sd, "\nTrap %ld:\n", (long) ((trap_vector - (EIT_VB + 0x20)) >> 3));
2326             for (reg = 0; reg < NR_GENERAL_PURPOSE_REGISTERS; reg += 8)
2327               {
2328                 sim_io_eprintf (sd, "r%.2d  - r%.2d: ", reg, reg+7);
2329                 for (i = 0; i < 8; i++)
2330                   sim_io_eprintf (sd, " 0x%.8lx", (long) GPR[reg+i]);
2331                 sim_io_eprintf (sd, "\n");
2332               }
2333
2334             for (reg = 0; reg < 16; reg += 8)
2335               {
2336                 sim_io_eprintf (sd, "cr%.2d - cr%.2d:", reg, reg+7);
2337                 for (i = 0; i < 8; i++)
2338                   sim_io_eprintf (sd, " 0x%.8lx", (long) CREG[reg+i]);
2339                 sim_io_eprintf (sd, "\n");
2340               }
2341
2342             sim_io_eprintf (sd, "a0   - a1:  ");
2343             for (reg = 0; reg < NR_ACCUMULATORS; reg++)
2344               sim_io_eprintf (sd, " 0x%.8lx 0x%.8lx",
2345                               (long)EXTRACTED64(ACC[reg], 0, 31),
2346                               (long)EXTRACTED64(ACC[reg], 32, 63));
2347             sim_io_eprintf (sd, "\n");
2348
2349             sim_io_eprintf (sd, "f0   - f7:  ");
2350             sim_io_eprintf (sd, "     (f0) %d", (int) PSW_VAL(PSW_F0));
2351             sim_io_eprintf (sd, "     (f1) %d", (int) PSW_VAL(PSW_F1));
2352             sim_io_eprintf (sd, "     (f2) %d", (int) PSW_VAL(PSW_F2));
2353             sim_io_eprintf (sd, "     (f3) %d", (int) PSW_VAL(PSW_F3));
2354             sim_io_eprintf (sd, "      (s) %d", (int) PSW_VAL(PSW_S));
2355             sim_io_eprintf (sd, "      (v) %d", (int) PSW_VAL(PSW_V));
2356             sim_io_eprintf (sd, "     (va) %d", (int) PSW_VAL(PSW_VA));
2357             sim_io_eprintf (sd, "      (c) %d\n", (int) PSW_VAL(PSW_C));
2358
2359             sim_io_eprintf (sd, "pswh:       ");
2360             sim_io_eprintf (sd, "     (sm) %d", (int) PSW_VAL(PSW_SM));
2361             sim_io_eprintf (sd, "     (ea) %d", (int) PSW_VAL(PSW_EA));
2362             sim_io_eprintf (sd, "     (ie) %d", (int) PSW_VAL(PSW_IE));
2363             sim_io_eprintf (sd, "     (rp) %d", (int) PSW_VAL(PSW_RP));
2364             sim_io_eprintf (sd, "     (md) %d", (int) PSW_VAL(PSW_MD));
2365
2366             if (PSW_VAL(PSW_DB))
2367               sim_io_eprintf (sd, "     (db) %d", (int) PSW_VAL(PSW_DB));
2368
2369             if (PSW_VAL(PSW_DS))
2370               sim_io_eprintf (sd, "     (ds) %d", (int) PSW_VAL(PSW_DS));
2371
2372             sim_io_eprintf (sd, "\n");
2373             return nia;
2374           }
2375         else
2376           {
2377             if(PSW_VAL(PSW_RP) && RPT_E == cia)
2378               {
2379                 WRITE32_QUEUE (&bPC, RPT_S);
2380                 if (RPT_C == 0)
2381                   PSW_SET (PSW_RP, 0);
2382               }
2383             else
2384               WRITE32_QUEUE (&bPC, cia + 8);
2385             DID_TRAP = 1;
2386             return trap_vector;
2387           }
2388
2389 _BRA,01001,00,6.**,6.**,6.RC:BRA:short:mu:TRAP
2390 "trap r<RC>"
2391         nia = do_trap (_SD, EIT_VB + 0x20 + MASKED32(Rc, 24, 28), nia);
2392 _BRA,01001,10,6.**,6.**,_IMM6:BRA:short:mu:TRAP imm
2393 "trap <imm>"
2394         nia = do_trap (_SD, EIT_VB + 0x20 + (imm_5 << 3), nia);
2395
2396
2397
2398 // XOR
2399
2400 _LOGIC,11011,00,6.RA,6.RB,6.RC:LOGIC:short:iu,mu:XOR
2401 "xor r<RA>, r<RB>, r<RC>"
2402         WRITE32_QUEUE (Ra, Rb ^ Rc);
2403 _LOGIC,11011,10,6.RA,6.RB,_IMM6:LOGIC:short:iu,mu:XOR imm
2404 "xor r<RA>, r<RB>, <imm>"
2405         WRITE32_QUEUE (Ra, Rb ^ imm);
2406 _LOGIC,11011,10,6.RA,6.RB,_IMM32:LOGIC:long:iu,mu:XOR imm long
2407 "xor r<RA>, r<RB>, <imm>"
2408         WRITE32_QUEUE (Ra, Rb ^ imm);
2409
2410
2411
2412 // XORFG
2413
2414 _LOGIC,01011,00,***,3.FA,***,3.FB,***,3.FC:LOGIC:short:iu,mu:XORFG
2415 "xorfg f<FA>, f<FB>, f<FC>"
2416         PSW_FLAG_SET_QUEUE(FA, PSW_FLAG_VAL(FB) ^ PSW_FLAG_VAL(FC));
2417 _LOGIC,01011,10,***,3.FA,***,3.FB,_IMM6:LOGIC:short:iu,mu:XORFG imm
2418 "xorfg f<FA>, f<FB>, <imm_6>"
2419         PSW_FLAG_SET_QUEUE(FA, PSW_FLAG_VAL(FB) ^ (imm_6 & 1));
2420
2421
2422