sim/frv/frv-sim.h

   1 /* collection of junk waiting time to sort out
   2    Copyright (C) 1998, 1999, 2000, 2001, 2003, 2007, 2008, 2009, 2010, 2011
   3    Free Software Foundation, Inc.
   4    Contributed by Red Hat
   5
   6 This file is part of the GNU Simulators.
   7
   8 This program is free software; you can redistribute it and/or modify
   9 it under the terms of the GNU General Public License as published by
  10 the Free Software Foundation; either version 3 of the License, or
  11 (at your option) any later version.
  12
  13 This program is distributed in the hope that it will be useful,
  14 but WITHOUT ANY WARRANTY; without even the implied warranty of
  15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16 GNU General Public License for more details.
  17
  18 You should have received a copy of the GNU General Public License
  19 along with this program.  If not, see <http://www.gnu.org/licenses/>.  */
  20
  21 #ifndef FRV_SIM_H
  22 #define FRV_SIM_H
  23
  24 #include "sim-options.h"
  25
  26 /* True if SPR is the number of accumulator or accumulator guard register.  */
  27 #define SPR_IS_ACC(SPR) ((SPR) >= 1408 && (SPR) <= 1535)
  28
  29 /* Initialization of the frv cpu.  */
  30 void frv_initialize (SIM_CPU *, SIM_DESC);
  31 void frv_term (SIM_DESC);
  32 void frv_power_on_reset (SIM_CPU *);
  33 void frv_hardware_reset (SIM_CPU *);
  34 void frv_software_reset (SIM_CPU *);
  35
  36 /* The reset register.  See FRV LSI section 10.3.1  */
  37 #define RSTR_ADDRESS        0xfeff0500
  38 #define RSTR_INITIAL_VALUE  0x00000400
  39 #define RSTR_HARDWARE_RESET 0x00000200
  40 #define RSTR_SOFTWARE_RESET 0x00000100
  41
  42 #define GET_RSTR_HR(rstr) (((rstr) >> 1) & 1)
  43 #define GET_RSTR_SR(rstr) (((rstr)     ) & 1)
  44
  45 #define SET_RSTR_H(rstr) ((rstr) |= (1 << 9))
  46 #define SET_RSTR_S(rstr) ((rstr) |= (1 << 8))
  47
  48 #define CLEAR_RSTR_P(rstr)  ((rstr) &= ~(1 << 10))
  49 #define CLEAR_RSTR_H(rstr)  ((rstr) &= ~(1 <<  9))
  50 #define CLEAR_RSTR_S(rstr)  ((rstr) &= ~(1 <<  8))
  51 #define CLEAR_RSTR_HR(rstr) ((rstr) &= ~(1 <<  1))
  52 #define CLEAR_RSTR_SR(rstr) ((rstr) &= ~1)
  53
  54 /* Cutomized hardware get/set functions.  */
  55 extern USI  frvbf_h_spr_get_handler (SIM_CPU *, UINT);
  56 extern void frvbf_h_spr_set_handler (SIM_CPU *, UINT, USI);
  57 extern USI  frvbf_h_gr_get_handler (SIM_CPU *, UINT);
  58 extern void frvbf_h_gr_set_handler (SIM_CPU *, UINT, USI);
  59 extern UHI  frvbf_h_gr_hi_get_handler (SIM_CPU *, UINT);
  60 extern void frvbf_h_gr_hi_set_handler (SIM_CPU *, UINT, UHI);
  61 extern UHI  frvbf_h_gr_lo_get_handler (SIM_CPU *, UINT);
  62 extern void frvbf_h_gr_lo_set_handler (SIM_CPU *, UINT, UHI);
  63 extern DI   frvbf_h_gr_double_get_handler (SIM_CPU *, UINT);
  64 extern void frvbf_h_gr_double_set_handler (SIM_CPU *, UINT, DI);
  65 extern SF   frvbf_h_fr_get_handler (SIM_CPU *, UINT);
  66 extern void frvbf_h_fr_set_handler (SIM_CPU *, UINT, SF);
  67 extern DF   frvbf_h_fr_double_get_handler (SIM_CPU *, UINT);
  68 extern void frvbf_h_fr_double_set_handler (SIM_CPU *, UINT, DF);
  69 extern USI  frvbf_h_fr_int_get_handler (SIM_CPU *, UINT);
  70 extern void frvbf_h_fr_int_set_handler (SIM_CPU *, UINT, USI);
  71 extern DI   frvbf_h_cpr_double_get_handler (SIM_CPU *, UINT);
  72 extern void frvbf_h_cpr_double_set_handler (SIM_CPU *, UINT, DI);
  73 extern void frvbf_h_gr_quad_set_handler (SIM_CPU *, UINT, SI *);
  74 extern void frvbf_h_fr_quad_set_handler (SIM_CPU *, UINT, SI *);
  75 extern void frvbf_h_cpr_quad_set_handler (SIM_CPU *, UINT, SI *);
  76 extern void frvbf_h_psr_s_set_handler (SIM_CPU *, BI);
  77
  78 extern USI  spr_psr_get_handler (SIM_CPU *);
  79 extern void spr_psr_set_handler (SIM_CPU *, USI);
  80 extern USI  spr_tbr_get_handler (SIM_CPU *);
  81 extern void spr_tbr_set_handler (SIM_CPU *, USI);
  82 extern USI  spr_bpsr_get_handler (SIM_CPU *);
  83 extern void spr_bpsr_set_handler (SIM_CPU *, USI);
  84 extern USI  spr_ccr_get_handler (SIM_CPU *);
  85 extern void spr_ccr_set_handler (SIM_CPU *, USI);
  86 extern void spr_cccr_set_handler (SIM_CPU *, USI);
  87 extern USI  spr_cccr_get_handler (SIM_CPU *);
  88 extern USI  spr_isr_get_handler (SIM_CPU *);
  89 extern void spr_isr_set_handler (SIM_CPU *, USI);
  90 extern USI  spr_sr_get_handler (SIM_CPU *, UINT);
  91 extern void spr_sr_set_handler (SIM_CPU *, UINT, USI);
  92
  93 extern void frvbf_switch_supervisor_user_context (SIM_CPU *);
  94
  95 extern QI frvbf_set_icc_for_shift_left  (SIM_CPU *, SI, SI, QI);
  96 extern QI frvbf_set_icc_for_shift_right (SIM_CPU *, SI, SI, QI);
  97
  98 /* Insn semantics.  */
  99 extern void frvbf_signed_integer_divide (SIM_CPU *, SI, SI, int, int);
 100 extern void frvbf_unsigned_integer_divide (SIM_CPU *, USI, USI, int, int);
 101 extern SI   frvbf_shift_left_arith_saturate (SIM_CPU *, SI, SI);
 102 extern SI   frvbf_iacc_cut (SIM_CPU *, DI, SI);
 103
 104 extern void frvbf_clear_accumulators (SIM_CPU *, SI, int);
 105
 106 extern SI   frvbf_scan_result (SIM_CPU *, SI);
 107 extern SI   frvbf_cut (SIM_CPU *, SI, SI, SI);
 108 extern SI   frvbf_media_cut (SIM_CPU *, DI, SI);
 109 extern SI   frvbf_media_cut_ss (SIM_CPU *, DI, SI);
 110 extern void frvbf_media_cop (SIM_CPU *, int);
 111 extern UQI  frvbf_cr_logic (SIM_CPU *, SI, UQI, UQI);
 112
 113 extern void frvbf_set_write_next_vliw_addr_to_LR (SIM_CPU *, int);
 114 extern int  frvbf_write_next_vliw_addr_to_LR;
 115
 116 extern void frvbf_set_ne_index (SIM_CPU *, int);
 117 extern void frvbf_force_update (SIM_CPU *);
 118 \f
 119 #define GETTWI GETTSI
 120 #define SETTWI SETTSI
 121 #define LEUINT LEUSI
 122 \f
 123 /* Hardware/device support.
 124    ??? Will eventually want to move device stuff to config files.  */
 125
 126 /* Support for the MCCR register (Cache Control Register) is needed in order
 127    for overlays to work correctly with the scache: cached instructions need
 128    to be flushed when the instruction space is changed at runtime.  */
 129
 130 /* These were just copied from another port and are necessary to build, but
 131    but don't appear to be used.  */
 132 #define MCCR_ADDR 0xffffffff
 133 #define MCCR_CP 0x80
 134 /* not supported */
 135 #define MCCR_CM0 2
 136 #define MCCR_CM1 1
 137
 138 /* sim_core_attach device argument.  */
 139 extern device frv_devices;
 140
 141 /* FIXME: Temporary, until device support ready.  */
 142 struct _device { int foo; };
 143
 144 /* maintain the address of the start of the previous VLIW insn sequence.  */
 145 extern IADDR previous_vliw_pc;
 146 extern CGEN_ATTR_VALUE_ENUM_TYPE frv_current_fm_slot;
 147
 148 /* Hardware status.  */
 149 #define GET_HSR0() GET_H_SPR (H_SPR_HSR0)
 150 #define SET_HSR0(hsr0) SET_H_SPR (H_SPR_HSR0, (hsr0))
 151
 152 #define GET_HSR0_ICE(hsr0) (((hsr0) >> 31) & 1)
 153 #define SET_HSR0_ICE(hsr0) ((hsr0) |= (1 << 31))
 154 #define CLEAR_HSR0_ICE(hsr0) ((hsr0) &= ~(1 << 31))
 155
 156 #define GET_HSR0_DCE(hsr0) (((hsr0) >> 30) & 1)
 157 #define SET_HSR0_DCE(hsr0) ((hsr0) |= (1 << 30))
 158 #define CLEAR_HSR0_DCE(hsr0) ((hsr0) &= ~(1 << 30))
 159
 160 #define GET_HSR0_CBM(hsr0) (((hsr0) >> 27) & 1)
 161 #define GET_HSR0_RME(hsr0) (((hsr0) >> 22) & 1)
 162 #define GET_HSR0_SA(hsr0)  (((hsr0) >> 12) & 1)
 163 #define GET_HSR0_FRN(hsr0) (((hsr0) >> 11) & 1)
 164 #define GET_HSR0_GRN(hsr0) (((hsr0) >> 10) & 1)
 165 #define GET_HSR0_FRHE(hsr0) (((hsr0) >> 9) & 1)
 166 #define GET_HSR0_FRLE(hsr0) (((hsr0) >> 8) & 1)
 167 #define GET_HSR0_GRHE(hsr0) (((hsr0) >> 7) & 1)
 168 #define GET_HSR0_GRLE(hsr0) (((hsr0) >> 6) & 1)
 169
 170 #define GET_IHSR8() GET_H_SPR (H_SPR_IHSR8)
 171 #define GET_IHSR8_NBC(ihsr8) ((ihsr8) & 1)
 172 #define GET_IHSR8_ICDM(ihsr8) (((ihsr8) >>  1) & 1)
 173 #define GET_IHSR8_ICWE(ihsr8) (((ihsr8) >>  8) & 7)
 174 #define GET_IHSR8_DCWE(ihsr8) (((ihsr8) >> 12) & 7)
 175
 176 void frvbf_insn_cache_preload (SIM_CPU *, SI, USI, int);
 177 void frvbf_data_cache_preload (SIM_CPU *, SI, USI, int);
 178 void frvbf_insn_cache_unlock (SIM_CPU *, SI);
 179 void frvbf_data_cache_unlock (SIM_CPU *, SI);
 180 void frvbf_insn_cache_invalidate (SIM_CPU *, SI, int);
 181 void frvbf_data_cache_invalidate (SIM_CPU *, SI, int);
 182 void frvbf_data_cache_flush (SIM_CPU *, SI, int);
 183
 184 /* FR-V Interrupt classes.
 185    These are declared in order of increasing priority.  */
 186 enum frv_interrupt_class
 187 {
 188   FRV_EXTERNAL_INTERRUPT,
 189   FRV_SOFTWARE_INTERRUPT,
 190   FRV_PROGRAM_INTERRUPT,
 191   FRV_BREAK_INTERRUPT,
 192   FRV_RESET_INTERRUPT,
 193   NUM_FRV_INTERRUPT_CLASSES
 194 };
 195
 196 /* FR-V Interrupt kinds.
 197    These are declared in order of increasing priority.  */
 198 enum frv_interrupt_kind
 199 {
 200   /* External interrupts */
 201   FRV_INTERRUPT_LEVEL_1,
 202   FRV_INTERRUPT_LEVEL_2,
 203   FRV_INTERRUPT_LEVEL_3,
 204   FRV_INTERRUPT_LEVEL_4,
 205   FRV_INTERRUPT_LEVEL_5,
 206   FRV_INTERRUPT_LEVEL_6,
 207   FRV_INTERRUPT_LEVEL_7,
 208   FRV_INTERRUPT_LEVEL_8,
 209   FRV_INTERRUPT_LEVEL_9,
 210   FRV_INTERRUPT_LEVEL_10,
 211   FRV_INTERRUPT_LEVEL_11,
 212   FRV_INTERRUPT_LEVEL_12,
 213   FRV_INTERRUPT_LEVEL_13,
 214   FRV_INTERRUPT_LEVEL_14,
 215   FRV_INTERRUPT_LEVEL_15,
 216   /* Software interrupt */
 217   FRV_TRAP_INSTRUCTION,
 218   /* Program interrupts */
 219   FRV_COMMIT_EXCEPTION,
 220   FRV_DIVISION_EXCEPTION,
 221   FRV_DATA_STORE_ERROR,
 222   FRV_DATA_ACCESS_EXCEPTION,
 223   FRV_DATA_ACCESS_MMU_MISS,
 224   FRV_DATA_ACCESS_ERROR,
 225   FRV_MP_EXCEPTION,
 226   FRV_FP_EXCEPTION,
 227   FRV_MEM_ADDRESS_NOT_ALIGNED,
 228   FRV_REGISTER_EXCEPTION,
 229   FRV_MP_DISABLED,
 230   FRV_FP_DISABLED,
 231   FRV_PRIVILEGED_INSTRUCTION,
 232   FRV_ILLEGAL_INSTRUCTION,
 233   FRV_INSTRUCTION_ACCESS_EXCEPTION,
 234   FRV_INSTRUCTION_ACCESS_ERROR,
 235   FRV_INSTRUCTION_ACCESS_MMU_MISS,
 236   FRV_COMPOUND_EXCEPTION,
 237   /* Break interrupt */
 238   FRV_BREAK_EXCEPTION,
 239   /* Reset interrupt */
 240   FRV_RESET,
 241   NUM_FRV_INTERRUPT_KINDS
 242 };
 243
 244 /* FRV interrupt exception codes */
 245 enum frv_ec
 246 {
 247   FRV_EC_DATA_STORE_ERROR             = 0x00,
 248   FRV_EC_INSTRUCTION_ACCESS_MMU_MISS  = 0x01,
 249   FRV_EC_INSTRUCTION_ACCESS_ERROR     = 0x02,
 250   FRV_EC_INSTRUCTION_ACCESS_EXCEPTION = 0x03,
 251   FRV_EC_PRIVILEGED_INSTRUCTION       = 0x04,
 252   FRV_EC_ILLEGAL_INSTRUCTION          = 0x05,
 253   FRV_EC_FP_DISABLED                  = 0x06,
 254   FRV_EC_MP_DISABLED                  = 0x07,
 255   FRV_EC_MEM_ADDRESS_NOT_ALIGNED      = 0x0b,
 256   FRV_EC_REGISTER_EXCEPTION           = 0x0c,
 257   FRV_EC_FP_EXCEPTION                 = 0x0d,
 258   FRV_EC_MP_EXCEPTION                 = 0x0e,
 259   FRV_EC_DATA_ACCESS_ERROR            = 0x10,
 260   FRV_EC_DATA_ACCESS_MMU_MISS         = 0x11,
 261   FRV_EC_DATA_ACCESS_EXCEPTION        = 0x12,
 262   FRV_EC_DIVISION_EXCEPTION           = 0x13,
 263   FRV_EC_COMMIT_EXCEPTION             = 0x14,
 264   FRV_EC_NOT_EXECUTED                 = 0x1f,
 265   FRV_EC_INTERRUPT_LEVEL_1            = FRV_EC_NOT_EXECUTED,
 266   FRV_EC_INTERRUPT_LEVEL_2            = FRV_EC_NOT_EXECUTED,
 267   FRV_EC_INTERRUPT_LEVEL_3            = FRV_EC_NOT_EXECUTED,
 268   FRV_EC_INTERRUPT_LEVEL_4            = FRV_EC_NOT_EXECUTED,
 269   FRV_EC_INTERRUPT_LEVEL_5            = FRV_EC_NOT_EXECUTED,
 270   FRV_EC_INTERRUPT_LEVEL_6            = FRV_EC_NOT_EXECUTED,
 271   FRV_EC_INTERRUPT_LEVEL_7            = FRV_EC_NOT_EXECUTED,
 272   FRV_EC_INTERRUPT_LEVEL_8            = FRV_EC_NOT_EXECUTED,
 273   FRV_EC_INTERRUPT_LEVEL_9            = FRV_EC_NOT_EXECUTED,
 274   FRV_EC_INTERRUPT_LEVEL_10           = FRV_EC_NOT_EXECUTED,
 275   FRV_EC_INTERRUPT_LEVEL_11           = FRV_EC_NOT_EXECUTED,
 276   FRV_EC_INTERRUPT_LEVEL_12           = FRV_EC_NOT_EXECUTED,
 277   FRV_EC_INTERRUPT_LEVEL_13           = FRV_EC_NOT_EXECUTED,
 278   FRV_EC_INTERRUPT_LEVEL_14           = FRV_EC_NOT_EXECUTED,
 279   FRV_EC_INTERRUPT_LEVEL_15           = FRV_EC_NOT_EXECUTED,
 280   FRV_EC_TRAP_INSTRUCTION             = FRV_EC_NOT_EXECUTED,
 281   FRV_EC_COMPOUND_EXCEPTION           = FRV_EC_NOT_EXECUTED,
 282   FRV_EC_BREAK_EXCEPTION              = FRV_EC_NOT_EXECUTED,
 283   FRV_EC_RESET                        = FRV_EC_NOT_EXECUTED
 284 };
 285
 286 /* FR-V Interrupt.
 287    This struct contains enough information to describe a particular interrupt
 288    occurance.  */
 289 struct frv_interrupt
 290 {
 291   enum frv_interrupt_kind  kind;
 292   enum frv_ec              ec;
 293   enum frv_interrupt_class iclass;
 294   unsigned char deferred;
 295   unsigned char precise;
 296   unsigned char handler_offset;
 297 };
 298
 299 /* FR-V Interrupt table.
 300    Describes the interrupts supported by the FR-V.  */
 301 extern struct frv_interrupt frv_interrupt_table[];
 302
 303 /* FR-V Interrupt State.
 304    Interrupts are queued during execution of parallel insns and the interupt(s)
 305    to be handled determined by analysing the queue after each VLIW insn.  */
 306 #define FRV_INTERRUPT_QUEUE_SIZE (4 * 4) /* 4 interrupts x 4 insns for now.  */
 307
 308 /* register_exception codes */
 309 enum frv_rec
 310 {
 311   FRV_REC_UNIMPLEMENTED = 0,
 312   FRV_REC_UNALIGNED     = 1
 313 };
 314
 315 /* instruction_access_exception codes */
 316 enum frv_iaec
 317 {
 318   FRV_IAEC_PROTECT_VIOLATION = 1
 319 };
 320
 321 /* data_access_exception codes */
 322 enum frv_daec
 323 {
 324   FRV_DAEC_PROTECT_VIOLATION = 1
 325 };
 326
 327 /* division_exception ISR codes */
 328 enum frv_dtt
 329 {
 330   FRV_DTT_NO_EXCEPTION     = 0,
 331   FRV_DTT_DIVISION_BY_ZERO = 1,
 332   FRV_DTT_OVERFLOW         = 2,
 333   FRV_DTT_BOTH             = 3
 334 };
 335
 336 /* data written during an insn causing an interrupt */
 337 struct frv_data_written
 338 {
 339   USI words[4]; /* Actual data in words */
 340   int length;   /* length of data written */
 341 };
 342
 343 /* fp_exception info */
 344 /* Trap codes for FSR0 and FQ registers.  */
 345 enum frv_fsr_traps
 346 {
 347   FSR_INVALID_OPERATION = 0x20,
 348   FSR_OVERFLOW          = 0x10,
 349   FSR_UNDERFLOW         = 0x08,
 350   FSR_DIVISION_BY_ZERO  = 0x04,
 351   FSR_INEXACT           = 0x02,
 352   FSR_DENORMAL_INPUT    = 0x01,
 353   FSR_NO_EXCEPTION      = 0
 354 };
 355
 356 /* Floating point trap types for FSR.  */
 357 enum frv_fsr_ftt
 358 {
 359   FTT_NONE               = 0,
 360   FTT_IEEE_754_EXCEPTION = 1,
 361   FTT_UNIMPLEMENTED_FPOP = 3,
 362   FTT_SEQUENCE_ERROR     = 4,
 363   FTT_INVALID_FR         = 6,
 364   FTT_DENORMAL_INPUT     = 7
 365 };
 366
 367 struct frv_fp_exception_info
 368 {
 369   enum frv_fsr_traps fsr_mask; /* interrupt code for FSR */
 370   enum frv_fsr_ftt   ftt;      /* floating point trap type */
 371 };
 372
 373 struct frv_interrupt_queue_element
 374 {
 375   enum frv_interrupt_kind kind;      /* kind of interrupt */
 376   IADDR                   vpc;       /* address of insn causing interrupt */
 377   int                     slot;      /* VLIW slot containing the insn.  */
 378   USI                     eaddress;  /* address of data access */
 379   union {
 380     enum frv_rec  rec;               /* register exception code */
 381     enum frv_iaec iaec;              /* insn access exception code */
 382     enum frv_daec daec;              /* data access exception code */
 383     enum frv_dtt  dtt;               /* division exception code */
 384     struct frv_fp_exception_info fp_info;
 385     struct frv_data_written data_written;
 386   } u;
 387 };
 388
 389 struct frv_interrupt_timer
 390 {
 391   int enabled;
 392   unsigned value;
 393   unsigned current;
 394   enum frv_interrupt_kind interrupt;
 395 };
 396
 397 struct frv_interrupt_state
 398 {
 399   /* The interrupt queue */
 400   struct frv_interrupt_queue_element queue[FRV_INTERRUPT_QUEUE_SIZE];
 401   int queue_index;
 402
 403   /* interrupt queue element causing imprecise interrupt.  */
 404   struct frv_interrupt_queue_element *imprecise_interrupt;
 405
 406   /* interrupt timer.  */
 407   struct frv_interrupt_timer timer;
 408
 409   /* The last data written stored as an array of words.  */
 410   struct frv_data_written data_written;
 411
 412   /* The vliw slot of the insn causing the interrupt.  */
 413   int slot;
 414
 415   /* target register index for non excepting insns.  */
 416 #define NE_NOFLAG (-1)
 417   int ne_index;
 418
 419   /* Accumulated NE flags for non excepting floating point insns.  */
 420   SI f_ne_flags[2];
 421 };
 422
 423 extern struct frv_interrupt_state frv_interrupt_state;
 424
 425 /* Macros to manipulate the PSR.  */
 426 #define GET_PSR() GET_H_SPR (H_SPR_PSR)
 427
 428 #define SET_PSR_ET(psr, et) (           \
 429   (psr) = ((psr) & ~0x1) | ((et) & 0x1) \
 430 )
 431
 432 #define GET_PSR_PS(psr) (((psr) >> 1) & 1)
 433
 434 #define SET_PSR_S(psr, s) (                          \
 435   (psr) = ((psr) & ~(0x1 << 2)) | (((s) & 0x1) << 2) \
 436 )
 437
 438 /* Macros to handle the ISR register.  */
 439 #define GET_ISR() GET_H_SPR (H_SPR_ISR)
 440 #define SET_ISR(isr) SET_H_SPR (H_SPR_ISR, (isr))
 441
 442 #define GET_ISR_EDE(isr) (((isr) >> 5) & 1)
 443
 444 #define GET_ISR_DTT(isr) (((isr) >> 3) & 3)
 445 #define SET_ISR_DTT(isr, dtt) (                        \
 446   (isr) = ((isr) & ~(0x3 << 3)) | (((dtt) & 0x3) << 3) \
 447 )
 448
 449 #define SET_ISR_AEXC(isr) ((isr) |= (1 << 2))
 450
 451 #define GET_ISR_EMAM(isr) ((isr) & 1)
 452
 453 /* Macros to handle exception status registers.
 454    Get and set the hardware directly, since we may be getting/setting fields
 455    which are not accessible to the user.  */
 456 #define GET_ESR(index) \
 457   (CPU (h_spr[H_SPR_ESR0 + (index)]))
 458 #define SET_ESR(index, esr) \
 459   (CPU (h_spr[H_SPR_ESR0 + (index)]) = (esr))
 460
 461 #define SET_ESR_VALID(esr) ((esr) |= 1)
 462 #define CLEAR_ESR_VALID(esr) ((esr) &= ~1)
 463
 464 #define SET_ESR_EC(esr, ec) (                           \
 465   (esr) = ((esr) & ~(0x1f << 1)) | (((ec) & 0x1f) << 1) \
 466 )
 467
 468 #define SET_ESR_REC(esr, rec) (                        \
 469   (esr) = ((esr) & ~(0x3 << 6)) | (((rec) & 0x3) << 6) \
 470 )
 471
 472 #define SET_ESR_IAEC(esr, iaec) (                       \
 473   (esr) = ((esr) & ~(0x1 << 8)) | (((iaec) & 0x1) << 8) \
 474 )
 475
 476 #define SET_ESR_DAEC(esr, daec) (                       \
 477   (esr) = ((esr) & ~(0x1 << 9)) | (((daec) & 0x1) << 9) \
 478 )
 479
 480 #define SET_ESR_EAV(esr) ((esr) |= (1 << 11))
 481 #define CLEAR_ESR_EAV(esr) ((esr) &= ~(1 << 11))
 482
 483 #define GET_ESR_EDV(esr) (((esr) >> 12) & 1)
 484 #define SET_ESR_EDV(esr) ((esr) |= (1 << 12))
 485 #define CLEAR_ESR_EDV(esr) ((esr) &= ~(1 << 12))
 486
 487 #define GET_ESR_EDN(esr) ( \
 488   ((esr) >> 13) & 0xf      \
 489 )
 490 #define SET_ESR_EDN(esr, edn) (                       \
 491   (esr) = ((esr) & ~(0xf << 13)) | (((edn) & 0xf) << 13) \
 492 )
 493
 494 #define SET_EPCR(index, address) \
 495   (CPU (h_spr[H_SPR_EPCR0 + (index)]) = (address))
 496
 497 #define SET_EAR(index, address) \
 498   (CPU (h_spr[H_SPR_EAR0 + (index)]) = (address))
 499
 500 #define SET_EDR(index, edr) \
 501   (CPU (h_spr[H_SPR_EDR0 + (index)]) = (edr))
 502
 503 #define GET_ESFR(index) \
 504   (CPU (h_spr[H_SPR_ESFR0 + (index)]))
 505 #define SET_ESFR(index, esfr) \
 506   (CPU (h_spr[H_SPR_ESFR0 + (index)]) = (esfr))
 507
 508 #define GET_ESFR_FLAG(findex) ( \
 509   (findex) > 31 ? \
 510     ((CPU (h_spr[H_SPR_ESFR0]) >> ((findex)-32)) & 1) \
 511     : \
 512     ((CPU (h_spr[H_SPR_ESFR1]) >> (findex)) & 1) \
 513 )
 514 #define SET_ESFR_FLAG(findex) ( \
 515   (findex) > 31 ? \
 516     (CPU (h_spr[H_SPR_ESFR0]) = \
 517       (CPU (h_spr[H_SPR_ESFR0]) | (1 << ((findex)-32))) \
 518     ) : \
 519     (CPU (h_spr[H_SPR_ESFR1]) = \
 520       (CPU (h_spr[H_SPR_ESFR1]) | (1 << (findex))) \
 521     ) \
 522 )
 523
 524 /* The FSR registers.
 525    Get and set the hardware directly, since we may be getting/setting fields
 526    which are not accessible to the user.  */
 527 #define GET_FSR(index) \
 528   (CPU (h_spr[H_SPR_FSR0 + (index)]))
 529 #define SET_FSR(index, fsr) \
 530   (CPU (h_spr[H_SPR_FSR0 + (index)]) = (fsr))
 531
 532 #define GET_FSR_TEM(fsr) ( \
 533   ((fsr) >> 24) & 0x3f     \
 534 )
 535
 536 #define SET_FSR_QNE(fsr) ((fsr) |= (1 << 20))
 537 #define GET_FSR_QNE(fsr) (((fsr) >> 20) & 1)
 538
 539 #define SET_FSR_FTT(fsr, ftt) (                          \
 540   (fsr) = ((fsr) & ~(0x7 << 17)) | (((ftt) & 0x7) << 17) \
 541 )
 542
 543 #define GET_FSR_AEXC(fsr) ( \
 544   ((fsr) >> 10) & 0x3f      \
 545 )
 546 #define SET_FSR_AEXC(fsr, aexc) (                          \
 547   (fsr) = ((fsr) & ~(0x3f << 10)) | (((aexc) & 0x3f) << 10) \
 548 )
 549
 550 /* SIMD instruction exception codes for FQ.  */
 551 enum frv_sie
 552 {
 553   SIE_NIL   = 0,
 554   SIE_FRi   = 1,
 555   SIE_FRi_1 = 2
 556 };
 557
 558 /* MIV field of FQ.  */
 559 enum frv_miv
 560 {
 561   MIV_FLOAT = 0,
 562   MIV_MEDIA = 1
 563 };
 564
 565 /* The FQ registers are 64 bits wide and are implemented as 32 bit pairs. The
 566    index here refers to the low order 32 bit element.
 567    Get and set the hardware directly, since we may be getting/setting fields
 568    which are not accessible to the user.  */
 569 #define GET_FQ(index) \
 570   (CPU (h_spr[H_SPR_FQST0 + 2 * (index)]))
 571 #define SET_FQ(index, fq) \
 572   (CPU (h_spr[H_SPR_FQST0 + 2 * (index)]) = (fq))
 573
 574 #define SET_FQ_MIV(fq, miv) (                          \
 575   (fq) = ((fq) & ~(0x1 << 31)) | (((miv) & 0x1) << 31) \
 576 )
 577
 578 #define SET_FQ_SIE(fq, sie) (                          \
 579   (fq) = ((fq) & ~(0x3 << 15)) | (((sie) & 0x3) << 15) \
 580 )
 581
 582 #define SET_FQ_FTT(fq, ftt) (                        \
 583   (fq) = ((fq) & ~(0x7 << 7)) | (((ftt) & 0x7) << 7) \
 584 )
 585
 586 #define SET_FQ_CEXC(fq, cexc) (                         \
 587   (fq) = ((fq) & ~(0x3f << 1)) | (((cexc) & 0x3f) << 1) \
 588 )
 589
 590 #define GET_FQ_VALID(fq) ((fq) & 1)
 591 #define SET_FQ_VALID(fq) ((fq) |= 1)
 592
 593 #define SET_FQ_OPC(index, insn) \
 594   (CPU (h_spr[H_SPR_FQOP0 + 2 * (index)]) = (insn))
 595
 596 /* mp_exception support.  */
 597 /* Media trap types for MSR.  */
 598 enum frv_msr_mtt
 599 {
 600   MTT_NONE                = 0,
 601   MTT_OVERFLOW            = 1,
 602   MTT_ACC_NOT_ALIGNED     = 2,
 603   MTT_ACC_NOT_IMPLEMENTED = 2, /* Yes -- same value as MTT_ACC_NOT_ALIGNED.  */
 604   MTT_CR_NOT_ALIGNED      = 3,
 605   MTT_UNIMPLEMENTED_MPOP  = 5,
 606   MTT_INVALID_FR          = 6
 607 };
 608
 609 /* Media status registers.
 610    Get and set the hardware directly, since we may be getting/setting fields
 611    which are not accessible to the user.  */
 612 #define GET_MSR(index) \
 613   (CPU (h_spr[H_SPR_MSR0 + (index)]))
 614 #define SET_MSR(index, msr) \
 615   (CPU (h_spr[H_SPR_MSR0 + (index)]) = (msr))
 616
 617 #define GET_MSR_AOVF(msr) ((msr) & 1)
 618 #define SET_MSR_AOVF(msr) ((msr) |=  1)
 619
 620 #define GET_MSR_OVF(msr) ( \
 621   ((msr) >> 1) & 0x1       \
 622 )
 623 #define SET_MSR_OVF(msr) ( \
 624   (msr) |= (1 << 1)        \
 625 )
 626 #define CLEAR_MSR_OVF(msr) ( \
 627   (msr) &= ~(1 << 1)         \
 628 )
 629
 630 #define OR_MSR_SIE(msr, sie) (  \
 631   (msr) |= (((sie) & 0xf) << 2) \
 632 )
 633 #define CLEAR_MSR_SIE(msr) ( \
 634   (msr) &= ~(0xf << 2)       \
 635 )
 636
 637 #define GET_MSR_MTT(msr) ( \
 638   ((msr) >> 12) & 0x7      \
 639 )
 640 #define SET_MSR_MTT(msr, mtt) (                          \
 641   (msr) = ((msr) & ~(0x7 << 12)) | (((mtt) & 0x7) << 12) \
 642 )
 643 #define GET_MSR_EMCI(msr) ( \
 644   ((msr) >> 24) & 0x1       \
 645 )
 646 #define GET_MSR_MPEM(msr) ( \
 647   ((msr) >> 27) & 0x1        \
 648 )
 649 #define GET_MSR_SRDAV(msr) ( \
 650   ((msr) >> 28) & 0x1        \
 651 )
 652 #define GET_MSR_RDAV(msr) ( \
 653   ((msr) >> 29) & 0x1       \
 654 )
 655 #define GET_MSR_RD(msr) ( \
 656   ((msr) >> 30) & 0x3     \
 657 )
 658
 659 void frvbf_media_register_not_aligned (SIM_CPU *);
 660 void frvbf_media_acc_not_aligned (SIM_CPU *);
 661 void frvbf_media_cr_not_aligned (SIM_CPU *);
 662 void frvbf_media_overflow (SIM_CPU *, int);
 663
 664 /* Functions for queuing and processing interrupts.  */
 665 struct frv_interrupt_queue_element *
 666 frv_queue_break_interrupt (SIM_CPU *);
 667
 668 struct frv_interrupt_queue_element *
 669 frv_queue_software_interrupt (SIM_CPU *, SI);
 670
 671 struct frv_interrupt_queue_element *
 672 frv_queue_program_interrupt (SIM_CPU *, enum frv_interrupt_kind);
 673
 674 struct frv_interrupt_queue_element *
 675 frv_queue_external_interrupt (SIM_CPU *, enum frv_interrupt_kind);
 676
 677 struct frv_interrupt_queue_element *
 678 frv_queue_illegal_instruction_interrupt (SIM_CPU *, const CGEN_INSN *);
 679
 680 struct frv_interrupt_queue_element *
 681 frv_queue_privileged_instruction_interrupt (SIM_CPU *, const CGEN_INSN *);
 682
 683 struct frv_interrupt_queue_element *
 684 frv_queue_float_disabled_interrupt (SIM_CPU *);
 685
 686 struct frv_interrupt_queue_element *
 687 frv_queue_media_disabled_interrupt (SIM_CPU *);
 688
 689 struct frv_interrupt_queue_element *
 690 frv_queue_non_implemented_instruction_interrupt (SIM_CPU *, const CGEN_INSN *);
 691
 692 struct frv_interrupt_queue_element *
 693 frv_queue_register_exception_interrupt (SIM_CPU *, enum frv_rec);
 694
 695 struct frv_interrupt_queue_element *
 696 frv_queue_mem_address_not_aligned_interrupt (SIM_CPU *, USI);
 697
 698 struct frv_interrupt_queue_element *
 699 frv_queue_data_access_error_interrupt (SIM_CPU *, USI);
 700
 701 struct frv_interrupt_queue_element *
 702 frv_queue_instruction_access_error_interrupt (SIM_CPU *);
 703
 704 struct frv_interrupt_queue_element *
 705 frv_queue_instruction_access_exception_interrupt (SIM_CPU *);
 706
 707 struct frv_interrupt_queue_element *
 708 frv_queue_fp_exception_interrupt (SIM_CPU *, struct frv_fp_exception_info *);
 709
 710 enum frv_dtt frvbf_division_exception (SIM_CPU *, enum frv_dtt, int, int);
 711
 712 struct frv_interrupt_queue_element *
 713 frv_queue_interrupt (SIM_CPU *, enum frv_interrupt_kind);
 714
 715 void
 716 frv_set_interrupt_queue_slot (SIM_CPU *, struct frv_interrupt_queue_element *);
 717
 718 void frv_set_mp_exception_registers (SIM_CPU *, enum frv_msr_mtt, int);
 719 void frv_detect_insn_access_interrupts (SIM_CPU *, SCACHE *);
 720
 721 void frv_process_interrupts (SIM_CPU *);
 722
 723 void frv_break_interrupt (SIM_CPU *, struct frv_interrupt *, IADDR);
 724 void frv_non_operating_interrupt (SIM_CPU *, enum frv_interrupt_kind, IADDR);
 725 void frv_program_interrupt (
 726   SIM_CPU *, struct frv_interrupt_queue_element *, IADDR
 727 );
 728 void frv_software_interrupt (
 729   SIM_CPU *, struct frv_interrupt_queue_element *, IADDR
 730 );
 731 void frv_external_interrupt (
 732   SIM_CPU *, struct frv_interrupt_queue_element *, IADDR
 733 );
 734 void frv_program_or_software_interrupt (
 735   SIM_CPU *, struct frv_interrupt *, IADDR
 736 );
 737 void frv_clear_interrupt_classes (
 738   enum frv_interrupt_class, enum frv_interrupt_class
 739 );
 740
 741 void
 742 frv_save_data_written_for_interrupts (SIM_CPU *, CGEN_WRITE_QUEUE_ELEMENT *);
 743
 744 /* Special purpose traps.  */
 745 #define TRAP_SYSCALL    0x80
 746 #define TRAP_BREAKPOINT 0x81
 747 #define TRAP_REGDUMP1   0x82
 748 #define TRAP_REGDUMP2   0x83
 749
 750 /* Handle the trap insns  */
 751 void frv_itrap (SIM_CPU *, PCADDR, USI, int);
 752 void frv_mtrap (SIM_CPU *);
 753 /* Handle the break insn.  */
 754 void frv_break (SIM_CPU *);
 755 /* Handle the rett insn.  */
 756 USI frv_rett (SIM_CPU *current_cpu, PCADDR pc, BI debug_field);
 757
 758 /* Parallel write queue flags.  */
 759 #define FRV_WRITE_QUEUE_FORCE_WRITE 1
 760
 761 #define CGEN_WRITE_QUEUE_ELEMENT_PIPE(element) CGEN_WRITE_QUEUE_ELEMENT_WORD1 (element)
 762
 763 /* Functions and macros for handling non-excepting instruction side effects.
 764    Get and set the hardware directly, since we may be getting/setting fields
 765    which are not accessible to the user.  */
 766 #define GET_NECR()           (GET_H_SPR (H_SPR_NECR))
 767 #define GET_NECR_ELOS(necr)  (((necr) >> 6) & 1)
 768 #define GET_NECR_NEN(necr)   (((necr) >> 1) & 0x1f)
 769 #define GET_NECR_VALID(necr) (((necr)     ) & 1)
 770
 771 #define NO_NESR    (-1)
 772 /* NESR field values. See Tables 30-33 in section 4.4.2.1 of the FRV
 773    Architecture volume 1.  */
 774 #define NESR_MEM_ADDRESS_NOT_ALIGNED 0x0b
 775 #define NESR_REGISTER_NOT_ALIGNED    0x1
 776 #define NESR_UQI_SIZE 0
 777 #define NESR_QI_SIZE  1
 778 #define NESR_UHI_SIZE 2
 779 #define NESR_HI_SIZE  3
 780 #define NESR_SI_SIZE  4
 781 #define NESR_DI_SIZE  5
 782 #define NESR_XI_SIZE  6
 783
 784 #define GET_NESR(index) GET_H_SPR (H_SPR_NESR0 + (index))
 785 #define SET_NESR(index, value) (                          \
 786   sim_queue_fn_si_write (current_cpu, frvbf_h_spr_set,    \
 787                          H_SPR_NESR0 + (index), (value)), \
 788   frvbf_force_update (current_cpu)                        \
 789 )
 790 #define GET_NESR_VALID(nesr) ((nesr) & 1)
 791 #define SET_NESR_VALID(nesr) ((nesr) |= 1)
 792
 793 #define SET_NESR_EAV(nesr)   ((nesr) |= (1 << 31))
 794
 795 #define GET_NESR_FR(nesr)    (((nesr) >> 30) & 1)
 796 #define SET_NESR_FR(nesr)    ((nesr) |= (1 << 30))
 797 #define CLEAR_NESR_FR(nesr)  ((nesr) &= ~(1 << 30))
 798
 799 #define GET_NESR_DRN(nesr)   (((nesr) >> 24) & 0x3f)
 800 #define SET_NESR_DRN(nesr, drn) (                            \
 801   (nesr) = ((nesr) & ~(0x3f << 24)) | (((drn) & 0x3f) << 24) \
 802 )
 803
 804 #define SET_NESR_SIZE(nesr, data_size) (                         \
 805   (nesr) = ((nesr) & ~(0x7 << 21)) | (((data_size) & 0x7) << 21) \
 806 )
 807
 808 #define SET_NESR_NEAN(nesr, index) (                           \
 809   (nesr) = ((nesr) & ~(0x1f << 10)) | (((index) & 0x1f) << 10) \
 810 )
 811
 812 #define GET_NESR_DAEC(nesr) (((nesr) >> 9) & 1)
 813 #define SET_NESR_DAEC(nesr, daec) (                   \
 814   (nesr) = ((nesr) & ~(1 << 9)) | (((daec) & 1) << 9) \
 815 )
 816
 817 #define GET_NESR_REC(nesr) (((nesr) >> 6) & 3)
 818 #define SET_NESR_REC(nesr, rec) (                    \
 819   (nesr) = ((nesr) & ~(3 << 6)) | (((rec) & 3) << 6) \
 820 )
 821
 822 #define GET_NESR_EC(nesr) (((nesr) >> 1) & 0x1f)
 823 #define SET_NESR_EC(nesr, ec) (                       \
 824   (nesr) = ((nesr) & ~(0x1f << 1)) | (((ec) & 0x1f) << 1) \
 825 )
 826
 827 #define SET_NEEAR(index, address) ( \
 828   sim_queue_fn_si_write (current_cpu, frvbf_h_spr_set,       \
 829                          H_SPR_NEEAR0 + (index), (address)), \
 830   frvbf_force_update (current_cpu)                           \
 831 )
 832
 833 #define GET_NE_FLAGS(flags, NE_base) (   \
 834   (flags)[0] = GET_H_SPR ((NE_base)),    \
 835   (flags)[1] = GET_H_SPR ((NE_base) + 1) \
 836 )
 837 #define SET_NE_FLAGS(NE_base, flags) ( \
 838   sim_queue_fn_si_write (current_cpu, frvbf_h_spr_set, (NE_base),      \
 839                          (flags)[0]),                                  \
 840   frvbf_force_update (current_cpu),                                    \
 841   sim_queue_fn_si_write (current_cpu, frvbf_h_spr_set, (NE_base) + 1,  \
 842                          (flags)[1]),                                  \
 843   frvbf_force_update (current_cpu)                                     \
 844 )
 845
 846 #define GET_NE_FLAG(flags, index) (    \
 847   (index) > 31 ?                       \
 848     ((flags[0] >> ((index) - 32)) & 1) \
 849   :                                    \
 850     ((flags[1] >> (index)) & 1)        \
 851 )
 852 #define SET_NE_FLAG(flags, index) (       \
 853   (index) > 31 ?                          \
 854     ((flags)[0] |= (1 << ((index) - 32))) \
 855   :                                       \
 856     ((flags)[1] |= (1 << (index)))        \
 857 )
 858 #define CLEAR_NE_FLAG(flags, index) (      \
 859   (index) > 31 ?                           \
 860     ((flags)[0] &= ~(1 << ((index) - 32))) \
 861   :                                        \
 862     ((flags)[1] &= ~(1 << (index)))        \
 863 )
 864
 865 BI   frvbf_check_non_excepting_load (SIM_CPU *, SI, SI, SI, SI, QI, BI);
 866 void frvbf_check_recovering_store (SIM_CPU *, PCADDR, SI, int, int);
 867
 868 void frvbf_clear_ne_flags (SIM_CPU *, SI, BI);
 869 void frvbf_commit (SIM_CPU *, SI, BI);
 870
 871 void frvbf_fpu_error (CGEN_FPU *, int);
 872
 873 void frv_vliw_setup_insn (SIM_CPU *, const CGEN_INSN *);
 874
 875 extern int insns_in_slot[];
 876
 877 #define COUNT_INSNS_IN_SLOT(slot) \
 878 {                                 \
 879   if (WITH_PROFILE_MODEL_P)       \
 880     ++insns_in_slot[slot];        \
 881 }
 882
 883 #define INSNS_IN_SLOT(slot) (insns_in_slot[slot])
 884
 885 /* Multiple loads and stores.  */
 886 void frvbf_load_multiple_GR (SIM_CPU *, PCADDR, SI, SI, int);
 887 void frvbf_load_multiple_FRint (SIM_CPU *, PCADDR, SI, SI, int);
 888 void frvbf_load_multiple_CPR (SIM_CPU *, PCADDR, SI, SI, int);
 889 void frvbf_store_multiple_GR (SIM_CPU *, PCADDR, SI, SI, int);
 890 void frvbf_store_multiple_FRint (SIM_CPU *, PCADDR, SI, SI, int);
 891 void frvbf_store_multiple_CPR (SIM_CPU *, PCADDR, SI, SI, int);
 892
 893 /* Memory and cache support.  */
 894 QI  frvbf_read_mem_QI  (SIM_CPU *, IADDR, SI);
 895 UQI frvbf_read_mem_UQI (SIM_CPU *, IADDR, SI);
 896 HI  frvbf_read_mem_HI  (SIM_CPU *, IADDR, SI);
 897 UHI frvbf_read_mem_UHI (SIM_CPU *, IADDR, SI);
 898 SI  frvbf_read_mem_SI  (SIM_CPU *, IADDR, SI);
 899 SI  frvbf_read_mem_WI  (SIM_CPU *, IADDR, SI);
 900 DI  frvbf_read_mem_DI  (SIM_CPU *, IADDR, SI);
 901 DF  frvbf_read_mem_DF  (SIM_CPU *, IADDR, SI);
 902
 903 USI frvbf_read_imem_USI (SIM_CPU *, PCADDR);
 904
 905 void frvbf_write_mem_QI  (SIM_CPU *, IADDR, SI, QI);
 906 void frvbf_write_mem_UQI (SIM_CPU *, IADDR, SI, UQI);
 907 void frvbf_write_mem_HI  (SIM_CPU *, IADDR, SI, HI);
 908 void frvbf_write_mem_UHI (SIM_CPU *, IADDR, SI, UHI);
 909 void frvbf_write_mem_SI  (SIM_CPU *, IADDR, SI, SI);
 910 void frvbf_write_mem_WI  (SIM_CPU *, IADDR, SI, SI);
 911 void frvbf_write_mem_DI  (SIM_CPU *, IADDR, SI, DI);
 912 void frvbf_write_mem_DF  (SIM_CPU *, IADDR, SI, DF);
 913
 914 void frvbf_mem_set_QI (SIM_CPU *, IADDR, SI, QI);
 915 void frvbf_mem_set_HI (SIM_CPU *, IADDR, SI, HI);
 916 void frvbf_mem_set_SI (SIM_CPU *, IADDR, SI, SI);
 917 void frvbf_mem_set_DI (SIM_CPU *, IADDR, SI, DI);
 918 void frvbf_mem_set_DF (SIM_CPU *, IADDR, SI, DF);
 919 void frvbf_mem_set_XI (SIM_CPU *, IADDR, SI, SI *);
 920
 921 void frv_set_write_queue_slot (SIM_CPU *current_cpu);
 922
 923 /* FRV specific options.  */
 924 extern const OPTION frv_options[];
 925
 926 #endif /* FRV_SIM_H */