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sim: h8300: delete opcode caching
[thirdparty/binutils-gdb.git] / sim / h8300 / compile.c
1 /*
2 * Simulator for the Renesas (formerly Hitachi) H8/300 architecture.
3 *
4 * Written by Steve Chamberlain of Cygnus Support. sac@cygnus.com
5 *
6 * This file is part of H8/300 sim
7 *
8 *
9 * THIS SOFTWARE IS NOT COPYRIGHTED
10 *
11 * Cygnus offers the following for use in the public domain. Cygnus makes no
12 * warranty with regard to the software or its performance and the user
13 * accepts the software "AS IS" with all faults.
14 *
15 * CYGNUS DISCLAIMS ANY WARRANTIES, EXPRESS OR IMPLIED, WITH REGARD TO THIS
16 * SOFTWARE INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
17 * AND FITNESS FOR A PARTICULAR PURPOSE.
18 */
19
20 #include "config.h"
21 #include <signal.h>
22 #ifdef HAVE_TIME_H
23 #include <time.h>
24 #endif
25 #ifdef HAVE_STDLIB_H
26 #include <stdlib.h>
27 #endif
28 #ifdef HAVE_SYS_PARAM_H
29 #include <sys/param.h>
30 #endif
31
32 #include "bfd.h"
33 #include "sim-main.h"
34 #include "gdb/sim-h8300.h"
35 #include "sys/stat.h"
36 #include "sys/types.h"
37 #include "sim-options.h"
38
39 #ifndef SIGTRAP
40 # define SIGTRAP 5
41 #endif
42
43 int debug;
44
45 #define X(op, size) (op * 4 + size)
46
47 #define SP (h8300hmode && !h8300_normal_mode ? SL : SW)
48
49 #define h8_opcodes ops
50 #define DEFINE_TABLE
51 #include "opcode/h8300.h"
52
53 /* CPU data object: */
54
55 static unsigned int
56 h8_get_pc (SIM_DESC sd)
57 {
58 return (STATE_CPU (sd, 0)) -> pc;
59 }
60
61 static void
62 h8_set_pc (SIM_DESC sd, unsigned int val)
63 {
64 (STATE_CPU (sd, 0)) -> pc = val;
65 }
66
67 static unsigned int
68 h8_get_ccr (SIM_DESC sd)
69 {
70 return (STATE_CPU (sd, 0)) -> regs[CCR_REGNUM];
71 }
72
73 static void
74 h8_set_ccr (SIM_DESC sd, unsigned int val)
75 {
76 (STATE_CPU (sd, 0)) -> regs[CCR_REGNUM] = val;
77 }
78
79 static unsigned int
80 h8_get_exr (SIM_DESC sd)
81 {
82 return (STATE_CPU (sd, 0)) -> regs[EXR_REGNUM];
83 }
84
85 static void
86 h8_set_exr (SIM_DESC sd, unsigned int val)
87 {
88 (STATE_CPU (sd, 0)) -> regs[EXR_REGNUM] = val;
89 }
90
91 static int
92 h8_get_sbr (SIM_DESC sd)
93 {
94 return (STATE_CPU (sd, 0)) -> regs[SBR_REGNUM];
95 }
96
97 static void
98 h8_set_sbr (SIM_DESC sd, int val)
99 {
100 (STATE_CPU (sd, 0)) -> regs[SBR_REGNUM] = val;
101 }
102
103 static int
104 h8_get_vbr (SIM_DESC sd)
105 {
106 return (STATE_CPU (sd, 0)) -> regs[VBR_REGNUM];
107 }
108
109 static void
110 h8_set_vbr (SIM_DESC sd, int val)
111 {
112 (STATE_CPU (sd, 0)) -> regs[VBR_REGNUM] = val;
113 }
114
115 static int
116 h8_get_mask (SIM_DESC sd)
117 {
118 return (STATE_CPU (sd, 0)) -> mask;
119 }
120
121 static void
122 h8_set_mask (SIM_DESC sd, int val)
123 {
124 (STATE_CPU (sd, 0)) -> mask = val;
125 }
126 #if 0
127 static int
128 h8_get_exception (SIM_DESC sd)
129 {
130 return (STATE_CPU (sd, 0)) -> exception;
131 }
132
133 static void
134 h8_set_exception (SIM_DESC sd, int val)
135 {
136 (STATE_CPU (sd, 0)) -> exception = val;
137 }
138
139 static enum h8300_sim_state
140 h8_get_state (SIM_DESC sd)
141 {
142 return sd -> state;
143 }
144
145 static void
146 h8_set_state (SIM_DESC sd, enum h8300_sim_state val)
147 {
148 sd -> state = val;
149 }
150 #endif
151 static unsigned int
152 h8_get_cycles (SIM_DESC sd)
153 {
154 return (STATE_CPU (sd, 0)) -> regs[CYCLE_REGNUM];
155 }
156
157 static void
158 h8_set_cycles (SIM_DESC sd, unsigned int val)
159 {
160 (STATE_CPU (sd, 0)) -> regs[CYCLE_REGNUM] = val;
161 }
162
163 static unsigned int
164 h8_get_insts (SIM_DESC sd)
165 {
166 return (STATE_CPU (sd, 0)) -> regs[INST_REGNUM];
167 }
168
169 static void
170 h8_set_insts (SIM_DESC sd, unsigned int val)
171 {
172 (STATE_CPU (sd, 0)) -> regs[INST_REGNUM] = val;
173 }
174
175 static unsigned int
176 h8_get_ticks (SIM_DESC sd)
177 {
178 return (STATE_CPU (sd, 0)) -> regs[TICK_REGNUM];
179 }
180
181 static void
182 h8_set_ticks (SIM_DESC sd, unsigned int val)
183 {
184 (STATE_CPU (sd, 0)) -> regs[TICK_REGNUM] = val;
185 }
186
187 static unsigned int
188 h8_get_mach (SIM_DESC sd)
189 {
190 return (STATE_CPU (sd, 0)) -> regs[MACH_REGNUM];
191 }
192
193 static void
194 h8_set_mach (SIM_DESC sd, unsigned int val)
195 {
196 (STATE_CPU (sd, 0)) -> regs[MACH_REGNUM] = val;
197 }
198
199 static unsigned int
200 h8_get_macl (SIM_DESC sd)
201 {
202 return (STATE_CPU (sd, 0)) -> regs[MACL_REGNUM];
203 }
204
205 static void
206 h8_set_macl (SIM_DESC sd, unsigned int val)
207 {
208 (STATE_CPU (sd, 0)) -> regs[MACL_REGNUM] = val;
209 }
210
211 static unsigned int *
212 h8_get_reg_buf (SIM_DESC sd)
213 {
214 return &(((STATE_CPU (sd, 0)) -> regs)[0]);
215 }
216
217 static unsigned int
218 h8_get_reg (SIM_DESC sd, int regnum)
219 {
220 return (STATE_CPU (sd, 0)) -> regs[regnum];
221 }
222
223 static void
224 h8_set_reg (SIM_DESC sd, int regnum, int val)
225 {
226 (STATE_CPU (sd, 0)) -> regs[regnum] = val;
227 }
228
229 #ifdef ADEBUG
230 static int
231 h8_get_stats (SIM_DESC sd, int idx)
232 {
233 return sd -> stats[idx];
234 }
235
236 static void
237 h8_increment_stats (SIM_DESC sd, int idx)
238 {
239 sd -> stats[idx] ++;
240 }
241 #endif /* ADEBUG */
242
243 static unsigned char *
244 h8_get_memory_buf (SIM_DESC sd)
245 {
246 return (STATE_CPU (sd, 0)) -> memory;
247 }
248
249 static void
250 h8_set_memory_buf (SIM_DESC sd, unsigned char *ptr)
251 {
252 (STATE_CPU (sd, 0)) -> memory = ptr;
253 }
254
255 static unsigned char
256 h8_get_memory (SIM_DESC sd, int idx)
257 {
258 return (STATE_CPU (sd, 0)) -> memory[idx];
259 }
260
261 static void
262 h8_set_memory (SIM_DESC sd, int idx, unsigned int val)
263 {
264 (STATE_CPU (sd, 0)) -> memory[idx] = (unsigned char) val;
265 }
266
267 static unsigned char *
268 h8_get_eightbit_buf (SIM_DESC sd)
269 {
270 return (STATE_CPU (sd, 0)) -> eightbit;
271 }
272
273 static void
274 h8_set_eightbit_buf (SIM_DESC sd, unsigned char *ptr)
275 {
276 (STATE_CPU (sd, 0)) -> eightbit = ptr;
277 }
278
279 static unsigned char
280 h8_get_eightbit (SIM_DESC sd, int idx)
281 {
282 return (STATE_CPU (sd, 0)) -> eightbit[idx];
283 }
284
285 static void
286 h8_set_eightbit (SIM_DESC sd, int idx, unsigned int val)
287 {
288 (STATE_CPU (sd, 0)) -> eightbit[idx] = (unsigned char) val;
289 }
290
291 static unsigned int
292 h8_get_delayed_branch (SIM_DESC sd)
293 {
294 return (STATE_CPU (sd, 0)) -> delayed_branch;
295 }
296
297 static void
298 h8_set_delayed_branch (SIM_DESC sd, unsigned int dest)
299 {
300 (STATE_CPU (sd, 0)) -> delayed_branch = dest;
301 }
302
303 static char **
304 h8_get_command_line (SIM_DESC sd)
305 {
306 return (STATE_CPU (sd, 0)) -> command_line;
307 }
308
309 static void
310 h8_set_command_line (SIM_DESC sd, char ** val)
311 {
312 (STATE_CPU (sd, 0)) -> command_line = val;
313 }
314
315 static char *
316 h8_get_cmdline_arg (SIM_DESC sd, int index)
317 {
318 return (STATE_CPU (sd, 0)) -> command_line[index];
319 }
320
321 static void
322 h8_set_cmdline_arg (SIM_DESC sd, int index, char * val)
323 {
324 (STATE_CPU (sd, 0)) -> command_line[index] = val;
325 }
326
327 /* MAC Saturation Mode */
328 static int
329 h8_get_macS (SIM_DESC sd)
330 {
331 return (STATE_CPU (sd, 0)) -> macS;
332 }
333
334 static void
335 h8_set_macS (SIM_DESC sd, int val)
336 {
337 (STATE_CPU (sd, 0)) -> macS = (val != 0);
338 }
339
340 /* MAC Zero Flag */
341 static int
342 h8_get_macZ (SIM_DESC sd)
343 {
344 return (STATE_CPU (sd, 0)) -> macZ;
345 }
346
347 static void
348 h8_set_macZ (SIM_DESC sd, int val)
349 {
350 (STATE_CPU (sd, 0)) -> macZ = (val != 0);
351 }
352
353 /* MAC Negative Flag */
354 static int
355 h8_get_macN (SIM_DESC sd)
356 {
357 return (STATE_CPU (sd, 0)) -> macN;
358 }
359
360 static void
361 h8_set_macN (SIM_DESC sd, int val)
362 {
363 (STATE_CPU (sd, 0)) -> macN = (val != 0);
364 }
365
366 /* MAC Overflow Flag */
367 static int
368 h8_get_macV (SIM_DESC sd)
369 {
370 return (STATE_CPU (sd, 0)) -> macV;
371 }
372
373 static void
374 h8_set_macV (SIM_DESC sd, int val)
375 {
376 (STATE_CPU (sd, 0)) -> macV = (val != 0);
377 }
378
379 /* End CPU data object. */
380
381 /* The rate at which to call the host's poll_quit callback. */
382
383 enum { POLL_QUIT_INTERVAL = 0x80000 };
384
385 #define LOW_BYTE(x) ((x) & 0xff)
386 #define HIGH_BYTE(x) (((x) >> 8) & 0xff)
387 #define P(X, Y) ((X << 8) | Y)
388
389 #define C (c != 0)
390 #define Z (nz == 0)
391 #define V (v != 0)
392 #define N (n != 0)
393 #define U (u != 0)
394 #define H (h != 0)
395 #define UI (ui != 0)
396 #define I (intMaskBit != 0)
397
398 #define BUILDSR(SD) \
399 h8_set_ccr (SD, (I << 7) | (UI << 6) | (H << 5) | (U << 4) \
400 | (N << 3) | (Z << 2) | (V << 1) | C)
401
402 #define GETSR(SD) \
403 /* Get Status Register (flags). */ \
404 c = (h8_get_ccr (sd) >> 0) & 1; \
405 v = (h8_get_ccr (sd) >> 1) & 1; \
406 nz = !((h8_get_ccr (sd) >> 2) & 1); \
407 n = (h8_get_ccr (sd) >> 3) & 1; \
408 u = (h8_get_ccr (sd) >> 4) & 1; \
409 h = (h8_get_ccr (sd) >> 5) & 1; \
410 ui = ((h8_get_ccr (sd) >> 6) & 1); \
411 intMaskBit = (h8_get_ccr (sd) >> 7) & 1
412
413
414 #ifdef __CHAR_IS_SIGNED__
415 #define SEXTCHAR(x) ((char) (x))
416 #endif
417
418 #ifndef SEXTCHAR
419 #define SEXTCHAR(x) ((x & 0x80) ? (x | ~0xff) : x & 0xff)
420 #endif
421
422 #define UEXTCHAR(x) ((x) & 0xff)
423 #define UEXTSHORT(x) ((x) & 0xffff)
424 #define SEXTSHORT(x) ((short) (x))
425
426 int h8300hmode = 0;
427 int h8300smode = 0;
428 int h8300_normal_mode = 0;
429 int h8300sxmode = 0;
430
431 static int memory_size;
432
433 static int
434 get_now (void)
435 {
436 return time (0); /* WinXX HAS UNIX like 'time', so why not use it? */
437 }
438
439 static int
440 now_persec (void)
441 {
442 return 1;
443 }
444
445 static int
446 bitfrom (int x)
447 {
448 switch (x & SIZE)
449 {
450 case L_8:
451 return SB;
452 case L_16:
453 case L_16U:
454 return SW;
455 case L_32:
456 return SL;
457 case L_P:
458 return (h8300hmode && !h8300_normal_mode)? SL : SW;
459 }
460 return 0;
461 }
462
463 /* Simulate an indirection / dereference.
464 return 0 for success, -1 for failure.
465 */
466
467 static unsigned int
468 lvalue (SIM_DESC sd, int x, int rn, unsigned int *val)
469 {
470 SIM_CPU *cpu = STATE_CPU (sd, 0);
471
472 if (val == NULL) /* Paranoia. */
473 return -1;
474
475 switch (x / 4)
476 {
477 case OP_DISP:
478 if (rn == ZERO_REGNUM)
479 *val = X (OP_IMM, SP);
480 else
481 *val = X (OP_REG, SP);
482 break;
483 case OP_MEM:
484 *val = X (OP_MEM, SP);
485 break;
486 default:
487 sim_engine_halt (sd, cpu, NULL, NULL_CIA, sim_stopped, SIM_SIGSEGV);
488 return -1;
489 }
490 return 0;
491 }
492
493 static int
494 cmdline_location()
495 {
496 if (h8300smode && !h8300_normal_mode)
497 return 0xffff00L;
498 else if (h8300hmode && !h8300_normal_mode)
499 return 0x2ff00L;
500 else
501 return 0xff00L;
502 }
503
504 static void
505 decode (SIM_DESC sd, int addr, unsigned char *data, decoded_inst *dst)
506 {
507 int cst[3] = {0, 0, 0};
508 int reg[3] = {0, 0, 0};
509 int rdisp[3] = {0, 0, 0};
510 int opnum;
511 const struct h8_opcode *q;
512
513 dst->dst.type = -1;
514 dst->src.type = -1;
515
516 /* Find the exact opcode/arg combo. */
517 for (q = h8_opcodes; q->name; q++)
518 {
519 const op_type *nib = q->data.nib;
520 unsigned int len = 0;
521
522 if ((q->available == AV_H8SX && !h8300sxmode) ||
523 (q->available == AV_H8S && !h8300smode) ||
524 (q->available == AV_H8H && !h8300hmode))
525 continue;
526
527 cst[0] = cst[1] = cst[2] = 0;
528 reg[0] = reg[1] = reg[2] = 0;
529 rdisp[0] = rdisp[1] = rdisp[2] = 0;
530
531 while (1)
532 {
533 op_type looking_for = *nib;
534 int thisnib = data[len / 2];
535
536 thisnib = (len & 1) ? (thisnib & 0xf) : ((thisnib >> 4) & 0xf);
537 opnum = ((looking_for & OP3) ? 2 :
538 (looking_for & DST) ? 1 : 0);
539
540 if (looking_for < 16 && looking_for >= 0)
541 {
542 if (looking_for != thisnib)
543 goto fail;
544 }
545 else
546 {
547 if (looking_for & B31)
548 {
549 if (!((thisnib & 0x8) != 0))
550 goto fail;
551
552 looking_for = (op_type) (looking_for & ~B31);
553 thisnib &= 0x7;
554 }
555 else if (looking_for & B30)
556 {
557 if (!((thisnib & 0x8) == 0))
558 goto fail;
559
560 looking_for = (op_type) (looking_for & ~B30);
561 }
562
563 if (looking_for & B21)
564 {
565 if (!((thisnib & 0x4) != 0))
566 goto fail;
567
568 looking_for = (op_type) (looking_for & ~B21);
569 thisnib &= 0xb;
570 }
571 else if (looking_for & B20)
572 {
573 if (!((thisnib & 0x4) == 0))
574 goto fail;
575
576 looking_for = (op_type) (looking_for & ~B20);
577 }
578
579 if (looking_for & B11)
580 {
581 if (!((thisnib & 0x2) != 0))
582 goto fail;
583
584 looking_for = (op_type) (looking_for & ~B11);
585 thisnib &= 0xd;
586 }
587 else if (looking_for & B10)
588 {
589 if (!((thisnib & 0x2) == 0))
590 goto fail;
591
592 looking_for = (op_type) (looking_for & ~B10);
593 }
594
595 if (looking_for & B01)
596 {
597 if (!((thisnib & 0x1) != 0))
598 goto fail;
599
600 looking_for = (op_type) (looking_for & ~B01);
601 thisnib &= 0xe;
602 }
603 else if (looking_for & B00)
604 {
605 if (!((thisnib & 0x1) == 0))
606 goto fail;
607
608 looking_for = (op_type) (looking_for & ~B00);
609 }
610
611 if (looking_for & IGNORE)
612 {
613 /* Hitachi has declared that IGNORE must be zero. */
614 if (thisnib != 0)
615 goto fail;
616 }
617 else if ((looking_for & MODE) == DATA)
618 {
619 ; /* Skip embedded data. */
620 }
621 else if ((looking_for & MODE) == DBIT)
622 {
623 /* Exclude adds/subs by looking at bit 0 and 2, and
624 make sure the operand size, either w or l,
625 matches by looking at bit 1. */
626 if ((looking_for & 7) != (thisnib & 7))
627 goto fail;
628
629 cst[opnum] = (thisnib & 0x8) ? 2 : 1;
630 }
631 else if ((looking_for & MODE) == REG ||
632 (looking_for & MODE) == LOWREG ||
633 (looking_for & MODE) == IND ||
634 (looking_for & MODE) == PREINC ||
635 (looking_for & MODE) == POSTINC ||
636 (looking_for & MODE) == PREDEC ||
637 (looking_for & MODE) == POSTDEC)
638 {
639 reg[opnum] = thisnib;
640 }
641 else if (looking_for & CTRL)
642 {
643 thisnib &= 7;
644 if (((looking_for & MODE) == CCR && (thisnib != C_CCR)) ||
645 ((looking_for & MODE) == EXR && (thisnib != C_EXR)) ||
646 ((looking_for & MODE) == MACH && (thisnib != C_MACH)) ||
647 ((looking_for & MODE) == MACL && (thisnib != C_MACL)) ||
648 ((looking_for & MODE) == VBR && (thisnib != C_VBR)) ||
649 ((looking_for & MODE) == SBR && (thisnib != C_SBR)))
650 goto fail;
651 if (((looking_for & MODE) == CCR_EXR &&
652 (thisnib != C_CCR && thisnib != C_EXR)) ||
653 ((looking_for & MODE) == VBR_SBR &&
654 (thisnib != C_VBR && thisnib != C_SBR)) ||
655 ((looking_for & MODE) == MACREG &&
656 (thisnib != C_MACH && thisnib != C_MACL)))
657 goto fail;
658 if (((looking_for & MODE) == CC_EX_VB_SB &&
659 (thisnib != C_CCR && thisnib != C_EXR &&
660 thisnib != C_VBR && thisnib != C_SBR)))
661 goto fail;
662
663 reg[opnum] = thisnib;
664 }
665 else if ((looking_for & MODE) == ABS)
666 {
667 /* Absolute addresses are unsigned. */
668 switch (looking_for & SIZE)
669 {
670 case L_8:
671 cst[opnum] = UEXTCHAR (data[len / 2]);
672 break;
673 case L_16:
674 case L_16U:
675 cst[opnum] = (data[len / 2] << 8) + data[len / 2 + 1];
676 break;
677 case L_32:
678 cst[opnum] =
679 (data[len / 2 + 0] << 24) +
680 (data[len / 2 + 1] << 16) +
681 (data[len / 2 + 2] << 8) +
682 (data[len / 2 + 3]);
683 break;
684 default:
685 printf ("decode: bad size ABS: %d\n",
686 (looking_for & SIZE));
687 goto end;
688 }
689 }
690 else if ((looking_for & MODE) == DISP ||
691 (looking_for & MODE) == PCREL ||
692 (looking_for & MODE) == INDEXB ||
693 (looking_for & MODE) == INDEXW ||
694 (looking_for & MODE) == INDEXL)
695 {
696 switch (looking_for & SIZE)
697 {
698 case L_2:
699 cst[opnum] = thisnib & 3;
700 break;
701 case L_8:
702 cst[opnum] = SEXTCHAR (data[len / 2]);
703 break;
704 case L_16:
705 cst[opnum] = (data[len / 2] << 8) + data[len / 2 + 1];
706 cst[opnum] = (short) cst[opnum]; /* Sign extend. */
707 break;
708 case L_16U:
709 cst[opnum] = (data[len / 2] << 8) + data[len / 2 + 1];
710 break;
711 case L_32:
712 cst[opnum] =
713 (data[len / 2 + 0] << 24) +
714 (data[len / 2 + 1] << 16) +
715 (data[len / 2 + 2] << 8) +
716 (data[len / 2 + 3]);
717 break;
718 default:
719 printf ("decode: bad size DISP/PCREL/INDEX: %d\n",
720 (looking_for & SIZE));
721 goto end;
722 }
723 }
724 else if ((looking_for & SIZE) == L_16 ||
725 (looking_for & SIZE) == L_16U)
726 {
727 cst[opnum] = (data[len / 2] << 8) + data[len / 2 + 1];
728 /* Immediates are always unsigned. */
729 if ((looking_for & SIZE) != L_16U &&
730 (looking_for & MODE) != IMM)
731 cst[opnum] = (short) cst[opnum]; /* Sign extend. */
732 }
733 else if (looking_for & ABSJMP)
734 {
735 switch (looking_for & SIZE) {
736 case L_24:
737 cst[opnum] = (data[1] << 16) | (data[2] << 8) | (data[3]);
738 break;
739 case L_32:
740 cst[opnum] =
741 (data[len / 2 + 0] << 24) +
742 (data[len / 2 + 1] << 16) +
743 (data[len / 2 + 2] << 8) +
744 (data[len / 2 + 3]);
745 break;
746 default:
747 printf ("decode: bad size ABSJMP: %d\n",
748 (looking_for & SIZE));
749 goto end;
750 }
751 }
752 else if ((looking_for & MODE) == MEMIND)
753 {
754 cst[opnum] = data[1];
755 }
756 else if ((looking_for & MODE) == VECIND)
757 {
758 if(h8300_normal_mode)
759 cst[opnum] = ((data[1] & 0x7f) + 0x80) * 2;
760 else
761 cst[opnum] = ((data[1] & 0x7f) + 0x80) * 4;
762 cst[opnum] += h8_get_vbr (sd); /* Add vector base reg. */
763 }
764 else if ((looking_for & SIZE) == L_32)
765 {
766 int i = len / 2;
767
768 cst[opnum] =
769 (data[i + 0] << 24) |
770 (data[i + 1] << 16) |
771 (data[i + 2] << 8) |
772 (data[i + 3]);
773 }
774 else if ((looking_for & SIZE) == L_24)
775 {
776 int i = len / 2;
777
778 cst[opnum] =
779 (data[i + 0] << 16) |
780 (data[i + 1] << 8) |
781 (data[i + 2]);
782 }
783 else if (looking_for & DISPREG)
784 {
785 rdisp[opnum] = thisnib & 0x7;
786 }
787 else if ((looking_for & MODE) == KBIT)
788 {
789 switch (thisnib)
790 {
791 case 9:
792 cst[opnum] = 4;
793 break;
794 case 8:
795 cst[opnum] = 2;
796 break;
797 case 0:
798 cst[opnum] = 1;
799 break;
800 default:
801 goto fail;
802 }
803 }
804 else if ((looking_for & SIZE) == L_8)
805 {
806 if ((looking_for & MODE) == ABS)
807 {
808 /* Will be combined with contents of SBR_REGNUM
809 by fetch (). For all modes except h8sx, this
810 will always contain the value 0xFFFFFF00. */
811 cst[opnum] = data[len / 2] & 0xff;
812 }
813 else
814 {
815 cst[opnum] = data[len / 2] & 0xff;
816 }
817 }
818 else if ((looking_for & SIZE) == L_2)
819 {
820 cst[opnum] = thisnib & 3;
821 }
822 else if ((looking_for & SIZE) == L_3 ||
823 (looking_for & SIZE) == L_3NZ)
824 {
825 cst[opnum] = thisnib & 7;
826 if (cst[opnum] == 0 && (looking_for & SIZE) == L_3NZ)
827 goto fail;
828 }
829 else if ((looking_for & SIZE) == L_4)
830 {
831 cst[opnum] = thisnib & 15;
832 }
833 else if ((looking_for & SIZE) == L_5)
834 {
835 cst[opnum] = data[len / 2] & 0x1f;
836 }
837 else if (looking_for == E)
838 {
839 #ifdef ADEBUG
840 dst->op = q;
841 #endif
842 /* Fill in the args. */
843 {
844 const op_type *args = q->args.nib;
845 int hadone = 0;
846 int nargs;
847
848 for (nargs = 0;
849 nargs < 3 && *args != E;
850 nargs++)
851 {
852 int x = *args;
853 ea_type *p;
854
855 opnum = ((x & OP3) ? 2 :
856 (x & DST) ? 1 : 0);
857 if (x & DST)
858 p = &dst->dst;
859 else if (x & OP3)
860 p = &dst->op3;
861 else
862 p = &dst->src;
863
864 if ((x & MODE) == IMM ||
865 (x & MODE) == KBIT ||
866 (x & MODE) == DBIT)
867 {
868 /* Use the instruction to determine
869 the operand size. */
870 p->type = X (OP_IMM, OP_SIZE (q->how));
871 p->literal = cst[opnum];
872 }
873 else if ((x & MODE) == CONST_2 ||
874 (x & MODE) == CONST_4 ||
875 (x & MODE) == CONST_8 ||
876 (x & MODE) == CONST_16)
877 {
878 /* Use the instruction to determine
879 the operand size. */
880 p->type = X (OP_IMM, OP_SIZE (q->how));
881 switch (x & MODE) {
882 case CONST_2: p->literal = 2; break;
883 case CONST_4: p->literal = 4; break;
884 case CONST_8: p->literal = 8; break;
885 case CONST_16: p->literal = 16; break;
886 }
887 }
888 else if ((x & MODE) == REG)
889 {
890 p->type = X (OP_REG, bitfrom (x));
891 p->reg = reg[opnum];
892 }
893 else if ((x & MODE) == LOWREG)
894 {
895 p->type = X (OP_LOWREG, bitfrom (x));
896 p->reg = reg[opnum];
897 }
898 else if ((x & MODE) == PREINC)
899 {
900 /* Use the instruction to determine
901 the operand size. */
902 p->type = X (OP_PREINC, OP_SIZE (q->how));
903 p->reg = reg[opnum] & 0x7;
904 }
905 else if ((x & MODE) == POSTINC)
906 {
907 /* Use the instruction to determine
908 the operand size. */
909 p->type = X (OP_POSTINC, OP_SIZE (q->how));
910 p->reg = reg[opnum] & 0x7;
911 }
912 else if ((x & MODE) == PREDEC)
913 {
914 /* Use the instruction to determine
915 the operand size. */
916 p->type = X (OP_PREDEC, OP_SIZE (q->how));
917 p->reg = reg[opnum] & 0x7;
918 }
919 else if ((x & MODE) == POSTDEC)
920 {
921 /* Use the instruction to determine
922 the operand size. */
923 p->type = X (OP_POSTDEC, OP_SIZE (q->how));
924 p->reg = reg[opnum] & 0x7;
925 }
926 else if ((x & MODE) == IND)
927 {
928 /* Note: an indirect is transformed into
929 a displacement of zero.
930 */
931 /* Use the instruction to determine
932 the operand size. */
933 p->type = X (OP_DISP, OP_SIZE (q->how));
934 p->reg = reg[opnum] & 0x7;
935 p->literal = 0;
936 if (OP_KIND (q->how) == O_JSR ||
937 OP_KIND (q->how) == O_JMP)
938 if (lvalue (sd, p->type, p->reg, (unsigned int *)&p->type))
939 goto end;
940 }
941 else if ((x & MODE) == ABS)
942 {
943 /* Note: a 16 or 32 bit ABS is transformed into a
944 displacement from pseudo-register ZERO_REGNUM,
945 which is always zero. An 8 bit ABS becomes
946 a displacement from SBR_REGNUM.
947 */
948 /* Use the instruction to determine
949 the operand size. */
950 p->type = X (OP_DISP, OP_SIZE (q->how));
951 p->literal = cst[opnum];
952
953 /* 8-bit ABS is displacement from SBR.
954 16 and 32-bit ABS are displacement from ZERO.
955 (SBR will always be zero except for h8/sx)
956 */
957 if ((x & SIZE) == L_8)
958 p->reg = SBR_REGNUM;
959 else
960 p->reg = ZERO_REGNUM;;
961 }
962 else if ((x & MODE) == MEMIND ||
963 (x & MODE) == VECIND)
964 {
965 /* Size doesn't matter. */
966 p->type = X (OP_MEM, SB);
967 p->literal = cst[opnum];
968 if (OP_KIND (q->how) == O_JSR ||
969 OP_KIND (q->how) == O_JMP)
970 if (lvalue (sd, p->type, p->reg, (unsigned int *)&p->type))
971 goto end;
972 }
973 else if ((x & MODE) == PCREL)
974 {
975 /* Size doesn't matter. */
976 p->type = X (OP_PCREL, SB);
977 p->literal = cst[opnum];
978 }
979 else if (x & ABSJMP)
980 {
981 p->type = X (OP_IMM, SP);
982 p->literal = cst[opnum];
983 }
984 else if ((x & MODE) == INDEXB)
985 {
986 p->type = X (OP_INDEXB, OP_SIZE (q->how));
987 p->literal = cst[opnum];
988 p->reg = rdisp[opnum];
989 }
990 else if ((x & MODE) == INDEXW)
991 {
992 p->type = X (OP_INDEXW, OP_SIZE (q->how));
993 p->literal = cst[opnum];
994 p->reg = rdisp[opnum];
995 }
996 else if ((x & MODE) == INDEXL)
997 {
998 p->type = X (OP_INDEXL, OP_SIZE (q->how));
999 p->literal = cst[opnum];
1000 p->reg = rdisp[opnum];
1001 }
1002 else if ((x & MODE) == DISP)
1003 {
1004 /* Yuck -- special for mova args. */
1005 if (strncmp (q->name, "mova", 4) == 0 &&
1006 (x & SIZE) == L_2)
1007 {
1008 /* Mova can have a DISP2 dest, with an
1009 INDEXB or INDEXW src. The multiplier
1010 for the displacement value is determined
1011 by the src operand, not by the insn. */
1012
1013 switch (OP_KIND (dst->src.type))
1014 {
1015 case OP_INDEXB:
1016 p->type = X (OP_DISP, SB);
1017 p->literal = cst[opnum];
1018 break;
1019 case OP_INDEXW:
1020 p->type = X (OP_DISP, SW);
1021 p->literal = cst[opnum] * 2;
1022 break;
1023 default:
1024 goto fail;
1025 }
1026 }
1027 else
1028 {
1029 p->type = X (OP_DISP, OP_SIZE (q->how));
1030 p->literal = cst[opnum];
1031 /* DISP2 is special. */
1032 if ((x & SIZE) == L_2)
1033 switch (OP_SIZE (q->how))
1034 {
1035 case SB: break;
1036 case SW: p->literal *= 2; break;
1037 case SL: p->literal *= 4; break;
1038 }
1039 }
1040 p->reg = rdisp[opnum];
1041 }
1042 else if (x & CTRL)
1043 {
1044 switch (reg[opnum])
1045 {
1046 case C_CCR:
1047 p->type = X (OP_CCR, SB);
1048 break;
1049 case C_EXR:
1050 p->type = X (OP_EXR, SB);
1051 break;
1052 case C_MACH:
1053 p->type = X (OP_MACH, SL);
1054 break;
1055 case C_MACL:
1056 p->type = X (OP_MACL, SL);
1057 break;
1058 case C_VBR:
1059 p->type = X (OP_VBR, SL);
1060 break;
1061 case C_SBR:
1062 p->type = X (OP_SBR, SL);
1063 break;
1064 }
1065 }
1066 else if ((x & MODE) == CCR)
1067 {
1068 p->type = OP_CCR;
1069 }
1070 else if ((x & MODE) == EXR)
1071 {
1072 p->type = OP_EXR;
1073 }
1074 else
1075 printf ("Hmmmm 0x%x...\n", x);
1076
1077 args++;
1078 }
1079 }
1080
1081 /* Unary operators: treat src and dst as equivalent. */
1082 if (dst->dst.type == -1)
1083 dst->dst = dst->src;
1084 if (dst->src.type == -1)
1085 dst->src = dst->dst;
1086
1087 dst->opcode = q->how;
1088 dst->cycles = q->time;
1089
1090 /* And jsr's to these locations are turned into
1091 magic traps. */
1092
1093 if (OP_KIND (dst->opcode) == O_JSR)
1094 {
1095 switch (dst->src.literal)
1096 {
1097 case 0xc5:
1098 dst->opcode = O (O_SYS_OPEN, SB);
1099 break;
1100 case 0xc6:
1101 dst->opcode = O (O_SYS_READ, SB);
1102 break;
1103 case 0xc7:
1104 dst->opcode = O (O_SYS_WRITE, SB);
1105 break;
1106 case 0xc8:
1107 dst->opcode = O (O_SYS_LSEEK, SB);
1108 break;
1109 case 0xc9:
1110 dst->opcode = O (O_SYS_CLOSE, SB);
1111 break;
1112 case 0xca:
1113 dst->opcode = O (O_SYS_STAT, SB);
1114 break;
1115 case 0xcb:
1116 dst->opcode = O (O_SYS_FSTAT, SB);
1117 break;
1118 case 0xcc:
1119 dst->opcode = O (O_SYS_CMDLINE, SB);
1120 break;
1121 }
1122 /* End of Processing for system calls. */
1123 }
1124
1125 dst->next_pc = addr + len / 2;
1126 return;
1127 }
1128 else
1129 printf ("Don't understand 0x%x \n", looking_for);
1130 }
1131
1132 len++;
1133 nib++;
1134 }
1135
1136 fail:
1137 ;
1138 }
1139 end:
1140 /* Fell off the end. */
1141 dst->opcode = O (O_ILL, SB);
1142 }
1143
1144 static unsigned char *breg[32];
1145 static unsigned short *wreg[16];
1146
1147 #define GET_B_REG(X) *(breg[X])
1148 #define SET_B_REG(X, Y) (*(breg[X])) = (Y)
1149 #define GET_W_REG(X) *(wreg[X])
1150 #define SET_W_REG(X, Y) (*(wreg[X])) = (Y)
1151 #define GET_L_REG(X) h8_get_reg (sd, X)
1152 #define SET_L_REG(X, Y) h8_set_reg (sd, X, Y)
1153
1154 #define GET_MEMORY_L(X) \
1155 ((X) < memory_size \
1156 ? ((h8_get_memory (sd, (X)+0) << 24) | (h8_get_memory (sd, (X)+1) << 16) \
1157 | (h8_get_memory (sd, (X)+2) << 8) | (h8_get_memory (sd, (X)+3) << 0)) \
1158 : ((h8_get_eightbit (sd, ((X)+0) & 0xff) << 24) \
1159 | (h8_get_eightbit (sd, ((X)+1) & 0xff) << 16) \
1160 | (h8_get_eightbit (sd, ((X)+2) & 0xff) << 8) \
1161 | (h8_get_eightbit (sd, ((X)+3) & 0xff) << 0)))
1162
1163 #define GET_MEMORY_W(X) \
1164 ((X) < memory_size \
1165 ? ((h8_get_memory (sd, (X)+0) << 8) \
1166 | (h8_get_memory (sd, (X)+1) << 0)) \
1167 : ((h8_get_eightbit (sd, ((X)+0) & 0xff) << 8) \
1168 | (h8_get_eightbit (sd, ((X)+1) & 0xff) << 0)))
1169
1170
1171 #define GET_MEMORY_B(X) \
1172 ((X) < memory_size ? (h8_get_memory (sd, (X))) \
1173 : (h8_get_eightbit (sd, (X) & 0xff)))
1174
1175 #define SET_MEMORY_L(X, Y) \
1176 { register unsigned char *_p; register int __y = (Y); \
1177 _p = ((X) < memory_size ? h8_get_memory_buf (sd) + (X) : \
1178 h8_get_eightbit_buf (sd) + ((X) & 0xff)); \
1179 _p[0] = __y >> 24; _p[1] = __y >> 16; \
1180 _p[2] = __y >> 8; _p[3] = __y >> 0; \
1181 }
1182
1183 #define SET_MEMORY_W(X, Y) \
1184 { register unsigned char *_p; register int __y = (Y); \
1185 _p = ((X) < memory_size ? h8_get_memory_buf (sd) + (X) : \
1186 h8_get_eightbit_buf (sd) + ((X) & 0xff)); \
1187 _p[0] = __y >> 8; _p[1] = __y; \
1188 }
1189
1190 #define SET_MEMORY_B(X, Y) \
1191 ((X) < memory_size ? (h8_set_memory (sd, (X), (Y))) \
1192 : (h8_set_eightbit (sd, (X) & 0xff, (Y))))
1193
1194 /* Simulate a memory fetch.
1195 Return 0 for success, -1 for failure.
1196 */
1197
1198 static int
1199 fetch_1 (SIM_DESC sd, ea_type *arg, int *val, int twice)
1200 {
1201 SIM_CPU *cpu = STATE_CPU (sd, 0);
1202 int rn = arg->reg;
1203 int abs = arg->literal;
1204 int r;
1205 int t;
1206
1207 if (val == NULL)
1208 return -1; /* Paranoia. */
1209
1210 switch (arg->type)
1211 {
1212 /* Indexed register plus displacement mode:
1213
1214 This new family of addressing modes are similar to OP_DISP
1215 (register plus displacement), with two differences:
1216 1) INDEXB uses only the least significant byte of the register,
1217 INDEXW uses only the least significant word, and
1218 INDEXL uses the entire register (just like OP_DISP).
1219 and
1220 2) The displacement value in abs is multiplied by two
1221 for SW-sized operations, and by four for SL-size.
1222
1223 This gives nine possible variations.
1224 */
1225
1226 case X (OP_INDEXB, SB):
1227 case X (OP_INDEXB, SW):
1228 case X (OP_INDEXB, SL):
1229 case X (OP_INDEXW, SB):
1230 case X (OP_INDEXW, SW):
1231 case X (OP_INDEXW, SL):
1232 case X (OP_INDEXL, SB):
1233 case X (OP_INDEXL, SW):
1234 case X (OP_INDEXL, SL):
1235 t = GET_L_REG (rn);
1236 switch (OP_KIND (arg->type)) {
1237 case OP_INDEXB: t &= 0xff; break;
1238 case OP_INDEXW: t &= 0xffff; break;
1239 case OP_INDEXL:
1240 default: break;
1241 }
1242 switch (OP_SIZE (arg->type)) {
1243 case SB:
1244 *val = GET_MEMORY_B ((t * 1 + abs) & h8_get_mask (sd));
1245 break;
1246 case SW:
1247 *val = GET_MEMORY_W ((t * 2 + abs) & h8_get_mask (sd));
1248 break;
1249 case SL:
1250 *val = GET_MEMORY_L ((t * 4 + abs) & h8_get_mask (sd));
1251 break;
1252 }
1253 break;
1254
1255 case X (OP_LOWREG, SB):
1256 *val = GET_L_REG (rn) & 0xff;
1257 break;
1258 case X (OP_LOWREG, SW):
1259 *val = GET_L_REG (rn) & 0xffff;
1260 break;
1261
1262 case X (OP_REG, SB): /* Register direct, byte. */
1263 *val = GET_B_REG (rn);
1264 break;
1265 case X (OP_REG, SW): /* Register direct, word. */
1266 *val = GET_W_REG (rn);
1267 break;
1268 case X (OP_REG, SL): /* Register direct, long. */
1269 *val = GET_L_REG (rn);
1270 break;
1271 case X (OP_IMM, SB): /* Immediate, byte. */
1272 case X (OP_IMM, SW): /* Immediate, word. */
1273 case X (OP_IMM, SL): /* Immediate, long. */
1274 *val = abs;
1275 break;
1276 case X (OP_POSTINC, SB): /* Register indirect w/post-incr: byte. */
1277 t = GET_L_REG (rn);
1278 r = GET_MEMORY_B (t & h8_get_mask (sd));
1279 if (!twice)
1280 t += 1;
1281 SET_L_REG (rn, t);
1282 *val = r;
1283 break;
1284 case X (OP_POSTINC, SW): /* Register indirect w/post-incr: word. */
1285 t = GET_L_REG (rn);
1286 r = GET_MEMORY_W (t & h8_get_mask (sd));
1287 if (!twice)
1288 t += 2;
1289 SET_L_REG (rn, t);
1290 *val = r;
1291 break;
1292 case X (OP_POSTINC, SL): /* Register indirect w/post-incr: long. */
1293 t = GET_L_REG (rn);
1294 r = GET_MEMORY_L (t & h8_get_mask (sd));
1295 if (!twice)
1296 t += 4;
1297 SET_L_REG (rn, t);
1298 *val = r;
1299 break;
1300
1301 case X (OP_POSTDEC, SB): /* Register indirect w/post-decr: byte. */
1302 t = GET_L_REG (rn);
1303 r = GET_MEMORY_B (t & h8_get_mask (sd));
1304 if (!twice)
1305 t -= 1;
1306 SET_L_REG (rn, t);
1307 *val = r;
1308 break;
1309 case X (OP_POSTDEC, SW): /* Register indirect w/post-decr: word. */
1310 t = GET_L_REG (rn);
1311 r = GET_MEMORY_W (t & h8_get_mask (sd));
1312 if (!twice)
1313 t -= 2;
1314 SET_L_REG (rn, t);
1315 *val = r;
1316 break;
1317 case X (OP_POSTDEC, SL): /* Register indirect w/post-decr: long. */
1318 t = GET_L_REG (rn);
1319 r = GET_MEMORY_L (t & h8_get_mask (sd));
1320 if (!twice)
1321 t -= 4;
1322 SET_L_REG (rn, t);
1323 *val = r;
1324 break;
1325
1326 case X (OP_PREDEC, SB): /* Register indirect w/pre-decr: byte. */
1327 t = GET_L_REG (rn) - 1;
1328 SET_L_REG (rn, t);
1329 t &= h8_get_mask (sd);
1330 *val = GET_MEMORY_B (t);
1331 break;
1332
1333 case X (OP_PREDEC, SW): /* Register indirect w/pre-decr: word. */
1334 t = GET_L_REG (rn) - 2;
1335 SET_L_REG (rn, t);
1336 t &= h8_get_mask (sd);
1337 *val = GET_MEMORY_W (t);
1338 break;
1339
1340 case X (OP_PREDEC, SL): /* Register indirect w/pre-decr: long. */
1341 t = GET_L_REG (rn) - 4;
1342 SET_L_REG (rn, t);
1343 t &= h8_get_mask (sd);
1344 *val = GET_MEMORY_L (t);
1345 break;
1346
1347 case X (OP_PREINC, SB): /* Register indirect w/pre-incr: byte. */
1348 t = GET_L_REG (rn) + 1;
1349 SET_L_REG (rn, t);
1350 t &= h8_get_mask (sd);
1351 *val = GET_MEMORY_B (t);
1352 break;
1353
1354 case X (OP_PREINC, SW): /* Register indirect w/pre-incr: long. */
1355 t = GET_L_REG (rn) + 2;
1356 SET_L_REG (rn, t);
1357 t &= h8_get_mask (sd);
1358 *val = GET_MEMORY_W (t);
1359 break;
1360
1361 case X (OP_PREINC, SL): /* Register indirect w/pre-incr: long. */
1362 t = GET_L_REG (rn) + 4;
1363 SET_L_REG (rn, t);
1364 t &= h8_get_mask (sd);
1365 *val = GET_MEMORY_L (t);
1366 break;
1367
1368 case X (OP_DISP, SB): /* Register indirect w/displacement: byte. */
1369 t = GET_L_REG (rn) + abs;
1370 t &= h8_get_mask (sd);
1371 *val = GET_MEMORY_B (t);
1372 break;
1373
1374 case X (OP_DISP, SW): /* Register indirect w/displacement: word. */
1375 t = GET_L_REG (rn) + abs;
1376 t &= h8_get_mask (sd);
1377 *val = GET_MEMORY_W (t);
1378 break;
1379
1380 case X (OP_DISP, SL): /* Register indirect w/displacement: long. */
1381 t = GET_L_REG (rn) + abs;
1382 t &= h8_get_mask (sd);
1383 *val =GET_MEMORY_L (t);
1384 break;
1385
1386 case X (OP_MEM, SL): /* Absolute memory address, long. */
1387 t = GET_MEMORY_L (abs);
1388 t &= h8_get_mask (sd);
1389 *val = t;
1390 break;
1391
1392 case X (OP_MEM, SW): /* Absolute memory address, word. */
1393 t = GET_MEMORY_W (abs);
1394 t &= h8_get_mask (sd);
1395 *val = t;
1396 break;
1397
1398 case X (OP_PCREL, SB): /* PC relative (for jump, branch etc). */
1399 case X (OP_PCREL, SW):
1400 case X (OP_PCREL, SL):
1401 case X (OP_PCREL, SN):
1402 *val = abs;
1403 break;
1404
1405 case X (OP_MEM, SB): /* Why isn't this implemented? */
1406 default:
1407 sim_engine_halt (sd, cpu, NULL, NULL_CIA, sim_stopped, SIM_SIGSEGV);
1408 return -1;
1409 }
1410 return 0; /* Success. */
1411 }
1412
1413 /* Normal fetch. */
1414
1415 static int
1416 fetch (SIM_DESC sd, ea_type *arg, int *val)
1417 {
1418 return fetch_1 (sd, arg, val, 0);
1419 }
1420
1421 /* Fetch which will be followed by a store to the same location.
1422 The difference being that we don't want to do a post-increment
1423 or post-decrement at this time: we'll do it when we store. */
1424
1425 static int
1426 fetch2 (SIM_DESC sd, ea_type *arg, int *val)
1427 {
1428 return fetch_1 (sd, arg, val, 1);
1429 }
1430
1431 /* Simulate a memory store.
1432 Return 0 for success, -1 for failure.
1433 */
1434
1435 static int
1436 store_1 (SIM_DESC sd, ea_type *arg, int n, int twice)
1437 {
1438 SIM_CPU *cpu = STATE_CPU (sd, 0);
1439 int rn = arg->reg;
1440 int abs = arg->literal;
1441 int t;
1442
1443 switch (arg->type)
1444 {
1445 /* Indexed register plus displacement mode:
1446
1447 This new family of addressing modes are similar to OP_DISP
1448 (register plus displacement), with two differences:
1449 1) INDEXB uses only the least significant byte of the register,
1450 INDEXW uses only the least significant word, and
1451 INDEXL uses the entire register (just like OP_DISP).
1452 and
1453 2) The displacement value in abs is multiplied by two
1454 for SW-sized operations, and by four for SL-size.
1455
1456 This gives nine possible variations.
1457 */
1458
1459 case X (OP_INDEXB, SB):
1460 case X (OP_INDEXB, SW):
1461 case X (OP_INDEXB, SL):
1462 case X (OP_INDEXW, SB):
1463 case X (OP_INDEXW, SW):
1464 case X (OP_INDEXW, SL):
1465 case X (OP_INDEXL, SB):
1466 case X (OP_INDEXL, SW):
1467 case X (OP_INDEXL, SL):
1468 t = GET_L_REG (rn);
1469 switch (OP_KIND (arg->type)) {
1470 case OP_INDEXB: t &= 0xff; break;
1471 case OP_INDEXW: t &= 0xffff; break;
1472 case OP_INDEXL:
1473 default: break;
1474 }
1475 switch (OP_SIZE (arg->type)) {
1476 case SB:
1477 SET_MEMORY_B ((t * 1 + abs) & h8_get_mask (sd), n);
1478 break;
1479 case SW:
1480 SET_MEMORY_W ((t * 2 + abs) & h8_get_mask (sd), n);
1481 break;
1482 case SL:
1483 SET_MEMORY_L ((t * 4 + abs) & h8_get_mask (sd), n);
1484 break;
1485 }
1486 break;
1487
1488 case X (OP_REG, SB): /* Register direct, byte. */
1489 SET_B_REG (rn, n);
1490 break;
1491 case X (OP_REG, SW): /* Register direct, word. */
1492 SET_W_REG (rn, n);
1493 break;
1494 case X (OP_REG, SL): /* Register direct, long. */
1495 SET_L_REG (rn, n);
1496 break;
1497
1498 case X (OP_PREDEC, SB): /* Register indirect w/pre-decr, byte. */
1499 t = GET_L_REG (rn);
1500 if (!twice)
1501 t -= 1;
1502 SET_L_REG (rn, t);
1503 t &= h8_get_mask (sd);
1504 SET_MEMORY_B (t, n);
1505
1506 break;
1507 case X (OP_PREDEC, SW): /* Register indirect w/pre-decr, word. */
1508 t = GET_L_REG (rn);
1509 if (!twice)
1510 t -= 2;
1511 SET_L_REG (rn, t);
1512 t &= h8_get_mask (sd);
1513 SET_MEMORY_W (t, n);
1514 break;
1515
1516 case X (OP_PREDEC, SL): /* Register indirect w/pre-decr, long. */
1517 t = GET_L_REG (rn);
1518 if (!twice)
1519 t -= 4;
1520 SET_L_REG (rn, t);
1521 t &= h8_get_mask (sd);
1522 SET_MEMORY_L (t, n);
1523 break;
1524
1525 case X (OP_PREINC, SB): /* Register indirect w/pre-incr, byte. */
1526 t = GET_L_REG (rn);
1527 if (!twice)
1528 t += 1;
1529 SET_L_REG (rn, t);
1530 t &= h8_get_mask (sd);
1531 SET_MEMORY_B (t, n);
1532
1533 break;
1534 case X (OP_PREINC, SW): /* Register indirect w/pre-incr, word. */
1535 t = GET_L_REG (rn);
1536 if (!twice)
1537 t += 2;
1538 SET_L_REG (rn, t);
1539 t &= h8_get_mask (sd);
1540 SET_MEMORY_W (t, n);
1541 break;
1542
1543 case X (OP_PREINC, SL): /* Register indirect w/pre-incr, long. */
1544 t = GET_L_REG (rn);
1545 if (!twice)
1546 t += 4;
1547 SET_L_REG (rn, t);
1548 t &= h8_get_mask (sd);
1549 SET_MEMORY_L (t, n);
1550 break;
1551
1552 case X (OP_POSTDEC, SB): /* Register indirect w/post-decr, byte. */
1553 t = GET_L_REG (rn);
1554 SET_L_REG (rn, t - 1);
1555 t &= h8_get_mask (sd);
1556 SET_MEMORY_B (t, n);
1557 break;
1558
1559 case X (OP_POSTDEC, SW): /* Register indirect w/post-decr, word. */
1560 t = GET_L_REG (rn);
1561 SET_L_REG (rn, t - 2);
1562 t &= h8_get_mask (sd);
1563 SET_MEMORY_W (t, n);
1564 break;
1565
1566 case X (OP_POSTDEC, SL): /* Register indirect w/post-decr, long. */
1567 t = GET_L_REG (rn);
1568 SET_L_REG (rn, t - 4);
1569 t &= h8_get_mask (sd);
1570 SET_MEMORY_L (t, n);
1571 break;
1572
1573 case X (OP_POSTINC, SB): /* Register indirect w/post-incr, byte. */
1574 t = GET_L_REG (rn);
1575 SET_L_REG (rn, t + 1);
1576 t &= h8_get_mask (sd);
1577 SET_MEMORY_B (t, n);
1578 break;
1579
1580 case X (OP_POSTINC, SW): /* Register indirect w/post-incr, word. */
1581 t = GET_L_REG (rn);
1582 SET_L_REG (rn, t + 2);
1583 t &= h8_get_mask (sd);
1584 SET_MEMORY_W (t, n);
1585 break;
1586
1587 case X (OP_POSTINC, SL): /* Register indirect w/post-incr, long. */
1588 t = GET_L_REG (rn);
1589 SET_L_REG (rn, t + 4);
1590 t &= h8_get_mask (sd);
1591 SET_MEMORY_L (t, n);
1592 break;
1593
1594 case X (OP_DISP, SB): /* Register indirect w/displacement, byte. */
1595 t = GET_L_REG (rn) + abs;
1596 t &= h8_get_mask (sd);
1597 SET_MEMORY_B (t, n);
1598 break;
1599
1600 case X (OP_DISP, SW): /* Register indirect w/displacement, word. */
1601 t = GET_L_REG (rn) + abs;
1602 t &= h8_get_mask (sd);
1603 SET_MEMORY_W (t, n);
1604 break;
1605
1606 case X (OP_DISP, SL): /* Register indirect w/displacement, long. */
1607 t = GET_L_REG (rn) + abs;
1608 t &= h8_get_mask (sd);
1609 SET_MEMORY_L (t, n);
1610 break;
1611
1612
1613 case X (OP_MEM, SB): /* Why isn't this implemented? */
1614 case X (OP_MEM, SW): /* Why isn't this implemented? */
1615 case X (OP_MEM, SL): /* Why isn't this implemented? */
1616 default:
1617 sim_engine_halt (sd, cpu, NULL, NULL_CIA, sim_stopped, SIM_SIGSEGV);
1618 return -1;
1619 }
1620 return 0;
1621 }
1622
1623 /* Normal store. */
1624
1625 static int
1626 store (SIM_DESC sd, ea_type *arg, int n)
1627 {
1628 return store_1 (sd, arg, n, 0);
1629 }
1630
1631 /* Store which follows a fetch from the same location.
1632 The difference being that we don't want to do a pre-increment
1633 or pre-decrement at this time: it was already done when we fetched. */
1634
1635 static int
1636 store2 (SIM_DESC sd, ea_type *arg, int n)
1637 {
1638 return store_1 (sd, arg, n, 1);
1639 }
1640
1641 /* Flag to be set whenever a new SIM_DESC object is created. */
1642 static int init_pointers_needed = 1;
1643
1644 static void
1645 init_pointers (SIM_DESC sd)
1646 {
1647 if (init_pointers_needed)
1648 {
1649 int i;
1650
1651 if (h8300smode && !h8300_normal_mode)
1652 memory_size = H8300S_MSIZE;
1653 else if (h8300hmode && !h8300_normal_mode)
1654 memory_size = H8300H_MSIZE;
1655 else
1656 memory_size = H8300_MSIZE;
1657 /* `msize' must be a power of two. */
1658 if ((memory_size & (memory_size - 1)) != 0)
1659 {
1660 sim_io_printf
1661 (sd,
1662 "init_pointers: bad memory size %d, defaulting to %d.\n",
1663 memory_size, memory_size = H8300S_MSIZE);
1664 }
1665
1666 if (h8_get_memory_buf (sd))
1667 free (h8_get_memory_buf (sd));
1668 if (h8_get_eightbit_buf (sd))
1669 free (h8_get_eightbit_buf (sd));
1670
1671 h8_set_memory_buf (sd, (unsigned char *)
1672 calloc (sizeof (char), memory_size));
1673 sd->memory_size = memory_size;
1674 h8_set_eightbit_buf (sd, (unsigned char *) calloc (sizeof (char), 256));
1675
1676 h8_set_mask (sd, memory_size - 1);
1677
1678 memset (h8_get_reg_buf (sd), 0, sizeof (((STATE_CPU (sd, 0))->regs)));
1679
1680 for (i = 0; i < 8; i++)
1681 {
1682 /* FIXME: rewrite using local buffer. */
1683 unsigned char *p = (unsigned char *) (h8_get_reg_buf (sd) + i);
1684 unsigned char *e = (unsigned char *) (h8_get_reg_buf (sd) + i + 1);
1685 unsigned short *q = (unsigned short *) (h8_get_reg_buf (sd) + i);
1686 unsigned short *u = (unsigned short *) (h8_get_reg_buf (sd) + i + 1);
1687 h8_set_reg (sd, i, 0x00112233);
1688
1689 while (p < e)
1690 {
1691 if (*p == 0x22)
1692 breg[i] = p;
1693 if (*p == 0x33)
1694 breg[i + 8] = p;
1695 if (*p == 0x11)
1696 breg[i + 16] = p;
1697 if (*p == 0x00)
1698 breg[i + 24] = p;
1699 p++;
1700 }
1701
1702 wreg[i] = wreg[i + 8] = 0;
1703 while (q < u)
1704 {
1705 if (*q == 0x2233)
1706 {
1707 wreg[i] = q;
1708 }
1709 if (*q == 0x0011)
1710 {
1711 wreg[i + 8] = q;
1712 }
1713 q++;
1714 }
1715
1716 if (wreg[i] == 0 || wreg[i + 8] == 0)
1717 sim_io_printf (sd, "init_pointers: internal error.\n");
1718
1719 h8_set_reg (sd, i, 0);
1720 }
1721
1722 init_pointers_needed = 0;
1723 }
1724 }
1725
1726 #define OBITOP(name, f, s, op) \
1727 case O (name, SB): \
1728 { \
1729 int m, tmp; \
1730 \
1731 if (f) \
1732 if (fetch (sd, &code->dst, &ea)) \
1733 goto end; \
1734 if (fetch (sd, &code->src, &tmp)) \
1735 goto end; \
1736 m = 1 << (tmp & 7); \
1737 op; \
1738 if (s) \
1739 if (store (sd, &code->dst,ea)) \
1740 goto end; \
1741 goto next; \
1742 }
1743
1744 static void
1745 step_once (SIM_DESC sd, SIM_CPU *cpu)
1746 {
1747 int cycles = 0;
1748 int insts = 0;
1749 int tick_start = get_now ();
1750 int res;
1751 int tmp;
1752 int rd;
1753 int ea;
1754 int bit;
1755 int pc;
1756 int c, nz, v, n, u, h, ui, intMaskBit;
1757 int trace, intMask;
1758 int oldmask;
1759 host_callback *sim_callback = STATE_CALLBACK (sd);
1760
1761 init_pointers (sd);
1762
1763 pc = h8_get_pc (sd);
1764
1765 /* The PC should never be odd. */
1766 if (pc & 0x1)
1767 {
1768 sim_engine_halt (sd, cpu, NULL, NULL_CIA, sim_stopped, SIM_SIGBUS);
1769 return;
1770 }
1771
1772 /* Get Status Register (flags). */
1773 GETSR (sd);
1774
1775 if (h8300smode) /* Get exr. */
1776 {
1777 trace = (h8_get_exr (sd) >> 7) & 1;
1778 intMask = h8_get_exr (sd) & 7;
1779 }
1780
1781 oldmask = h8_get_mask (sd);
1782 if (!h8300hmode || h8300_normal_mode)
1783 h8_set_mask (sd, 0xffff);
1784 do
1785 {
1786 decoded_inst _code, *code = &_code;
1787 memset (code, 0, sizeof (*code));
1788 decode (sd, pc, h8_get_memory_buf (sd) + pc, code);
1789 code->oldpc = pc;
1790
1791 #if ADEBUG
1792 if (debug)
1793 {
1794 printf ("%x %d %s\n", pc, code->opcode,
1795 code->op ? code->op->name : "**");
1796 }
1797 h8_increment_stats (sd, code->opcode);
1798 #endif
1799
1800 if (code->opcode)
1801 {
1802 cycles += code->cycles;
1803 insts++;
1804 }
1805
1806 switch (code->opcode)
1807 {
1808 case O (O_MOVAB, SL):
1809 case O (O_MOVAW, SL):
1810 case O (O_MOVAL, SL):
1811 /* 1) Evaluate 2nd argument (dst).
1812 2) Mask / zero extend according to whether 1st argument (src)
1813 is INDEXB, INDEXW, or INDEXL.
1814 3) Left-shift the result by 0, 1 or 2, according to size of mova
1815 (mova/b, mova/w, mova/l).
1816 4) Add literal value of 1st argument (src).
1817 5) Store result in 3rd argument (op3).
1818 */
1819
1820 /* Alas, since this is the only instruction with 3 arguments,
1821 decode doesn't handle them very well. Some fix-up is required.
1822
1823 a) The size of dst is determined by whether src is
1824 INDEXB or INDEXW. */
1825
1826 if (OP_KIND (code->src.type) == OP_INDEXB)
1827 code->dst.type = X (OP_KIND (code->dst.type), SB);
1828 else if (OP_KIND (code->src.type) == OP_INDEXW)
1829 code->dst.type = X (OP_KIND (code->dst.type), SW);
1830
1831 /* b) If op3 == null, then this is the short form of the insn.
1832 Dst is the dispreg of src, and op3 is the 32-bit form
1833 of the same register.
1834 */
1835
1836 if (code->op3.type == 0)
1837 {
1838 /* Short form: src == INDEXB/INDEXW, dst == op3 == 0.
1839 We get to compose dst and op3 as follows:
1840
1841 op3 is a 32-bit register, ID == src.reg.
1842 dst is the same register, but 8 or 16 bits
1843 depending on whether src is INDEXB or INDEXW.
1844 */
1845
1846 code->op3.type = X (OP_REG, SL);
1847 code->op3.reg = code->src.reg;
1848 code->op3.literal = 0;
1849
1850 if (OP_KIND (code->src.type) == OP_INDEXB)
1851 {
1852 code->dst.type = X (OP_REG, SB);
1853 code->dst.reg = code->op3.reg + 8;
1854 }
1855 else
1856 code->dst.type = X (OP_REG, SW);
1857 }
1858
1859 if (fetch (sd, &code->dst, &ea))
1860 goto end;
1861
1862 switch (OP_KIND (code->src.type)) {
1863 case OP_INDEXB: ea = ea & 0xff; break;
1864 case OP_INDEXW: ea = ea & 0xffff; break;
1865 case OP_INDEXL: break;
1866 default: goto illegal;
1867 }
1868
1869 switch (code->opcode) {
1870 case O (O_MOVAB, SL): break;
1871 case O (O_MOVAW, SL): ea = ea << 1; break;
1872 case O (O_MOVAL, SL): ea = ea << 2; break;
1873 default: goto illegal;
1874 }
1875
1876 ea = ea + code->src.literal;
1877
1878 if (store (sd, &code->op3, ea))
1879 goto end;
1880
1881 goto next;
1882
1883 case O (O_SUBX, SB): /* subx, extended sub */
1884 if (fetch2 (sd, &code->dst, &rd))
1885 goto end;
1886 if (fetch (sd, &code->src, &ea))
1887 goto end;
1888 ea = -(ea + C);
1889 res = rd + ea;
1890 goto alu8;
1891
1892 case O (O_SUBX, SW): /* subx, extended sub */
1893 if (fetch2 (sd, &code->dst, &rd))
1894 goto end;
1895 if (fetch (sd, &code->src, &ea))
1896 goto end;
1897 ea = -(ea + C);
1898 res = rd + ea;
1899 goto alu16;
1900
1901 case O (O_SUBX, SL): /* subx, extended sub */
1902 if (fetch2 (sd, &code->dst, &rd))
1903 goto end;
1904 if (fetch (sd, &code->src, &ea))
1905 goto end;
1906 ea = -(ea + C);
1907 res = rd + ea;
1908 goto alu32;
1909
1910 case O (O_ADDX, SB): /* addx, extended add */
1911 if (fetch2 (sd, &code->dst, &rd))
1912 goto end;
1913 if (fetch (sd, &code->src, &ea))
1914 goto end;
1915 ea = ea + C;
1916 res = rd + ea;
1917 goto alu8;
1918
1919 case O (O_ADDX, SW): /* addx, extended add */
1920 if (fetch2 (sd, &code->dst, &rd))
1921 goto end;
1922 if (fetch (sd, &code->src, &ea))
1923 goto end;
1924 ea = ea + C;
1925 res = rd + ea;
1926 goto alu16;
1927
1928 case O (O_ADDX, SL): /* addx, extended add */
1929 if (fetch2 (sd, &code->dst, &rd))
1930 goto end;
1931 if (fetch (sd, &code->src, &ea))
1932 goto end;
1933 ea = ea + C;
1934 res = rd + ea;
1935 goto alu32;
1936
1937 case O (O_SUB, SB): /* sub.b */
1938 /* Fetch rd and ea. */
1939 if (fetch (sd, &code->src, &ea) || fetch2 (sd, &code->dst, &rd))
1940 goto end;
1941 ea = -ea;
1942 res = rd + ea;
1943 goto alu8;
1944
1945 case O (O_SUB, SW): /* sub.w */
1946 /* Fetch rd and ea. */
1947 if (fetch (sd, &code->src, &ea) || fetch2 (sd, &code->dst, &rd))
1948 goto end;
1949 ea = -ea;
1950 res = rd + ea;
1951 goto alu16;
1952
1953 case O (O_SUB, SL): /* sub.l */
1954 /* Fetch rd and ea. */
1955 if (fetch (sd, &code->src, &ea) || fetch2 (sd, &code->dst, &rd))
1956 goto end;
1957 ea = -ea;
1958 res = rd + ea;
1959 goto alu32;
1960
1961 case O (O_NEG, SB): /* neg.b */
1962 /* Fetch ea. */
1963 if (fetch2 (sd, &code->src, &ea))
1964 goto end;
1965 ea = -ea;
1966 rd = 0;
1967 res = rd + ea;
1968 goto alu8;
1969
1970 case O (O_NEG, SW): /* neg.w */
1971 /* Fetch ea. */
1972 if (fetch2 (sd, &code->src, &ea))
1973 goto end;
1974 ea = -ea;
1975 rd = 0;
1976 res = rd + ea;
1977 goto alu16;
1978
1979 case O (O_NEG, SL): /* neg.l */
1980 /* Fetch ea. */
1981 if (fetch2 (sd, &code->src, &ea))
1982 goto end;
1983 ea = -ea;
1984 rd = 0;
1985 res = rd + ea;
1986 goto alu32;
1987
1988 case O (O_ADD, SB): /* add.b */
1989 if (fetch2 (sd, &code->dst, &rd))
1990 goto end;
1991 if (fetch (sd, &code->src, &ea))
1992 goto end;
1993 res = rd + ea;
1994 goto alu8;
1995
1996 case O (O_ADD, SW): /* add.w */
1997 if (fetch2 (sd, &code->dst, &rd))
1998 goto end;
1999 if (fetch (sd, &code->src, &ea))
2000 goto end;
2001 res = rd + ea;
2002 goto alu16;
2003
2004 case O (O_ADD, SL): /* add.l */
2005 if (fetch2 (sd, &code->dst, &rd))
2006 goto end;
2007 if (fetch (sd, &code->src, &ea))
2008 goto end;
2009 res = rd + ea;
2010 goto alu32;
2011
2012 case O (O_AND, SB): /* and.b */
2013 /* Fetch rd and ea. */
2014 if (fetch (sd, &code->src, &ea) || fetch2 (sd, &code->dst, &rd))
2015 goto end;
2016 res = rd & ea;
2017 goto log8;
2018
2019 case O (O_AND, SW): /* and.w */
2020 /* Fetch rd and ea. */
2021 if (fetch (sd, &code->src, &ea) || fetch2 (sd, &code->dst, &rd))
2022 goto end;
2023 res = rd & ea;
2024 goto log16;
2025
2026 case O (O_AND, SL): /* and.l */
2027 /* Fetch rd and ea. */
2028 if (fetch (sd, &code->src, &ea) || fetch2 (sd, &code->dst, &rd))
2029 goto end;
2030 res = rd & ea;
2031 goto log32;
2032
2033 case O (O_OR, SB): /* or.b */
2034 /* Fetch rd and ea. */
2035 if (fetch (sd, &code->src, &ea) || fetch2 (sd, &code->dst, &rd))
2036 goto end;
2037 res = rd | ea;
2038 goto log8;
2039
2040 case O (O_OR, SW): /* or.w */
2041 /* Fetch rd and ea. */
2042 if (fetch (sd, &code->src, &ea) || fetch2 (sd, &code->dst, &rd))
2043 goto end;
2044 res = rd | ea;
2045 goto log16;
2046
2047 case O (O_OR, SL): /* or.l */
2048 /* Fetch rd and ea. */
2049 if (fetch (sd, &code->src, &ea) || fetch2 (sd, &code->dst, &rd))
2050 goto end;
2051 res = rd | ea;
2052 goto log32;
2053
2054 case O (O_XOR, SB): /* xor.b */
2055 /* Fetch rd and ea. */
2056 if (fetch (sd, &code->src, &ea) || fetch2 (sd, &code->dst, &rd))
2057 goto end;
2058 res = rd ^ ea;
2059 goto log8;
2060
2061 case O (O_XOR, SW): /* xor.w */
2062 /* Fetch rd and ea. */
2063 if (fetch (sd, &code->src, &ea) || fetch2 (sd, &code->dst, &rd))
2064 goto end;
2065 res = rd ^ ea;
2066 goto log16;
2067
2068 case O (O_XOR, SL): /* xor.l */
2069 /* Fetch rd and ea. */
2070 if (fetch (sd, &code->src, &ea) || fetch2 (sd, &code->dst, &rd))
2071 goto end;
2072 res = rd ^ ea;
2073 goto log32;
2074
2075 case O (O_MOV, SB):
2076 if (fetch (sd, &code->src, &res))
2077 goto end;
2078 if (store (sd, &code->dst, res))
2079 goto end;
2080 goto just_flags_log8;
2081 case O (O_MOV, SW):
2082 if (fetch (sd, &code->src, &res))
2083 goto end;
2084 if (store (sd, &code->dst, res))
2085 goto end;
2086 goto just_flags_log16;
2087 case O (O_MOV, SL):
2088 if (fetch (sd, &code->src, &res))
2089 goto end;
2090 if (store (sd, &code->dst, res))
2091 goto end;
2092 goto just_flags_log32;
2093
2094 case O (O_MOVMD, SB): /* movmd.b */
2095 ea = GET_W_REG (4);
2096 if (ea == 0)
2097 ea = 0x10000;
2098
2099 while (ea--)
2100 {
2101 rd = GET_MEMORY_B (GET_L_REG (5));
2102 SET_MEMORY_B (GET_L_REG (6), rd);
2103 SET_L_REG (5, GET_L_REG (5) + 1);
2104 SET_L_REG (6, GET_L_REG (6) + 1);
2105 SET_W_REG (4, ea);
2106 }
2107 goto next;
2108
2109 case O (O_MOVMD, SW): /* movmd.w */
2110 ea = GET_W_REG (4);
2111 if (ea == 0)
2112 ea = 0x10000;
2113
2114 while (ea--)
2115 {
2116 rd = GET_MEMORY_W (GET_L_REG (5));
2117 SET_MEMORY_W (GET_L_REG (6), rd);
2118 SET_L_REG (5, GET_L_REG (5) + 2);
2119 SET_L_REG (6, GET_L_REG (6) + 2);
2120 SET_W_REG (4, ea);
2121 }
2122 goto next;
2123
2124 case O (O_MOVMD, SL): /* movmd.l */
2125 ea = GET_W_REG (4);
2126 if (ea == 0)
2127 ea = 0x10000;
2128
2129 while (ea--)
2130 {
2131 rd = GET_MEMORY_L (GET_L_REG (5));
2132 SET_MEMORY_L (GET_L_REG (6), rd);
2133 SET_L_REG (5, GET_L_REG (5) + 4);
2134 SET_L_REG (6, GET_L_REG (6) + 4);
2135 SET_W_REG (4, ea);
2136 }
2137 goto next;
2138
2139 case O (O_MOVSD, SB): /* movsd.b */
2140 /* This instruction implements strncpy, with a conditional branch.
2141 r4 contains n, r5 contains src, and r6 contains dst.
2142 The 16-bit displacement operand is added to the pc
2143 if and only if the end of string is reached before
2144 n bytes are transferred. */
2145
2146 ea = GET_L_REG (4) & 0xffff;
2147 if (ea == 0)
2148 ea = 0x10000;
2149
2150 while (ea--)
2151 {
2152 rd = GET_MEMORY_B (GET_L_REG (5));
2153 SET_MEMORY_B (GET_L_REG (6), rd);
2154 SET_L_REG (5, GET_L_REG (5) + 1);
2155 SET_L_REG (6, GET_L_REG (6) + 1);
2156 SET_W_REG (4, ea);
2157 if (rd == 0)
2158 goto condtrue;
2159 }
2160 goto next;
2161
2162 case O (O_EEPMOV, SB): /* eepmov.b */
2163 case O (O_EEPMOV, SW): /* eepmov.w */
2164 if (h8300hmode || h8300smode)
2165 {
2166 register unsigned char *_src, *_dst;
2167 unsigned int count = ((code->opcode == O (O_EEPMOV, SW))
2168 ? h8_get_reg (sd, R4_REGNUM) & 0xffff
2169 : h8_get_reg (sd, R4_REGNUM) & 0xff);
2170
2171 _src = (h8_get_reg (sd, R5_REGNUM) < memory_size
2172 ? h8_get_memory_buf (sd) + h8_get_reg (sd, R5_REGNUM)
2173 : h8_get_eightbit_buf (sd) +
2174 (h8_get_reg (sd, R5_REGNUM) & 0xff));
2175 if ((_src + count) >= (h8_get_memory_buf (sd) + memory_size))
2176 {
2177 if ((_src + count) >= (h8_get_eightbit_buf (sd) + 0x100))
2178 goto illegal;
2179 }
2180 _dst = (h8_get_reg (sd, R6_REGNUM) < memory_size
2181 ? h8_get_memory_buf (sd) + h8_get_reg (sd, R6_REGNUM)
2182 : h8_get_eightbit_buf (sd) +
2183 (h8_get_reg (sd, R6_REGNUM) & 0xff));
2184
2185 if ((_dst + count) >= (h8_get_memory_buf (sd) + memory_size))
2186 {
2187 if ((_dst + count) >= (h8_get_eightbit_buf (sd) + 0x100))
2188 goto illegal;
2189 }
2190 memcpy (_dst, _src, count);
2191
2192 h8_set_reg (sd, R5_REGNUM, h8_get_reg (sd, R5_REGNUM) + count);
2193 h8_set_reg (sd, R6_REGNUM, h8_get_reg (sd, R6_REGNUM) + count);
2194 h8_set_reg (sd, R4_REGNUM, h8_get_reg (sd, R4_REGNUM) &
2195 ((code->opcode == O (O_EEPMOV, SW))
2196 ? (~0xffff) : (~0xff)));
2197 cycles += 2 * count;
2198 goto next;
2199 }
2200 goto illegal;
2201
2202 case O (O_ADDS, SL): /* adds (.l) */
2203 /* FIXME fetch.
2204 * This insn only uses register operands, but still
2205 * it would be cleaner to use fetch and store... */
2206 SET_L_REG (code->dst.reg,
2207 GET_L_REG (code->dst.reg)
2208 + code->src.literal);
2209
2210 goto next;
2211
2212 case O (O_SUBS, SL): /* subs (.l) */
2213 /* FIXME fetch.
2214 * This insn only uses register operands, but still
2215 * it would be cleaner to use fetch and store... */
2216 SET_L_REG (code->dst.reg,
2217 GET_L_REG (code->dst.reg)
2218 - code->src.literal);
2219 goto next;
2220
2221 case O (O_CMP, SB): /* cmp.b */
2222 if (fetch (sd, &code->dst, &rd))
2223 goto end;
2224 if (fetch (sd, &code->src, &ea))
2225 goto end;
2226 ea = -ea;
2227 res = rd + ea;
2228 goto just_flags_alu8;
2229
2230 case O (O_CMP, SW): /* cmp.w */
2231 if (fetch (sd, &code->dst, &rd))
2232 goto end;
2233 if (fetch (sd, &code->src, &ea))
2234 goto end;
2235 ea = -ea;
2236 res = rd + ea;
2237 goto just_flags_alu16;
2238
2239 case O (O_CMP, SL): /* cmp.l */
2240 if (fetch (sd, &code->dst, &rd))
2241 goto end;
2242 if (fetch (sd, &code->src, &ea))
2243 goto end;
2244 ea = -ea;
2245 res = rd + ea;
2246 goto just_flags_alu32;
2247
2248 case O (O_DEC, SB): /* dec.b */
2249 /* FIXME fetch.
2250 * This insn only uses register operands, but still
2251 * it would be cleaner to use fetch and store... */
2252 rd = GET_B_REG (code->src.reg);
2253 ea = -1;
2254 res = rd + ea;
2255 SET_B_REG (code->src.reg, res);
2256 goto just_flags_inc8;
2257
2258 case O (O_DEC, SW): /* dec.w */
2259 /* FIXME fetch.
2260 * This insn only uses register operands, but still
2261 * it would be cleaner to use fetch and store... */
2262 rd = GET_W_REG (code->dst.reg);
2263 ea = -code->src.literal;
2264 res = rd + ea;
2265 SET_W_REG (code->dst.reg, res);
2266 goto just_flags_inc16;
2267
2268 case O (O_DEC, SL): /* dec.l */
2269 /* FIXME fetch.
2270 * This insn only uses register operands, but still
2271 * it would be cleaner to use fetch and store... */
2272 rd = GET_L_REG (code->dst.reg);
2273 ea = -code->src.literal;
2274 res = rd + ea;
2275 SET_L_REG (code->dst.reg, res);
2276 goto just_flags_inc32;
2277
2278 case O (O_INC, SB): /* inc.b */
2279 /* FIXME fetch.
2280 * This insn only uses register operands, but still
2281 * it would be cleaner to use fetch and store... */
2282 rd = GET_B_REG (code->src.reg);
2283 ea = 1;
2284 res = rd + ea;
2285 SET_B_REG (code->src.reg, res);
2286 goto just_flags_inc8;
2287
2288 case O (O_INC, SW): /* inc.w */
2289 /* FIXME fetch.
2290 * This insn only uses register operands, but still
2291 * it would be cleaner to use fetch and store... */
2292 rd = GET_W_REG (code->dst.reg);
2293 ea = code->src.literal;
2294 res = rd + ea;
2295 SET_W_REG (code->dst.reg, res);
2296 goto just_flags_inc16;
2297
2298 case O (O_INC, SL): /* inc.l */
2299 /* FIXME fetch.
2300 * This insn only uses register operands, but still
2301 * it would be cleaner to use fetch and store... */
2302 rd = GET_L_REG (code->dst.reg);
2303 ea = code->src.literal;
2304 res = rd + ea;
2305 SET_L_REG (code->dst.reg, res);
2306 goto just_flags_inc32;
2307
2308 case O (O_LDC, SB): /* ldc.b */
2309 if (fetch (sd, &code->src, &res))
2310 goto end;
2311 goto setc;
2312
2313 case O (O_LDC, SW): /* ldc.w */
2314 if (fetch (sd, &code->src, &res))
2315 goto end;
2316
2317 /* Word operand, value from MSB, must be shifted. */
2318 res >>= 8;
2319 goto setc;
2320
2321 case O (O_LDC, SL): /* ldc.l */
2322 if (fetch (sd, &code->src, &res))
2323 goto end;
2324 switch (code->dst.type) {
2325 case X (OP_SBR, SL):
2326 h8_set_sbr (sd, res);
2327 break;
2328 case X (OP_VBR, SL):
2329 h8_set_vbr (sd, res);
2330 break;
2331 default:
2332 goto illegal;
2333 }
2334 goto next;
2335
2336 case O (O_STC, SW): /* stc.w */
2337 case O (O_STC, SB): /* stc.b */
2338 if (code->src.type == X (OP_CCR, SB))
2339 {
2340 BUILDSR (sd);
2341 res = h8_get_ccr (sd);
2342 }
2343 else if (code->src.type == X (OP_EXR, SB) && h8300smode)
2344 {
2345 if (h8300smode)
2346 h8_set_exr (sd, (trace << 7) | intMask);
2347 res = h8_get_exr (sd);
2348 }
2349 else
2350 goto illegal;
2351
2352 /* Word operand, value to MSB, must be shifted. */
2353 if (code->opcode == X (O_STC, SW))
2354 res <<= 8;
2355 if (store (sd, &code->dst, res))
2356 goto end;
2357 goto next;
2358 case O (O_STC, SL): /* stc.l */
2359 switch (code->src.type) {
2360 case X (OP_SBR, SL):
2361 res = h8_get_sbr (sd);
2362 break;
2363 case X (OP_VBR, SL):
2364 res = h8_get_vbr (sd);
2365 break;
2366 default:
2367 goto illegal;
2368 }
2369 if (store (sd, &code->dst, res))
2370 goto end;
2371 goto next;
2372
2373 case O (O_ANDC, SB): /* andc.b */
2374 if (code->dst.type == X (OP_CCR, SB))
2375 {
2376 BUILDSR (sd);
2377 rd = h8_get_ccr (sd);
2378 }
2379 else if (code->dst.type == X (OP_EXR, SB) && h8300smode)
2380 {
2381 if (h8300smode)
2382 h8_set_exr (sd, (trace << 7) | intMask);
2383 rd = h8_get_exr (sd);
2384 }
2385 else
2386 goto illegal;
2387 ea = code->src.literal;
2388 res = rd & ea;
2389 goto setc;
2390
2391 case O (O_ORC, SB): /* orc.b */
2392 if (code->dst.type == X (OP_CCR, SB))
2393 {
2394 BUILDSR (sd);
2395 rd = h8_get_ccr (sd);
2396 }
2397 else if (code->dst.type == X (OP_EXR, SB) && h8300smode)
2398 {
2399 if (h8300smode)
2400 h8_set_exr (sd, (trace << 7) | intMask);
2401 rd = h8_get_exr (sd);
2402 }
2403 else
2404 goto illegal;
2405 ea = code->src.literal;
2406 res = rd | ea;
2407 goto setc;
2408
2409 case O (O_XORC, SB): /* xorc.b */
2410 if (code->dst.type == X (OP_CCR, SB))
2411 {
2412 BUILDSR (sd);
2413 rd = h8_get_ccr (sd);
2414 }
2415 else if (code->dst.type == X (OP_EXR, SB) && h8300smode)
2416 {
2417 if (h8300smode)
2418 h8_set_exr (sd, (trace << 7) | intMask);
2419 rd = h8_get_exr (sd);
2420 }
2421 else
2422 goto illegal;
2423 ea = code->src.literal;
2424 res = rd ^ ea;
2425 goto setc;
2426
2427 case O (O_BRAS, SB): /* bra/s */
2428 /* This is basically an ordinary branch, with a delay slot. */
2429 if (fetch (sd, &code->src, &res))
2430 goto end;
2431
2432 if ((res & 1) == 0)
2433 goto illegal;
2434
2435 res -= 1;
2436
2437 /* Execution continues at next instruction, but
2438 delayed_branch is set up for next cycle. */
2439 h8_set_delayed_branch (sd, code->next_pc + res);
2440 pc = code->next_pc;
2441 goto end;
2442
2443 case O (O_BRAB, SB): /* bra rd.b */
2444 case O (O_BRAW, SW): /* bra rd.w */
2445 case O (O_BRAL, SL): /* bra erd.l */
2446 if (fetch (sd, &code->src, &rd))
2447 goto end;
2448 switch (OP_SIZE (code->opcode)) {
2449 case SB: rd &= 0xff; break;
2450 case SW: rd &= 0xffff; break;
2451 case SL: rd &= 0xffffffff; break;
2452 }
2453 pc = code->next_pc + rd;
2454 goto end;
2455
2456 case O (O_BRABC, SB): /* bra/bc, branch if bit clear */
2457 case O (O_BRABS, SB): /* bra/bs, branch if bit set */
2458 case O (O_BSRBC, SB): /* bsr/bc, call if bit clear */
2459 case O (O_BSRBS, SB): /* bsr/bs, call if bit set */
2460 if (fetch (sd, &code->dst, &rd) ||
2461 fetch (sd, &code->src, &bit))
2462 goto end;
2463
2464 if (code->opcode == O (O_BRABC, SB) || /* branch if clear */
2465 code->opcode == O (O_BSRBC, SB)) /* call if clear */
2466 {
2467 if ((rd & (1 << bit))) /* no branch */
2468 goto next;
2469 }
2470 else /* branch/call if set */
2471 {
2472 if (!(rd & (1 << bit))) /* no branch */
2473 goto next;
2474 }
2475
2476 if (fetch (sd, &code->op3, &res)) /* branch */
2477 goto end;
2478 pc = code->next_pc + res;
2479
2480 if (code->opcode == O (O_BRABC, SB) ||
2481 code->opcode == O (O_BRABS, SB)) /* branch */
2482 goto end;
2483 else /* call */
2484 goto call;
2485
2486 case O (O_BRA, SN):
2487 case O (O_BRA, SL):
2488 case O (O_BRA, SW):
2489 case O (O_BRA, SB): /* bra, branch always */
2490 if (1)
2491 goto condtrue;
2492 goto next;
2493
2494 case O (O_BRN, SB): /* brn, ;-/ branch never? */
2495 if (0)
2496 goto condtrue;
2497 goto next;
2498
2499 case O (O_BHI, SB): /* bhi */
2500 if ((C || Z) == 0)
2501 goto condtrue;
2502 goto next;
2503
2504
2505 case O (O_BLS, SB): /* bls */
2506 if ((C || Z))
2507 goto condtrue;
2508 goto next;
2509
2510 case O (O_BCS, SB): /* bcs, branch if carry set */
2511 if ((C == 1))
2512 goto condtrue;
2513 goto next;
2514
2515 case O (O_BCC, SB): /* bcc, branch if carry clear */
2516 if ((C == 0))
2517 goto condtrue;
2518 goto next;
2519
2520 case O (O_BEQ, SB): /* beq, branch if zero set */
2521 if (Z)
2522 goto condtrue;
2523 goto next;
2524 case O (O_BGT, SB): /* bgt */
2525 if (((Z || (N ^ V)) == 0))
2526 goto condtrue;
2527 goto next;
2528
2529 case O (O_BLE, SB): /* ble */
2530 if (((Z || (N ^ V)) == 1))
2531 goto condtrue;
2532 goto next;
2533
2534 case O (O_BGE, SB): /* bge */
2535 if ((N ^ V) == 0)
2536 goto condtrue;
2537 goto next;
2538 case O (O_BLT, SB): /* blt */
2539 if ((N ^ V))
2540 goto condtrue;
2541 goto next;
2542 case O (O_BMI, SB): /* bmi */
2543 if ((N))
2544 goto condtrue;
2545 goto next;
2546 case O (O_BNE, SB): /* bne, branch if zero clear */
2547 if ((Z == 0))
2548 goto condtrue;
2549 goto next;
2550
2551 case O (O_BPL, SB): /* bpl */
2552 if (N == 0)
2553 goto condtrue;
2554 goto next;
2555 case O (O_BVC, SB): /* bvc */
2556 if ((V == 0))
2557 goto condtrue;
2558 goto next;
2559 case O (O_BVS, SB): /* bvs */
2560 if ((V == 1))
2561 goto condtrue;
2562 goto next;
2563
2564 /* Trap for Command Line setup. */
2565 case O (O_SYS_CMDLINE, SB):
2566 {
2567 int i = 0; /* Loop counter. */
2568 int j = 0; /* Loop counter. */
2569 int ind_arg_len = 0; /* Length of each argument. */
2570 int no_of_args = 0; /* The no. or cmdline args. */
2571 int current_location = 0; /* Location of string. */
2572 int old_sp = 0; /* The Initial Stack Pointer. */
2573 int no_of_slots = 0; /* No. of slots required on the stack
2574 for storing cmdline args. */
2575 int sp_move = 0; /* No. of locations by which the stack needs
2576 to grow. */
2577 int new_sp = 0; /* The final stack pointer location passed
2578 back. */
2579 int *argv_ptrs; /* Pointers of argv strings to be stored. */
2580 int argv_ptrs_location = 0; /* Location of pointers to cmdline
2581 args on the stack. */
2582 int char_ptr_size = 0; /* Size of a character pointer on
2583 target machine. */
2584 int addr_cmdline = 0; /* Memory location where cmdline has
2585 to be stored. */
2586 int size_cmdline = 0; /* Size of cmdline. */
2587
2588 /* Set the address of 256 free locations where command line is
2589 stored. */
2590 addr_cmdline = cmdline_location();
2591 h8_set_reg (sd, 0, addr_cmdline);
2592
2593 /* Counting the no. of commandline arguments. */
2594 for (i = 0; h8_get_cmdline_arg (sd, i) != NULL; i++)
2595 continue;
2596
2597 /* No. of arguments in the command line. */
2598 no_of_args = i;
2599
2600 /* Current location is just a temporary variable,which we are
2601 setting to the point to the start of our commandline string. */
2602 current_location = addr_cmdline;
2603
2604 /* Allocating space for storing pointers of the command line
2605 arguments. */
2606 argv_ptrs = (int *) malloc (sizeof (int) * no_of_args);
2607
2608 /* Setting char_ptr_size to the sizeof (char *) on the different
2609 architectures. */
2610 if ((h8300hmode || h8300smode) && !h8300_normal_mode)
2611 {
2612 char_ptr_size = 4;
2613 }
2614 else
2615 {
2616 char_ptr_size = 2;
2617 }
2618
2619 for (i = 0; i < no_of_args; i++)
2620 {
2621 ind_arg_len = 0;
2622
2623 /* The size of the commandline argument. */
2624 ind_arg_len = strlen (h8_get_cmdline_arg (sd, i)) + 1;
2625
2626 /* The total size of the command line string. */
2627 size_cmdline += ind_arg_len;
2628
2629 /* As we have only 256 bytes, we need to provide a graceful
2630 exit. Anyways, a program using command line arguments
2631 where we cannot store all the command line arguments
2632 given may behave unpredictably. */
2633 if (size_cmdline >= 256)
2634 {
2635 h8_set_reg (sd, 0, 0);
2636 goto next;
2637 }
2638 else
2639 {
2640 /* current_location points to the memory where the next
2641 commandline argument is stored. */
2642 argv_ptrs[i] = current_location;
2643 for (j = 0; j < ind_arg_len; j++)
2644 {
2645 SET_MEMORY_B ((current_location +
2646 (sizeof (char) * j)),
2647 *(h8_get_cmdline_arg (sd, i) +
2648 sizeof (char) * j));
2649 }
2650
2651 /* Setting current_location to the starting of next
2652 argument. */
2653 current_location += ind_arg_len;
2654 }
2655 }
2656
2657 /* This is the original position of the stack pointer. */
2658 old_sp = h8_get_reg (sd, SP_REGNUM);
2659
2660 /* We need space from the stack to store the pointers to argvs. */
2661 /* As we will infringe on the stack, we need to shift the stack
2662 pointer so that the data is not overwritten. We calculate how
2663 much space is required. */
2664 sp_move = (no_of_args) * (char_ptr_size);
2665
2666 /* The final position of stack pointer, we have thus taken some
2667 space from the stack. */
2668 new_sp = old_sp - sp_move;
2669
2670 /* Temporary variable holding value where the argv pointers need
2671 to be stored. */
2672 argv_ptrs_location = new_sp;
2673
2674 /* The argv pointers are stored at sequential locations. As per
2675 the H8300 ABI. */
2676 for (i = 0; i < no_of_args; i++)
2677 {
2678 /* Saving the argv pointer. */
2679 if ((h8300hmode || h8300smode) && !h8300_normal_mode)
2680 {
2681 SET_MEMORY_L (argv_ptrs_location, argv_ptrs[i]);
2682 }
2683 else
2684 {
2685 SET_MEMORY_W (argv_ptrs_location, argv_ptrs[i]);
2686 }
2687
2688 /* The next location where the pointer to the next argv
2689 string has to be stored. */
2690 argv_ptrs_location += char_ptr_size;
2691 }
2692
2693 /* Required by POSIX, Setting 0x0 at the end of the list of argv
2694 pointers. */
2695 if ((h8300hmode || h8300smode) && !h8300_normal_mode)
2696 {
2697 SET_MEMORY_L (old_sp, 0x0);
2698 }
2699 else
2700 {
2701 SET_MEMORY_W (old_sp, 0x0);
2702 }
2703
2704 /* Freeing allocated memory. */
2705 free (argv_ptrs);
2706 for (i = 0; i <= no_of_args; i++)
2707 {
2708 free (h8_get_cmdline_arg (sd, i));
2709 }
2710 free (h8_get_command_line (sd));
2711
2712 /* The no. of argv arguments are returned in Reg 0. */
2713 h8_set_reg (sd, 0, no_of_args);
2714 /* The Pointer to argv in Register 1. */
2715 h8_set_reg (sd, 1, new_sp);
2716 /* Setting the stack pointer to the new value. */
2717 h8_set_reg (sd, SP_REGNUM, new_sp);
2718 }
2719 goto next;
2720
2721 /* System call processing starts. */
2722 case O (O_SYS_OPEN, SB):
2723 {
2724 int len = 0; /* Length of filename. */
2725 char *filename; /* Filename would go here. */
2726 char temp_char; /* Temporary character */
2727 int mode = 0; /* Mode bits for the file. */
2728 int open_return; /* Return value of open, file descriptor. */
2729 int i; /* Loop counter */
2730 int filename_ptr; /* Pointer to filename in cpu memory. */
2731
2732 /* Setting filename_ptr to first argument of open, */
2733 /* and trying to get mode. */
2734 if ((h8300sxmode || h8300hmode || h8300smode) && !h8300_normal_mode)
2735 {
2736 filename_ptr = GET_L_REG (0);
2737 mode = GET_MEMORY_L (h8_get_reg (sd, SP_REGNUM) + 4);
2738 }
2739 else
2740 {
2741 filename_ptr = GET_W_REG (0);
2742 mode = GET_MEMORY_W (h8_get_reg (sd, SP_REGNUM) + 2);
2743 }
2744
2745 /* Trying to find the length of the filename. */
2746 temp_char = GET_MEMORY_B (h8_get_reg (sd, 0));
2747
2748 len = 1;
2749 while (temp_char != '\0')
2750 {
2751 temp_char = GET_MEMORY_B (filename_ptr + len);
2752 len++;
2753 }
2754
2755 /* Allocating space for the filename. */
2756 filename = (char *) malloc (sizeof (char) * len);
2757
2758 /* String copying the filename from memory. */
2759 for (i = 0; i < len; i++)
2760 {
2761 temp_char = GET_MEMORY_B (filename_ptr + i);
2762 filename[i] = temp_char;
2763 }
2764
2765 /* Callback to open and return the file descriptor. */
2766 open_return = sim_callback->open (sim_callback, filename, mode);
2767
2768 /* Return value in register 0. */
2769 h8_set_reg (sd, 0, open_return);
2770
2771 /* Freeing memory used for filename. */
2772 free (filename);
2773 }
2774 goto next;
2775
2776 case O (O_SYS_READ, SB):
2777 {
2778 char *char_ptr; /* Where characters read would be stored. */
2779 int fd; /* File descriptor */
2780 int buf_size; /* BUF_SIZE parameter in read. */
2781 int i = 0; /* Temporary Loop counter */
2782 int read_return = 0; /* Return value from callback to
2783 read. */
2784
2785 fd = (h8300hmode && !h8300_normal_mode) ? GET_L_REG (0) : GET_W_REG (0);
2786 buf_size = (h8300hmode && !h8300_normal_mode) ? GET_L_REG (2) : GET_W_REG (2);
2787
2788 char_ptr = (char *) malloc (sizeof (char) * buf_size);
2789
2790 /* Callback to read and return the no. of characters read. */
2791 read_return =
2792 sim_callback->read (sim_callback, fd, char_ptr, buf_size);
2793
2794 /* The characters read are stored in cpu memory. */
2795 for (i = 0; i < buf_size; i++)
2796 {
2797 SET_MEMORY_B ((h8_get_reg (sd, 1) + (sizeof (char) * i)),
2798 *(char_ptr + (sizeof (char) * i)));
2799 }
2800
2801 /* Return value in Register 0. */
2802 h8_set_reg (sd, 0, read_return);
2803
2804 /* Freeing memory used as buffer. */
2805 free (char_ptr);
2806 }
2807 goto next;
2808
2809 case O (O_SYS_WRITE, SB):
2810 {
2811 int fd; /* File descriptor */
2812 char temp_char; /* Temporary character */
2813 int len; /* Length of write, Parameter II to write. */
2814 int char_ptr; /* Character Pointer, Parameter I of write. */
2815 char *ptr; /* Where characters to be written are stored.
2816 */
2817 int write_return; /* Return value from callback to write. */
2818 int i = 0; /* Loop counter */
2819
2820 fd = (h8300hmode && !h8300_normal_mode) ? GET_L_REG (0) : GET_W_REG (0);
2821 char_ptr = (h8300hmode && !h8300_normal_mode) ? GET_L_REG (1) : GET_W_REG (1);
2822 len = (h8300hmode && !h8300_normal_mode) ? GET_L_REG (2) : GET_W_REG (2);
2823
2824 /* Allocating space for the characters to be written. */
2825 ptr = (char *) malloc (sizeof (char) * len);
2826
2827 /* Fetching the characters from cpu memory. */
2828 for (i = 0; i < len; i++)
2829 {
2830 temp_char = GET_MEMORY_B (char_ptr + i);
2831 ptr[i] = temp_char;
2832 }
2833
2834 /* Callback write and return the no. of characters written. */
2835 write_return = sim_callback->write (sim_callback, fd, ptr, len);
2836
2837 /* Return value in Register 0. */
2838 h8_set_reg (sd, 0, write_return);
2839
2840 /* Freeing memory used as buffer. */
2841 free (ptr);
2842 }
2843 goto next;
2844
2845 case O (O_SYS_LSEEK, SB):
2846 {
2847 int fd; /* File descriptor */
2848 int offset; /* Offset */
2849 int origin; /* Origin */
2850 int lseek_return; /* Return value from callback to lseek. */
2851
2852 fd = (h8300hmode && !h8300_normal_mode) ? GET_L_REG (0) : GET_W_REG (0);
2853 offset = (h8300hmode && !h8300_normal_mode) ? GET_L_REG (1) : GET_W_REG (1);
2854 origin = (h8300hmode && !h8300_normal_mode) ? GET_L_REG (2) : GET_W_REG (2);
2855
2856 /* Callback lseek and return offset. */
2857 lseek_return =
2858 sim_callback->lseek (sim_callback, fd, offset, origin);
2859
2860 /* Return value in register 0. */
2861 h8_set_reg (sd, 0, lseek_return);
2862 }
2863 goto next;
2864
2865 case O (O_SYS_CLOSE, SB):
2866 {
2867 int fd; /* File descriptor */
2868 int close_return; /* Return value from callback to close. */
2869
2870 fd = (h8300hmode && !h8300_normal_mode) ? GET_L_REG (0) : GET_W_REG (0);
2871
2872 /* Callback close and return. */
2873 close_return = sim_callback->close (sim_callback, fd);
2874
2875 /* Return value in register 0. */
2876 h8_set_reg (sd, 0, close_return);
2877 }
2878 goto next;
2879
2880 case O (O_SYS_FSTAT, SB):
2881 {
2882 int fd; /* File descriptor */
2883 struct stat stat_rec; /* Stat record */
2884 int fstat_return; /* Return value from callback to stat. */
2885 int stat_ptr; /* Pointer to stat record. */
2886 char *temp_stat_ptr; /* Temporary stat_rec pointer. */
2887
2888 fd = (h8300hmode && !h8300_normal_mode) ? GET_L_REG (0) : GET_W_REG (0);
2889
2890 /* Setting stat_ptr to second argument of stat. */
2891 stat_ptr = (h8300hmode && !h8300_normal_mode) ? GET_L_REG (1) : GET_W_REG (1);
2892
2893 /* Callback stat and return. */
2894 fstat_return = sim_callback->to_fstat (sim_callback, fd,
2895 &stat_rec);
2896
2897 /* Have stat_ptr point to starting of stat_rec. */
2898 temp_stat_ptr = (char *) (&stat_rec);
2899
2900 /* Setting up the stat structure returned. */
2901 SET_MEMORY_W (stat_ptr, stat_rec.st_dev);
2902 stat_ptr += 2;
2903 SET_MEMORY_W (stat_ptr, stat_rec.st_ino);
2904 stat_ptr += 2;
2905 SET_MEMORY_L (stat_ptr, stat_rec.st_mode);
2906 stat_ptr += 4;
2907 SET_MEMORY_W (stat_ptr, stat_rec.st_nlink);
2908 stat_ptr += 2;
2909 SET_MEMORY_W (stat_ptr, stat_rec.st_uid);
2910 stat_ptr += 2;
2911 SET_MEMORY_W (stat_ptr, stat_rec.st_gid);
2912 stat_ptr += 2;
2913 SET_MEMORY_W (stat_ptr, stat_rec.st_rdev);
2914 stat_ptr += 2;
2915 SET_MEMORY_L (stat_ptr, stat_rec.st_size);
2916 stat_ptr += 4;
2917 SET_MEMORY_L (stat_ptr, stat_rec.st_atime);
2918 stat_ptr += 8;
2919 SET_MEMORY_L (stat_ptr, stat_rec.st_mtime);
2920 stat_ptr += 8;
2921 SET_MEMORY_L (stat_ptr, stat_rec.st_ctime);
2922
2923 /* Return value in register 0. */
2924 h8_set_reg (sd, 0, fstat_return);
2925 }
2926 goto next;
2927
2928 case O (O_SYS_STAT, SB):
2929 {
2930 int len = 0; /* Length of filename. */
2931 char *filename; /* Filename would go here. */
2932 char temp_char; /* Temporary character */
2933 int filename_ptr; /* Pointer to filename in cpu memory. */
2934 struct stat stat_rec; /* Stat record */
2935 int stat_return; /* Return value from callback to stat */
2936 int stat_ptr; /* Pointer to stat record. */
2937 char *temp_stat_ptr; /* Temporary stat_rec pointer. */
2938 int i = 0; /* Loop Counter */
2939
2940 /* Setting filename_ptr to first argument of open. */
2941 filename_ptr = (h8300hmode && !h8300_normal_mode) ? GET_L_REG (0) : GET_W_REG (0);
2942
2943 /* Trying to find the length of the filename. */
2944 temp_char = GET_MEMORY_B (h8_get_reg (sd, 0));
2945
2946 len = 1;
2947 while (temp_char != '\0')
2948 {
2949 temp_char = GET_MEMORY_B (filename_ptr + len);
2950 len++;
2951 }
2952
2953 /* Allocating space for the filename. */
2954 filename = (char *) malloc (sizeof (char) * len);
2955
2956 /* String copying the filename from memory. */
2957 for (i = 0; i < len; i++)
2958 {
2959 temp_char = GET_MEMORY_B (filename_ptr + i);
2960 filename[i] = temp_char;
2961 }
2962
2963 /* Setting stat_ptr to second argument of stat. */
2964 /* stat_ptr = h8_get_reg (sd, 1); */
2965 stat_ptr = (h8300hmode && !h8300_normal_mode) ? GET_L_REG (1) : GET_W_REG (1);
2966
2967 /* Callback stat and return. */
2968 stat_return =
2969 sim_callback->to_stat (sim_callback, filename, &stat_rec);
2970
2971 /* Have stat_ptr point to starting of stat_rec. */
2972 temp_stat_ptr = (char *) (&stat_rec);
2973
2974 /* Freeing memory used for filename. */
2975 free (filename);
2976
2977 /* Setting up the stat structure returned. */
2978 SET_MEMORY_W (stat_ptr, stat_rec.st_dev);
2979 stat_ptr += 2;
2980 SET_MEMORY_W (stat_ptr, stat_rec.st_ino);
2981 stat_ptr += 2;
2982 SET_MEMORY_L (stat_ptr, stat_rec.st_mode);
2983 stat_ptr += 4;
2984 SET_MEMORY_W (stat_ptr, stat_rec.st_nlink);
2985 stat_ptr += 2;
2986 SET_MEMORY_W (stat_ptr, stat_rec.st_uid);
2987 stat_ptr += 2;
2988 SET_MEMORY_W (stat_ptr, stat_rec.st_gid);
2989 stat_ptr += 2;
2990 SET_MEMORY_W (stat_ptr, stat_rec.st_rdev);
2991 stat_ptr += 2;
2992 SET_MEMORY_L (stat_ptr, stat_rec.st_size);
2993 stat_ptr += 4;
2994 SET_MEMORY_L (stat_ptr, stat_rec.st_atime);
2995 stat_ptr += 8;
2996 SET_MEMORY_L (stat_ptr, stat_rec.st_mtime);
2997 stat_ptr += 8;
2998 SET_MEMORY_L (stat_ptr, stat_rec.st_ctime);
2999
3000 /* Return value in register 0. */
3001 h8_set_reg (sd, 0, stat_return);
3002 }
3003 goto next;
3004 /* End of system call processing. */
3005
3006 case O (O_NOT, SB): /* not.b */
3007 if (fetch2 (sd, &code->src, &rd))
3008 goto end;
3009 rd = ~rd;
3010 v = 0;
3011 goto shift8;
3012
3013 case O (O_NOT, SW): /* not.w */
3014 if (fetch2 (sd, &code->src, &rd))
3015 goto end;
3016 rd = ~rd;
3017 v = 0;
3018 goto shift16;
3019
3020 case O (O_NOT, SL): /* not.l */
3021 if (fetch2 (sd, &code->src, &rd))
3022 goto end;
3023 rd = ~rd;
3024 v = 0;
3025 goto shift32;
3026
3027 case O (O_SHLL, SB): /* shll.b */
3028 case O (O_SHLR, SB): /* shlr.b */
3029 if (fetch2 (sd, &code->dst, &rd))
3030 goto end;
3031
3032 if (memcmp (&code->src, &code->dst, sizeof (code->src)) == 0)
3033 ea = 1; /* unary op */
3034 else /* binary op */
3035 fetch (sd, &code->src, &ea);
3036
3037 if (code->opcode == O (O_SHLL, SB))
3038 {
3039 v = (ea > 8);
3040 c = rd & (0x80 >> (ea - 1));
3041 rd <<= ea;
3042 }
3043 else
3044 {
3045 v = 0;
3046 c = rd & (1 << (ea - 1));
3047 rd = (unsigned char) rd >> ea;
3048 }
3049 goto shift8;
3050
3051 case O (O_SHLL, SW): /* shll.w */
3052 case O (O_SHLR, SW): /* shlr.w */
3053 if (fetch2 (sd, &code->dst, &rd))
3054 goto end;
3055
3056 if (memcmp (&code->src, &code->dst, sizeof (code->src)) == 0)
3057 ea = 1; /* unary op */
3058 else
3059 fetch (sd, &code->src, &ea);
3060
3061 if (code->opcode == O (O_SHLL, SW))
3062 {
3063 v = (ea > 16);
3064 c = rd & (0x8000 >> (ea - 1));
3065 rd <<= ea;
3066 }
3067 else
3068 {
3069 v = 0;
3070 c = rd & (1 << (ea - 1));
3071 rd = (unsigned short) rd >> ea;
3072 }
3073 goto shift16;
3074
3075 case O (O_SHLL, SL): /* shll.l */
3076 case O (O_SHLR, SL): /* shlr.l */
3077 if (fetch2 (sd, &code->dst, &rd))
3078 goto end;
3079
3080 if (memcmp (&code->src, &code->dst, sizeof (code->src)) == 0)
3081 ea = 1; /* unary op */
3082 else
3083 fetch (sd, &code->src, &ea);
3084
3085 if (code->opcode == O (O_SHLL, SL))
3086 {
3087 v = (ea > 32);
3088 c = rd & (0x80000000 >> (ea - 1));
3089 rd <<= ea;
3090 }
3091 else
3092 {
3093 v = 0;
3094 c = rd & (1 << (ea - 1));
3095 rd = (unsigned int) rd >> ea;
3096 }
3097 goto shift32;
3098
3099 case O (O_SHAL, SB):
3100 case O (O_SHAR, SB):
3101 if (fetch2 (sd, &code->dst, &rd))
3102 goto end;
3103
3104 if (code->src.type == X (OP_IMM, SB))
3105 fetch (sd, &code->src, &ea);
3106 else
3107 ea = 1;
3108
3109 if (code->opcode == O (O_SHAL, SB))
3110 {
3111 c = rd & (0x80 >> (ea - 1));
3112 res = rd >> (7 - ea);
3113 v = ((res & 1) && !(res & 2))
3114 || (!(res & 1) && (res & 2));
3115 rd <<= ea;
3116 }
3117 else
3118 {
3119 c = rd & (1 << (ea - 1));
3120 v = 0;
3121 rd = ((signed char) rd) >> ea;
3122 }
3123 goto shift8;
3124
3125 case O (O_SHAL, SW):
3126 case O (O_SHAR, SW):
3127 if (fetch2 (sd, &code->dst, &rd))
3128 goto end;
3129
3130 if (code->src.type == X (OP_IMM, SW))
3131 fetch (sd, &code->src, &ea);
3132 else
3133 ea = 1;
3134
3135 if (code->opcode == O (O_SHAL, SW))
3136 {
3137 c = rd & (0x8000 >> (ea - 1));
3138 res = rd >> (15 - ea);
3139 v = ((res & 1) && !(res & 2))
3140 || (!(res & 1) && (res & 2));
3141 rd <<= ea;
3142 }
3143 else
3144 {
3145 c = rd & (1 << (ea - 1));
3146 v = 0;
3147 rd = ((signed short) rd) >> ea;
3148 }
3149 goto shift16;
3150
3151 case O (O_SHAL, SL):
3152 case O (O_SHAR, SL):
3153 if (fetch2 (sd, &code->dst, &rd))
3154 goto end;
3155
3156 if (code->src.type == X (OP_IMM, SL))
3157 fetch (sd, &code->src, &ea);
3158 else
3159 ea = 1;
3160
3161 if (code->opcode == O (O_SHAL, SL))
3162 {
3163 c = rd & (0x80000000 >> (ea - 1));
3164 res = rd >> (31 - ea);
3165 v = ((res & 1) && !(res & 2))
3166 || (!(res & 1) && (res & 2));
3167 rd <<= ea;
3168 }
3169 else
3170 {
3171 c = rd & (1 << (ea - 1));
3172 v = 0;
3173 rd = ((signed int) rd) >> ea;
3174 }
3175 goto shift32;
3176
3177 case O (O_ROTL, SB):
3178 case O (O_ROTR, SB):
3179 if (fetch2 (sd, &code->dst, &rd))
3180 goto end;
3181
3182 if (code->src.type == X (OP_IMM, SB))
3183 fetch (sd, &code->src, &ea);
3184 else
3185 ea = 1;
3186
3187 while (ea--)
3188 if (code->opcode == O (O_ROTL, SB))
3189 {
3190 c = rd & 0x80;
3191 rd <<= 1;
3192 if (c)
3193 rd |= 1;
3194 }
3195 else
3196 {
3197 c = rd & 1;
3198 rd = ((unsigned char) rd) >> 1;
3199 if (c)
3200 rd |= 0x80;
3201 }
3202
3203 v = 0;
3204 goto shift8;
3205
3206 case O (O_ROTL, SW):
3207 case O (O_ROTR, SW):
3208 if (fetch2 (sd, &code->dst, &rd))
3209 goto end;
3210
3211 if (code->src.type == X (OP_IMM, SW))
3212 fetch (sd, &code->src, &ea);
3213 else
3214 ea = 1;
3215
3216 while (ea--)
3217 if (code->opcode == O (O_ROTL, SW))
3218 {
3219 c = rd & 0x8000;
3220 rd <<= 1;
3221 if (c)
3222 rd |= 1;
3223 }
3224 else
3225 {
3226 c = rd & 1;
3227 rd = ((unsigned short) rd) >> 1;
3228 if (c)
3229 rd |= 0x8000;
3230 }
3231
3232 v = 0;
3233 goto shift16;
3234
3235 case O (O_ROTL, SL):
3236 case O (O_ROTR, SL):
3237 if (fetch2 (sd, &code->dst, &rd))
3238 goto end;
3239
3240 if (code->src.type == X (OP_IMM, SL))
3241 fetch (sd, &code->src, &ea);
3242 else
3243 ea = 1;
3244
3245 while (ea--)
3246 if (code->opcode == O (O_ROTL, SL))
3247 {
3248 c = rd & 0x80000000;
3249 rd <<= 1;
3250 if (c)
3251 rd |= 1;
3252 }
3253 else
3254 {
3255 c = rd & 1;
3256 rd = ((unsigned int) rd) >> 1;
3257 if (c)
3258 rd |= 0x80000000;
3259 }
3260
3261 v = 0;
3262 goto shift32;
3263
3264 case O (O_ROTXL, SB):
3265 case O (O_ROTXR, SB):
3266 if (fetch2 (sd, &code->dst, &rd))
3267 goto end;
3268
3269 if (code->src.type == X (OP_IMM, SB))
3270 fetch (sd, &code->src, &ea);
3271 else
3272 ea = 1;
3273
3274 while (ea--)
3275 if (code->opcode == O (O_ROTXL, SB))
3276 {
3277 res = rd & 0x80;
3278 rd <<= 1;
3279 if (C)
3280 rd |= 1;
3281 c = res;
3282 }
3283 else
3284 {
3285 res = rd & 1;
3286 rd = ((unsigned char) rd) >> 1;
3287 if (C)
3288 rd |= 0x80;
3289 c = res;
3290 }
3291
3292 v = 0;
3293 goto shift8;
3294
3295 case O (O_ROTXL, SW):
3296 case O (O_ROTXR, SW):
3297 if (fetch2 (sd, &code->dst, &rd))
3298 goto end;
3299
3300 if (code->src.type == X (OP_IMM, SW))
3301 fetch (sd, &code->src, &ea);
3302 else
3303 ea = 1;
3304
3305 while (ea--)
3306 if (code->opcode == O (O_ROTXL, SW))
3307 {
3308 res = rd & 0x8000;
3309 rd <<= 1;
3310 if (C)
3311 rd |= 1;
3312 c = res;
3313 }
3314 else
3315 {
3316 res = rd & 1;
3317 rd = ((unsigned short) rd) >> 1;
3318 if (C)
3319 rd |= 0x8000;
3320 c = res;
3321 }
3322
3323 v = 0;
3324 goto shift16;
3325
3326 case O (O_ROTXL, SL):
3327 case O (O_ROTXR, SL):
3328 if (fetch2 (sd, &code->dst, &rd))
3329 goto end;
3330
3331 if (code->src.type == X (OP_IMM, SL))
3332 fetch (sd, &code->src, &ea);
3333 else
3334 ea = 1;
3335
3336 while (ea--)
3337 if (code->opcode == O (O_ROTXL, SL))
3338 {
3339 res = rd & 0x80000000;
3340 rd <<= 1;
3341 if (C)
3342 rd |= 1;
3343 c = res;
3344 }
3345 else
3346 {
3347 res = rd & 1;
3348 rd = ((unsigned int) rd) >> 1;
3349 if (C)
3350 rd |= 0x80000000;
3351 c = res;
3352 }
3353
3354 v = 0;
3355 goto shift32;
3356
3357 case O (O_JMP, SN):
3358 case O (O_JMP, SL):
3359 case O (O_JMP, SB): /* jmp */
3360 case O (O_JMP, SW):
3361 fetch (sd, &code->src, &pc);
3362 goto end;
3363
3364 case O (O_JSR, SN):
3365 case O (O_JSR, SL):
3366 case O (O_JSR, SB): /* jsr, jump to subroutine */
3367 case O (O_JSR, SW):
3368 if (fetch (sd, &code->src, &pc))
3369 goto end;
3370 call:
3371 tmp = h8_get_reg (sd, SP_REGNUM);
3372
3373 if (h8300hmode && !h8300_normal_mode)
3374 {
3375 tmp -= 4;
3376 SET_MEMORY_L (tmp, code->next_pc);
3377 }
3378 else
3379 {
3380 tmp -= 2;
3381 SET_MEMORY_W (tmp, code->next_pc);
3382 }
3383 h8_set_reg (sd, SP_REGNUM, tmp);
3384
3385 goto end;
3386
3387 case O (O_BSR, SW):
3388 case O (O_BSR, SL):
3389 case O (O_BSR, SB): /* bsr, branch to subroutine */
3390 if (fetch (sd, &code->src, &res))
3391 goto end;
3392 pc = code->next_pc + res;
3393 goto call;
3394
3395 case O (O_RTE, SN): /* rte, return from exception */
3396 rte:
3397 /* Pops exr and ccr before pc -- otherwise identical to rts. */
3398 tmp = h8_get_reg (sd, SP_REGNUM);
3399
3400 if (h8300smode) /* pop exr */
3401 {
3402 h8_set_exr (sd, GET_MEMORY_L (tmp));
3403 tmp += 4;
3404 }
3405 if (h8300hmode && !h8300_normal_mode)
3406 {
3407 h8_set_ccr (sd, GET_MEMORY_L (tmp));
3408 tmp += 4;
3409 pc = GET_MEMORY_L (tmp);
3410 tmp += 4;
3411 }
3412 else
3413 {
3414 h8_set_ccr (sd, GET_MEMORY_W (tmp));
3415 tmp += 2;
3416 pc = GET_MEMORY_W (tmp);
3417 tmp += 2;
3418 }
3419
3420 GETSR (sd);
3421 h8_set_reg (sd, SP_REGNUM, tmp);
3422 goto end;
3423
3424 case O (O_RTS, SN): /* rts, return from subroutine */
3425 rts:
3426 tmp = h8_get_reg (sd, SP_REGNUM);
3427
3428 if (h8300hmode && !h8300_normal_mode)
3429 {
3430 pc = GET_MEMORY_L (tmp);
3431 tmp += 4;
3432 }
3433 else
3434 {
3435 pc = GET_MEMORY_W (tmp);
3436 tmp += 2;
3437 }
3438
3439 h8_set_reg (sd, SP_REGNUM, tmp);
3440 goto end;
3441
3442 case O (O_ILL, SB): /* illegal */
3443 sim_engine_halt (sd, cpu, NULL, pc, sim_stopped, SIM_SIGILL);
3444 goto end;
3445
3446 case O (O_SLEEP, SN): /* sleep */
3447 /* Check for magic numbers in r1 and r2. */
3448 if ((h8_get_reg (sd, R1_REGNUM) & 0xffff) == LIBC_EXIT_MAGIC1 &&
3449 (h8_get_reg (sd, R2_REGNUM) & 0xffff) == LIBC_EXIT_MAGIC2 &&
3450 SIM_WIFEXITED (h8_get_reg (sd, 0)))
3451 {
3452 /* This trap comes from _exit, not from gdb. */
3453 sim_engine_halt (sd, cpu, NULL, pc, sim_exited,
3454 SIM_WEXITSTATUS (h8_get_reg (sd, 0)));
3455 }
3456 #if 0
3457 /* Unfortunately this won't really work, because
3458 when we take a breakpoint trap, R0 has a "random",
3459 user-defined value. Don't see any immediate solution. */
3460 else if (SIM_WIFSTOPPED (h8_get_reg (sd, 0)))
3461 {
3462 /* Pass the stop signal up to gdb. */
3463 sim_engine_halt (sd, cpu, NULL, pc, sim_stopped,
3464 SIM_WSTOPSIG (h8_get_reg (sd, 0)));
3465 }
3466 #endif
3467 else
3468 {
3469 /* Treat it as a sigtrap. */
3470 sim_engine_halt (sd, cpu, NULL, pc, sim_stopped, SIM_SIGTRAP);
3471 }
3472 goto end;
3473
3474 case O (O_TRAPA, SB): /* trapa */
3475 if (fetch (sd, &code->src, &res))
3476 goto end; /* res is vector number. */
3477
3478 tmp = h8_get_reg (sd, SP_REGNUM);
3479 if(h8300_normal_mode)
3480 {
3481 tmp -= 2;
3482 SET_MEMORY_W (tmp, code->next_pc);
3483 tmp -= 2;
3484 SET_MEMORY_W (tmp, h8_get_ccr (sd));
3485 }
3486 else
3487 {
3488 tmp -= 4;
3489 SET_MEMORY_L (tmp, code->next_pc);
3490 tmp -= 4;
3491 SET_MEMORY_L (tmp, h8_get_ccr (sd));
3492 }
3493 intMaskBit = 1;
3494 BUILDSR (sd);
3495
3496 if (h8300smode)
3497 {
3498 tmp -= 4;
3499 SET_MEMORY_L (tmp, h8_get_exr (sd));
3500 }
3501
3502 h8_set_reg (sd, SP_REGNUM, tmp);
3503
3504 if(h8300_normal_mode)
3505 pc = GET_MEMORY_L (0x10 + res * 2); /* Vector addresses are 0x10,0x12,0x14 and 0x16 */
3506 else
3507 pc = GET_MEMORY_L (0x20 + res * 4);
3508 goto end;
3509
3510 case O (O_BPT, SN):
3511 sim_engine_halt (sd, cpu, NULL, pc, sim_stopped, SIM_SIGTRAP);
3512 goto end;
3513
3514 case O (O_BSETEQ, SB):
3515 if (Z)
3516 goto bset;
3517 goto next;
3518
3519 case O (O_BSETNE, SB):
3520 if (!Z)
3521 goto bset;
3522 goto next;
3523
3524 case O (O_BCLREQ, SB):
3525 if (Z)
3526 goto bclr;
3527 goto next;
3528
3529 case O (O_BCLRNE, SB):
3530 if (!Z)
3531 goto bclr;
3532 goto next;
3533
3534 OBITOP (O_BNOT, 1, 1, ea ^= m); /* bnot */
3535 OBITOP (O_BTST, 1, 0, nz = ea & m); /* btst */
3536 bset:
3537 OBITOP (O_BSET, 1, 1, ea |= m); /* bset */
3538 bclr:
3539 OBITOP (O_BCLR, 1, 1, ea &= ~m); /* bclr */
3540 OBITOP (O_BLD, 1, 0, c = ea & m); /* bld */
3541 OBITOP (O_BILD, 1, 0, c = !(ea & m)); /* bild */
3542 OBITOP (O_BST, 1, 1, ea &= ~m;
3543 if (C) ea |= m); /* bst */
3544 OBITOP (O_BIST, 1, 1, ea &= ~m;
3545 if (!C) ea |= m); /* bist */
3546 OBITOP (O_BSTZ, 1, 1, ea &= ~m;
3547 if (Z) ea |= m); /* bstz */
3548 OBITOP (O_BISTZ, 1, 1, ea &= ~m;
3549 if (!Z) ea |= m); /* bistz */
3550 OBITOP (O_BAND, 1, 0, c = (ea & m) && C); /* band */
3551 OBITOP (O_BIAND, 1, 0, c = !(ea & m) && C); /* biand */
3552 OBITOP (O_BOR, 1, 0, c = (ea & m) || C); /* bor */
3553 OBITOP (O_BIOR, 1, 0, c = !(ea & m) || C); /* bior */
3554 OBITOP (O_BXOR, 1, 0, c = ((ea & m) != 0)!= C); /* bxor */
3555 OBITOP (O_BIXOR, 1, 0, c = !(ea & m) != C); /* bixor */
3556
3557 case O (O_BFLD, SB): /* bfld */
3558 /* bitfield load */
3559 ea = 0;
3560 if (fetch (sd, &code->src, &bit))
3561 goto end;
3562
3563 if (bit != 0)
3564 {
3565 if (fetch (sd, &code->dst, &ea))
3566 goto end;
3567
3568 ea &= bit;
3569 while (!(bit & 1))
3570 {
3571 ea >>= 1;
3572 bit >>= 1;
3573 }
3574 }
3575 if (store (sd, &code->op3, ea))
3576 goto end;
3577
3578 goto next;
3579
3580 case O(O_BFST, SB): /* bfst */
3581 /* bitfield store */
3582 /* NOTE: the imm8 value is in dst, and the ea value
3583 (which is actually the destination) is in op3.
3584 It has to be that way, to avoid breaking the assembler. */
3585
3586 if (fetch (sd, &code->dst, &bit)) /* imm8 */
3587 goto end;
3588 if (bit == 0) /* noop -- nothing to do. */
3589 goto next;
3590
3591 if (fetch (sd, &code->src, &rd)) /* reg8 src */
3592 goto end;
3593
3594 if (fetch2 (sd, &code->op3, &ea)) /* ea dst */
3595 goto end;
3596
3597 /* Left-shift the register data into position. */
3598 for (tmp = bit; !(tmp & 1); tmp >>= 1)
3599 rd <<= 1;
3600
3601 /* Combine it with the neighboring bits. */
3602 ea = (ea & ~bit) | (rd & bit);
3603
3604 /* Put it back. */
3605 if (store2 (sd, &code->op3, ea))
3606 goto end;
3607 goto next;
3608
3609 case O (O_CLRMAC, SN): /* clrmac */
3610 h8_set_mach (sd, 0);
3611 h8_set_macl (sd, 0);
3612 h8_set_macZ (sd, 1);
3613 h8_set_macV (sd, 0);
3614 h8_set_macN (sd, 0);
3615 goto next;
3616
3617 case O (O_STMAC, SL): /* stmac, 260 */
3618 switch (code->src.type) {
3619 case X (OP_MACH, SL):
3620 res = h8_get_mach (sd);
3621 if (res & 0x200) /* sign extend */
3622 res |= 0xfffffc00;
3623 break;
3624 case X (OP_MACL, SL):
3625 res = h8_get_macl (sd);
3626 break;
3627 default: goto illegal;
3628 }
3629 nz = !h8_get_macZ (sd);
3630 n = h8_get_macN (sd);
3631 v = h8_get_macV (sd);
3632
3633 if (store (sd, &code->dst, res))
3634 goto end;
3635
3636 goto next;
3637
3638 case O (O_LDMAC, SL): /* ldmac, 179 */
3639 if (fetch (sd, &code->src, &rd))
3640 goto end;
3641
3642 switch (code->dst.type) {
3643 case X (OP_MACH, SL):
3644 rd &= 0x3ff; /* Truncate to 10 bits */
3645 h8_set_mach (sd, rd);
3646 break;
3647 case X (OP_MACL, SL):
3648 h8_set_macl (sd, rd);
3649 break;
3650 default: goto illegal;
3651 }
3652 h8_set_macV (sd, 0);
3653 goto next;
3654
3655 case O (O_MAC, SW):
3656 if (fetch (sd, &code->src, &rd) ||
3657 fetch (sd, &code->dst, &res))
3658 goto end;
3659
3660 /* Ye gods, this is non-portable!
3661 However, the existing mul/div code is similar. */
3662 res = SEXTSHORT (res) * SEXTSHORT (rd);
3663
3664 if (h8_get_macS (sd)) /* Saturating mode */
3665 {
3666 long long mac = h8_get_macl (sd);
3667
3668 if (mac & 0x80000000) /* sign extend */
3669 mac |= 0xffffffff00000000LL;
3670
3671 mac += res;
3672 if (mac > 0x7fffffff || mac < 0xffffffff80000000LL)
3673 h8_set_macV (sd, 1);
3674 h8_set_macZ (sd, (mac == 0));
3675 h8_set_macN (sd, (mac < 0));
3676 h8_set_macl (sd, (int) mac);
3677 }
3678 else /* "Less Saturating" mode */
3679 {
3680 long long mac = h8_get_mach (sd);
3681 mac <<= 32;
3682 mac += h8_get_macl (sd);
3683
3684 if (mac & 0x20000000000LL) /* sign extend */
3685 mac |= 0xfffffc0000000000LL;
3686
3687 mac += res;
3688 if (mac > 0x1ffffffffffLL ||
3689 mac < (long long) 0xfffffe0000000000LL)
3690 h8_set_macV (sd, 1);
3691 h8_set_macZ (sd, (mac == 0));
3692 h8_set_macN (sd, (mac < 0));
3693 h8_set_macl (sd, (int) mac);
3694 mac >>= 32;
3695 h8_set_mach (sd, (int) (mac & 0x3ff));
3696 }
3697 goto next;
3698
3699 case O (O_MULS, SW): /* muls.w */
3700 if (fetch (sd, &code->src, &ea) ||
3701 fetch (sd, &code->dst, &rd))
3702 goto end;
3703
3704 ea = SEXTSHORT (ea);
3705 res = SEXTSHORT (ea * SEXTSHORT (rd));
3706
3707 n = res & 0x8000;
3708 nz = res & 0xffff;
3709 if (store (sd, &code->dst, res))
3710 goto end;
3711
3712 goto next;
3713
3714 case O (O_MULS, SL): /* muls.l */
3715 if (fetch (sd, &code->src, &ea) ||
3716 fetch (sd, &code->dst, &rd))
3717 goto end;
3718
3719 res = ea * rd;
3720
3721 n = res & 0x80000000;
3722 nz = res & 0xffffffff;
3723 if (store (sd, &code->dst, res))
3724 goto end;
3725 goto next;
3726
3727 case O (O_MULSU, SL): /* muls/u.l */
3728 if (fetch (sd, &code->src, &ea) ||
3729 fetch (sd, &code->dst, &rd))
3730 goto end;
3731
3732 /* Compute upper 32 bits of the 64-bit result. */
3733 res = (((long long) ea) * ((long long) rd)) >> 32;
3734
3735 n = res & 0x80000000;
3736 nz = res & 0xffffffff;
3737 if (store (sd, &code->dst, res))
3738 goto end;
3739 goto next;
3740
3741 case O (O_MULU, SW): /* mulu.w */
3742 if (fetch (sd, &code->src, &ea) ||
3743 fetch (sd, &code->dst, &rd))
3744 goto end;
3745
3746 res = UEXTSHORT ((UEXTSHORT (ea) * UEXTSHORT (rd)));
3747
3748 /* Don't set Z or N. */
3749 if (store (sd, &code->dst, res))
3750 goto end;
3751
3752 goto next;
3753
3754 case O (O_MULU, SL): /* mulu.l */
3755 if (fetch (sd, &code->src, &ea) ||
3756 fetch (sd, &code->dst, &rd))
3757 goto end;
3758
3759 res = ea * rd;
3760
3761 /* Don't set Z or N. */
3762 if (store (sd, &code->dst, res))
3763 goto end;
3764
3765 goto next;
3766
3767 case O (O_MULUU, SL): /* mulu/u.l */
3768 if (fetch (sd, &code->src, &ea) ||
3769 fetch (sd, &code->dst, &rd))
3770 goto end;
3771
3772 /* Compute upper 32 bits of the 64-bit result. */
3773 res = (((unsigned long long) (unsigned) ea) *
3774 ((unsigned long long) (unsigned) rd)) >> 32;
3775
3776 /* Don't set Z or N. */
3777 if (store (sd, &code->dst, res))
3778 goto end;
3779
3780 goto next;
3781
3782 case O (O_MULXS, SB): /* mulxs.b */
3783 if (fetch (sd, &code->src, &ea) ||
3784 fetch (sd, &code->dst, &rd))
3785 goto end;
3786
3787 ea = SEXTCHAR (ea);
3788 res = ea * SEXTCHAR (rd);
3789
3790 n = res & 0x8000;
3791 nz = res & 0xffff;
3792 if (store (sd, &code->dst, res))
3793 goto end;
3794
3795 goto next;
3796
3797 case O (O_MULXS, SW): /* mulxs.w */
3798 if (fetch (sd, &code->src, &ea) ||
3799 fetch (sd, &code->dst, &rd))
3800 goto end;
3801
3802 ea = SEXTSHORT (ea);
3803 res = ea * SEXTSHORT (rd & 0xffff);
3804
3805 n = res & 0x80000000;
3806 nz = res & 0xffffffff;
3807 if (store (sd, &code->dst, res))
3808 goto end;
3809
3810 goto next;
3811
3812 case O (O_MULXU, SB): /* mulxu.b */
3813 if (fetch (sd, &code->src, &ea) ||
3814 fetch (sd, &code->dst, &rd))
3815 goto end;
3816
3817 res = UEXTCHAR (ea) * UEXTCHAR (rd);
3818
3819 if (store (sd, &code->dst, res))
3820 goto end;
3821
3822 goto next;
3823
3824 case O (O_MULXU, SW): /* mulxu.w */
3825 if (fetch (sd, &code->src, &ea) ||
3826 fetch (sd, &code->dst, &rd))
3827 goto end;
3828
3829 res = UEXTSHORT (ea) * UEXTSHORT (rd);
3830
3831 if (store (sd, &code->dst, res))
3832 goto end;
3833
3834 goto next;
3835
3836 case O (O_TAS, SB): /* tas (test and set) */
3837 if (!h8300sxmode) /* h8sx can use any register. */
3838 switch (code->src.reg)
3839 {
3840 case R0_REGNUM:
3841 case R1_REGNUM:
3842 case R4_REGNUM:
3843 case R5_REGNUM:
3844 break;
3845 default:
3846 goto illegal;
3847 }
3848
3849 if (fetch (sd, &code->src, &res))
3850 goto end;
3851 if (store (sd, &code->src, res | 0x80))
3852 goto end;
3853
3854 goto just_flags_log8;
3855
3856 case O (O_DIVU, SW): /* divu.w */
3857 if (fetch (sd, &code->src, &ea) ||
3858 fetch (sd, &code->dst, &rd))
3859 goto end;
3860
3861 n = ea & 0x8000;
3862 nz = ea & 0xffff;
3863 if (ea)
3864 res = (unsigned) (UEXTSHORT (rd) / UEXTSHORT (ea));
3865 else
3866 res = 0;
3867
3868 if (store (sd, &code->dst, res))
3869 goto end;
3870 goto next;
3871
3872 case O (O_DIVU, SL): /* divu.l */
3873 if (fetch (sd, &code->src, &ea) ||
3874 fetch (sd, &code->dst, &rd))
3875 goto end;
3876
3877 n = ea & 0x80000000;
3878 nz = ea & 0xffffffff;
3879 if (ea)
3880 res = (unsigned) rd / ea;
3881 else
3882 res = 0;
3883
3884 if (store (sd, &code->dst, res))
3885 goto end;
3886 goto next;
3887
3888 case O (O_DIVS, SW): /* divs.w */
3889 if (fetch (sd, &code->src, &ea) ||
3890 fetch (sd, &code->dst, &rd))
3891 goto end;
3892
3893 if (ea)
3894 {
3895 res = SEXTSHORT (rd) / SEXTSHORT (ea);
3896 nz = 1;
3897 }
3898 else
3899 {
3900 res = 0;
3901 nz = 0;
3902 }
3903
3904 n = res & 0x8000;
3905 if (store (sd, &code->dst, res))
3906 goto end;
3907 goto next;
3908
3909 case O (O_DIVS, SL): /* divs.l */
3910 if (fetch (sd, &code->src, &ea) ||
3911 fetch (sd, &code->dst, &rd))
3912 goto end;
3913
3914 if (ea)
3915 {
3916 res = rd / ea;
3917 nz = 1;
3918 }
3919 else
3920 {
3921 res = 0;
3922 nz = 0;
3923 }
3924
3925 n = res & 0x80000000;
3926 if (store (sd, &code->dst, res))
3927 goto end;
3928 goto next;
3929
3930 case O (O_DIVXU, SB): /* divxu.b */
3931 if (fetch (sd, &code->src, &ea) ||
3932 fetch (sd, &code->dst, &rd))
3933 goto end;
3934
3935 rd = UEXTSHORT (rd);
3936 ea = UEXTCHAR (ea);
3937
3938 n = ea & 0x80;
3939 nz = ea & 0xff;
3940 if (ea)
3941 {
3942 tmp = (unsigned) rd % ea;
3943 res = (unsigned) rd / ea;
3944 }
3945 else
3946 {
3947 tmp = 0;
3948 res = 0;
3949 }
3950
3951 if (store (sd, &code->dst, (res & 0xff) | (tmp << 8)))
3952 goto end;
3953 goto next;
3954
3955 case O (O_DIVXU, SW): /* divxu.w */
3956 if (fetch (sd, &code->src, &ea) ||
3957 fetch (sd, &code->dst, &rd))
3958 goto end;
3959
3960 ea = UEXTSHORT (ea);
3961
3962 n = ea & 0x8000;
3963 nz = ea & 0xffff;
3964 if (ea)
3965 {
3966 tmp = (unsigned) rd % ea;
3967 res = (unsigned) rd / ea;
3968 }
3969 else
3970 {
3971 tmp = 0;
3972 res = 0;
3973 }
3974
3975 if (store (sd, &code->dst, (res & 0xffff) | (tmp << 16)))
3976 goto end;
3977 goto next;
3978
3979 case O (O_DIVXS, SB): /* divxs.b */
3980 if (fetch (sd, &code->src, &ea) ||
3981 fetch (sd, &code->dst, &rd))
3982 goto end;
3983
3984 rd = SEXTSHORT (rd);
3985 ea = SEXTCHAR (ea);
3986
3987 if (ea)
3988 {
3989 tmp = (int) rd % (int) ea;
3990 res = (int) rd / (int) ea;
3991 nz = 1;
3992 }
3993 else
3994 {
3995 tmp = 0;
3996 res = 0;
3997 nz = 0;
3998 }
3999
4000 n = res & 0x8000;
4001 if (store (sd, &code->dst, (res & 0xff) | (tmp << 8)))
4002 goto end;
4003 goto next;
4004
4005 case O (O_DIVXS, SW): /* divxs.w */
4006 if (fetch (sd, &code->src, &ea) ||
4007 fetch (sd, &code->dst, &rd))
4008 goto end;
4009
4010 ea = SEXTSHORT (ea);
4011
4012 if (ea)
4013 {
4014 tmp = (int) rd % (int) ea;
4015 res = (int) rd / (int) ea;
4016 nz = 1;
4017 }
4018 else
4019 {
4020 tmp = 0;
4021 res = 0;
4022 nz = 0;
4023 }
4024
4025 n = res & 0x80000000;
4026 if (store (sd, &code->dst, (res & 0xffff) | (tmp << 16)))
4027 goto end;
4028 goto next;
4029
4030 case O (O_EXTS, SW): /* exts.w, signed extend */
4031 if (fetch2 (sd, &code->dst, &rd))
4032 goto end;
4033 ea = rd & 0x80 ? -256 : 0;
4034 res = (rd & 0xff) + ea;
4035 goto log16;
4036
4037 case O (O_EXTS, SL): /* exts.l, signed extend */
4038 if (fetch2 (sd, &code->dst, &rd))
4039 goto end;
4040 if (code->src.type == X (OP_IMM, SL))
4041 {
4042 if (fetch (sd, &code->src, &ea))
4043 goto end;
4044
4045 if (ea == 2) /* exts.l #2, nn */
4046 {
4047 /* Sign-extend from 8-bit to 32-bit. */
4048 ea = rd & 0x80 ? -256 : 0;
4049 res = (rd & 0xff) + ea;
4050 goto log32;
4051 }
4052 }
4053 /* Sign-extend from 16-bit to 32-bit. */
4054 ea = rd & 0x8000 ? -65536 : 0;
4055 res = (rd & 0xffff) + ea;
4056 goto log32;
4057
4058 case O (O_EXTU, SW): /* extu.w, unsigned extend */
4059 if (fetch2 (sd, &code->dst, &rd))
4060 goto end;
4061 ea = 0;
4062 res = (rd & 0xff) + ea;
4063 goto log16;
4064
4065 case O (O_EXTU, SL): /* extu.l, unsigned extend */
4066 if (fetch2 (sd, &code->dst, &rd))
4067 goto end;
4068 if (code->src.type == X (OP_IMM, SL))
4069 {
4070 if (fetch (sd, &code->src, &ea))
4071 goto end;
4072
4073 if (ea == 2) /* extu.l #2, nn */
4074 {
4075 /* Zero-extend from 8-bit to 32-bit. */
4076 ea = 0;
4077 res = (rd & 0xff) + ea;
4078 goto log32;
4079 }
4080 }
4081 /* Zero-extend from 16-bit to 32-bit. */
4082 ea = 0;
4083 res = (rd & 0xffff) + ea;
4084 goto log32;
4085
4086 case O (O_NOP, SN): /* nop */
4087 goto next;
4088
4089 case O (O_STM, SL): /* stm, store to memory */
4090 {
4091 int nregs, firstreg, i;
4092
4093 nregs = GET_MEMORY_B (pc + 1);
4094 nregs >>= 4;
4095 nregs &= 0xf;
4096 firstreg = code->src.reg;
4097 firstreg &= 0xf;
4098 for (i = firstreg; i <= firstreg + nregs; i++)
4099 {
4100 h8_set_reg (sd, SP_REGNUM, h8_get_reg (sd, SP_REGNUM) - 4);
4101 SET_MEMORY_L (h8_get_reg (sd, SP_REGNUM), h8_get_reg (sd, i));
4102 }
4103 }
4104 goto next;
4105
4106 case O (O_LDM, SL): /* ldm, load from memory */
4107 case O (O_RTEL, SN): /* rte/l, ldm plus rte */
4108 case O (O_RTSL, SN): /* rts/l, ldm plus rts */
4109 {
4110 int nregs, firstreg, i;
4111
4112 nregs = ((GET_MEMORY_B (pc + 1) >> 4) & 0xf);
4113 firstreg = code->dst.reg & 0xf;
4114 for (i = firstreg; i >= firstreg - nregs; i--)
4115 {
4116 h8_set_reg (sd, i, GET_MEMORY_L (h8_get_reg (sd, SP_REGNUM)));
4117 h8_set_reg (sd, SP_REGNUM, h8_get_reg (sd, SP_REGNUM) + 4);
4118 }
4119 }
4120 switch (code->opcode) {
4121 case O (O_RTEL, SN):
4122 goto rte;
4123 case O (O_RTSL, SN):
4124 goto rts;
4125 case O (O_LDM, SL):
4126 goto next;
4127 default:
4128 goto illegal;
4129 }
4130
4131 case O (O_DAA, SB):
4132 /* Decimal Adjust Addition. This is for BCD arithmetic. */
4133 res = GET_B_REG (code->src.reg); /* FIXME fetch? */
4134 if (!c && (0 <= (res >> 4) && (res >> 4) <= 9) &&
4135 !h && (0 <= (res & 0xf) && (res & 0xf) <= 9))
4136 res = res; /* Value added == 0. */
4137 else if (!c && (0 <= (res >> 4) && (res >> 4) <= 8) &&
4138 !h && (10 <= (res & 0xf) && (res & 0xf) <= 15))
4139 res = res + 0x6; /* Value added == 6. */
4140 else if (!c && (0 <= (res >> 4) && (res >> 4) <= 9) &&
4141 h && (0 <= (res & 0xf) && (res & 0xf) <= 3))
4142 res = res + 0x6; /* Value added == 6. */
4143 else if (!c && (10 <= (res >> 4) && (res >> 4) <= 15) &&
4144 !h && (0 <= (res & 0xf) && (res & 0xf) <= 9))
4145 res = res + 0x60; /* Value added == 60. */
4146 else if (!c && (9 <= (res >> 4) && (res >> 4) <= 15) &&
4147 !h && (10 <= (res & 0xf) && (res & 0xf) <= 15))
4148 res = res + 0x66; /* Value added == 66. */
4149 else if (!c && (10 <= (res >> 4) && (res >> 4) <= 15) &&
4150 h && (0 <= (res & 0xf) && (res & 0xf) <= 3))
4151 res = res + 0x66; /* Value added == 66. */
4152 else if ( c && (1 <= (res >> 4) && (res >> 4) <= 2) &&
4153 !h && (0 <= (res & 0xf) && (res & 0xf) <= 9))
4154 res = res + 0x60; /* Value added == 60. */
4155 else if ( c && (1 <= (res >> 4) && (res >> 4) <= 2) &&
4156 !h && (10 <= (res & 0xf) && (res & 0xf) <= 15))
4157 res = res + 0x66; /* Value added == 66. */
4158 else if (c && (1 <= (res >> 4) && (res >> 4) <= 3) &&
4159 h && (0 <= (res & 0xf) && (res & 0xf) <= 3))
4160 res = res + 0x66; /* Value added == 66. */
4161
4162 goto alu8;
4163
4164 case O (O_DAS, SB):
4165 /* Decimal Adjust Subtraction. This is for BCD arithmetic. */
4166 res = GET_B_REG (code->src.reg); /* FIXME fetch, fetch2... */
4167 if (!c && (0 <= (res >> 4) && (res >> 4) <= 9) &&
4168 !h && (0 <= (res & 0xf) && (res & 0xf) <= 9))
4169 res = res; /* Value added == 0. */
4170 else if (!c && (0 <= (res >> 4) && (res >> 4) <= 8) &&
4171 h && (6 <= (res & 0xf) && (res & 0xf) <= 15))
4172 res = res + 0xfa; /* Value added == 0xfa. */
4173 else if ( c && (7 <= (res >> 4) && (res >> 4) <= 15) &&
4174 !h && (0 <= (res & 0xf) && (res & 0xf) <= 9))
4175 res = res + 0xa0; /* Value added == 0xa0. */
4176 else if (c && (6 <= (res >> 4) && (res >> 4) <= 15) &&
4177 h && (6 <= (res & 0xf) && (res & 0xf) <= 15))
4178 res = res + 0x9a; /* Value added == 0x9a. */
4179
4180 goto alu8;
4181
4182 default:
4183 illegal:
4184 sim_engine_halt (sd, cpu, NULL, pc, sim_stopped, SIM_SIGILL);
4185 goto end;
4186
4187 }
4188
4189 sim_io_printf (sd, "sim_resume: internal error.\n");
4190 sim_engine_halt (sd, cpu, NULL, pc, sim_stopped, SIM_SIGILL);
4191 goto end;
4192
4193 setc:
4194 if (code->dst.type == X (OP_CCR, SB) ||
4195 code->dst.type == X (OP_CCR, SW))
4196 {
4197 h8_set_ccr (sd, res);
4198 GETSR (sd);
4199 }
4200 else if (h8300smode &&
4201 (code->dst.type == X (OP_EXR, SB) ||
4202 code->dst.type == X (OP_EXR, SW)))
4203 {
4204 h8_set_exr (sd, res);
4205 if (h8300smode) /* Get exr. */
4206 {
4207 trace = (h8_get_exr (sd) >> 7) & 1;
4208 intMask = h8_get_exr (sd) & 7;
4209 }
4210 }
4211 else
4212 goto illegal;
4213
4214 goto next;
4215
4216 condtrue:
4217 /* When a branch works */
4218 if (fetch (sd, &code->src, &res))
4219 goto end;
4220 if (res & 1) /* bad address */
4221 goto illegal;
4222 pc = code->next_pc + res;
4223 goto end;
4224
4225 /* Set the cond codes from res */
4226 bitop:
4227
4228 /* Set the flags after an 8 bit inc/dec operation */
4229 just_flags_inc8:
4230 n = res & 0x80;
4231 nz = res & 0xff;
4232 v = (rd & 0x7f) == 0x7f;
4233 goto next;
4234
4235 /* Set the flags after an 16 bit inc/dec operation */
4236 just_flags_inc16:
4237 n = res & 0x8000;
4238 nz = res & 0xffff;
4239 v = (rd & 0x7fff) == 0x7fff;
4240 goto next;
4241
4242 /* Set the flags after an 32 bit inc/dec operation */
4243 just_flags_inc32:
4244 n = res & 0x80000000;
4245 nz = res & 0xffffffff;
4246 v = (rd & 0x7fffffff) == 0x7fffffff;
4247 goto next;
4248
4249 shift8:
4250 /* Set flags after an 8 bit shift op, carry,overflow set in insn */
4251 n = (rd & 0x80);
4252 nz = rd & 0xff;
4253 if (store2 (sd, &code->dst, rd))
4254 goto end;
4255 goto next;
4256
4257 shift16:
4258 /* Set flags after an 16 bit shift op, carry,overflow set in insn */
4259 n = (rd & 0x8000);
4260 nz = rd & 0xffff;
4261 if (store2 (sd, &code->dst, rd))
4262 goto end;
4263 goto next;
4264
4265 shift32:
4266 /* Set flags after an 32 bit shift op, carry,overflow set in insn */
4267 n = (rd & 0x80000000);
4268 nz = rd & 0xffffffff;
4269 if (store2 (sd, &code->dst, rd))
4270 goto end;
4271 goto next;
4272
4273 log32:
4274 if (store2 (sd, &code->dst, res))
4275 goto end;
4276
4277 just_flags_log32:
4278 /* flags after a 32bit logical operation */
4279 n = res & 0x80000000;
4280 nz = res & 0xffffffff;
4281 v = 0;
4282 goto next;
4283
4284 log16:
4285 if (store2 (sd, &code->dst, res))
4286 goto end;
4287
4288 just_flags_log16:
4289 /* flags after a 16bit logical operation */
4290 n = res & 0x8000;
4291 nz = res & 0xffff;
4292 v = 0;
4293 goto next;
4294
4295 log8:
4296 if (store2 (sd, &code->dst, res))
4297 goto end;
4298
4299 just_flags_log8:
4300 n = res & 0x80;
4301 nz = res & 0xff;
4302 v = 0;
4303 goto next;
4304
4305 alu8:
4306 if (store2 (sd, &code->dst, res))
4307 goto end;
4308
4309 just_flags_alu8:
4310 n = res & 0x80;
4311 nz = res & 0xff;
4312 c = (res & 0x100);
4313 switch (code->opcode / 4)
4314 {
4315 case O_ADD:
4316 case O_ADDX:
4317 v = ((rd & 0x80) == (ea & 0x80)
4318 && (rd & 0x80) != (res & 0x80));
4319 break;
4320 case O_SUB:
4321 case O_SUBX:
4322 case O_CMP:
4323 v = ((rd & 0x80) != (-ea & 0x80)
4324 && (rd & 0x80) != (res & 0x80));
4325 break;
4326 case O_NEG:
4327 v = (rd == 0x80);
4328 break;
4329 case O_DAA:
4330 case O_DAS:
4331 break; /* No effect on v flag. */
4332 }
4333 goto next;
4334
4335 alu16:
4336 if (store2 (sd, &code->dst, res))
4337 goto end;
4338
4339 just_flags_alu16:
4340 n = res & 0x8000;
4341 nz = res & 0xffff;
4342 c = (res & 0x10000);
4343 switch (code->opcode / 4)
4344 {
4345 case O_ADD:
4346 case O_ADDX:
4347 v = ((rd & 0x8000) == (ea & 0x8000)
4348 && (rd & 0x8000) != (res & 0x8000));
4349 break;
4350 case O_SUB:
4351 case O_SUBX:
4352 case O_CMP:
4353 v = ((rd & 0x8000) != (-ea & 0x8000)
4354 && (rd & 0x8000) != (res & 0x8000));
4355 break;
4356 case O_NEG:
4357 v = (rd == 0x8000);
4358 break;
4359 }
4360 goto next;
4361
4362 alu32:
4363 if (store2 (sd, &code->dst, res))
4364 goto end;
4365
4366 just_flags_alu32:
4367 n = res & 0x80000000;
4368 nz = res & 0xffffffff;
4369 switch (code->opcode / 4)
4370 {
4371 case O_ADD:
4372 case O_ADDX:
4373 v = ((rd & 0x80000000) == (ea & 0x80000000)
4374 && (rd & 0x80000000) != (res & 0x80000000));
4375 c = ((unsigned) res < (unsigned) rd) ||
4376 ((unsigned) res < (unsigned) ea);
4377 break;
4378 case O_SUB:
4379 case O_SUBX:
4380 case O_CMP:
4381 v = ((rd & 0x80000000) != (-ea & 0x80000000)
4382 && (rd & 0x80000000) != (res & 0x80000000));
4383 c = (unsigned) rd < (unsigned) -ea;
4384 break;
4385 case O_NEG:
4386 v = (rd == 0x80000000);
4387 c = res != 0;
4388 break;
4389 }
4390 goto next;
4391
4392 next:
4393 if ((res = h8_get_delayed_branch (sd)) != 0)
4394 {
4395 pc = res;
4396 h8_set_delayed_branch (sd, 0);
4397 }
4398 else
4399 pc = code->next_pc;
4400
4401 } while (0);
4402
4403 end:
4404 h8_set_ticks (sd, h8_get_ticks (sd) + get_now () - tick_start);
4405 h8_set_cycles (sd, h8_get_cycles (sd) + cycles);
4406 h8_set_insts (sd, h8_get_insts (sd) + insts);
4407 h8_set_pc (sd, pc);
4408 BUILDSR (sd);
4409
4410 if (h8300smode)
4411 h8_set_exr (sd, (trace<<7) | intMask);
4412
4413 h8_set_mask (sd, oldmask);
4414 }
4415
4416 void
4417 sim_engine_run (SIM_DESC sd,
4418 int next_cpu_nr, /* ignore */
4419 int nr_cpus, /* ignore */
4420 int siggnal)
4421 {
4422 sim_cpu *cpu;
4423
4424 SIM_ASSERT (STATE_MAGIC (sd) == SIM_MAGIC_NUMBER);
4425
4426 cpu = STATE_CPU (sd, 0);
4427
4428 while (1)
4429 {
4430 step_once (sd, cpu);
4431 if (sim_events_tick (sd))
4432 sim_events_process (sd);
4433 }
4434 }
4435
4436 int
4437 sim_write (SIM_DESC sd, SIM_ADDR addr, const unsigned char *buffer, int size)
4438 {
4439 int i;
4440
4441 init_pointers (sd);
4442 if (addr < 0)
4443 return 0;
4444 for (i = 0; i < size; i++)
4445 {
4446 if (addr < memory_size)
4447 {
4448 h8_set_memory (sd, addr + i, buffer[i]);
4449 }
4450 else
4451 {
4452 h8_set_eightbit (sd, (addr + i) & 0xff, buffer[i]);
4453 }
4454 }
4455 return size;
4456 }
4457
4458 int
4459 sim_read (SIM_DESC sd, SIM_ADDR addr, unsigned char *buffer, int size)
4460 {
4461 init_pointers (sd);
4462 if (addr < 0)
4463 return 0;
4464 if (addr < memory_size)
4465 memcpy (buffer, h8_get_memory_buf (sd) + addr, size);
4466 else
4467 memcpy (buffer, h8_get_eightbit_buf (sd) + (addr & 0xff), size);
4468 return size;
4469 }
4470
4471 static int
4472 h8300_reg_store (SIM_CPU *cpu, int rn, unsigned char *value, int length)
4473 {
4474 int longval;
4475 int shortval;
4476 int intval;
4477 longval = (value[0] << 24) | (value[1] << 16) | (value[2] << 8) | value[3];
4478 shortval = (value[0] << 8) | (value[1]);
4479 intval = h8300hmode ? longval : shortval;
4480
4481 init_pointers (CPU_STATE (cpu));
4482 switch (rn)
4483 {
4484 case PC_REGNUM:
4485 if(h8300_normal_mode)
4486 cpu->pc = shortval; /* PC for Normal mode is 2 bytes */
4487 else
4488 cpu->pc = intval;
4489 break;
4490 default:
4491 return -1;
4492 case R0_REGNUM:
4493 case R1_REGNUM:
4494 case R2_REGNUM:
4495 case R3_REGNUM:
4496 case R4_REGNUM:
4497 case R5_REGNUM:
4498 case R6_REGNUM:
4499 case R7_REGNUM:
4500 case CCR_REGNUM:
4501 case EXR_REGNUM:
4502 case SBR_REGNUM:
4503 case VBR_REGNUM:
4504 case MACH_REGNUM:
4505 case MACL_REGNUM:
4506 cpu->regs[rn] = intval;
4507 break;
4508 case CYCLE_REGNUM:
4509 case INST_REGNUM:
4510 case TICK_REGNUM:
4511 cpu->regs[rn] = longval;
4512 break;
4513 }
4514 return length;
4515 }
4516
4517 static int
4518 h8300_reg_fetch (SIM_CPU *cpu, int rn, unsigned char *buf, int length)
4519 {
4520 int v;
4521 int longreg = 0;
4522
4523 init_pointers (CPU_STATE (cpu));
4524
4525 if (!h8300smode && rn >= EXR_REGNUM)
4526 rn++;
4527 switch (rn)
4528 {
4529 default:
4530 return -1;
4531 case PC_REGNUM:
4532 v = cpu->pc;
4533 break;
4534 case CCR_REGNUM:
4535 case EXR_REGNUM:
4536 case SBR_REGNUM:
4537 case VBR_REGNUM:
4538 case MACH_REGNUM:
4539 case MACL_REGNUM:
4540 case R0_REGNUM:
4541 case R1_REGNUM:
4542 case R2_REGNUM:
4543 case R3_REGNUM:
4544 case R4_REGNUM:
4545 case R5_REGNUM:
4546 case R6_REGNUM:
4547 case R7_REGNUM:
4548 v = cpu->regs[rn];
4549 break;
4550 case CYCLE_REGNUM:
4551 case TICK_REGNUM:
4552 case INST_REGNUM:
4553 v = cpu->regs[rn];
4554 longreg = 1;
4555 break;
4556 case ZERO_REGNUM:
4557 v = 0;
4558 break;
4559 }
4560 /* In Normal mode PC is 2 byte, but other registers are 4 byte */
4561 if ((h8300hmode || longreg) && !(rn == PC_REGNUM && h8300_normal_mode))
4562 {
4563 buf[0] = v >> 24;
4564 buf[1] = v >> 16;
4565 buf[2] = v >> 8;
4566 buf[3] = v >> 0;
4567 return 4;
4568 }
4569 else
4570 {
4571 buf[0] = v >> 8;
4572 buf[1] = v;
4573 return 2;
4574 }
4575 }
4576
4577 void
4578 sim_info (SIM_DESC sd, int verbose)
4579 {
4580 double timetaken = (double) h8_get_ticks (sd) / (double) now_persec ();
4581 double virttime = h8_get_cycles (sd) / 10.0e6;
4582
4583 sim_io_printf (sd, "\n\n#instructions executed %10d\n", h8_get_insts (sd));
4584 sim_io_printf (sd, "#cycles (v approximate) %10d\n", h8_get_cycles (sd));
4585 sim_io_printf (sd, "#real time taken %10.4f\n", timetaken);
4586 sim_io_printf (sd, "#virtual time taken %10.4f\n", virttime);
4587 if (timetaken != 0.0)
4588 sim_io_printf (sd, "#simulation ratio %10.4f\n", virttime / timetaken);
4589
4590 #ifdef ADEBUG
4591 /* This to be conditional on `what' (aka `verbose'),
4592 however it was never passed as non-zero. */
4593 if (1)
4594 {
4595 int i;
4596 for (i = 0; i < O_LAST; i++)
4597 {
4598 if (h8_get_stats (sd, i))
4599 sim_io_printf (sd, "%d: %d\n", i, h8_get_stats (sd, i));
4600 }
4601 }
4602 #endif
4603 }
4604
4605 /* Indicate whether the cpu is an H8/300 or H8/300H.
4606 FLAG is non-zero for the H8/300H. */
4607
4608 void
4609 set_h8300h (unsigned long machine)
4610 {
4611 /* FIXME: Much of the code in sim_load can be moved to sim_open.
4612 This function being replaced by a sim_open:ARGV configuration
4613 option. */
4614
4615 h8300hmode = h8300smode = h8300sxmode = h8300_normal_mode = 0;
4616
4617 if (machine == bfd_mach_h8300sx || machine == bfd_mach_h8300sxn)
4618 h8300sxmode = 1;
4619
4620 if (machine == bfd_mach_h8300s || machine == bfd_mach_h8300sn || h8300sxmode)
4621 h8300smode = 1;
4622
4623 if (machine == bfd_mach_h8300h || machine == bfd_mach_h8300hn || h8300smode)
4624 h8300hmode = 1;
4625
4626 if(machine == bfd_mach_h8300hn || machine == bfd_mach_h8300sn || machine == bfd_mach_h8300sxn)
4627 h8300_normal_mode = 1;
4628 }
4629
4630 /* H8300-specific options.
4631 TODO: These really should be merged into the common model modules. */
4632 typedef enum {
4633 OPTION_H8300H,
4634 OPTION_H8300S,
4635 OPTION_H8300SX
4636 } H8300_OPTIONS;
4637
4638 static SIM_RC
4639 h8300_option_handler (SIM_DESC sd, sim_cpu *cpu ATTRIBUTE_UNUSED, int opt,
4640 char *arg, int is_command ATTRIBUTE_UNUSED)
4641 {
4642 switch ((H8300_OPTIONS) opt)
4643 {
4644 case OPTION_H8300H:
4645 set_h8300h (bfd_mach_h8300h);
4646 break;
4647 case OPTION_H8300S:
4648 set_h8300h (bfd_mach_h8300s);
4649 break;
4650 case OPTION_H8300SX:
4651 set_h8300h (bfd_mach_h8300sx);
4652 break;
4653
4654 default:
4655 /* We'll actually never get here; the caller handles the error
4656 case. */
4657 sim_io_eprintf (sd, "Unknown option `%s'\n", arg);
4658 return SIM_RC_FAIL;
4659 }
4660
4661 return SIM_RC_OK;
4662 }
4663
4664 static const OPTION h8300_options[] =
4665 {
4666 { {"h8300h", no_argument, NULL, OPTION_H8300H},
4667 'h', NULL, "Indicate the CPU is H8/300H",
4668 h8300_option_handler },
4669 { {"h8300s", no_argument, NULL, OPTION_H8300S},
4670 'S', NULL, "Indicate the CPU is H8S",
4671 h8300_option_handler },
4672 { {"h8300sx", no_argument, NULL, OPTION_H8300SX},
4673 'x', NULL, "Indicate the CPU is H8SX",
4674 h8300_option_handler },
4675 { {NULL, no_argument, NULL, 0}, '\0', NULL, NULL, NULL, NULL }
4676 };
4677
4678 static sim_cia
4679 h8300_pc_get (sim_cpu *cpu)
4680 {
4681 return cpu->pc;
4682 }
4683
4684 static void
4685 h8300_pc_set (sim_cpu *cpu, sim_cia pc)
4686 {
4687 cpu->pc = pc;
4688 }
4689
4690 /* Cover function of sim_state_free to free the cpu buffers as well. */
4691
4692 static void
4693 free_state (SIM_DESC sd)
4694 {
4695 if (STATE_MODULES (sd) != NULL)
4696 sim_module_uninstall (sd);
4697
4698 /* Fixme: free buffers in _sim_cpu. */
4699 sim_state_free (sd);
4700 }
4701
4702 SIM_DESC
4703 sim_open (SIM_OPEN_KIND kind,
4704 struct host_callback_struct *callback,
4705 struct bfd *abfd,
4706 char * const *argv)
4707 {
4708 int i;
4709 SIM_DESC sd;
4710 sim_cpu *cpu;
4711
4712 sd = sim_state_alloc (kind, callback);
4713
4714 /* The cpu data is kept in a separately allocated chunk of memory. */
4715 if (sim_cpu_alloc_all (sd, 1, /*cgen_cpu_max_extra_bytes ()*/0) != SIM_RC_OK)
4716 {
4717 free_state (sd);
4718 return 0;
4719 }
4720
4721 cpu = STATE_CPU (sd, 0);
4722 SIM_ASSERT (STATE_MAGIC (sd) == SIM_MAGIC_NUMBER);
4723 cpu->regs[SBR_REGNUM] = 0xFFFFFF00;
4724 /* sim_cpu object is new, so some initialization is needed. */
4725 init_pointers_needed = 1;
4726
4727 if (sim_pre_argv_init (sd, argv[0]) != SIM_RC_OK)
4728 {
4729 free_state (sd);
4730 return 0;
4731 }
4732
4733 if (sim_add_option_table (sd, NULL, h8300_options) != SIM_RC_OK)
4734 {
4735 free_state (sd);
4736 return 0;
4737 }
4738
4739 /* The parser will print an error message for us, so we silently return. */
4740 if (sim_parse_args (sd, argv) != SIM_RC_OK)
4741 {
4742 /* Uninstall the modules to avoid memory leaks,
4743 file descriptor leaks, etc. */
4744 free_state (sd);
4745 return 0;
4746 }
4747
4748 /* Check for/establish the a reference program image. */
4749 if (sim_analyze_program (sd,
4750 (STATE_PROG_ARGV (sd) != NULL
4751 ? *STATE_PROG_ARGV (sd)
4752 : NULL), abfd) != SIM_RC_OK)
4753 {
4754 free_state (sd);
4755 return 0;
4756 }
4757
4758 /* Establish any remaining configuration options. */
4759 if (sim_config (sd) != SIM_RC_OK)
4760 {
4761 free_state (sd);
4762 return 0;
4763 }
4764
4765 if (sim_post_argv_init (sd) != SIM_RC_OK)
4766 {
4767 /* Uninstall the modules to avoid memory leaks,
4768 file descriptor leaks, etc. */
4769 free_state (sd);
4770 return 0;
4771 }
4772
4773 /* CPU specific initialization. */
4774 for (i = 0; i < MAX_NR_PROCESSORS; ++i)
4775 {
4776 SIM_CPU *cpu = STATE_CPU (sd, i);
4777
4778 CPU_REG_FETCH (cpu) = h8300_reg_fetch;
4779 CPU_REG_STORE (cpu) = h8300_reg_store;
4780 CPU_PC_FETCH (cpu) = h8300_pc_get;
4781 CPU_PC_STORE (cpu) = h8300_pc_set;
4782 }
4783
4784 /* sim_hw_configure (sd); */
4785
4786 /* FIXME: Much of the code in sim_load can be moved here. */
4787
4788 return sd;
4789 }
4790
4791 /* Called by gdb to load a program into memory. */
4792
4793 SIM_RC
4794 sim_load (SIM_DESC sd, const char *prog, bfd *abfd, int from_tty)
4795 {
4796 bfd *prog_bfd;
4797
4798 /* FIXME: The code below that sets a specific variant of the H8/300
4799 being simulated should be moved to sim_open(). */
4800
4801 /* See if the file is for the H8/300 or H8/300H. */
4802 /* ??? This may not be the most efficient way. The z8k simulator
4803 does this via a different mechanism (INIT_EXTRA_SYMTAB_INFO). */
4804 if (abfd != NULL)
4805 prog_bfd = abfd;
4806 else
4807 prog_bfd = bfd_openr (prog, NULL);
4808 if (prog_bfd != NULL)
4809 {
4810 /* Set the cpu type. We ignore failure from bfd_check_format
4811 and bfd_openr as sim_load_file checks too. */
4812 if (bfd_check_format (prog_bfd, bfd_object))
4813 {
4814 set_h8300h (bfd_get_mach (prog_bfd));
4815 }
4816 }
4817
4818 /* If we're using gdb attached to the simulator, then we have to
4819 reallocate memory for the simulator.
4820
4821 When gdb first starts, it calls fetch_registers (among other
4822 functions), which in turn calls init_pointers, which allocates
4823 simulator memory.
4824
4825 The problem is when we do that, we don't know whether we're
4826 debugging an H8/300 or H8/300H program.
4827
4828 This is the first point at which we can make that determination,
4829 so we just reallocate memory now; this will also allow us to handle
4830 switching between H8/300 and H8/300H programs without exiting
4831 gdb. */
4832
4833 if (h8300smode && !h8300_normal_mode)
4834 memory_size = H8300S_MSIZE;
4835 else if (h8300hmode && !h8300_normal_mode)
4836 memory_size = H8300H_MSIZE;
4837 else
4838 memory_size = H8300_MSIZE;
4839
4840 if (h8_get_memory_buf (sd))
4841 free (h8_get_memory_buf (sd));
4842 if (h8_get_eightbit_buf (sd))
4843 free (h8_get_eightbit_buf (sd));
4844
4845 h8_set_memory_buf (sd, (unsigned char *)
4846 calloc (sizeof (char), memory_size));
4847 sd->memory_size = memory_size;
4848 h8_set_eightbit_buf (sd, (unsigned char *) calloc (sizeof (char), 256));
4849
4850 /* `msize' must be a power of two. */
4851 if ((memory_size & (memory_size - 1)) != 0)
4852 {
4853 sim_io_printf (sd, "sim_load: bad memory size.\n");
4854 return SIM_RC_FAIL;
4855 }
4856 h8_set_mask (sd, memory_size - 1);
4857
4858 if (sim_load_file (sd, STATE_MY_NAME (sd), STATE_CALLBACK (sd), prog,
4859 prog_bfd, STATE_OPEN_KIND (sd) == SIM_OPEN_DEBUG,
4860 0, sim_write)
4861 == NULL)
4862 {
4863 /* Close the bfd if we opened it. */
4864 if (abfd == NULL && prog_bfd != NULL)
4865 bfd_close (prog_bfd);
4866 return SIM_RC_FAIL;
4867 }
4868
4869 /* Close the bfd if we opened it. */
4870 if (abfd == NULL && prog_bfd != NULL)
4871 bfd_close (prog_bfd);
4872 return SIM_RC_OK;
4873 }
4874
4875 SIM_RC
4876 sim_create_inferior (SIM_DESC sd, struct bfd *abfd,
4877 char * const *argv, char * const *env)
4878 {
4879 int i = 0;
4880 int len_arg = 0;
4881 int no_of_args = 0;
4882
4883 if (abfd != NULL)
4884 h8_set_pc (sd, bfd_get_start_address (abfd));
4885 else
4886 h8_set_pc (sd, 0);
4887
4888 /* Command Line support. */
4889 if (argv != NULL)
4890 {
4891 /* Counting the no. of commandline arguments. */
4892 for (no_of_args = 0; argv[no_of_args] != NULL; no_of_args++)
4893 continue;
4894
4895 /* Allocating memory for the argv pointers. */
4896 h8_set_command_line (sd, (char **) malloc ((sizeof (char *))
4897 * (no_of_args + 1)));
4898
4899 for (i = 0; i < no_of_args; i++)
4900 {
4901 /* Copying the argument string. */
4902 h8_set_cmdline_arg (sd, i, (char *) strdup (argv[i]));
4903 }
4904 h8_set_cmdline_arg (sd, i, NULL);
4905 }
4906
4907 return SIM_RC_OK;
4908 }
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