2 * Simulator for the Renesas (formerly Hitachi) H8/300 architecture.
4 * Written by Steve Chamberlain of Cygnus Support. sac@cygnus.com
6 * This file is part of H8/300 sim
9 * THIS SOFTWARE IS NOT COPYRIGHTED
11 * Cygnus offers the following for use in the public domain. Cygnus makes no
12 * warranty with regard to the software or its performance and the user
13 * accepts the software "AS IS" with all faults.
15 * CYGNUS DISCLAIMS ANY WARRANTIES, EXPRESS OR IMPLIED, WITH REGARD TO THIS
16 * SOFTWARE INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
17 * AND FITNESS FOR A PARTICULAR PURPOSE.
20 /* This must come before any other includes. */
26 #ifdef HAVE_SYS_PARAM_H
27 #include <sys/param.h>
32 #include "gdb/sim-h8300.h"
34 #include "sys/types.h"
35 #include "sim-options.h"
36 #include "sim-signal.h"
37 #include "sim/callback.h"
45 static int memory_size
;
47 #define X(op, size) (op * 4 + size)
49 #define SP (h8300hmode && !h8300_normal_mode ? SL : SW)
51 #define h8_opcodes ops
53 #include "opcode/h8300.h"
55 /* CPU data object: */
58 h8_get_pc (SIM_DESC sd
)
60 return (STATE_CPU (sd
, 0)) -> pc
;
64 h8_set_pc (SIM_DESC sd
, unsigned int val
)
66 (STATE_CPU (sd
, 0)) -> pc
= val
;
70 h8_get_ccr (SIM_DESC sd
)
72 return (STATE_CPU (sd
, 0)) -> regs
[CCR_REGNUM
];
76 h8_set_ccr (SIM_DESC sd
, unsigned int val
)
78 (STATE_CPU (sd
, 0)) -> regs
[CCR_REGNUM
] = val
;
82 h8_get_exr (SIM_DESC sd
)
84 return (STATE_CPU (sd
, 0)) -> regs
[EXR_REGNUM
];
88 h8_set_exr (SIM_DESC sd
, unsigned int val
)
90 (STATE_CPU (sd
, 0)) -> regs
[EXR_REGNUM
] = val
;
94 h8_get_sbr (SIM_DESC sd
)
96 return (STATE_CPU (sd
, 0)) -> regs
[SBR_REGNUM
];
100 h8_set_sbr (SIM_DESC sd
, int val
)
102 (STATE_CPU (sd
, 0)) -> regs
[SBR_REGNUM
] = val
;
106 h8_get_vbr (SIM_DESC sd
)
108 return (STATE_CPU (sd
, 0)) -> regs
[VBR_REGNUM
];
112 h8_set_vbr (SIM_DESC sd
, int val
)
114 (STATE_CPU (sd
, 0)) -> regs
[VBR_REGNUM
] = val
;
118 h8_get_mask (SIM_DESC sd
)
120 return (STATE_CPU (sd
, 0)) -> mask
;
124 h8_set_mask (SIM_DESC sd
, int val
)
126 (STATE_CPU (sd
, 0)) -> mask
= val
;
130 h8_get_exception (SIM_DESC sd
)
132 return (STATE_CPU (sd
, 0)) -> exception
;
136 h8_set_exception (SIM_DESC sd
, int val
)
138 (STATE_CPU (sd
, 0)) -> exception
= val
;
141 static enum h8300_sim_state
142 h8_get_state (SIM_DESC sd
)
144 return H8300_SIM_STATE (sd
)->state
;
148 h8_set_state (SIM_DESC sd
, enum h8300_sim_state val
)
150 H8300_SIM_STATE (sd
)->state
= val
;
154 h8_get_cycles (SIM_DESC sd
)
156 return (STATE_CPU (sd
, 0)) -> regs
[CYCLE_REGNUM
];
160 h8_set_cycles (SIM_DESC sd
, unsigned int val
)
162 (STATE_CPU (sd
, 0)) -> regs
[CYCLE_REGNUM
] = val
;
166 h8_get_insts (SIM_DESC sd
)
168 return (STATE_CPU (sd
, 0)) -> regs
[INST_REGNUM
];
172 h8_set_insts (SIM_DESC sd
, unsigned int val
)
174 (STATE_CPU (sd
, 0)) -> regs
[INST_REGNUM
] = val
;
178 h8_get_ticks (SIM_DESC sd
)
180 return (STATE_CPU (sd
, 0)) -> regs
[TICK_REGNUM
];
184 h8_set_ticks (SIM_DESC sd
, unsigned int val
)
186 (STATE_CPU (sd
, 0)) -> regs
[TICK_REGNUM
] = val
;
190 h8_get_mach (SIM_DESC sd
)
192 return (STATE_CPU (sd
, 0)) -> regs
[MACH_REGNUM
];
196 h8_set_mach (SIM_DESC sd
, unsigned int val
)
198 (STATE_CPU (sd
, 0)) -> regs
[MACH_REGNUM
] = val
;
202 h8_get_macl (SIM_DESC sd
)
204 return (STATE_CPU (sd
, 0)) -> regs
[MACL_REGNUM
];
208 h8_set_macl (SIM_DESC sd
, unsigned int val
)
210 (STATE_CPU (sd
, 0)) -> regs
[MACL_REGNUM
] = val
;
213 static unsigned int *
214 h8_get_reg_buf (SIM_DESC sd
)
216 return &(((STATE_CPU (sd
, 0)) -> regs
)[0]);
220 h8_get_reg (SIM_DESC sd
, int regnum
)
222 return (STATE_CPU (sd
, 0)) -> regs
[regnum
];
226 h8_set_reg (SIM_DESC sd
, int regnum
, int val
)
228 (STATE_CPU (sd
, 0)) -> regs
[regnum
] = val
;
233 h8_get_stats (SIM_DESC sd
, int idx
)
235 return H8300_SIM_STATE (sd
)->stats
[idx
];
239 h8_increment_stats (SIM_DESC sd
, int idx
)
241 H8300_SIM_STATE (sd
)->stats
[idx
] ++;
245 static unsigned char *
246 h8_get_memory_buf (SIM_DESC sd
)
248 return (STATE_CPU (sd
, 0)) -> memory
;
252 h8_set_memory_buf (SIM_DESC sd
, unsigned char *ptr
)
254 (STATE_CPU (sd
, 0)) -> memory
= ptr
;
258 h8_get_memory (SIM_DESC sd
, int idx
)
260 ASSERT (idx
< memory_size
);
261 return (STATE_CPU (sd
, 0)) -> memory
[idx
];
265 h8_set_memory (SIM_DESC sd
, int idx
, unsigned int val
)
267 ASSERT (idx
< memory_size
);
268 (STATE_CPU (sd
, 0)) -> memory
[idx
] = (unsigned char) val
;
272 h8_get_delayed_branch (SIM_DESC sd
)
274 return (STATE_CPU (sd
, 0)) -> delayed_branch
;
278 h8_set_delayed_branch (SIM_DESC sd
, unsigned int dest
)
280 (STATE_CPU (sd
, 0)) -> delayed_branch
= dest
;
284 h8_get_command_line (SIM_DESC sd
)
286 return (STATE_CPU (sd
, 0)) -> command_line
;
290 h8_set_command_line (SIM_DESC sd
, char ** val
)
292 (STATE_CPU (sd
, 0)) -> command_line
= val
;
296 h8_get_cmdline_arg (SIM_DESC sd
, int index
)
298 return (STATE_CPU (sd
, 0)) -> command_line
[index
];
302 h8_set_cmdline_arg (SIM_DESC sd
, int index
, char * val
)
304 (STATE_CPU (sd
, 0)) -> command_line
[index
] = val
;
307 /* MAC Saturation Mode */
309 h8_get_macS (SIM_DESC sd
)
311 return (STATE_CPU (sd
, 0)) -> macS
;
316 h8_set_macS (SIM_DESC sd
, int val
)
318 (STATE_CPU (sd
, 0)) -> macS
= (val
!= 0);
324 h8_get_macZ (SIM_DESC sd
)
326 return (STATE_CPU (sd
, 0)) -> macZ
;
330 h8_set_macZ (SIM_DESC sd
, int val
)
332 (STATE_CPU (sd
, 0)) -> macZ
= (val
!= 0);
335 /* MAC Negative Flag */
337 h8_get_macN (SIM_DESC sd
)
339 return (STATE_CPU (sd
, 0)) -> macN
;
343 h8_set_macN (SIM_DESC sd
, int val
)
345 (STATE_CPU (sd
, 0)) -> macN
= (val
!= 0);
348 /* MAC Overflow Flag */
350 h8_get_macV (SIM_DESC sd
)
352 return (STATE_CPU (sd
, 0)) -> macV
;
356 h8_set_macV (SIM_DESC sd
, int val
)
358 (STATE_CPU (sd
, 0)) -> macV
= (val
!= 0);
361 /* End CPU data object. */
363 /* The rate at which to call the host's poll_quit callback. */
365 enum { POLL_QUIT_INTERVAL
= 0x80000 };
367 #define LOW_BYTE(x) ((x) & 0xff)
368 #define HIGH_BYTE(x) (((x) >> 8) & 0xff)
369 #define P(X, Y) ((X << 8) | Y)
378 #define I (intMaskBit != 0)
380 #define BUILDSR(SD) \
381 h8_set_ccr (SD, (I << 7) | (UI << 6) | (H << 5) | (U << 4) \
382 | (N << 3) | (Z << 2) | (V << 1) | C)
385 /* Get Status Register (flags). */ \
386 c = (h8_get_ccr (sd) >> 0) & 1; \
387 v = (h8_get_ccr (sd) >> 1) & 1; \
388 nz = !((h8_get_ccr (sd) >> 2) & 1); \
389 n = (h8_get_ccr (sd) >> 3) & 1; \
390 u = (h8_get_ccr (sd) >> 4) & 1; \
391 h = (h8_get_ccr (sd) >> 5) & 1; \
392 ui = ((h8_get_ccr (sd) >> 6) & 1); \
393 intMaskBit = (h8_get_ccr (sd) >> 7) & 1
396 #ifdef __CHAR_IS_SIGNED__
397 #define SEXTCHAR(x) ((char) (x))
401 #define SEXTCHAR(x) ((x & 0x80) ? (x | ~0xff) : x & 0xff)
404 #define UEXTCHAR(x) ((x) & 0xff)
405 #define UEXTSHORT(x) ((x) & 0xffff)
406 #define SEXTSHORT(x) ((short) (x))
410 int h8300_normal_mode
= 0;
416 return time (0); /* WinXX HAS UNIX like 'time', so why not use it? */
438 return (h8300hmode
&& !h8300_normal_mode
)? SL
: SW
;
443 /* Simulate an indirection / dereference.
444 return 0 for success, -1 for failure.
448 lvalue (SIM_DESC sd
, int x
, int rn
, unsigned int *val
)
450 SIM_CPU
*cpu
= STATE_CPU (sd
, 0);
452 if (val
== NULL
) /* Paranoia. */
458 if (rn
== ZERO_REGNUM
)
459 *val
= X (OP_IMM
, SP
);
461 *val
= X (OP_REG
, SP
);
464 *val
= X (OP_MEM
, SP
);
467 sim_engine_halt (sd
, cpu
, NULL
, NULL_CIA
, sim_stopped
, SIM_SIGSEGV
);
474 cmdline_location(void)
476 if (h8300smode
&& !h8300_normal_mode
)
478 else if (h8300hmode
&& !h8300_normal_mode
)
485 decode (SIM_DESC sd
, int addr
, unsigned char *data
, decoded_inst
*dst
)
487 int cst
[3] = {0, 0, 0};
488 int reg
[3] = {0, 0, 0};
489 int rdisp
[3] = {0, 0, 0};
491 const struct h8_opcode
*q
;
496 /* Find the exact opcode/arg combo. */
497 for (q
= h8_opcodes
; q
->name
; q
++)
499 const op_type
*nib
= q
->data
.nib
;
500 unsigned int len
= 0;
502 if ((q
->available
== AV_H8SX
&& !h8300sxmode
) ||
503 (q
->available
== AV_H8S
&& !h8300smode
) ||
504 (q
->available
== AV_H8H
&& !h8300hmode
))
507 cst
[0] = cst
[1] = cst
[2] = 0;
508 reg
[0] = reg
[1] = reg
[2] = 0;
509 rdisp
[0] = rdisp
[1] = rdisp
[2] = 0;
513 op_type looking_for
= *nib
;
514 int thisnib
= data
[len
/ 2];
516 thisnib
= (len
& 1) ? (thisnib
& 0xf) : ((thisnib
>> 4) & 0xf);
517 opnum
= ((looking_for
& OP3
) ? 2 :
518 (looking_for
& DST
) ? 1 : 0);
520 if (looking_for
< 16 && looking_for
>= 0)
522 if (looking_for
!= thisnib
)
527 if (looking_for
& B31
)
529 if (!((thisnib
& 0x8) != 0))
532 looking_for
= (op_type
) (looking_for
& ~B31
);
535 else if (looking_for
& B30
)
537 if (!((thisnib
& 0x8) == 0))
540 looking_for
= (op_type
) (looking_for
& ~B30
);
543 if (looking_for
& B21
)
545 if (!((thisnib
& 0x4) != 0))
548 looking_for
= (op_type
) (looking_for
& ~B21
);
551 else if (looking_for
& B20
)
553 if (!((thisnib
& 0x4) == 0))
556 looking_for
= (op_type
) (looking_for
& ~B20
);
559 if (looking_for
& B11
)
561 if (!((thisnib
& 0x2) != 0))
564 looking_for
= (op_type
) (looking_for
& ~B11
);
567 else if (looking_for
& B10
)
569 if (!((thisnib
& 0x2) == 0))
572 looking_for
= (op_type
) (looking_for
& ~B10
);
575 if (looking_for
& B01
)
577 if (!((thisnib
& 0x1) != 0))
580 looking_for
= (op_type
) (looking_for
& ~B01
);
583 else if (looking_for
& B00
)
585 if (!((thisnib
& 0x1) == 0))
588 looking_for
= (op_type
) (looking_for
& ~B00
);
591 if (looking_for
& IGNORE
)
593 /* Hitachi has declared that IGNORE must be zero. */
597 else if ((looking_for
& MODE
) == DATA
)
599 ; /* Skip embedded data. */
601 else if ((looking_for
& MODE
) == DBIT
)
603 /* Exclude adds/subs by looking at bit 0 and 2, and
604 make sure the operand size, either w or l,
605 matches by looking at bit 1. */
606 if ((looking_for
& 7) != (thisnib
& 7))
609 cst
[opnum
] = (thisnib
& 0x8) ? 2 : 1;
611 else if ((looking_for
& MODE
) == REG
||
612 (looking_for
& MODE
) == LOWREG
||
613 (looking_for
& MODE
) == IND
||
614 (looking_for
& MODE
) == PREINC
||
615 (looking_for
& MODE
) == POSTINC
||
616 (looking_for
& MODE
) == PREDEC
||
617 (looking_for
& MODE
) == POSTDEC
)
619 reg
[opnum
] = thisnib
;
621 else if (looking_for
& CTRL
)
624 if (((looking_for
& MODE
) == CCR
&& (thisnib
!= C_CCR
)) ||
625 ((looking_for
& MODE
) == EXR
&& (thisnib
!= C_EXR
)) ||
626 ((looking_for
& MODE
) == MACH
&& (thisnib
!= C_MACH
)) ||
627 ((looking_for
& MODE
) == MACL
&& (thisnib
!= C_MACL
)) ||
628 ((looking_for
& MODE
) == VBR
&& (thisnib
!= C_VBR
)) ||
629 ((looking_for
& MODE
) == SBR
&& (thisnib
!= C_SBR
)))
631 if (((looking_for
& MODE
) == CCR_EXR
&&
632 (thisnib
!= C_CCR
&& thisnib
!= C_EXR
)) ||
633 ((looking_for
& MODE
) == VBR_SBR
&&
634 (thisnib
!= C_VBR
&& thisnib
!= C_SBR
)) ||
635 ((looking_for
& MODE
) == MACREG
&&
636 (thisnib
!= C_MACH
&& thisnib
!= C_MACL
)))
638 if (((looking_for
& MODE
) == CC_EX_VB_SB
&&
639 (thisnib
!= C_CCR
&& thisnib
!= C_EXR
&&
640 thisnib
!= C_VBR
&& thisnib
!= C_SBR
)))
643 reg
[opnum
] = thisnib
;
645 else if ((looking_for
& MODE
) == ABS
)
647 /* Absolute addresses are unsigned. */
648 switch (looking_for
& SIZE
)
651 cst
[opnum
] = UEXTCHAR (data
[len
/ 2]);
655 cst
[opnum
] = (data
[len
/ 2] << 8) + data
[len
/ 2 + 1];
659 (data
[len
/ 2 + 0] << 24) +
660 (data
[len
/ 2 + 1] << 16) +
661 (data
[len
/ 2 + 2] << 8) +
665 printf ("decode: bad size ABS: %d\n",
666 (looking_for
& SIZE
));
670 else if ((looking_for
& MODE
) == DISP
||
671 (looking_for
& MODE
) == PCREL
||
672 (looking_for
& MODE
) == INDEXB
||
673 (looking_for
& MODE
) == INDEXW
||
674 (looking_for
& MODE
) == INDEXL
)
676 switch (looking_for
& SIZE
)
679 cst
[opnum
] = thisnib
& 3;
682 cst
[opnum
] = SEXTCHAR (data
[len
/ 2]);
685 cst
[opnum
] = (data
[len
/ 2] << 8) + data
[len
/ 2 + 1];
686 cst
[opnum
] = (short) cst
[opnum
]; /* Sign extend. */
689 cst
[opnum
] = (data
[len
/ 2] << 8) + data
[len
/ 2 + 1];
693 (data
[len
/ 2 + 0] << 24) +
694 (data
[len
/ 2 + 1] << 16) +
695 (data
[len
/ 2 + 2] << 8) +
699 printf ("decode: bad size DISP/PCREL/INDEX: %d\n",
700 (looking_for
& SIZE
));
704 else if ((looking_for
& SIZE
) == L_16
||
705 (looking_for
& SIZE
) == L_16U
)
707 cst
[opnum
] = (data
[len
/ 2] << 8) + data
[len
/ 2 + 1];
708 /* Immediates are always unsigned. */
709 if ((looking_for
& SIZE
) != L_16U
&&
710 (looking_for
& MODE
) != IMM
)
711 cst
[opnum
] = (short) cst
[opnum
]; /* Sign extend. */
713 else if (looking_for
& ABSJMP
)
715 switch (looking_for
& SIZE
) {
717 cst
[opnum
] = (data
[1] << 16) | (data
[2] << 8) | (data
[3]);
721 (data
[len
/ 2 + 0] << 24) +
722 (data
[len
/ 2 + 1] << 16) +
723 (data
[len
/ 2 + 2] << 8) +
727 printf ("decode: bad size ABSJMP: %d\n",
728 (looking_for
& SIZE
));
732 else if ((looking_for
& MODE
) == MEMIND
)
734 cst
[opnum
] = data
[1];
736 else if ((looking_for
& MODE
) == VECIND
)
738 if(h8300_normal_mode
)
739 cst
[opnum
] = ((data
[1] & 0x7f) + 0x80) * 2;
741 cst
[opnum
] = ((data
[1] & 0x7f) + 0x80) * 4;
742 cst
[opnum
] += h8_get_vbr (sd
); /* Add vector base reg. */
744 else if ((looking_for
& SIZE
) == L_32
)
749 (data
[i
+ 0] << 24) |
750 (data
[i
+ 1] << 16) |
754 else if ((looking_for
& SIZE
) == L_24
)
759 (data
[i
+ 0] << 16) |
763 else if (looking_for
& DISPREG
)
765 rdisp
[opnum
] = thisnib
& 0x7;
767 else if ((looking_for
& MODE
) == KBIT
)
784 else if ((looking_for
& SIZE
) == L_8
)
786 if ((looking_for
& MODE
) == ABS
)
788 /* Will be combined with contents of SBR_REGNUM
789 by fetch (). For all modes except h8sx, this
790 will always contain the value 0xFFFFFF00. */
791 cst
[opnum
] = data
[len
/ 2] & 0xff;
795 cst
[opnum
] = data
[len
/ 2] & 0xff;
798 else if ((looking_for
& SIZE
) == L_2
)
800 cst
[opnum
] = thisnib
& 3;
802 else if ((looking_for
& SIZE
) == L_3
||
803 (looking_for
& SIZE
) == L_3NZ
)
805 cst
[opnum
] = thisnib
& 7;
806 if (cst
[opnum
] == 0 && (looking_for
& SIZE
) == L_3NZ
)
809 else if ((looking_for
& SIZE
) == L_4
)
811 cst
[opnum
] = thisnib
& 15;
813 else if ((looking_for
& SIZE
) == L_5
)
815 cst
[opnum
] = data
[len
/ 2] & 0x1f;
817 else if (looking_for
== E
)
822 /* Fill in the args. */
824 const op_type
*args
= q
->args
.nib
;
829 nargs
< 3 && *args
!= E
;
835 opnum
= ((x
& OP3
) ? 2 :
844 if ((x
& MODE
) == IMM
||
845 (x
& MODE
) == KBIT
||
848 /* Use the instruction to determine
850 p
->type
= X (OP_IMM
, OP_SIZE (q
->how
));
851 p
->literal
= cst
[opnum
];
853 else if ((x
& MODE
) == CONST_2
||
854 (x
& MODE
) == CONST_4
||
855 (x
& MODE
) == CONST_8
||
856 (x
& MODE
) == CONST_16
)
858 /* Use the instruction to determine
860 p
->type
= X (OP_IMM
, OP_SIZE (q
->how
));
862 case CONST_2
: p
->literal
= 2; break;
863 case CONST_4
: p
->literal
= 4; break;
864 case CONST_8
: p
->literal
= 8; break;
865 case CONST_16
: p
->literal
= 16; break;
868 else if ((x
& MODE
) == REG
)
870 p
->type
= X (OP_REG
, bitfrom (x
));
873 else if ((x
& MODE
) == LOWREG
)
875 p
->type
= X (OP_LOWREG
, bitfrom (x
));
878 else if ((x
& MODE
) == PREINC
)
880 /* Use the instruction to determine
882 p
->type
= X (OP_PREINC
, OP_SIZE (q
->how
));
883 p
->reg
= reg
[opnum
] & 0x7;
885 else if ((x
& MODE
) == POSTINC
)
887 /* Use the instruction to determine
889 p
->type
= X (OP_POSTINC
, OP_SIZE (q
->how
));
890 p
->reg
= reg
[opnum
] & 0x7;
892 else if ((x
& MODE
) == PREDEC
)
894 /* Use the instruction to determine
896 p
->type
= X (OP_PREDEC
, OP_SIZE (q
->how
));
897 p
->reg
= reg
[opnum
] & 0x7;
899 else if ((x
& MODE
) == POSTDEC
)
901 /* Use the instruction to determine
903 p
->type
= X (OP_POSTDEC
, OP_SIZE (q
->how
));
904 p
->reg
= reg
[opnum
] & 0x7;
906 else if ((x
& MODE
) == IND
)
908 /* Note: an indirect is transformed into
909 a displacement of zero.
911 /* Use the instruction to determine
913 p
->type
= X (OP_DISP
, OP_SIZE (q
->how
));
914 p
->reg
= reg
[opnum
] & 0x7;
916 if (OP_KIND (q
->how
) == O_JSR
||
917 OP_KIND (q
->how
) == O_JMP
)
918 if (lvalue (sd
, p
->type
, p
->reg
, (unsigned int *)&p
->type
))
921 else if ((x
& MODE
) == ABS
)
923 /* Note: a 16 or 32 bit ABS is transformed into a
924 displacement from pseudo-register ZERO_REGNUM,
925 which is always zero. An 8 bit ABS becomes
926 a displacement from SBR_REGNUM.
928 /* Use the instruction to determine
930 p
->type
= X (OP_DISP
, OP_SIZE (q
->how
));
931 p
->literal
= cst
[opnum
];
933 /* 8-bit ABS is displacement from SBR.
934 16 and 32-bit ABS are displacement from ZERO.
935 (SBR will always be zero except for h8/sx)
937 if ((x
& SIZE
) == L_8
)
940 p
->reg
= ZERO_REGNUM
;;
942 else if ((x
& MODE
) == MEMIND
||
943 (x
& MODE
) == VECIND
)
945 /* Size doesn't matter. */
946 p
->type
= X (OP_MEM
, SB
);
947 p
->literal
= cst
[opnum
];
948 if (OP_KIND (q
->how
) == O_JSR
||
949 OP_KIND (q
->how
) == O_JMP
)
950 if (lvalue (sd
, p
->type
, p
->reg
, (unsigned int *)&p
->type
))
953 else if ((x
& MODE
) == PCREL
)
955 /* Size doesn't matter. */
956 p
->type
= X (OP_PCREL
, SB
);
957 p
->literal
= cst
[opnum
];
961 p
->type
= X (OP_IMM
, SP
);
962 p
->literal
= cst
[opnum
];
964 else if ((x
& MODE
) == INDEXB
)
966 p
->type
= X (OP_INDEXB
, OP_SIZE (q
->how
));
967 p
->literal
= cst
[opnum
];
968 p
->reg
= rdisp
[opnum
];
970 else if ((x
& MODE
) == INDEXW
)
972 p
->type
= X (OP_INDEXW
, OP_SIZE (q
->how
));
973 p
->literal
= cst
[opnum
];
974 p
->reg
= rdisp
[opnum
];
976 else if ((x
& MODE
) == INDEXL
)
978 p
->type
= X (OP_INDEXL
, OP_SIZE (q
->how
));
979 p
->literal
= cst
[opnum
];
980 p
->reg
= rdisp
[opnum
];
982 else if ((x
& MODE
) == DISP
)
984 /* Yuck -- special for mova args. */
985 if (strncmp (q
->name
, "mova", 4) == 0 &&
988 /* Mova can have a DISP2 dest, with an
989 INDEXB or INDEXW src. The multiplier
990 for the displacement value is determined
991 by the src operand, not by the insn. */
993 switch (OP_KIND (dst
->src
.type
))
996 p
->type
= X (OP_DISP
, SB
);
997 p
->literal
= cst
[opnum
];
1000 p
->type
= X (OP_DISP
, SW
);
1001 p
->literal
= cst
[opnum
] * 2;
1009 p
->type
= X (OP_DISP
, OP_SIZE (q
->how
));
1010 p
->literal
= cst
[opnum
];
1011 /* DISP2 is special. */
1012 if ((x
& SIZE
) == L_2
)
1013 switch (OP_SIZE (q
->how
))
1016 case SW
: p
->literal
*= 2; break;
1017 case SL
: p
->literal
*= 4; break;
1020 p
->reg
= rdisp
[opnum
];
1027 p
->type
= X (OP_CCR
, SB
);
1030 p
->type
= X (OP_EXR
, SB
);
1033 p
->type
= X (OP_MACH
, SL
);
1036 p
->type
= X (OP_MACL
, SL
);
1039 p
->type
= X (OP_VBR
, SL
);
1042 p
->type
= X (OP_SBR
, SL
);
1046 else if ((x
& MODE
) == CCR
)
1050 else if ((x
& MODE
) == EXR
)
1055 printf ("Hmmmm 0x%x...\n", x
);
1061 /* Unary operators: treat src and dst as equivalent. */
1062 if (dst
->dst
.type
== -1)
1063 dst
->dst
= dst
->src
;
1064 if (dst
->src
.type
== -1)
1065 dst
->src
= dst
->dst
;
1067 dst
->opcode
= q
->how
;
1068 dst
->cycles
= q
->time
;
1070 /* And jsr's to these locations are turned into
1073 if (OP_KIND (dst
->opcode
) == O_JSR
)
1075 switch (dst
->src
.literal
)
1078 dst
->opcode
= O (O_SYS_OPEN
, SB
);
1081 dst
->opcode
= O (O_SYS_READ
, SB
);
1084 dst
->opcode
= O (O_SYS_WRITE
, SB
);
1087 dst
->opcode
= O (O_SYS_LSEEK
, SB
);
1090 dst
->opcode
= O (O_SYS_CLOSE
, SB
);
1093 dst
->opcode
= O (O_SYS_STAT
, SB
);
1096 dst
->opcode
= O (O_SYS_FSTAT
, SB
);
1099 dst
->opcode
= O (O_SYS_CMDLINE
, SB
);
1102 /* End of Processing for system calls. */
1105 /* Use same register is specified for source
1107 The value of source will be the value after
1108 address calculation. */
1109 if (OP_KIND (dst
->opcode
) != O_CMP
&&
1110 OP_KIND (dst
->src
.type
) == OP_REG
&&
1111 (dst
->src
.reg
& 7) == dst
->dst
.reg
) {
1112 switch (OP_KIND (dst
->dst
.type
))
1115 dst
->src
.type
= X (OP_REG_DEC
,
1116 OP_SIZE (dst
->dst
.type
));
1119 dst
->src
.type
= X (OP_REG_INC
,
1120 OP_SIZE (dst
->dst
.type
));
1123 if (OP_KIND (dst
->opcode
) == O_MOV
)
1124 dst
->src
.type
= X (OP_REG_INC
,
1125 OP_SIZE (dst
->dst
.type
));
1128 if (OP_KIND (dst
->opcode
) == O_MOV
)
1129 dst
->src
.type
= X (OP_REG_DEC
,
1130 OP_SIZE (dst
->dst
.type
));
1134 dst
->next_pc
= addr
+ len
/ 2;
1138 printf ("Don't understand 0x%x \n", looking_for
);
1149 /* Fell off the end. */
1150 dst
->opcode
= O (O_ILL
, SB
);
1153 static unsigned char *breg
[32];
1154 static unsigned short *wreg
[16];
1156 #define GET_B_REG(X) *(breg[X])
1157 #define SET_B_REG(X, Y) (*(breg[X])) = (Y)
1158 #define GET_W_REG(X) *(wreg[X])
1159 #define SET_W_REG(X, Y) (*(wreg[X])) = (Y)
1160 #define GET_L_REG(X) h8_get_reg (sd, X)
1161 #define SET_L_REG(X, Y) h8_set_reg (sd, X, Y)
1163 #define GET_MEMORY_L(X) \
1164 ((X) < memory_size \
1165 ? ((h8_get_memory (sd, (X)+0) << 24) | (h8_get_memory (sd, (X)+1) << 16) \
1166 | (h8_get_memory (sd, (X)+2) << 8) | (h8_get_memory (sd, (X)+3) << 0)) \
1169 #define GET_MEMORY_W(X) \
1170 ((X) < memory_size \
1171 ? ((h8_get_memory (sd, (X)+0) << 8) | (h8_get_memory (sd, (X)+1) << 0)) \
1174 #define GET_MEMORY_B(X) \
1175 ((X) < memory_size ? h8_get_memory (sd, (X)) : 0)
1177 #define SET_MEMORY_L(X, Y) \
1178 { register unsigned char *_p; register int __y = (Y); \
1179 _p = ((X) < memory_size ? h8_get_memory_buf (sd) + (X) : 0); \
1180 _p[0] = __y >> 24; _p[1] = __y >> 16; \
1181 _p[2] = __y >> 8; _p[3] = __y >> 0; \
1184 #define SET_MEMORY_W(X, Y) \
1185 { register unsigned char *_p; register int __y = (Y); \
1186 _p = ((X) < memory_size ? h8_get_memory_buf (sd) + (X) : 0); \
1187 _p[0] = __y >> 8; _p[1] = __y; \
1190 #define SET_MEMORY_B(X, Y) \
1191 ((X) < memory_size ? h8_set_memory (sd, (X), (Y)) : 0)
1193 /* Simulate a memory fetch.
1194 Return 0 for success, -1 for failure.
1198 fetch_1 (SIM_DESC sd
, ea_type
*arg
, int *val
, int twice
)
1200 SIM_CPU
*cpu
= STATE_CPU (sd
, 0);
1202 int abs
= arg
->literal
;
1207 return -1; /* Paranoia. */
1211 /* Indexed register plus displacement mode:
1213 This new family of addressing modes are similar to OP_DISP
1214 (register plus displacement), with two differences:
1215 1) INDEXB uses only the least significant byte of the register,
1216 INDEXW uses only the least significant word, and
1217 INDEXL uses the entire register (just like OP_DISP).
1219 2) The displacement value in abs is multiplied by two
1220 for SW-sized operations, and by four for SL-size.
1222 This gives nine possible variations.
1225 case X (OP_INDEXB
, SB
):
1226 case X (OP_INDEXB
, SW
):
1227 case X (OP_INDEXB
, SL
):
1228 case X (OP_INDEXW
, SB
):
1229 case X (OP_INDEXW
, SW
):
1230 case X (OP_INDEXW
, SL
):
1231 case X (OP_INDEXL
, SB
):
1232 case X (OP_INDEXL
, SW
):
1233 case X (OP_INDEXL
, SL
):
1235 switch (OP_KIND (arg
->type
)) {
1236 case OP_INDEXB
: t
&= 0xff; break;
1237 case OP_INDEXW
: t
&= 0xffff; break;
1241 switch (OP_SIZE (arg
->type
)) {
1243 *val
= GET_MEMORY_B ((t
* 1 + abs
) & h8_get_mask (sd
));
1246 *val
= GET_MEMORY_W ((t
* 2 + abs
) & h8_get_mask (sd
));
1249 *val
= GET_MEMORY_L ((t
* 4 + abs
) & h8_get_mask (sd
));
1254 case X (OP_LOWREG
, SB
):
1255 *val
= GET_L_REG (rn
) & 0xff;
1257 case X (OP_LOWREG
, SW
):
1258 *val
= GET_L_REG (rn
) & 0xffff;
1261 case X (OP_REG
, SB
): /* Register direct, byte. */
1262 *val
= GET_B_REG (rn
);
1264 case X (OP_REG
, SW
): /* Register direct, word. */
1265 *val
= GET_W_REG (rn
);
1267 case X (OP_REG
, SL
): /* Register direct, long. */
1268 *val
= GET_L_REG (rn
);
1270 case X (OP_IMM
, SB
): /* Immediate, byte. */
1271 case X (OP_IMM
, SW
): /* Immediate, word. */
1272 case X (OP_IMM
, SL
): /* Immediate, long. */
1275 case X (OP_POSTINC
, SB
): /* Register indirect w/post-incr: byte. */
1277 r
= GET_MEMORY_B (t
& h8_get_mask (sd
));
1283 case X (OP_POSTINC
, SW
): /* Register indirect w/post-incr: word. */
1285 r
= GET_MEMORY_W (t
& h8_get_mask (sd
));
1291 case X (OP_POSTINC
, SL
): /* Register indirect w/post-incr: long. */
1293 r
= GET_MEMORY_L (t
& h8_get_mask (sd
));
1300 case X (OP_POSTDEC
, SB
): /* Register indirect w/post-decr: byte. */
1302 r
= GET_MEMORY_B (t
& h8_get_mask (sd
));
1308 case X (OP_POSTDEC
, SW
): /* Register indirect w/post-decr: word. */
1310 r
= GET_MEMORY_W (t
& h8_get_mask (sd
));
1316 case X (OP_POSTDEC
, SL
): /* Register indirect w/post-decr: long. */
1318 r
= GET_MEMORY_L (t
& h8_get_mask (sd
));
1325 case X (OP_PREDEC
, SB
): /* Register indirect w/pre-decr: byte. */
1326 t
= GET_L_REG (rn
) - 1;
1328 t
&= h8_get_mask (sd
);
1329 *val
= GET_MEMORY_B (t
);
1332 case X (OP_PREDEC
, SW
): /* Register indirect w/pre-decr: word. */
1333 t
= GET_L_REG (rn
) - 2;
1335 t
&= h8_get_mask (sd
);
1336 *val
= GET_MEMORY_W (t
);
1339 case X (OP_PREDEC
, SL
): /* Register indirect w/pre-decr: long. */
1340 t
= GET_L_REG (rn
) - 4;
1342 t
&= h8_get_mask (sd
);
1343 *val
= GET_MEMORY_L (t
);
1346 case X (OP_PREINC
, SB
): /* Register indirect w/pre-incr: byte. */
1347 t
= GET_L_REG (rn
) + 1;
1349 t
&= h8_get_mask (sd
);
1350 *val
= GET_MEMORY_B (t
);
1353 case X (OP_PREINC
, SW
): /* Register indirect w/pre-incr: long. */
1354 t
= GET_L_REG (rn
) + 2;
1356 t
&= h8_get_mask (sd
);
1357 *val
= GET_MEMORY_W (t
);
1360 case X (OP_PREINC
, SL
): /* Register indirect w/pre-incr: long. */
1361 t
= GET_L_REG (rn
) + 4;
1363 t
&= h8_get_mask (sd
);
1364 *val
= GET_MEMORY_L (t
);
1367 case X (OP_DISP
, SB
): /* Register indirect w/displacement: byte. */
1368 t
= GET_L_REG (rn
) + abs
;
1369 t
&= h8_get_mask (sd
);
1370 *val
= GET_MEMORY_B (t
);
1373 case X (OP_DISP
, SW
): /* Register indirect w/displacement: word. */
1374 t
= GET_L_REG (rn
) + abs
;
1375 t
&= h8_get_mask (sd
);
1376 *val
= GET_MEMORY_W (t
);
1379 case X (OP_DISP
, SL
): /* Register indirect w/displacement: long. */
1380 t
= GET_L_REG (rn
) + abs
;
1381 t
&= h8_get_mask (sd
);
1382 *val
=GET_MEMORY_L (t
);
1385 case X (OP_MEM
, SL
): /* Absolute memory address, long. */
1386 t
= GET_MEMORY_L (abs
);
1387 t
&= h8_get_mask (sd
);
1391 case X (OP_MEM
, SW
): /* Absolute memory address, word. */
1392 t
= GET_MEMORY_W (abs
);
1393 t
&= h8_get_mask (sd
);
1397 case X (OP_PCREL
, SB
): /* PC relative (for jump, branch etc). */
1398 case X (OP_PCREL
, SW
):
1399 case X (OP_PCREL
, SL
):
1400 case X (OP_PCREL
, SN
):
1404 case X (OP_REG_DEC
, SB
): /* Register direct, affected decrement byte. */
1405 *val
= GET_B_REG (rn
) - 1;
1407 case X (OP_REG_DEC
, SW
): /* Register direct, affected decrement word. */
1408 *val
= GET_W_REG (rn
) - 2;
1410 case X (OP_REG_DEC
, SL
): /* Register direct, affected decrement long. */
1411 *val
= GET_L_REG (rn
) - 4;
1413 case X (OP_REG_INC
, SB
): /* Register direct, affected increment byte. */
1414 *val
= GET_B_REG (rn
) + 1;
1416 case X (OP_REG_INC
, SW
): /* Register direct, affected increment word. */
1417 *val
= GET_W_REG (rn
) + 2;
1419 case X (OP_REG_INC
, SL
): /* Register direct, affected increment long. */
1420 *val
= GET_L_REG (rn
) + 4;
1423 case X (OP_MEM
, SB
): /* Why isn't this implemented? */
1425 sim_engine_halt (sd
, cpu
, NULL
, NULL_CIA
, sim_stopped
, SIM_SIGSEGV
);
1428 return 0; /* Success. */
1434 fetch (SIM_DESC sd
, ea_type
*arg
, int *val
)
1436 return fetch_1 (sd
, arg
, val
, 0);
1439 /* Fetch which will be followed by a store to the same location.
1440 The difference being that we don't want to do a post-increment
1441 or post-decrement at this time: we'll do it when we store. */
1444 fetch2 (SIM_DESC sd
, ea_type
*arg
, int *val
)
1446 return fetch_1 (sd
, arg
, val
, 1);
1449 /* Simulate a memory store.
1450 Return 0 for success, -1 for failure.
1454 store_1 (SIM_DESC sd
, ea_type
*arg
, int n
, int twice
)
1456 SIM_CPU
*cpu
= STATE_CPU (sd
, 0);
1458 int abs
= arg
->literal
;
1463 /* Indexed register plus displacement mode:
1465 This new family of addressing modes are similar to OP_DISP
1466 (register plus displacement), with two differences:
1467 1) INDEXB uses only the least significant byte of the register,
1468 INDEXW uses only the least significant word, and
1469 INDEXL uses the entire register (just like OP_DISP).
1471 2) The displacement value in abs is multiplied by two
1472 for SW-sized operations, and by four for SL-size.
1474 This gives nine possible variations.
1477 case X (OP_INDEXB
, SB
):
1478 case X (OP_INDEXB
, SW
):
1479 case X (OP_INDEXB
, SL
):
1480 case X (OP_INDEXW
, SB
):
1481 case X (OP_INDEXW
, SW
):
1482 case X (OP_INDEXW
, SL
):
1483 case X (OP_INDEXL
, SB
):
1484 case X (OP_INDEXL
, SW
):
1485 case X (OP_INDEXL
, SL
):
1487 switch (OP_KIND (arg
->type
)) {
1488 case OP_INDEXB
: t
&= 0xff; break;
1489 case OP_INDEXW
: t
&= 0xffff; break;
1493 switch (OP_SIZE (arg
->type
)) {
1495 SET_MEMORY_B ((t
* 1 + abs
) & h8_get_mask (sd
), n
);
1498 SET_MEMORY_W ((t
* 2 + abs
) & h8_get_mask (sd
), n
);
1501 SET_MEMORY_L ((t
* 4 + abs
) & h8_get_mask (sd
), n
);
1506 case X (OP_REG
, SB
): /* Register direct, byte. */
1509 case X (OP_REG
, SW
): /* Register direct, word. */
1512 case X (OP_REG
, SL
): /* Register direct, long. */
1516 case X (OP_PREDEC
, SB
): /* Register indirect w/pre-decr, byte. */
1521 t
&= h8_get_mask (sd
);
1522 SET_MEMORY_B (t
, n
);
1525 case X (OP_PREDEC
, SW
): /* Register indirect w/pre-decr, word. */
1530 t
&= h8_get_mask (sd
);
1531 SET_MEMORY_W (t
, n
);
1534 case X (OP_PREDEC
, SL
): /* Register indirect w/pre-decr, long. */
1539 t
&= h8_get_mask (sd
);
1540 SET_MEMORY_L (t
, n
);
1543 case X (OP_PREINC
, SB
): /* Register indirect w/pre-incr, byte. */
1548 t
&= h8_get_mask (sd
);
1549 SET_MEMORY_B (t
, n
);
1552 case X (OP_PREINC
, SW
): /* Register indirect w/pre-incr, word. */
1557 t
&= h8_get_mask (sd
);
1558 SET_MEMORY_W (t
, n
);
1561 case X (OP_PREINC
, SL
): /* Register indirect w/pre-incr, long. */
1566 t
&= h8_get_mask (sd
);
1567 SET_MEMORY_L (t
, n
);
1570 case X (OP_POSTDEC
, SB
): /* Register indirect w/post-decr, byte. */
1572 SET_L_REG (rn
, t
- 1);
1573 t
&= h8_get_mask (sd
);
1574 SET_MEMORY_B (t
, n
);
1577 case X (OP_POSTDEC
, SW
): /* Register indirect w/post-decr, word. */
1579 SET_L_REG (rn
, t
- 2);
1580 t
&= h8_get_mask (sd
);
1581 SET_MEMORY_W (t
, n
);
1584 case X (OP_POSTDEC
, SL
): /* Register indirect w/post-decr, long. */
1586 SET_L_REG (rn
, t
- 4);
1587 t
&= h8_get_mask (sd
);
1588 SET_MEMORY_L (t
, n
);
1591 case X (OP_POSTINC
, SB
): /* Register indirect w/post-incr, byte. */
1593 SET_L_REG (rn
, t
+ 1);
1594 t
&= h8_get_mask (sd
);
1595 SET_MEMORY_B (t
, n
);
1598 case X (OP_POSTINC
, SW
): /* Register indirect w/post-incr, word. */
1600 SET_L_REG (rn
, t
+ 2);
1601 t
&= h8_get_mask (sd
);
1602 SET_MEMORY_W (t
, n
);
1605 case X (OP_POSTINC
, SL
): /* Register indirect w/post-incr, long. */
1607 SET_L_REG (rn
, t
+ 4);
1608 t
&= h8_get_mask (sd
);
1609 SET_MEMORY_L (t
, n
);
1612 case X (OP_DISP
, SB
): /* Register indirect w/displacement, byte. */
1613 t
= GET_L_REG (rn
) + abs
;
1614 t
&= h8_get_mask (sd
);
1615 SET_MEMORY_B (t
, n
);
1618 case X (OP_DISP
, SW
): /* Register indirect w/displacement, word. */
1619 t
= GET_L_REG (rn
) + abs
;
1620 t
&= h8_get_mask (sd
);
1621 SET_MEMORY_W (t
, n
);
1624 case X (OP_DISP
, SL
): /* Register indirect w/displacement, long. */
1625 t
= GET_L_REG (rn
) + abs
;
1626 t
&= h8_get_mask (sd
);
1627 SET_MEMORY_L (t
, n
);
1631 case X (OP_MEM
, SB
): /* Why isn't this implemented? */
1632 case X (OP_MEM
, SW
): /* Why isn't this implemented? */
1633 case X (OP_MEM
, SL
): /* Why isn't this implemented? */
1635 sim_engine_halt (sd
, cpu
, NULL
, NULL_CIA
, sim_stopped
, SIM_SIGSEGV
);
1644 store (SIM_DESC sd
, ea_type
*arg
, int n
)
1646 return store_1 (sd
, arg
, n
, 0);
1649 /* Store which follows a fetch from the same location.
1650 The difference being that we don't want to do a pre-increment
1651 or pre-decrement at this time: it was already done when we fetched. */
1654 store2 (SIM_DESC sd
, ea_type
*arg
, int n
)
1656 return store_1 (sd
, arg
, n
, 1);
1659 /* Flag to be set whenever a new SIM_DESC object is created. */
1660 static int init_pointers_needed
= 1;
1663 init_pointers (SIM_DESC sd
)
1665 struct h8300_sim_state
*state
= H8300_SIM_STATE (sd
);
1667 if (init_pointers_needed
)
1671 if (h8300smode
&& !h8300_normal_mode
)
1672 memory_size
= H8300S_MSIZE
;
1673 else if (h8300hmode
&& !h8300_normal_mode
)
1674 memory_size
= H8300H_MSIZE
;
1676 memory_size
= H8300_MSIZE
;
1677 /* `msize' must be a power of two. */
1678 if ((memory_size
& (memory_size
- 1)) != 0)
1682 "init_pointers: bad memory size %d, defaulting to %d.\n",
1683 memory_size
, H8300S_MSIZE
);
1684 memory_size
= H8300S_MSIZE
;
1687 if (h8_get_memory_buf (sd
))
1688 free (h8_get_memory_buf (sd
));
1690 h8_set_memory_buf (sd
, (unsigned char *)
1691 calloc (sizeof (char), memory_size
));
1692 state
->memory_size
= memory_size
;
1694 h8_set_mask (sd
, memory_size
- 1);
1696 memset (h8_get_reg_buf (sd
), 0, sizeof (((STATE_CPU (sd
, 0))->regs
)));
1698 for (i
= 0; i
< 8; i
++)
1700 /* FIXME: rewrite using local buffer. */
1701 unsigned char *p
= (unsigned char *) (h8_get_reg_buf (sd
) + i
);
1702 unsigned char *e
= (unsigned char *) (h8_get_reg_buf (sd
) + i
+ 1);
1703 unsigned short *q
= (unsigned short *) (h8_get_reg_buf (sd
) + i
);
1704 unsigned short *u
= (unsigned short *) (h8_get_reg_buf (sd
) + i
+ 1);
1705 h8_set_reg (sd
, i
, 0x00112233);
1720 wreg
[i
] = wreg
[i
+ 8] = 0;
1734 if (wreg
[i
] == 0 || wreg
[i
+ 8] == 0)
1735 sim_io_printf (sd
, "init_pointers: internal error.\n");
1737 h8_set_reg (sd
, i
, 0);
1740 init_pointers_needed
= 0;
1744 #define OBITOP(name, f, s, op) \
1745 case O (name, SB): \
1750 if (fetch (sd, &code->dst, &ea)) \
1752 if (fetch (sd, &code->src, &tmp)) \
1754 m = 1 << (tmp & 7); \
1757 if (store (sd, &code->dst,ea)) \
1763 step_once (SIM_DESC sd
, SIM_CPU
*cpu
)
1767 int tick_start
= get_now ();
1774 int c
, nz
, v
, n
, u
, h
, ui
, intMaskBit
;
1778 const struct h8300_sim_state
*state
= H8300_SIM_STATE (sd
);
1779 host_callback
*sim_callback
= STATE_CALLBACK (sd
);
1783 pc
= h8_get_pc (sd
);
1785 /* The PC should never be odd. */
1788 sim_engine_halt (sd
, cpu
, NULL
, NULL_CIA
, sim_stopped
, SIM_SIGBUS
);
1792 /* Get Status Register (flags). */
1795 if (h8300smode
) /* Get exr. */
1797 trace
= (h8_get_exr (sd
) >> 7) & 1;
1798 intMask
= h8_get_exr (sd
) & 7;
1801 oldmask
= h8_get_mask (sd
);
1802 if (!h8300hmode
|| h8300_normal_mode
)
1803 h8_set_mask (sd
, 0xffff);
1806 decoded_inst _code
, *code
= &_code
;
1807 memset (code
, 0, sizeof (*code
));
1808 decode (sd
, pc
, h8_get_memory_buf (sd
) + pc
, code
);
1814 printf ("%x %d %s\n", pc
, code
->opcode
,
1815 code
->op
? code
->op
->name
: "**");
1817 h8_increment_stats (sd
, code
->opcode
);
1822 cycles
+= code
->cycles
;
1826 switch (code
->opcode
)
1828 case O (O_MOVAB
, SL
):
1829 case O (O_MOVAW
, SL
):
1830 case O (O_MOVAL
, SL
):
1831 /* 1) Evaluate 2nd argument (dst).
1832 2) Mask / zero extend according to whether 1st argument (src)
1833 is INDEXB, INDEXW, or INDEXL.
1834 3) Left-shift the result by 0, 1 or 2, according to size of mova
1835 (mova/b, mova/w, mova/l).
1836 4) Add literal value of 1st argument (src).
1837 5) Store result in 3rd argument (op3).
1840 /* Alas, since this is the only instruction with 3 arguments,
1841 decode doesn't handle them very well. Some fix-up is required.
1843 a) The size of dst is determined by whether src is
1844 INDEXB or INDEXW. */
1846 if (OP_KIND (code
->src
.type
) == OP_INDEXB
)
1847 code
->dst
.type
= X (OP_KIND (code
->dst
.type
), SB
);
1848 else if (OP_KIND (code
->src
.type
) == OP_INDEXW
)
1849 code
->dst
.type
= X (OP_KIND (code
->dst
.type
), SW
);
1851 /* b) If op3 == null, then this is the short form of the insn.
1852 Dst is the dispreg of src, and op3 is the 32-bit form
1853 of the same register.
1856 if (code
->op3
.type
== 0)
1858 /* Short form: src == INDEXB/INDEXW, dst == op3 == 0.
1859 We get to compose dst and op3 as follows:
1861 op3 is a 32-bit register, ID == src.reg.
1862 dst is the same register, but 8 or 16 bits
1863 depending on whether src is INDEXB or INDEXW.
1866 code
->op3
.type
= X (OP_REG
, SL
);
1867 code
->op3
.reg
= code
->src
.reg
;
1868 code
->op3
.literal
= 0;
1870 if (OP_KIND (code
->src
.type
) == OP_INDEXB
)
1872 code
->dst
.type
= X (OP_REG
, SB
);
1873 code
->dst
.reg
= code
->op3
.reg
+ 8;
1876 code
->dst
.type
= X (OP_REG
, SW
);
1879 if (fetch (sd
, &code
->dst
, &ea
))
1882 switch (OP_KIND (code
->src
.type
)) {
1883 case OP_INDEXB
: ea
= ea
& 0xff; break;
1884 case OP_INDEXW
: ea
= ea
& 0xffff; break;
1885 case OP_INDEXL
: break;
1886 default: goto illegal
;
1889 switch (code
->opcode
) {
1890 case O (O_MOVAB
, SL
): break;
1891 case O (O_MOVAW
, SL
): ea
= ea
<< 1; break;
1892 case O (O_MOVAL
, SL
): ea
= ea
<< 2; break;
1893 default: goto illegal
;
1896 ea
= ea
+ code
->src
.literal
;
1898 if (store (sd
, &code
->op3
, ea
))
1903 case O (O_SUBX
, SB
): /* subx, extended sub */
1904 if (fetch2 (sd
, &code
->dst
, &rd
))
1906 if (fetch (sd
, &code
->src
, &ea
))
1912 case O (O_SUBX
, SW
): /* subx, extended sub */
1913 if (fetch2 (sd
, &code
->dst
, &rd
))
1915 if (fetch (sd
, &code
->src
, &ea
))
1921 case O (O_SUBX
, SL
): /* subx, extended sub */
1922 if (fetch2 (sd
, &code
->dst
, &rd
))
1924 if (fetch (sd
, &code
->src
, &ea
))
1930 case O (O_ADDX
, SB
): /* addx, extended add */
1931 if (fetch2 (sd
, &code
->dst
, &rd
))
1933 if (fetch (sd
, &code
->src
, &ea
))
1939 case O (O_ADDX
, SW
): /* addx, extended add */
1940 if (fetch2 (sd
, &code
->dst
, &rd
))
1942 if (fetch (sd
, &code
->src
, &ea
))
1948 case O (O_ADDX
, SL
): /* addx, extended add */
1949 if (fetch2 (sd
, &code
->dst
, &rd
))
1951 if (fetch (sd
, &code
->src
, &ea
))
1957 case O (O_SUB
, SB
): /* sub.b */
1958 /* Fetch rd and ea. */
1959 if (fetch (sd
, &code
->src
, &ea
) || fetch2 (sd
, &code
->dst
, &rd
))
1965 case O (O_SUB
, SW
): /* sub.w */
1966 /* Fetch rd and ea. */
1967 if (fetch (sd
, &code
->src
, &ea
) || fetch2 (sd
, &code
->dst
, &rd
))
1973 case O (O_SUB
, SL
): /* sub.l */
1974 /* Fetch rd and ea. */
1975 if (fetch (sd
, &code
->src
, &ea
) || fetch2 (sd
, &code
->dst
, &rd
))
1981 case O (O_NEG
, SB
): /* neg.b */
1983 if (fetch2 (sd
, &code
->src
, &ea
))
1990 case O (O_NEG
, SW
): /* neg.w */
1992 if (fetch2 (sd
, &code
->src
, &ea
))
1999 case O (O_NEG
, SL
): /* neg.l */
2001 if (fetch2 (sd
, &code
->src
, &ea
))
2008 case O (O_ADD
, SB
): /* add.b */
2009 if (fetch2 (sd
, &code
->dst
, &rd
))
2011 if (fetch (sd
, &code
->src
, &ea
))
2016 case O (O_ADD
, SW
): /* add.w */
2017 if (fetch2 (sd
, &code
->dst
, &rd
))
2019 if (fetch (sd
, &code
->src
, &ea
))
2024 case O (O_ADD
, SL
): /* add.l */
2025 if (fetch2 (sd
, &code
->dst
, &rd
))
2027 if (fetch (sd
, &code
->src
, &ea
))
2032 case O (O_AND
, SB
): /* and.b */
2033 /* Fetch rd and ea. */
2034 if (fetch2 (sd
, &code
->dst
, &rd
) || fetch (sd
, &code
->src
, &ea
))
2039 case O (O_AND
, SW
): /* and.w */
2040 /* Fetch rd and ea. */
2041 if (fetch (sd
, &code
->src
, &ea
) || fetch2 (sd
, &code
->dst
, &rd
))
2046 case O (O_AND
, SL
): /* and.l */
2047 /* Fetch rd and ea. */
2048 if (fetch (sd
, &code
->src
, &ea
) || fetch2 (sd
, &code
->dst
, &rd
))
2053 case O (O_OR
, SB
): /* or.b */
2054 /* Fetch rd and ea. */
2055 if (fetch2 (sd
, &code
->dst
, &rd
) || fetch (sd
, &code
->src
, &ea
))
2060 case O (O_OR
, SW
): /* or.w */
2061 /* Fetch rd and ea. */
2062 if (fetch (sd
, &code
->src
, &ea
) || fetch2 (sd
, &code
->dst
, &rd
))
2067 case O (O_OR
, SL
): /* or.l */
2068 /* Fetch rd and ea. */
2069 if (fetch (sd
, &code
->src
, &ea
) || fetch2 (sd
, &code
->dst
, &rd
))
2074 case O (O_XOR
, SB
): /* xor.b */
2075 /* Fetch rd and ea. */
2076 if (fetch (sd
, &code
->src
, &ea
) || fetch2 (sd
, &code
->dst
, &rd
))
2081 case O (O_XOR
, SW
): /* xor.w */
2082 /* Fetch rd and ea. */
2083 if (fetch (sd
, &code
->src
, &ea
) || fetch2 (sd
, &code
->dst
, &rd
))
2088 case O (O_XOR
, SL
): /* xor.l */
2089 /* Fetch rd and ea. */
2090 if (fetch (sd
, &code
->src
, &ea
) || fetch2 (sd
, &code
->dst
, &rd
))
2096 if (fetch (sd
, &code
->src
, &res
))
2098 if (store (sd
, &code
->dst
, res
))
2100 goto just_flags_log8
;
2102 if (fetch (sd
, &code
->src
, &res
))
2104 if (store (sd
, &code
->dst
, res
))
2106 goto just_flags_log16
;
2108 if (fetch (sd
, &code
->src
, &res
))
2110 if (store (sd
, &code
->dst
, res
))
2112 goto just_flags_log32
;
2114 case O (O_MOVMD
, SB
): /* movmd.b */
2121 rd
= GET_MEMORY_B (GET_L_REG (5));
2122 SET_MEMORY_B (GET_L_REG (6), rd
);
2123 SET_L_REG (5, GET_L_REG (5) + 1);
2124 SET_L_REG (6, GET_L_REG (6) + 1);
2129 case O (O_MOVMD
, SW
): /* movmd.w */
2136 rd
= GET_MEMORY_W (GET_L_REG (5));
2137 SET_MEMORY_W (GET_L_REG (6), rd
);
2138 SET_L_REG (5, GET_L_REG (5) + 2);
2139 SET_L_REG (6, GET_L_REG (6) + 2);
2144 case O (O_MOVMD
, SL
): /* movmd.l */
2151 rd
= GET_MEMORY_L (GET_L_REG (5));
2152 SET_MEMORY_L (GET_L_REG (6), rd
);
2153 SET_L_REG (5, GET_L_REG (5) + 4);
2154 SET_L_REG (6, GET_L_REG (6) + 4);
2159 case O (O_MOVSD
, SB
): /* movsd.b */
2160 /* This instruction implements strncpy, with a conditional branch.
2161 r4 contains n, r5 contains src, and r6 contains dst.
2162 The 16-bit displacement operand is added to the pc
2163 if and only if the end of string is reached before
2164 n bytes are transferred. */
2166 ea
= GET_L_REG (4) & 0xffff;
2172 rd
= GET_MEMORY_B (GET_L_REG (5));
2173 SET_MEMORY_B (GET_L_REG (6), rd
);
2174 SET_L_REG (5, GET_L_REG (5) + 1);
2175 SET_L_REG (6, GET_L_REG (6) + 1);
2182 case O (O_EEPMOV
, SB
): /* eepmov.b */
2183 case O (O_EEPMOV
, SW
): /* eepmov.w */
2184 if (h8300hmode
|| h8300smode
)
2186 register unsigned char *_src
, *_dst
;
2187 unsigned int count
= ((code
->opcode
== O (O_EEPMOV
, SW
))
2188 ? h8_get_reg (sd
, R4_REGNUM
) & 0xffff
2189 : h8_get_reg (sd
, R4_REGNUM
) & 0xff);
2191 _src
= h8_get_memory_buf (sd
) + h8_get_reg (sd
, R5_REGNUM
);
2192 if ((_src
+ count
) >= (h8_get_memory_buf (sd
) + memory_size
))
2194 _dst
= h8_get_memory_buf (sd
) + h8_get_reg (sd
, R6_REGNUM
);
2195 if ((_dst
+ count
) >= (h8_get_memory_buf (sd
) + memory_size
))
2197 memcpy (_dst
, _src
, count
);
2199 h8_set_reg (sd
, R5_REGNUM
, h8_get_reg (sd
, R5_REGNUM
) + count
);
2200 h8_set_reg (sd
, R6_REGNUM
, h8_get_reg (sd
, R6_REGNUM
) + count
);
2201 h8_set_reg (sd
, R4_REGNUM
, h8_get_reg (sd
, R4_REGNUM
) &
2202 ((code
->opcode
== O (O_EEPMOV
, SW
))
2203 ? (~0xffff) : (~0xff)));
2204 cycles
+= 2 * count
;
2209 case O (O_ADDS
, SL
): /* adds (.l) */
2211 * This insn only uses register operands, but still
2212 * it would be cleaner to use fetch and store... */
2213 SET_L_REG (code
->dst
.reg
,
2214 GET_L_REG (code
->dst
.reg
)
2215 + code
->src
.literal
);
2219 case O (O_SUBS
, SL
): /* subs (.l) */
2221 * This insn only uses register operands, but still
2222 * it would be cleaner to use fetch and store... */
2223 SET_L_REG (code
->dst
.reg
,
2224 GET_L_REG (code
->dst
.reg
)
2225 - code
->src
.literal
);
2228 case O (O_CMP
, SB
): /* cmp.b */
2229 if (fetch (sd
, &code
->dst
, &rd
))
2231 if (fetch (sd
, &code
->src
, &ea
))
2235 goto just_flags_alu8
;
2237 case O (O_CMP
, SW
): /* cmp.w */
2238 if (fetch (sd
, &code
->dst
, &rd
))
2240 if (fetch (sd
, &code
->src
, &ea
))
2244 goto just_flags_alu16
;
2246 case O (O_CMP
, SL
): /* cmp.l */
2247 if (fetch (sd
, &code
->dst
, &rd
))
2249 if (fetch (sd
, &code
->src
, &ea
))
2253 goto just_flags_alu32
;
2255 case O (O_DEC
, SB
): /* dec.b */
2257 * This insn only uses register operands, but still
2258 * it would be cleaner to use fetch and store... */
2259 rd
= GET_B_REG (code
->src
.reg
);
2262 SET_B_REG (code
->src
.reg
, res
);
2263 goto just_flags_inc8
;
2265 case O (O_DEC
, SW
): /* dec.w */
2267 * This insn only uses register operands, but still
2268 * it would be cleaner to use fetch and store... */
2269 rd
= GET_W_REG (code
->dst
.reg
);
2270 ea
= -code
->src
.literal
;
2272 SET_W_REG (code
->dst
.reg
, res
);
2273 goto just_flags_inc16
;
2275 case O (O_DEC
, SL
): /* dec.l */
2277 * This insn only uses register operands, but still
2278 * it would be cleaner to use fetch and store... */
2279 rd
= GET_L_REG (code
->dst
.reg
);
2280 ea
= -code
->src
.literal
;
2282 SET_L_REG (code
->dst
.reg
, res
);
2283 goto just_flags_inc32
;
2285 case O (O_INC
, SB
): /* inc.b */
2287 * This insn only uses register operands, but still
2288 * it would be cleaner to use fetch and store... */
2289 rd
= GET_B_REG (code
->src
.reg
);
2292 SET_B_REG (code
->src
.reg
, res
);
2293 goto just_flags_inc8
;
2295 case O (O_INC
, SW
): /* inc.w */
2297 * This insn only uses register operands, but still
2298 * it would be cleaner to use fetch and store... */
2299 rd
= GET_W_REG (code
->dst
.reg
);
2300 ea
= code
->src
.literal
;
2302 SET_W_REG (code
->dst
.reg
, res
);
2303 goto just_flags_inc16
;
2305 case O (O_INC
, SL
): /* inc.l */
2307 * This insn only uses register operands, but still
2308 * it would be cleaner to use fetch and store... */
2309 rd
= GET_L_REG (code
->dst
.reg
);
2310 ea
= code
->src
.literal
;
2312 SET_L_REG (code
->dst
.reg
, res
);
2313 goto just_flags_inc32
;
2315 case O (O_LDC
, SB
): /* ldc.b */
2316 if (fetch (sd
, &code
->src
, &res
))
2320 case O (O_LDC
, SW
): /* ldc.w */
2321 if (fetch (sd
, &code
->src
, &res
))
2324 /* Word operand, value from MSB, must be shifted. */
2328 case O (O_LDC
, SL
): /* ldc.l */
2329 if (fetch (sd
, &code
->src
, &res
))
2331 switch (code
->dst
.type
) {
2332 case X (OP_SBR
, SL
):
2333 h8_set_sbr (sd
, res
);
2335 case X (OP_VBR
, SL
):
2336 h8_set_vbr (sd
, res
);
2343 case O (O_STC
, SW
): /* stc.w */
2344 case O (O_STC
, SB
): /* stc.b */
2345 if (code
->src
.type
== X (OP_CCR
, SB
))
2348 res
= h8_get_ccr (sd
);
2350 else if (code
->src
.type
== X (OP_EXR
, SB
) && h8300smode
)
2353 h8_set_exr (sd
, (trace
<< 7) | intMask
);
2354 res
= h8_get_exr (sd
);
2359 /* Word operand, value to MSB, must be shifted. */
2360 if (code
->opcode
== X (O_STC
, SW
))
2362 if (store (sd
, &code
->dst
, res
))
2365 case O (O_STC
, SL
): /* stc.l */
2366 switch (code
->src
.type
) {
2367 case X (OP_SBR
, SL
):
2368 res
= h8_get_sbr (sd
);
2370 case X (OP_VBR
, SL
):
2371 res
= h8_get_vbr (sd
);
2376 if (store (sd
, &code
->dst
, res
))
2380 case O (O_ANDC
, SB
): /* andc.b */
2381 if (code
->dst
.type
== X (OP_CCR
, SB
))
2384 rd
= h8_get_ccr (sd
);
2386 else if (code
->dst
.type
== X (OP_EXR
, SB
) && h8300smode
)
2389 h8_set_exr (sd
, (trace
<< 7) | intMask
);
2390 rd
= h8_get_exr (sd
);
2394 ea
= code
->src
.literal
;
2398 case O (O_ORC
, SB
): /* orc.b */
2399 if (code
->dst
.type
== X (OP_CCR
, SB
))
2402 rd
= h8_get_ccr (sd
);
2404 else if (code
->dst
.type
== X (OP_EXR
, SB
) && h8300smode
)
2407 h8_set_exr (sd
, (trace
<< 7) | intMask
);
2408 rd
= h8_get_exr (sd
);
2412 ea
= code
->src
.literal
;
2416 case O (O_XORC
, SB
): /* xorc.b */
2417 if (code
->dst
.type
== X (OP_CCR
, SB
))
2420 rd
= h8_get_ccr (sd
);
2422 else if (code
->dst
.type
== X (OP_EXR
, SB
) && h8300smode
)
2425 h8_set_exr (sd
, (trace
<< 7) | intMask
);
2426 rd
= h8_get_exr (sd
);
2430 ea
= code
->src
.literal
;
2434 case O (O_BRAS
, SB
): /* bra/s */
2435 /* This is basically an ordinary branch, with a delay slot. */
2436 if (fetch (sd
, &code
->src
, &res
))
2444 /* Execution continues at next instruction, but
2445 delayed_branch is set up for next cycle. */
2446 h8_set_delayed_branch (sd
, code
->next_pc
+ res
);
2450 case O (O_BRAB
, SB
): /* bra rd.b */
2451 case O (O_BRAW
, SW
): /* bra rd.w */
2452 case O (O_BRAL
, SL
): /* bra erd.l */
2453 if (fetch (sd
, &code
->src
, &rd
))
2455 switch (OP_SIZE (code
->opcode
)) {
2456 case SB
: rd
&= 0xff; break;
2457 case SW
: rd
&= 0xffff; break;
2458 case SL
: rd
&= 0xffffffff; break;
2460 pc
= code
->next_pc
+ rd
;
2463 case O (O_BRABC
, SB
): /* bra/bc, branch if bit clear */
2464 case O (O_BRABS
, SB
): /* bra/bs, branch if bit set */
2465 case O (O_BSRBC
, SB
): /* bsr/bc, call if bit clear */
2466 case O (O_BSRBS
, SB
): /* bsr/bs, call if bit set */
2467 if (fetch (sd
, &code
->dst
, &rd
) ||
2468 fetch (sd
, &code
->src
, &bit
))
2471 if (code
->opcode
== O (O_BRABC
, SB
) || /* branch if clear */
2472 code
->opcode
== O (O_BSRBC
, SB
)) /* call if clear */
2474 if ((rd
& (1 << bit
))) /* no branch */
2477 else /* branch/call if set */
2479 if (!(rd
& (1 << bit
))) /* no branch */
2483 if (fetch (sd
, &code
->op3
, &res
)) /* branch */
2485 pc
= code
->next_pc
+ res
;
2487 if (code
->opcode
== O (O_BRABC
, SB
) ||
2488 code
->opcode
== O (O_BRABS
, SB
)) /* branch */
2496 case O (O_BRA
, SB
): /* bra, branch always */
2501 case O (O_BRN
, SB
): /* brn, ;-/ branch never? */
2506 case O (O_BHI
, SB
): /* bhi */
2512 case O (O_BLS
, SB
): /* bls */
2517 case O (O_BCS
, SB
): /* bcs, branch if carry set */
2522 case O (O_BCC
, SB
): /* bcc, branch if carry clear */
2527 case O (O_BEQ
, SB
): /* beq, branch if zero set */
2531 case O (O_BGT
, SB
): /* bgt */
2532 if (((Z
|| (N
^ V
)) == 0))
2536 case O (O_BLE
, SB
): /* ble */
2537 if (((Z
|| (N
^ V
)) == 1))
2541 case O (O_BGE
, SB
): /* bge */
2545 case O (O_BLT
, SB
): /* blt */
2549 case O (O_BMI
, SB
): /* bmi */
2553 case O (O_BNE
, SB
): /* bne, branch if zero clear */
2558 case O (O_BPL
, SB
): /* bpl */
2562 case O (O_BVC
, SB
): /* bvc */
2566 case O (O_BVS
, SB
): /* bvs */
2571 /* Trap for Command Line setup. */
2572 case O (O_SYS_CMDLINE
, SB
):
2574 int i
= 0; /* Loop counter. */
2575 int j
= 0; /* Loop counter. */
2576 int ind_arg_len
= 0; /* Length of each argument. */
2577 int no_of_args
= 0; /* The no. or cmdline args. */
2578 int current_location
= 0; /* Location of string. */
2579 int old_sp
= 0; /* The Initial Stack Pointer. */
2580 int no_of_slots
= 0; /* No. of slots required on the stack
2581 for storing cmdline args. */
2582 int sp_move
= 0; /* No. of locations by which the stack needs
2584 int new_sp
= 0; /* The final stack pointer location passed
2586 int *argv_ptrs
; /* Pointers of argv strings to be stored. */
2587 int argv_ptrs_location
= 0; /* Location of pointers to cmdline
2588 args on the stack. */
2589 int char_ptr_size
= 0; /* Size of a character pointer on
2591 int addr_cmdline
= 0; /* Memory location where cmdline has
2593 int size_cmdline
= 0; /* Size of cmdline. */
2595 /* Set the address of 256 free locations where command line is
2597 addr_cmdline
= cmdline_location();
2598 h8_set_reg (sd
, 0, addr_cmdline
);
2600 /* Counting the no. of commandline arguments. */
2601 for (i
= 0; h8_get_cmdline_arg (sd
, i
) != NULL
; i
++)
2604 /* No. of arguments in the command line. */
2607 /* Current location is just a temporary variable,which we are
2608 setting to the point to the start of our commandline string. */
2609 current_location
= addr_cmdline
;
2611 /* Allocating space for storing pointers of the command line
2613 argv_ptrs
= (int *) malloc (sizeof (int) * no_of_args
);
2615 /* Setting char_ptr_size to the sizeof (char *) on the different
2617 if ((h8300hmode
|| h8300smode
) && !h8300_normal_mode
)
2626 for (i
= 0; i
< no_of_args
; i
++)
2630 /* The size of the commandline argument. */
2631 ind_arg_len
= strlen (h8_get_cmdline_arg (sd
, i
)) + 1;
2633 /* The total size of the command line string. */
2634 size_cmdline
+= ind_arg_len
;
2636 /* As we have only 256 bytes, we need to provide a graceful
2637 exit. Anyways, a program using command line arguments
2638 where we cannot store all the command line arguments
2639 given may behave unpredictably. */
2640 if (size_cmdline
>= 256)
2642 h8_set_reg (sd
, 0, 0);
2647 /* current_location points to the memory where the next
2648 commandline argument is stored. */
2649 argv_ptrs
[i
] = current_location
;
2650 for (j
= 0; j
< ind_arg_len
; j
++)
2652 SET_MEMORY_B ((current_location
+
2653 (sizeof (char) * j
)),
2654 *(h8_get_cmdline_arg (sd
, i
) +
2655 sizeof (char) * j
));
2658 /* Setting current_location to the starting of next
2660 current_location
+= ind_arg_len
;
2664 /* This is the original position of the stack pointer. */
2665 old_sp
= h8_get_reg (sd
, SP_REGNUM
);
2667 /* We need space from the stack to store the pointers to argvs. */
2668 /* As we will infringe on the stack, we need to shift the stack
2669 pointer so that the data is not overwritten. We calculate how
2670 much space is required. */
2671 sp_move
= (no_of_args
) * (char_ptr_size
);
2673 /* The final position of stack pointer, we have thus taken some
2674 space from the stack. */
2675 new_sp
= old_sp
- sp_move
;
2677 /* Temporary variable holding value where the argv pointers need
2679 argv_ptrs_location
= new_sp
;
2681 /* The argv pointers are stored at sequential locations. As per
2683 for (i
= 0; i
< no_of_args
; i
++)
2685 /* Saving the argv pointer. */
2686 if ((h8300hmode
|| h8300smode
) && !h8300_normal_mode
)
2688 SET_MEMORY_L (argv_ptrs_location
, argv_ptrs
[i
]);
2692 SET_MEMORY_W (argv_ptrs_location
, argv_ptrs
[i
]);
2695 /* The next location where the pointer to the next argv
2696 string has to be stored. */
2697 argv_ptrs_location
+= char_ptr_size
;
2700 /* Required by POSIX, Setting 0x0 at the end of the list of argv
2702 if ((h8300hmode
|| h8300smode
) && !h8300_normal_mode
)
2704 SET_MEMORY_L (old_sp
, 0x0);
2708 SET_MEMORY_W (old_sp
, 0x0);
2711 /* Freeing allocated memory. */
2713 for (i
= 0; i
<= no_of_args
; i
++)
2715 free (h8_get_cmdline_arg (sd
, i
));
2717 free (h8_get_command_line (sd
));
2719 /* The no. of argv arguments are returned in Reg 0. */
2720 h8_set_reg (sd
, 0, no_of_args
);
2721 /* The Pointer to argv in Register 1. */
2722 h8_set_reg (sd
, 1, new_sp
);
2723 /* Setting the stack pointer to the new value. */
2724 h8_set_reg (sd
, SP_REGNUM
, new_sp
);
2728 /* System call processing starts. */
2729 case O (O_SYS_OPEN
, SB
):
2731 int len
= 0; /* Length of filename. */
2732 char *filename
; /* Filename would go here. */
2733 char temp_char
; /* Temporary character */
2734 int mode
= 0; /* Mode bits for the file. */
2735 int open_return
; /* Return value of open, file descriptor. */
2736 int i
; /* Loop counter */
2737 int filename_ptr
; /* Pointer to filename in cpu memory. */
2739 /* Setting filename_ptr to first argument of open, */
2740 /* and trying to get mode. */
2741 if ((h8300sxmode
|| h8300hmode
|| h8300smode
) && !h8300_normal_mode
)
2743 filename_ptr
= GET_L_REG (0);
2744 mode
= GET_MEMORY_L (h8_get_reg (sd
, SP_REGNUM
) + 4);
2748 filename_ptr
= GET_W_REG (0);
2749 mode
= GET_MEMORY_W (h8_get_reg (sd
, SP_REGNUM
) + 2);
2752 /* Trying to find the length of the filename. */
2753 temp_char
= GET_MEMORY_B (h8_get_reg (sd
, 0));
2756 while (temp_char
!= '\0')
2758 temp_char
= GET_MEMORY_B (filename_ptr
+ len
);
2762 /* Allocating space for the filename. */
2763 filename
= (char *) malloc (sizeof (char) * len
);
2765 /* String copying the filename from memory. */
2766 for (i
= 0; i
< len
; i
++)
2768 temp_char
= GET_MEMORY_B (filename_ptr
+ i
);
2769 filename
[i
] = temp_char
;
2772 /* Callback to open and return the file descriptor. */
2773 open_return
= sim_callback
->open (sim_callback
, filename
, mode
);
2775 /* Return value in register 0. */
2776 h8_set_reg (sd
, 0, open_return
);
2778 /* Freeing memory used for filename. */
2783 case O (O_SYS_READ
, SB
):
2785 char *char_ptr
; /* Where characters read would be stored. */
2786 int fd
; /* File descriptor */
2787 int buf_size
; /* BUF_SIZE parameter in read. */
2788 int i
= 0; /* Temporary Loop counter */
2789 int read_return
= 0; /* Return value from callback to
2792 fd
= (h8300hmode
&& !h8300_normal_mode
) ? GET_L_REG (0) : GET_W_REG (0);
2793 buf_size
= (h8300hmode
&& !h8300_normal_mode
) ? GET_L_REG (2) : GET_W_REG (2);
2795 char_ptr
= (char *) malloc (sizeof (char) * buf_size
);
2797 /* Callback to read and return the no. of characters read. */
2799 sim_callback
->read (sim_callback
, fd
, char_ptr
, buf_size
);
2801 /* The characters read are stored in cpu memory. */
2802 for (i
= 0; i
< buf_size
; i
++)
2804 SET_MEMORY_B ((h8_get_reg (sd
, 1) + (sizeof (char) * i
)),
2805 *(char_ptr
+ (sizeof (char) * i
)));
2808 /* Return value in Register 0. */
2809 h8_set_reg (sd
, 0, read_return
);
2811 /* Freeing memory used as buffer. */
2816 case O (O_SYS_WRITE
, SB
):
2818 int fd
; /* File descriptor */
2819 char temp_char
; /* Temporary character */
2820 int len
; /* Length of write, Parameter II to write. */
2821 int char_ptr
; /* Character Pointer, Parameter I of write. */
2822 char *ptr
; /* Where characters to be written are stored.
2824 int write_return
; /* Return value from callback to write. */
2825 int i
= 0; /* Loop counter */
2827 fd
= (h8300hmode
&& !h8300_normal_mode
) ? GET_L_REG (0) : GET_W_REG (0);
2828 char_ptr
= (h8300hmode
&& !h8300_normal_mode
) ? GET_L_REG (1) : GET_W_REG (1);
2829 len
= (h8300hmode
&& !h8300_normal_mode
) ? GET_L_REG (2) : GET_W_REG (2);
2831 /* Allocating space for the characters to be written. */
2832 ptr
= (char *) malloc (sizeof (char) * len
);
2834 /* Fetching the characters from cpu memory. */
2835 for (i
= 0; i
< len
; i
++)
2837 temp_char
= GET_MEMORY_B (char_ptr
+ i
);
2841 /* Callback write and return the no. of characters written. */
2842 write_return
= sim_callback
->write (sim_callback
, fd
, ptr
, len
);
2844 /* Return value in Register 0. */
2845 h8_set_reg (sd
, 0, write_return
);
2847 /* Freeing memory used as buffer. */
2852 case O (O_SYS_LSEEK
, SB
):
2854 int fd
; /* File descriptor */
2855 int offset
; /* Offset */
2856 int origin
; /* Origin */
2857 int lseek_return
; /* Return value from callback to lseek. */
2859 fd
= (h8300hmode
&& !h8300_normal_mode
) ? GET_L_REG (0) : GET_W_REG (0);
2860 offset
= (h8300hmode
&& !h8300_normal_mode
) ? GET_L_REG (1) : GET_W_REG (1);
2861 origin
= (h8300hmode
&& !h8300_normal_mode
) ? GET_L_REG (2) : GET_W_REG (2);
2863 /* Callback lseek and return offset. */
2865 sim_callback
->lseek (sim_callback
, fd
, offset
, origin
);
2867 /* Return value in register 0. */
2868 h8_set_reg (sd
, 0, lseek_return
);
2872 case O (O_SYS_CLOSE
, SB
):
2874 int fd
; /* File descriptor */
2875 int close_return
; /* Return value from callback to close. */
2877 fd
= (h8300hmode
&& !h8300_normal_mode
) ? GET_L_REG (0) : GET_W_REG (0);
2879 /* Callback close and return. */
2880 close_return
= sim_callback
->close (sim_callback
, fd
);
2882 /* Return value in register 0. */
2883 h8_set_reg (sd
, 0, close_return
);
2887 case O (O_SYS_FSTAT
, SB
):
2889 int fd
; /* File descriptor */
2890 struct stat stat_rec
; /* Stat record */
2891 int fstat_return
; /* Return value from callback to stat. */
2892 int stat_ptr
; /* Pointer to stat record. */
2893 char *temp_stat_ptr
; /* Temporary stat_rec pointer. */
2895 fd
= (h8300hmode
&& !h8300_normal_mode
) ? GET_L_REG (0) : GET_W_REG (0);
2897 /* Setting stat_ptr to second argument of stat. */
2898 stat_ptr
= (h8300hmode
&& !h8300_normal_mode
) ? GET_L_REG (1) : GET_W_REG (1);
2900 /* Callback stat and return. */
2901 fstat_return
= sim_callback
->to_fstat (sim_callback
, fd
,
2904 /* Have stat_ptr point to starting of stat_rec. */
2905 temp_stat_ptr
= (char *) (&stat_rec
);
2907 /* Setting up the stat structure returned. */
2908 SET_MEMORY_W (stat_ptr
, stat_rec
.st_dev
);
2910 SET_MEMORY_W (stat_ptr
, stat_rec
.st_ino
);
2912 SET_MEMORY_L (stat_ptr
, stat_rec
.st_mode
);
2914 SET_MEMORY_W (stat_ptr
, stat_rec
.st_nlink
);
2916 SET_MEMORY_W (stat_ptr
, stat_rec
.st_uid
);
2918 SET_MEMORY_W (stat_ptr
, stat_rec
.st_gid
);
2920 SET_MEMORY_W (stat_ptr
, stat_rec
.st_rdev
);
2922 SET_MEMORY_L (stat_ptr
, stat_rec
.st_size
);
2924 SET_MEMORY_L (stat_ptr
, stat_rec
.st_atime
);
2926 SET_MEMORY_L (stat_ptr
, stat_rec
.st_mtime
);
2928 SET_MEMORY_L (stat_ptr
, stat_rec
.st_ctime
);
2930 /* Return value in register 0. */
2931 h8_set_reg (sd
, 0, fstat_return
);
2935 case O (O_SYS_STAT
, SB
):
2937 int len
= 0; /* Length of filename. */
2938 char *filename
; /* Filename would go here. */
2939 char temp_char
; /* Temporary character */
2940 int filename_ptr
; /* Pointer to filename in cpu memory. */
2941 struct stat stat_rec
; /* Stat record */
2942 int stat_return
; /* Return value from callback to stat */
2943 int stat_ptr
; /* Pointer to stat record. */
2944 char *temp_stat_ptr
; /* Temporary stat_rec pointer. */
2945 int i
= 0; /* Loop Counter */
2947 /* Setting filename_ptr to first argument of open. */
2948 filename_ptr
= (h8300hmode
&& !h8300_normal_mode
) ? GET_L_REG (0) : GET_W_REG (0);
2950 /* Trying to find the length of the filename. */
2951 temp_char
= GET_MEMORY_B (h8_get_reg (sd
, 0));
2954 while (temp_char
!= '\0')
2956 temp_char
= GET_MEMORY_B (filename_ptr
+ len
);
2960 /* Allocating space for the filename. */
2961 filename
= (char *) malloc (sizeof (char) * len
);
2963 /* String copying the filename from memory. */
2964 for (i
= 0; i
< len
; i
++)
2966 temp_char
= GET_MEMORY_B (filename_ptr
+ i
);
2967 filename
[i
] = temp_char
;
2970 /* Setting stat_ptr to second argument of stat. */
2971 /* stat_ptr = h8_get_reg (sd, 1); */
2972 stat_ptr
= (h8300hmode
&& !h8300_normal_mode
) ? GET_L_REG (1) : GET_W_REG (1);
2974 /* Callback stat and return. */
2976 sim_callback
->to_stat (sim_callback
, filename
, &stat_rec
);
2978 /* Have stat_ptr point to starting of stat_rec. */
2979 temp_stat_ptr
= (char *) (&stat_rec
);
2981 /* Freeing memory used for filename. */
2984 /* Setting up the stat structure returned. */
2985 SET_MEMORY_W (stat_ptr
, stat_rec
.st_dev
);
2987 SET_MEMORY_W (stat_ptr
, stat_rec
.st_ino
);
2989 SET_MEMORY_L (stat_ptr
, stat_rec
.st_mode
);
2991 SET_MEMORY_W (stat_ptr
, stat_rec
.st_nlink
);
2993 SET_MEMORY_W (stat_ptr
, stat_rec
.st_uid
);
2995 SET_MEMORY_W (stat_ptr
, stat_rec
.st_gid
);
2997 SET_MEMORY_W (stat_ptr
, stat_rec
.st_rdev
);
2999 SET_MEMORY_L (stat_ptr
, stat_rec
.st_size
);
3001 SET_MEMORY_L (stat_ptr
, stat_rec
.st_atime
);
3003 SET_MEMORY_L (stat_ptr
, stat_rec
.st_mtime
);
3005 SET_MEMORY_L (stat_ptr
, stat_rec
.st_ctime
);
3007 /* Return value in register 0. */
3008 h8_set_reg (sd
, 0, stat_return
);
3011 /* End of system call processing. */
3013 case O (O_NOT
, SB
): /* not.b */
3014 if (fetch2 (sd
, &code
->src
, &rd
))
3020 case O (O_NOT
, SW
): /* not.w */
3021 if (fetch2 (sd
, &code
->src
, &rd
))
3027 case O (O_NOT
, SL
): /* not.l */
3028 if (fetch2 (sd
, &code
->src
, &rd
))
3034 case O (O_SHLL
, SB
): /* shll.b */
3035 case O (O_SHLR
, SB
): /* shlr.b */
3036 if (fetch2 (sd
, &code
->dst
, &rd
))
3039 if (memcmp (&code
->src
, &code
->dst
, sizeof (code
->src
)) == 0)
3040 ea
= 1; /* unary op */
3041 else /* binary op */
3042 fetch (sd
, &code
->src
, &ea
);
3044 if (code
->opcode
== O (O_SHLL
, SB
))
3047 c
= rd
& (0x80 >> (ea
- 1));
3053 c
= rd
& (1 << (ea
- 1));
3054 rd
= (unsigned char) rd
>> ea
;
3058 case O (O_SHLL
, SW
): /* shll.w */
3059 case O (O_SHLR
, SW
): /* shlr.w */
3060 if (fetch2 (sd
, &code
->dst
, &rd
))
3063 if (memcmp (&code
->src
, &code
->dst
, sizeof (code
->src
)) == 0)
3064 ea
= 1; /* unary op */
3066 fetch (sd
, &code
->src
, &ea
);
3068 if (code
->opcode
== O (O_SHLL
, SW
))
3071 c
= rd
& (0x8000 >> (ea
- 1));
3077 c
= rd
& (1 << (ea
- 1));
3078 rd
= (unsigned short) rd
>> ea
;
3082 case O (O_SHLL
, SL
): /* shll.l */
3083 case O (O_SHLR
, SL
): /* shlr.l */
3084 if (fetch2 (sd
, &code
->dst
, &rd
))
3087 if (memcmp (&code
->src
, &code
->dst
, sizeof (code
->src
)) == 0)
3088 ea
= 1; /* unary op */
3090 fetch (sd
, &code
->src
, &ea
);
3092 if (code
->opcode
== O (O_SHLL
, SL
))
3095 c
= rd
& (0x80000000 >> (ea
- 1));
3101 c
= rd
& (1 << (ea
- 1));
3102 rd
= (unsigned int) rd
>> ea
;
3106 case O (O_SHAL
, SB
):
3107 case O (O_SHAR
, SB
):
3108 if (fetch2 (sd
, &code
->dst
, &rd
))
3111 if (code
->src
.type
== X (OP_IMM
, SB
))
3112 fetch (sd
, &code
->src
, &ea
);
3116 if (code
->opcode
== O (O_SHAL
, SB
))
3118 c
= rd
& (0x80 >> (ea
- 1));
3119 res
= rd
>> (7 - ea
);
3120 v
= ((res
& 1) && !(res
& 2))
3121 || (!(res
& 1) && (res
& 2));
3126 c
= rd
& (1 << (ea
- 1));
3128 rd
= ((signed char) rd
) >> ea
;
3132 case O (O_SHAL
, SW
):
3133 case O (O_SHAR
, SW
):
3134 if (fetch2 (sd
, &code
->dst
, &rd
))
3137 if (code
->src
.type
== X (OP_IMM
, SW
))
3138 fetch (sd
, &code
->src
, &ea
);
3142 if (code
->opcode
== O (O_SHAL
, SW
))
3144 c
= rd
& (0x8000 >> (ea
- 1));
3145 res
= rd
>> (15 - ea
);
3146 v
= ((res
& 1) && !(res
& 2))
3147 || (!(res
& 1) && (res
& 2));
3152 c
= rd
& (1 << (ea
- 1));
3154 rd
= ((signed short) rd
) >> ea
;
3158 case O (O_SHAL
, SL
):
3159 case O (O_SHAR
, SL
):
3160 if (fetch2 (sd
, &code
->dst
, &rd
))
3163 if (code
->src
.type
== X (OP_IMM
, SL
))
3164 fetch (sd
, &code
->src
, &ea
);
3168 if (code
->opcode
== O (O_SHAL
, SL
))
3170 c
= rd
& (0x80000000 >> (ea
- 1));
3171 res
= rd
>> (31 - ea
);
3172 v
= ((res
& 1) && !(res
& 2))
3173 || (!(res
& 1) && (res
& 2));
3178 c
= rd
& (1 << (ea
- 1));
3180 rd
= ((signed int) rd
) >> ea
;
3184 case O (O_ROTL
, SB
):
3185 case O (O_ROTR
, SB
):
3186 if (fetch2 (sd
, &code
->dst
, &rd
))
3189 if (code
->src
.type
== X (OP_IMM
, SB
))
3190 fetch (sd
, &code
->src
, &ea
);
3195 if (code
->opcode
== O (O_ROTL
, SB
))
3205 rd
= ((unsigned char) rd
) >> 1;
3213 case O (O_ROTL
, SW
):
3214 case O (O_ROTR
, SW
):
3215 if (fetch2 (sd
, &code
->dst
, &rd
))
3218 if (code
->src
.type
== X (OP_IMM
, SW
))
3219 fetch (sd
, &code
->src
, &ea
);
3224 if (code
->opcode
== O (O_ROTL
, SW
))
3234 rd
= ((unsigned short) rd
) >> 1;
3242 case O (O_ROTL
, SL
):
3243 case O (O_ROTR
, SL
):
3244 if (fetch2 (sd
, &code
->dst
, &rd
))
3247 if (code
->src
.type
== X (OP_IMM
, SL
))
3248 fetch (sd
, &code
->src
, &ea
);
3253 if (code
->opcode
== O (O_ROTL
, SL
))
3255 c
= rd
& 0x80000000;
3263 rd
= ((unsigned int) rd
) >> 1;
3271 case O (O_ROTXL
, SB
):
3272 case O (O_ROTXR
, SB
):
3273 if (fetch2 (sd
, &code
->dst
, &rd
))
3276 if (code
->src
.type
== X (OP_IMM
, SB
))
3277 fetch (sd
, &code
->src
, &ea
);
3282 if (code
->opcode
== O (O_ROTXL
, SB
))
3293 rd
= ((unsigned char) rd
) >> 1;
3302 case O (O_ROTXL
, SW
):
3303 case O (O_ROTXR
, SW
):
3304 if (fetch2 (sd
, &code
->dst
, &rd
))
3307 if (code
->src
.type
== X (OP_IMM
, SW
))
3308 fetch (sd
, &code
->src
, &ea
);
3313 if (code
->opcode
== O (O_ROTXL
, SW
))
3324 rd
= ((unsigned short) rd
) >> 1;
3333 case O (O_ROTXL
, SL
):
3334 case O (O_ROTXR
, SL
):
3335 if (fetch2 (sd
, &code
->dst
, &rd
))
3338 if (code
->src
.type
== X (OP_IMM
, SL
))
3339 fetch (sd
, &code
->src
, &ea
);
3344 if (code
->opcode
== O (O_ROTXL
, SL
))
3346 res
= rd
& 0x80000000;
3355 rd
= ((unsigned int) rd
) >> 1;
3366 case O (O_JMP
, SB
): /* jmp */
3368 fetch (sd
, &code
->src
, &pc
);
3373 case O (O_JSR
, SB
): /* jsr, jump to subroutine */
3375 if (fetch (sd
, &code
->src
, &pc
))
3378 tmp
= h8_get_reg (sd
, SP_REGNUM
);
3380 if (h8300hmode
&& !h8300_normal_mode
)
3383 SET_MEMORY_L (tmp
, code
->next_pc
);
3388 SET_MEMORY_W (tmp
, code
->next_pc
);
3390 h8_set_reg (sd
, SP_REGNUM
, tmp
);
3396 case O (O_BSR
, SB
): /* bsr, branch to subroutine */
3397 if (fetch (sd
, &code
->src
, &res
))
3399 pc
= code
->next_pc
+ res
;
3402 case O (O_RTE
, SN
): /* rte, return from exception */
3404 /* Pops exr and ccr before pc -- otherwise identical to rts. */
3405 tmp
= h8_get_reg (sd
, SP_REGNUM
);
3407 if (h8300smode
) /* pop exr */
3409 h8_set_exr (sd
, GET_MEMORY_L (tmp
));
3412 if (h8300hmode
&& !h8300_normal_mode
)
3414 h8_set_ccr (sd
, GET_MEMORY_L (tmp
));
3416 pc
= GET_MEMORY_L (tmp
);
3421 h8_set_ccr (sd
, GET_MEMORY_W (tmp
));
3423 pc
= GET_MEMORY_W (tmp
);
3428 h8_set_reg (sd
, SP_REGNUM
, tmp
);
3431 case O (O_RTS
, SN
): /* rts, return from subroutine */
3433 tmp
= h8_get_reg (sd
, SP_REGNUM
);
3435 if (h8300hmode
&& !h8300_normal_mode
)
3437 pc
= GET_MEMORY_L (tmp
);
3442 pc
= GET_MEMORY_W (tmp
);
3446 h8_set_reg (sd
, SP_REGNUM
, tmp
);
3449 case O (O_ILL
, SB
): /* illegal */
3450 sim_engine_halt (sd
, cpu
, NULL
, pc
, sim_stopped
, SIM_SIGILL
);
3453 case O (O_SLEEP
, SN
): /* sleep */
3454 /* Check for magic numbers in r1 and r2. */
3455 if ((h8_get_reg (sd
, R1_REGNUM
) & 0xffff) == LIBC_EXIT_MAGIC1
&&
3456 (h8_get_reg (sd
, R2_REGNUM
) & 0xffff) == LIBC_EXIT_MAGIC2
&&
3457 SIM_WIFEXITED (h8_get_reg (sd
, 0)))
3459 /* This trap comes from _exit, not from gdb. */
3460 sim_engine_halt (sd
, cpu
, NULL
, pc
, sim_exited
,
3461 SIM_WEXITSTATUS (h8_get_reg (sd
, 0)));
3464 /* Unfortunately this won't really work, because
3465 when we take a breakpoint trap, R0 has a "random",
3466 user-defined value. Don't see any immediate solution. */
3467 else if (SIM_WIFSTOPPED (h8_get_reg (sd
, 0)))
3469 /* Pass the stop signal up to gdb. */
3470 sim_engine_halt (sd
, cpu
, NULL
, pc
, sim_stopped
,
3471 SIM_WSTOPSIG (h8_get_reg (sd
, 0)));
3476 /* Treat it as a sigtrap. */
3477 sim_engine_halt (sd
, cpu
, NULL
, pc
, sim_stopped
, SIM_SIGTRAP
);
3481 case O (O_TRAPA
, SB
): /* trapa */
3482 if (fetch (sd
, &code
->src
, &res
))
3483 goto end
; /* res is vector number. */
3485 tmp
= h8_get_reg (sd
, SP_REGNUM
);
3486 if(h8300_normal_mode
)
3489 SET_MEMORY_W (tmp
, code
->next_pc
);
3491 SET_MEMORY_W (tmp
, h8_get_ccr (sd
));
3496 SET_MEMORY_L (tmp
, code
->next_pc
);
3498 SET_MEMORY_L (tmp
, h8_get_ccr (sd
));
3506 SET_MEMORY_L (tmp
, h8_get_exr (sd
));
3509 h8_set_reg (sd
, SP_REGNUM
, tmp
);
3511 if(h8300_normal_mode
)
3512 pc
= GET_MEMORY_L (0x10 + res
* 2); /* Vector addresses are 0x10,0x12,0x14 and 0x16 */
3514 pc
= GET_MEMORY_L (0x20 + res
* 4);
3518 sim_engine_halt (sd
, cpu
, NULL
, pc
, sim_stopped
, SIM_SIGTRAP
);
3521 case O (O_BSETEQ
, SB
):
3526 case O (O_BSETNE
, SB
):
3531 case O (O_BCLREQ
, SB
):
3536 case O (O_BCLRNE
, SB
):
3541 OBITOP (O_BNOT
, 1, 1, ea
^= m
); /* bnot */
3542 OBITOP (O_BTST
, 1, 0, nz
= ea
& m
); /* btst */
3544 OBITOP (O_BSET
, 1, 1, ea
|= m
); /* bset */
3546 OBITOP (O_BCLR
, 1, 1, ea
&= ~m
); /* bclr */
3547 OBITOP (O_BLD
, 1, 0, c
= ea
& m
); /* bld */
3548 OBITOP (O_BILD
, 1, 0, c
= !(ea
& m
)); /* bild */
3549 OBITOP (O_BST
, 1, 1, ea
&= ~m
;
3550 if (C
) ea
|= m
); /* bst */
3551 OBITOP (O_BIST
, 1, 1, ea
&= ~m
;
3552 if (!C
) ea
|= m
); /* bist */
3553 OBITOP (O_BSTZ
, 1, 1, ea
&= ~m
;
3554 if (Z
) ea
|= m
); /* bstz */
3555 OBITOP (O_BISTZ
, 1, 1, ea
&= ~m
;
3556 if (!Z
) ea
|= m
); /* bistz */
3557 OBITOP (O_BAND
, 1, 0, c
= (ea
& m
) && C
); /* band */
3558 OBITOP (O_BIAND
, 1, 0, c
= !(ea
& m
) && C
); /* biand */
3559 OBITOP (O_BOR
, 1, 0, c
= (ea
& m
) || C
); /* bor */
3560 OBITOP (O_BIOR
, 1, 0, c
= !(ea
& m
) || C
); /* bior */
3561 OBITOP (O_BXOR
, 1, 0, c
= ((ea
& m
) != 0)!= C
); /* bxor */
3562 OBITOP (O_BIXOR
, 1, 0, c
= !(ea
& m
) != C
); /* bixor */
3564 case O (O_BFLD
, SB
): /* bfld */
3567 if (fetch (sd
, &code
->src
, &bit
))
3572 if (fetch (sd
, &code
->dst
, &ea
))
3582 if (store (sd
, &code
->op3
, ea
))
3587 case O(O_BFST
, SB
): /* bfst */
3588 /* bitfield store */
3589 /* NOTE: the imm8 value is in dst, and the ea value
3590 (which is actually the destination) is in op3.
3591 It has to be that way, to avoid breaking the assembler. */
3593 if (fetch (sd
, &code
->dst
, &bit
)) /* imm8 */
3595 if (bit
== 0) /* noop -- nothing to do. */
3598 if (fetch (sd
, &code
->src
, &rd
)) /* reg8 src */
3601 if (fetch2 (sd
, &code
->op3
, &ea
)) /* ea dst */
3604 /* Left-shift the register data into position. */
3605 for (tmp
= bit
; !(tmp
& 1); tmp
>>= 1)
3608 /* Combine it with the neighboring bits. */
3609 ea
= (ea
& ~bit
) | (rd
& bit
);
3612 if (store2 (sd
, &code
->op3
, ea
))
3616 case O (O_CLRMAC
, SN
): /* clrmac */
3617 h8_set_mach (sd
, 0);
3618 h8_set_macl (sd
, 0);
3619 h8_set_macZ (sd
, 1);
3620 h8_set_macV (sd
, 0);
3621 h8_set_macN (sd
, 0);
3624 case O (O_STMAC
, SL
): /* stmac, 260 */
3625 switch (code
->src
.type
) {
3626 case X (OP_MACH
, SL
):
3627 res
= h8_get_mach (sd
);
3628 if (res
& 0x200) /* sign extend */
3631 case X (OP_MACL
, SL
):
3632 res
= h8_get_macl (sd
);
3634 default: goto illegal
;
3636 nz
= !h8_get_macZ (sd
);
3637 n
= h8_get_macN (sd
);
3638 v
= h8_get_macV (sd
);
3640 if (store (sd
, &code
->dst
, res
))
3645 case O (O_LDMAC
, SL
): /* ldmac, 179 */
3646 if (fetch (sd
, &code
->src
, &rd
))
3649 switch (code
->dst
.type
) {
3650 case X (OP_MACH
, SL
):
3651 rd
&= 0x3ff; /* Truncate to 10 bits */
3652 h8_set_mach (sd
, rd
);
3654 case X (OP_MACL
, SL
):
3655 h8_set_macl (sd
, rd
);
3657 default: goto illegal
;
3659 h8_set_macV (sd
, 0);
3663 if (fetch (sd
, &code
->src
, &rd
) ||
3664 fetch (sd
, &code
->dst
, &res
))
3667 /* Ye gods, this is non-portable!
3668 However, the existing mul/div code is similar. */
3669 res
= SEXTSHORT (res
) * SEXTSHORT (rd
);
3671 if (h8_get_macS (sd
)) /* Saturating mode */
3673 long long mac
= h8_get_macl (sd
);
3675 if (mac
& 0x80000000) /* sign extend */
3676 mac
|= 0xffffffff00000000LL
;
3679 if (mac
> 0x7fffffff || mac
< 0xffffffff80000000LL
)
3680 h8_set_macV (sd
, 1);
3681 h8_set_macZ (sd
, (mac
== 0));
3682 h8_set_macN (sd
, (mac
< 0));
3683 h8_set_macl (sd
, (int) mac
);
3685 else /* "Less Saturating" mode */
3687 long long mac
= h8_get_mach (sd
);
3689 mac
+= h8_get_macl (sd
);
3691 if (mac
& 0x20000000000LL
) /* sign extend */
3692 mac
|= 0xfffffc0000000000LL
;
3695 if (mac
> 0x1ffffffffffLL
||
3696 mac
< (long long) 0xfffffe0000000000LL
)
3697 h8_set_macV (sd
, 1);
3698 h8_set_macZ (sd
, (mac
== 0));
3699 h8_set_macN (sd
, (mac
< 0));
3700 h8_set_macl (sd
, (int) mac
);
3702 h8_set_mach (sd
, (int) (mac
& 0x3ff));
3706 case O (O_MULS
, SW
): /* muls.w */
3707 if (fetch (sd
, &code
->src
, &ea
) ||
3708 fetch (sd
, &code
->dst
, &rd
))
3711 ea
= SEXTSHORT (ea
);
3712 res
= SEXTSHORT (ea
* SEXTSHORT (rd
));
3716 if (store (sd
, &code
->dst
, res
))
3721 case O (O_MULS
, SL
): /* muls.l */
3722 if (fetch (sd
, &code
->src
, &ea
) ||
3723 fetch (sd
, &code
->dst
, &rd
))
3728 n
= res
& 0x80000000;
3729 nz
= res
& 0xffffffff;
3730 if (store (sd
, &code
->dst
, res
))
3734 case O (O_MULSU
, SL
): /* muls/u.l */
3735 if (fetch (sd
, &code
->src
, &ea
) ||
3736 fetch (sd
, &code
->dst
, &rd
))
3739 /* Compute upper 32 bits of the 64-bit result. */
3740 res
= (((long long) ea
) * ((long long) rd
)) >> 32;
3742 n
= res
& 0x80000000;
3743 nz
= res
& 0xffffffff;
3744 if (store (sd
, &code
->dst
, res
))
3748 case O (O_MULU
, SW
): /* mulu.w */
3749 if (fetch (sd
, &code
->src
, &ea
) ||
3750 fetch (sd
, &code
->dst
, &rd
))
3753 res
= UEXTSHORT ((UEXTSHORT (ea
) * UEXTSHORT (rd
)));
3755 /* Don't set Z or N. */
3756 if (store (sd
, &code
->dst
, res
))
3761 case O (O_MULU
, SL
): /* mulu.l */
3762 if (fetch (sd
, &code
->src
, &ea
) ||
3763 fetch (sd
, &code
->dst
, &rd
))
3768 /* Don't set Z or N. */
3769 if (store (sd
, &code
->dst
, res
))
3774 case O (O_MULUU
, SL
): /* mulu/u.l */
3775 if (fetch (sd
, &code
->src
, &ea
) ||
3776 fetch (sd
, &code
->dst
, &rd
))
3779 /* Compute upper 32 bits of the 64-bit result. */
3780 res
= (((unsigned long long) (unsigned) ea
) *
3781 ((unsigned long long) (unsigned) rd
)) >> 32;
3783 /* Don't set Z or N. */
3784 if (store (sd
, &code
->dst
, res
))
3789 case O (O_MULXS
, SB
): /* mulxs.b */
3790 if (fetch (sd
, &code
->src
, &ea
) ||
3791 fetch (sd
, &code
->dst
, &rd
))
3795 res
= ea
* SEXTCHAR (rd
);
3799 if (store (sd
, &code
->dst
, res
))
3804 case O (O_MULXS
, SW
): /* mulxs.w */
3805 if (fetch (sd
, &code
->src
, &ea
) ||
3806 fetch (sd
, &code
->dst
, &rd
))
3809 ea
= SEXTSHORT (ea
);
3810 res
= ea
* SEXTSHORT (rd
& 0xffff);
3812 n
= res
& 0x80000000;
3813 nz
= res
& 0xffffffff;
3814 if (store (sd
, &code
->dst
, res
))
3819 case O (O_MULXU
, SB
): /* mulxu.b */
3820 if (fetch (sd
, &code
->src
, &ea
) ||
3821 fetch (sd
, &code
->dst
, &rd
))
3824 res
= UEXTCHAR (ea
) * UEXTCHAR (rd
);
3826 if (store (sd
, &code
->dst
, res
))
3831 case O (O_MULXU
, SW
): /* mulxu.w */
3832 if (fetch (sd
, &code
->src
, &ea
) ||
3833 fetch (sd
, &code
->dst
, &rd
))
3836 res
= UEXTSHORT (ea
) * UEXTSHORT (rd
);
3838 if (store (sd
, &code
->dst
, res
))
3843 case O (O_TAS
, SB
): /* tas (test and set) */
3844 if (!h8300sxmode
) /* h8sx can use any register. */
3845 switch (code
->src
.reg
)
3856 if (fetch (sd
, &code
->src
, &res
))
3858 if (store (sd
, &code
->src
, res
| 0x80))
3861 goto just_flags_log8
;
3863 case O (O_DIVU
, SW
): /* divu.w */
3864 if (fetch (sd
, &code
->src
, &ea
) ||
3865 fetch (sd
, &code
->dst
, &rd
))
3871 res
= (unsigned) (UEXTSHORT (rd
) / UEXTSHORT (ea
));
3875 if (store (sd
, &code
->dst
, res
))
3879 case O (O_DIVU
, SL
): /* divu.l */
3880 if (fetch (sd
, &code
->src
, &ea
) ||
3881 fetch (sd
, &code
->dst
, &rd
))
3884 n
= ea
& 0x80000000;
3885 nz
= ea
& 0xffffffff;
3887 res
= (unsigned) rd
/ ea
;
3891 if (store (sd
, &code
->dst
, res
))
3895 case O (O_DIVS
, SW
): /* divs.w */
3896 if (fetch (sd
, &code
->src
, &ea
) ||
3897 fetch (sd
, &code
->dst
, &rd
))
3902 res
= SEXTSHORT (rd
) / SEXTSHORT (ea
);
3912 if (store (sd
, &code
->dst
, res
))
3916 case O (O_DIVS
, SL
): /* divs.l */
3917 if (fetch (sd
, &code
->src
, &ea
) ||
3918 fetch (sd
, &code
->dst
, &rd
))
3932 n
= res
& 0x80000000;
3933 if (store (sd
, &code
->dst
, res
))
3937 case O (O_DIVXU
, SB
): /* divxu.b */
3938 if (fetch (sd
, &code
->src
, &ea
) ||
3939 fetch (sd
, &code
->dst
, &rd
))
3942 rd
= UEXTSHORT (rd
);
3949 tmp
= (unsigned) rd
% ea
;
3950 res
= (unsigned) rd
/ ea
;
3958 if (store (sd
, &code
->dst
, (res
& 0xff) | (tmp
<< 8)))
3962 case O (O_DIVXU
, SW
): /* divxu.w */
3963 if (fetch (sd
, &code
->src
, &ea
) ||
3964 fetch (sd
, &code
->dst
, &rd
))
3967 ea
= UEXTSHORT (ea
);
3973 tmp
= (unsigned) rd
% ea
;
3974 res
= (unsigned) rd
/ ea
;
3982 if (store (sd
, &code
->dst
, (res
& 0xffff) | (tmp
<< 16)))
3986 case O (O_DIVXS
, SB
): /* divxs.b */
3987 if (fetch (sd
, &code
->src
, &ea
) ||
3988 fetch (sd
, &code
->dst
, &rd
))
3991 rd
= SEXTSHORT (rd
);
3996 tmp
= (int) rd
% (int) ea
;
3997 res
= (int) rd
/ (int) ea
;
4008 if (store (sd
, &code
->dst
, (res
& 0xff) | (tmp
<< 8)))
4012 case O (O_DIVXS
, SW
): /* divxs.w */
4013 if (fetch (sd
, &code
->src
, &ea
) ||
4014 fetch (sd
, &code
->dst
, &rd
))
4017 ea
= SEXTSHORT (ea
);
4021 tmp
= (int) rd
% (int) ea
;
4022 res
= (int) rd
/ (int) ea
;
4032 n
= res
& 0x80000000;
4033 if (store (sd
, &code
->dst
, (res
& 0xffff) | (tmp
<< 16)))
4037 case O (O_EXTS
, SW
): /* exts.w, signed extend */
4038 if (fetch2 (sd
, &code
->dst
, &rd
))
4040 ea
= rd
& 0x80 ? -256 : 0;
4041 res
= (rd
& 0xff) + ea
;
4044 case O (O_EXTS
, SL
): /* exts.l, signed extend */
4045 if (fetch2 (sd
, &code
->dst
, &rd
))
4047 if (code
->src
.type
== X (OP_IMM
, SL
))
4049 if (fetch (sd
, &code
->src
, &ea
))
4052 if (ea
== 2) /* exts.l #2, nn */
4054 /* Sign-extend from 8-bit to 32-bit. */
4055 ea
= rd
& 0x80 ? -256 : 0;
4056 res
= (rd
& 0xff) + ea
;
4060 /* Sign-extend from 16-bit to 32-bit. */
4061 ea
= rd
& 0x8000 ? -65536 : 0;
4062 res
= (rd
& 0xffff) + ea
;
4065 case O (O_EXTU
, SW
): /* extu.w, unsigned extend */
4066 if (fetch2 (sd
, &code
->dst
, &rd
))
4069 res
= (rd
& 0xff) + ea
;
4072 case O (O_EXTU
, SL
): /* extu.l, unsigned extend */
4073 if (fetch2 (sd
, &code
->dst
, &rd
))
4075 if (code
->src
.type
== X (OP_IMM
, SL
))
4077 if (fetch (sd
, &code
->src
, &ea
))
4080 if (ea
== 2) /* extu.l #2, nn */
4082 /* Zero-extend from 8-bit to 32-bit. */
4084 res
= (rd
& 0xff) + ea
;
4088 /* Zero-extend from 16-bit to 32-bit. */
4090 res
= (rd
& 0xffff) + ea
;
4093 case O (O_NOP
, SN
): /* nop */
4096 case O (O_STM
, SL
): /* stm, store to memory */
4098 int nregs
, firstreg
, i
;
4100 nregs
= GET_MEMORY_B (pc
+ 1);
4103 firstreg
= code
->src
.reg
;
4105 for (i
= firstreg
; i
<= firstreg
+ nregs
; i
++)
4107 h8_set_reg (sd
, SP_REGNUM
, h8_get_reg (sd
, SP_REGNUM
) - 4);
4108 SET_MEMORY_L (h8_get_reg (sd
, SP_REGNUM
), h8_get_reg (sd
, i
));
4113 case O (O_LDM
, SL
): /* ldm, load from memory */
4114 case O (O_RTEL
, SN
): /* rte/l, ldm plus rte */
4115 case O (O_RTSL
, SN
): /* rts/l, ldm plus rts */
4117 int nregs
, firstreg
, i
;
4119 nregs
= ((GET_MEMORY_B (pc
+ 1) >> 4) & 0xf);
4120 firstreg
= code
->dst
.reg
& 0xf;
4121 for (i
= firstreg
; i
>= firstreg
- nregs
; i
--)
4123 h8_set_reg (sd
, i
, GET_MEMORY_L (h8_get_reg (sd
, SP_REGNUM
)));
4124 h8_set_reg (sd
, SP_REGNUM
, h8_get_reg (sd
, SP_REGNUM
) + 4);
4127 switch (code
->opcode
) {
4128 case O (O_RTEL
, SN
):
4130 case O (O_RTSL
, SN
):
4139 /* Decimal Adjust Addition. This is for BCD arithmetic. */
4140 res
= GET_B_REG (code
->src
.reg
); /* FIXME fetch? */
4141 if (!c
&& (0 <= (res
>> 4) && (res
>> 4) <= 9) &&
4142 !h
&& (0 <= (res
& 0xf) && (res
& 0xf) <= 9))
4143 res
= res
; /* Value added == 0. */
4144 else if (!c
&& (0 <= (res
>> 4) && (res
>> 4) <= 8) &&
4145 !h
&& (10 <= (res
& 0xf) && (res
& 0xf) <= 15))
4146 res
= res
+ 0x6; /* Value added == 6. */
4147 else if (!c
&& (0 <= (res
>> 4) && (res
>> 4) <= 9) &&
4148 h
&& (0 <= (res
& 0xf) && (res
& 0xf) <= 3))
4149 res
= res
+ 0x6; /* Value added == 6. */
4150 else if (!c
&& (10 <= (res
>> 4) && (res
>> 4) <= 15) &&
4151 !h
&& (0 <= (res
& 0xf) && (res
& 0xf) <= 9))
4152 res
= res
+ 0x60; /* Value added == 60. */
4153 else if (!c
&& (9 <= (res
>> 4) && (res
>> 4) <= 15) &&
4154 !h
&& (10 <= (res
& 0xf) && (res
& 0xf) <= 15))
4155 res
= res
+ 0x66; /* Value added == 66. */
4156 else if (!c
&& (10 <= (res
>> 4) && (res
>> 4) <= 15) &&
4157 h
&& (0 <= (res
& 0xf) && (res
& 0xf) <= 3))
4158 res
= res
+ 0x66; /* Value added == 66. */
4159 else if ( c
&& (1 <= (res
>> 4) && (res
>> 4) <= 2) &&
4160 !h
&& (0 <= (res
& 0xf) && (res
& 0xf) <= 9))
4161 res
= res
+ 0x60; /* Value added == 60. */
4162 else if ( c
&& (1 <= (res
>> 4) && (res
>> 4) <= 2) &&
4163 !h
&& (10 <= (res
& 0xf) && (res
& 0xf) <= 15))
4164 res
= res
+ 0x66; /* Value added == 66. */
4165 else if (c
&& (1 <= (res
>> 4) && (res
>> 4) <= 3) &&
4166 h
&& (0 <= (res
& 0xf) && (res
& 0xf) <= 3))
4167 res
= res
+ 0x66; /* Value added == 66. */
4172 /* Decimal Adjust Subtraction. This is for BCD arithmetic. */
4173 res
= GET_B_REG (code
->src
.reg
); /* FIXME fetch, fetch2... */
4174 if (!c
&& (0 <= (res
>> 4) && (res
>> 4) <= 9) &&
4175 !h
&& (0 <= (res
& 0xf) && (res
& 0xf) <= 9))
4176 res
= res
; /* Value added == 0. */
4177 else if (!c
&& (0 <= (res
>> 4) && (res
>> 4) <= 8) &&
4178 h
&& (6 <= (res
& 0xf) && (res
& 0xf) <= 15))
4179 res
= res
+ 0xfa; /* Value added == 0xfa. */
4180 else if ( c
&& (7 <= (res
>> 4) && (res
>> 4) <= 15) &&
4181 !h
&& (0 <= (res
& 0xf) && (res
& 0xf) <= 9))
4182 res
= res
+ 0xa0; /* Value added == 0xa0. */
4183 else if (c
&& (6 <= (res
>> 4) && (res
>> 4) <= 15) &&
4184 h
&& (6 <= (res
& 0xf) && (res
& 0xf) <= 15))
4185 res
= res
+ 0x9a; /* Value added == 0x9a. */
4191 sim_engine_halt (sd
, cpu
, NULL
, pc
, sim_stopped
, SIM_SIGILL
);
4196 sim_io_printf (sd
, "sim_resume: internal error.\n");
4197 sim_engine_halt (sd
, cpu
, NULL
, pc
, sim_stopped
, SIM_SIGILL
);
4201 if (code
->dst
.type
== X (OP_CCR
, SB
) ||
4202 code
->dst
.type
== X (OP_CCR
, SW
))
4204 h8_set_ccr (sd
, res
);
4207 else if (h8300smode
&&
4208 (code
->dst
.type
== X (OP_EXR
, SB
) ||
4209 code
->dst
.type
== X (OP_EXR
, SW
)))
4211 h8_set_exr (sd
, res
);
4212 if (h8300smode
) /* Get exr. */
4214 trace
= (h8_get_exr (sd
) >> 7) & 1;
4215 intMask
= h8_get_exr (sd
) & 7;
4224 /* When a branch works */
4225 if (fetch (sd
, &code
->src
, &res
))
4227 if (res
& 1) /* bad address */
4229 pc
= code
->next_pc
+ res
;
4232 /* Set the cond codes from res */
4235 /* Set the flags after an 8 bit inc/dec operation */
4239 v
= (rd
& 0x7f) == 0x7f;
4242 /* Set the flags after an 16 bit inc/dec operation */
4246 v
= (rd
& 0x7fff) == 0x7fff;
4249 /* Set the flags after an 32 bit inc/dec operation */
4251 n
= res
& 0x80000000;
4252 nz
= res
& 0xffffffff;
4253 v
= (rd
& 0x7fffffff) == 0x7fffffff;
4257 /* Set flags after an 8 bit shift op, carry,overflow set in insn */
4260 if (store2 (sd
, &code
->dst
, rd
))
4265 /* Set flags after an 16 bit shift op, carry,overflow set in insn */
4268 if (store2 (sd
, &code
->dst
, rd
))
4273 /* Set flags after an 32 bit shift op, carry,overflow set in insn */
4274 n
= (rd
& 0x80000000);
4275 nz
= rd
& 0xffffffff;
4276 if (store2 (sd
, &code
->dst
, rd
))
4281 if (store2 (sd
, &code
->dst
, res
))
4285 /* flags after a 32bit logical operation */
4286 n
= res
& 0x80000000;
4287 nz
= res
& 0xffffffff;
4292 if (store2 (sd
, &code
->dst
, res
))
4296 /* flags after a 16bit logical operation */
4303 if (store2 (sd
, &code
->dst
, res
))
4313 if (store2 (sd
, &code
->dst
, res
))
4320 switch (code
->opcode
/ 4)
4324 v
= ((rd
& 0x80) == (ea
& 0x80)
4325 && (rd
& 0x80) != (res
& 0x80));
4330 v
= ((rd
& 0x80) != (-ea
& 0x80)
4331 && (rd
& 0x80) != (res
& 0x80));
4338 break; /* No effect on v flag. */
4343 if (store2 (sd
, &code
->dst
, res
))
4349 c
= (res
& 0x10000);
4350 switch (code
->opcode
/ 4)
4354 v
= ((rd
& 0x8000) == (ea
& 0x8000)
4355 && (rd
& 0x8000) != (res
& 0x8000));
4360 v
= ((rd
& 0x8000) != (-ea
& 0x8000)
4361 && (rd
& 0x8000) != (res
& 0x8000));
4370 if (store2 (sd
, &code
->dst
, res
))
4374 n
= res
& 0x80000000;
4375 nz
= res
& 0xffffffff;
4376 switch (code
->opcode
/ 4)
4380 v
= ((rd
& 0x80000000) == (ea
& 0x80000000)
4381 && (rd
& 0x80000000) != (res
& 0x80000000));
4382 c
= ((unsigned) res
< (unsigned) rd
) ||
4383 ((unsigned) res
< (unsigned) ea
);
4388 v
= ((rd
& 0x80000000) != (-ea
& 0x80000000)
4389 && (rd
& 0x80000000) != (res
& 0x80000000));
4390 c
= (unsigned) rd
< (unsigned) -ea
;
4393 v
= (rd
== 0x80000000);
4400 if ((res
= h8_get_delayed_branch (sd
)) != 0)
4403 h8_set_delayed_branch (sd
, 0);
4411 h8_set_ticks (sd
, h8_get_ticks (sd
) + get_now () - tick_start
);
4412 h8_set_cycles (sd
, h8_get_cycles (sd
) + cycles
);
4413 h8_set_insts (sd
, h8_get_insts (sd
) + insts
);
4418 h8_set_exr (sd
, (trace
<<7) | intMask
);
4420 h8_set_mask (sd
, oldmask
);
4424 sim_engine_run (SIM_DESC sd
,
4425 int next_cpu_nr
, /* ignore */
4426 int nr_cpus
, /* ignore */
4431 SIM_ASSERT (STATE_MAGIC (sd
) == SIM_MAGIC_NUMBER
);
4433 cpu
= STATE_CPU (sd
, 0);
4437 step_once (sd
, cpu
);
4438 if (sim_events_tick (sd
))
4439 sim_events_process (sd
);
4444 sim_write (SIM_DESC sd
, SIM_ADDR addr
, const unsigned char *buffer
, int size
)
4451 for (i
= 0; i
< size
; i
++)
4453 if (addr
< memory_size
)
4455 h8_set_memory (sd
, addr
+ i
, buffer
[i
]);
4464 sim_read (SIM_DESC sd
, SIM_ADDR addr
, unsigned char *buffer
, int size
)
4469 if (addr
+ size
< memory_size
)
4470 memcpy (buffer
, h8_get_memory_buf (sd
) + addr
, size
);
4477 h8300_reg_store (SIM_CPU
*cpu
, int rn
, unsigned char *value
, int length
)
4482 longval
= (value
[0] << 24) | (value
[1] << 16) | (value
[2] << 8) | value
[3];
4483 shortval
= (value
[0] << 8) | (value
[1]);
4484 intval
= h8300hmode
? longval
: shortval
;
4486 init_pointers (CPU_STATE (cpu
));
4490 if(h8300_normal_mode
)
4491 cpu
->pc
= shortval
; /* PC for Normal mode is 2 bytes */
4511 cpu
->regs
[rn
] = intval
;
4516 cpu
->regs
[rn
] = longval
;
4523 h8300_reg_fetch (SIM_CPU
*cpu
, int rn
, unsigned char *buf
, int length
)
4528 init_pointers (CPU_STATE (cpu
));
4530 if (!h8300smode
&& rn
>= EXR_REGNUM
)
4565 /* In Normal mode PC is 2 byte, but other registers are 4 byte */
4566 if ((h8300hmode
|| longreg
) && !(rn
== PC_REGNUM
&& h8300_normal_mode
))
4583 sim_info (SIM_DESC sd
, int verbose
)
4585 const struct h8300_sim_state
*state
= H8300_SIM_STATE (sd
);
4586 double timetaken
= (double) h8_get_ticks (sd
) / (double) now_persec ();
4587 double virttime
= h8_get_cycles (sd
) / 10.0e6
;
4589 sim_io_printf (sd
, "\n\n#instructions executed %10d\n", h8_get_insts (sd
));
4590 sim_io_printf (sd
, "#cycles (v approximate) %10d\n", h8_get_cycles (sd
));
4591 sim_io_printf (sd
, "#real time taken %10.4f\n", timetaken
);
4592 sim_io_printf (sd
, "#virtual time taken %10.4f\n", virttime
);
4593 if (timetaken
!= 0.0)
4594 sim_io_printf (sd
, "#simulation ratio %10.4f\n", virttime
/ timetaken
);
4597 /* This to be conditional on `what' (aka `verbose'),
4598 however it was never passed as non-zero. */
4602 for (i
= 0; i
< O_LAST
; i
++)
4604 if (h8_get_stats (sd
, i
))
4605 sim_io_printf (sd
, "%d: %d\n", i
, h8_get_stats (sd
, i
));
4611 /* Indicate whether the cpu is an H8/300 or H8/300H.
4612 FLAG is non-zero for the H8/300H. */
4615 set_h8300h (unsigned long machine
)
4617 /* FIXME: Much of the code in sim_load can be moved to sim_open.
4618 This function being replaced by a sim_open:ARGV configuration
4621 h8300hmode
= h8300smode
= h8300sxmode
= h8300_normal_mode
= 0;
4623 if (machine
== bfd_mach_h8300sx
|| machine
== bfd_mach_h8300sxn
)
4626 if (machine
== bfd_mach_h8300s
|| machine
== bfd_mach_h8300sn
|| h8300sxmode
)
4629 if (machine
== bfd_mach_h8300h
|| machine
== bfd_mach_h8300hn
|| h8300smode
)
4632 if(machine
== bfd_mach_h8300hn
|| machine
== bfd_mach_h8300sn
|| machine
== bfd_mach_h8300sxn
)
4633 h8300_normal_mode
= 1;
4636 /* H8300-specific options.
4637 TODO: These really should be merged into the common model modules. */
4645 h8300_option_handler (SIM_DESC sd
, sim_cpu
*cpu ATTRIBUTE_UNUSED
, int opt
,
4646 char *arg
, int is_command ATTRIBUTE_UNUSED
)
4648 switch ((H8300_OPTIONS
) opt
)
4651 set_h8300h (bfd_mach_h8300h
);
4654 set_h8300h (bfd_mach_h8300s
);
4656 case OPTION_H8300SX
:
4657 set_h8300h (bfd_mach_h8300sx
);
4661 /* We'll actually never get here; the caller handles the error
4663 sim_io_eprintf (sd
, "Unknown option `%s'\n", arg
);
4670 static const OPTION h8300_options
[] =
4672 { {"h8300h", no_argument
, NULL
, OPTION_H8300H
},
4673 'h', NULL
, "Indicate the CPU is H8/300H",
4674 h8300_option_handler
},
4675 { {"h8300s", no_argument
, NULL
, OPTION_H8300S
},
4676 'S', NULL
, "Indicate the CPU is H8S",
4677 h8300_option_handler
},
4678 { {"h8300sx", no_argument
, NULL
, OPTION_H8300SX
},
4679 'x', NULL
, "Indicate the CPU is H8SX",
4680 h8300_option_handler
},
4681 { {NULL
, no_argument
, NULL
, 0}, '\0', NULL
, NULL
, NULL
, NULL
}
4685 h8300_pc_get (sim_cpu
*cpu
)
4691 h8300_pc_set (sim_cpu
*cpu
, sim_cia pc
)
4696 /* Cover function of sim_state_free to free the cpu buffers as well. */
4699 free_state (SIM_DESC sd
)
4701 if (STATE_MODULES (sd
) != NULL
)
4702 sim_module_uninstall (sd
);
4704 /* Fixme: free buffers in _sim_cpu. */
4705 sim_state_free (sd
);
4709 sim_open (SIM_OPEN_KIND kind
,
4710 struct host_callback_struct
*callback
,
4718 sd
= sim_state_alloc_extra (kind
, callback
, sizeof (struct h8300_sim_state
));
4720 /* Set default options before parsing user options. */
4721 current_target_byte_order
= BFD_ENDIAN_BIG
;
4723 /* The cpu data is kept in a separately allocated chunk of memory. */
4724 if (sim_cpu_alloc_all (sd
, 1) != SIM_RC_OK
)
4730 cpu
= STATE_CPU (sd
, 0);
4731 SIM_ASSERT (STATE_MAGIC (sd
) == SIM_MAGIC_NUMBER
);
4732 cpu
->regs
[SBR_REGNUM
] = 0xFFFFFF00;
4733 /* sim_cpu object is new, so some initialization is needed. */
4734 init_pointers_needed
= 1;
4736 if (sim_pre_argv_init (sd
, argv
[0]) != SIM_RC_OK
)
4742 if (sim_add_option_table (sd
, NULL
, h8300_options
) != SIM_RC_OK
)
4748 /* The parser will print an error message for us, so we silently return. */
4749 if (sim_parse_args (sd
, argv
) != SIM_RC_OK
)
4751 /* Uninstall the modules to avoid memory leaks,
4752 file descriptor leaks, etc. */
4757 /* Check for/establish the a reference program image. */
4758 if (sim_analyze_program (sd
, STATE_PROG_FILE (sd
), abfd
) != SIM_RC_OK
)
4764 /* Establish any remaining configuration options. */
4765 if (sim_config (sd
) != SIM_RC_OK
)
4771 if (sim_post_argv_init (sd
) != SIM_RC_OK
)
4773 /* Uninstall the modules to avoid memory leaks,
4774 file descriptor leaks, etc. */
4779 /* CPU specific initialization. */
4780 for (i
= 0; i
< MAX_NR_PROCESSORS
; ++i
)
4782 SIM_CPU
*cpu
= STATE_CPU (sd
, i
);
4784 CPU_REG_FETCH (cpu
) = h8300_reg_fetch
;
4785 CPU_REG_STORE (cpu
) = h8300_reg_store
;
4786 CPU_PC_FETCH (cpu
) = h8300_pc_get
;
4787 CPU_PC_STORE (cpu
) = h8300_pc_set
;
4790 /* sim_hw_configure (sd); */
4792 /* FIXME: Much of the code in sim_load can be moved here. */
4797 /* Called by gdb to load a program into memory. */
4800 sim_load (SIM_DESC sd
, const char *prog
, bfd
*abfd
, int from_tty
)
4802 struct h8300_sim_state
*state
= H8300_SIM_STATE (sd
);
4805 /* FIXME: The code below that sets a specific variant of the H8/300
4806 being simulated should be moved to sim_open(). */
4808 /* See if the file is for the H8/300 or H8/300H. */
4809 /* ??? This may not be the most efficient way. The z8k simulator
4810 does this via a different mechanism (INIT_EXTRA_SYMTAB_INFO). */
4814 prog_bfd
= bfd_openr (prog
, NULL
);
4815 if (prog_bfd
!= NULL
)
4817 /* Set the cpu type. We ignore failure from bfd_check_format
4818 and bfd_openr as sim_load_file checks too. */
4819 if (bfd_check_format (prog_bfd
, bfd_object
))
4821 set_h8300h (bfd_get_mach (prog_bfd
));
4825 /* If we're using gdb attached to the simulator, then we have to
4826 reallocate memory for the simulator.
4828 When gdb first starts, it calls fetch_registers (among other
4829 functions), which in turn calls init_pointers, which allocates
4832 The problem is when we do that, we don't know whether we're
4833 debugging an H8/300 or H8/300H program.
4835 This is the first point at which we can make that determination,
4836 so we just reallocate memory now; this will also allow us to handle
4837 switching between H8/300 and H8/300H programs without exiting
4840 if (h8300smode
&& !h8300_normal_mode
)
4841 memory_size
= H8300S_MSIZE
;
4842 else if (h8300hmode
&& !h8300_normal_mode
)
4843 memory_size
= H8300H_MSIZE
;
4845 memory_size
= H8300_MSIZE
;
4847 if (h8_get_memory_buf (sd
))
4848 free (h8_get_memory_buf (sd
));
4850 h8_set_memory_buf (sd
, (unsigned char *)
4851 calloc (sizeof (char), memory_size
));
4852 state
->memory_size
= memory_size
;
4854 /* `msize' must be a power of two. */
4855 if ((memory_size
& (memory_size
- 1)) != 0)
4857 sim_io_printf (sd
, "sim_load: bad memory size.\n");
4860 h8_set_mask (sd
, memory_size
- 1);
4862 if (sim_load_file (sd
, STATE_MY_NAME (sd
), STATE_CALLBACK (sd
), prog
,
4863 prog_bfd
, STATE_OPEN_KIND (sd
) == SIM_OPEN_DEBUG
,
4867 /* Close the bfd if we opened it. */
4868 if (abfd
== NULL
&& prog_bfd
!= NULL
)
4869 bfd_close (prog_bfd
);
4873 /* Close the bfd if we opened it. */
4874 if (abfd
== NULL
&& prog_bfd
!= NULL
)
4875 bfd_close (prog_bfd
);
4880 sim_create_inferior (SIM_DESC sd
, struct bfd
*abfd
,
4881 char * const *argv
, char * const *env
)
4888 h8_set_pc (sd
, bfd_get_start_address (abfd
));
4892 /* Command Line support. */
4895 /* Counting the no. of commandline arguments. */
4896 for (no_of_args
= 0; argv
[no_of_args
] != NULL
; no_of_args
++)
4899 /* Allocating memory for the argv pointers. */
4900 h8_set_command_line (sd
, (char **) malloc ((sizeof (char *))
4901 * (no_of_args
+ 1)));
4903 for (i
= 0; i
< no_of_args
; i
++)
4905 /* Copying the argument string. */
4906 h8_set_cmdline_arg (sd
, i
, (char *) strdup (argv
[i
]));
4908 h8_set_cmdline_arg (sd
, i
, NULL
);