2 * Simulator for the Renesas (formerly Hitachi) H8/300 architecture.
4 * Written by Steve Chamberlain of Cygnus Support. sac@cygnus.com
6 * This file is part of H8/300 sim
9 * THIS SOFTWARE IS NOT COPYRIGHTED
11 * Cygnus offers the following for use in the public domain. Cygnus makes no
12 * warranty with regard to the software or its performance and the user
13 * accepts the software "AS IS" with all faults.
15 * CYGNUS DISCLAIMS ANY WARRANTIES, EXPRESS OR IMPLIED, WITH REGARD TO THIS
16 * SOFTWARE INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
17 * AND FITNESS FOR A PARTICULAR PURPOSE.
28 #ifdef HAVE_SYS_PARAM_H
29 #include <sys/param.h>
34 #include "gdb/sim-h8300.h"
36 #include "sys/types.h"
37 #include "sim-options.h"
45 /* FIXME: Needs to live in header file.
46 This header should also include the things in remote-sim.h.
47 One could move this to remote-sim.h but this function isn't needed
49 static void set_simcache_size (SIM_DESC
, int);
51 #define X(op, size) (op * 4 + size)
53 #define SP (h8300hmode && !h8300_normal_mode ? SL : SW)
55 #define h8_opcodes ops
57 #include "opcode/h8300.h"
59 /* CPU data object: */
62 sim_state_initialize (SIM_DESC sd
, sim_cpu
*cpu
)
64 /* FIXME: not really necessary, since sim_cpu_alloc calls zalloc. */
66 memset (&cpu
->regs
, 0, sizeof(cpu
->regs
));
67 cpu
->regs
[SBR_REGNUM
] = 0xFFFFFF00;
69 cpu
->delayed_branch
= 0;
74 /* Initialize local simulator state. */
76 sd
->sim_cache_size
= 0;
82 memset (&cpu
->stats
, 0, sizeof (cpu
->stats
));
88 h8_get_pc (SIM_DESC sd
)
90 return (STATE_CPU (sd
, 0)) -> pc
;
94 h8_set_pc (SIM_DESC sd
, unsigned int val
)
96 (STATE_CPU (sd
, 0)) -> pc
= val
;
100 h8_get_ccr (SIM_DESC sd
)
102 return (STATE_CPU (sd
, 0)) -> regs
[CCR_REGNUM
];
106 h8_set_ccr (SIM_DESC sd
, unsigned int val
)
108 (STATE_CPU (sd
, 0)) -> regs
[CCR_REGNUM
] = val
;
112 h8_get_exr (SIM_DESC sd
)
114 return (STATE_CPU (sd
, 0)) -> regs
[EXR_REGNUM
];
118 h8_set_exr (SIM_DESC sd
, unsigned int val
)
120 (STATE_CPU (sd
, 0)) -> regs
[EXR_REGNUM
] = val
;
124 h8_get_sbr (SIM_DESC sd
)
126 return (STATE_CPU (sd
, 0)) -> regs
[SBR_REGNUM
];
130 h8_set_sbr (SIM_DESC sd
, int val
)
132 (STATE_CPU (sd
, 0)) -> regs
[SBR_REGNUM
] = val
;
136 h8_get_vbr (SIM_DESC sd
)
138 return (STATE_CPU (sd
, 0)) -> regs
[VBR_REGNUM
];
142 h8_set_vbr (SIM_DESC sd
, int val
)
144 (STATE_CPU (sd
, 0)) -> regs
[VBR_REGNUM
] = val
;
148 h8_get_cache_top (SIM_DESC sd
)
150 return sd
-> cache_top
;
154 h8_set_cache_top (SIM_DESC sd
, int val
)
156 sd
-> cache_top
= val
;
160 h8_get_mask (SIM_DESC sd
)
162 return (STATE_CPU (sd
, 0)) -> mask
;
166 h8_set_mask (SIM_DESC sd
, int val
)
168 (STATE_CPU (sd
, 0)) -> mask
= val
;
172 h8_get_exception (SIM_DESC sd
)
174 return (STATE_CPU (sd
, 0)) -> exception
;
178 h8_set_exception (SIM_DESC sd
, int val
)
180 (STATE_CPU (sd
, 0)) -> exception
= val
;
183 static enum h8300_sim_state
184 h8_get_state (SIM_DESC sd
)
190 h8_set_state (SIM_DESC sd
, enum h8300_sim_state val
)
196 h8_get_cycles (SIM_DESC sd
)
198 return (STATE_CPU (sd
, 0)) -> regs
[CYCLE_REGNUM
];
202 h8_set_cycles (SIM_DESC sd
, unsigned int val
)
204 (STATE_CPU (sd
, 0)) -> regs
[CYCLE_REGNUM
] = val
;
208 h8_get_insts (SIM_DESC sd
)
210 return (STATE_CPU (sd
, 0)) -> regs
[INST_REGNUM
];
214 h8_set_insts (SIM_DESC sd
, unsigned int val
)
216 (STATE_CPU (sd
, 0)) -> regs
[INST_REGNUM
] = val
;
220 h8_get_ticks (SIM_DESC sd
)
222 return (STATE_CPU (sd
, 0)) -> regs
[TICK_REGNUM
];
226 h8_set_ticks (SIM_DESC sd
, unsigned int val
)
228 (STATE_CPU (sd
, 0)) -> regs
[TICK_REGNUM
] = val
;
232 h8_get_mach (SIM_DESC sd
)
234 return (STATE_CPU (sd
, 0)) -> regs
[MACH_REGNUM
];
238 h8_set_mach (SIM_DESC sd
, unsigned int val
)
240 (STATE_CPU (sd
, 0)) -> regs
[MACH_REGNUM
] = val
;
244 h8_get_macl (SIM_DESC sd
)
246 return (STATE_CPU (sd
, 0)) -> regs
[MACL_REGNUM
];
250 h8_set_macl (SIM_DESC sd
, unsigned int val
)
252 (STATE_CPU (sd
, 0)) -> regs
[MACL_REGNUM
] = val
;
256 h8_get_compiles (SIM_DESC sd
)
258 return sd
-> compiles
;
262 h8_increment_compiles (SIM_DESC sd
)
267 static unsigned int *
268 h8_get_reg_buf (SIM_DESC sd
)
270 return &(((STATE_CPU (sd
, 0)) -> regs
)[0]);
274 h8_get_reg (SIM_DESC sd
, int regnum
)
276 return (STATE_CPU (sd
, 0)) -> regs
[regnum
];
280 h8_set_reg (SIM_DESC sd
, int regnum
, int val
)
282 (STATE_CPU (sd
, 0)) -> regs
[regnum
] = val
;
287 h8_get_stats (SIM_DESC sd
, int idx
)
289 return sd
-> stats
[idx
];
293 h8_increment_stats (SIM_DESC sd
, int idx
)
299 static unsigned short *
300 h8_get_cache_idx_buf (SIM_DESC sd
)
302 return sd
-> cache_idx
;
306 h8_set_cache_idx_buf (SIM_DESC sd
, unsigned short *ptr
)
308 sd
-> cache_idx
= ptr
;
311 static unsigned short
312 h8_get_cache_idx (SIM_DESC sd
, unsigned int idx
)
314 if (idx
> sd
->memory_size
)
315 return (unsigned short) -1;
316 return sd
-> cache_idx
[idx
];
320 h8_set_cache_idx (SIM_DESC sd
, int idx
, unsigned int val
)
322 sd
-> cache_idx
[idx
] = (unsigned short) val
;
325 static unsigned char *
326 h8_get_memory_buf (SIM_DESC sd
)
328 return (STATE_CPU (sd
, 0)) -> memory
;
332 h8_set_memory_buf (SIM_DESC sd
, unsigned char *ptr
)
334 (STATE_CPU (sd
, 0)) -> memory
= ptr
;
338 h8_get_memory (SIM_DESC sd
, int idx
)
340 return (STATE_CPU (sd
, 0)) -> memory
[idx
];
344 h8_set_memory (SIM_DESC sd
, int idx
, unsigned int val
)
346 (STATE_CPU (sd
, 0)) -> memory
[idx
] = (unsigned char) val
;
349 static unsigned char *
350 h8_get_eightbit_buf (SIM_DESC sd
)
352 return (STATE_CPU (sd
, 0)) -> eightbit
;
356 h8_set_eightbit_buf (SIM_DESC sd
, unsigned char *ptr
)
358 (STATE_CPU (sd
, 0)) -> eightbit
= ptr
;
362 h8_get_eightbit (SIM_DESC sd
, int idx
)
364 return (STATE_CPU (sd
, 0)) -> eightbit
[idx
];
368 h8_set_eightbit (SIM_DESC sd
, int idx
, unsigned int val
)
370 (STATE_CPU (sd
, 0)) -> eightbit
[idx
] = (unsigned char) val
;
374 h8_get_delayed_branch (SIM_DESC sd
)
376 return (STATE_CPU (sd
, 0)) -> delayed_branch
;
380 h8_set_delayed_branch (SIM_DESC sd
, unsigned int dest
)
382 (STATE_CPU (sd
, 0)) -> delayed_branch
= dest
;
386 h8_get_command_line (SIM_DESC sd
)
388 return (STATE_CPU (sd
, 0)) -> command_line
;
392 h8_set_command_line (SIM_DESC sd
, char ** val
)
394 (STATE_CPU (sd
, 0)) -> command_line
= val
;
398 h8_get_cmdline_arg (SIM_DESC sd
, int index
)
400 return (STATE_CPU (sd
, 0)) -> command_line
[index
];
404 h8_set_cmdline_arg (SIM_DESC sd
, int index
, char * val
)
406 (STATE_CPU (sd
, 0)) -> command_line
[index
] = val
;
409 /* MAC Saturation Mode */
411 h8_get_macS (SIM_DESC sd
)
413 return (STATE_CPU (sd
, 0)) -> macS
;
417 h8_set_macS (SIM_DESC sd
, int val
)
419 (STATE_CPU (sd
, 0)) -> macS
= (val
!= 0);
424 h8_get_macZ (SIM_DESC sd
)
426 return (STATE_CPU (sd
, 0)) -> macZ
;
430 h8_set_macZ (SIM_DESC sd
, int val
)
432 (STATE_CPU (sd
, 0)) -> macZ
= (val
!= 0);
435 /* MAC Negative Flag */
437 h8_get_macN (SIM_DESC sd
)
439 return (STATE_CPU (sd
, 0)) -> macN
;
443 h8_set_macN (SIM_DESC sd
, int val
)
445 (STATE_CPU (sd
, 0)) -> macN
= (val
!= 0);
448 /* MAC Overflow Flag */
450 h8_get_macV (SIM_DESC sd
)
452 return (STATE_CPU (sd
, 0)) -> macV
;
456 h8_set_macV (SIM_DESC sd
, int val
)
458 (STATE_CPU (sd
, 0)) -> macV
= (val
!= 0);
461 /* End CPU data object. */
463 /* The rate at which to call the host's poll_quit callback. */
465 enum { POLL_QUIT_INTERVAL
= 0x80000 };
467 #define LOW_BYTE(x) ((x) & 0xff)
468 #define HIGH_BYTE(x) (((x) >> 8) & 0xff)
469 #define P(X, Y) ((X << 8) | Y)
478 #define I (intMaskBit != 0)
480 #define BUILDSR(SD) \
481 h8_set_ccr (SD, (I << 7) | (UI << 6) | (H << 5) | (U << 4) \
482 | (N << 3) | (Z << 2) | (V << 1) | C)
485 /* Get Status Register (flags). */ \
486 c = (h8_get_ccr (sd) >> 0) & 1; \
487 v = (h8_get_ccr (sd) >> 1) & 1; \
488 nz = !((h8_get_ccr (sd) >> 2) & 1); \
489 n = (h8_get_ccr (sd) >> 3) & 1; \
490 u = (h8_get_ccr (sd) >> 4) & 1; \
491 h = (h8_get_ccr (sd) >> 5) & 1; \
492 ui = ((h8_get_ccr (sd) >> 6) & 1); \
493 intMaskBit = (h8_get_ccr (sd) >> 7) & 1
496 #ifdef __CHAR_IS_SIGNED__
497 #define SEXTCHAR(x) ((char) (x))
501 #define SEXTCHAR(x) ((x & 0x80) ? (x | ~0xff) : x & 0xff)
504 #define UEXTCHAR(x) ((x) & 0xff)
505 #define UEXTSHORT(x) ((x) & 0xffff)
506 #define SEXTSHORT(x) ((short) (x))
510 int h8300_normal_mode
= 0;
513 static int memory_size
;
518 return time (0); /* WinXX HAS UNIX like 'time', so why not use it? */
540 return (h8300hmode
&& !h8300_normal_mode
)? SL
: SW
;
545 /* Simulate an indirection / dereference.
546 return 0 for success, -1 for failure.
550 lvalue (SIM_DESC sd
, int x
, int rn
, unsigned int *val
)
552 SIM_CPU
*cpu
= STATE_CPU (sd
, 0);
554 if (val
== NULL
) /* Paranoia. */
560 if (rn
== ZERO_REGNUM
)
561 *val
= X (OP_IMM
, SP
);
563 *val
= X (OP_REG
, SP
);
566 *val
= X (OP_MEM
, SP
);
569 sim_engine_halt (sd
, cpu
, NULL
, NULL_CIA
, sim_stopped
, SIM_SIGSEGV
);
578 if (h8300smode
&& !h8300_normal_mode
)
580 else if (h8300hmode
&& !h8300_normal_mode
)
587 decode (SIM_DESC sd
, int addr
, unsigned char *data
, decoded_inst
*dst
)
589 int cst
[3] = {0, 0, 0};
590 int reg
[3] = {0, 0, 0};
591 int rdisp
[3] = {0, 0, 0};
593 const struct h8_opcode
*q
;
598 /* Find the exact opcode/arg combo. */
599 for (q
= h8_opcodes
; q
->name
; q
++)
601 const op_type
*nib
= q
->data
.nib
;
602 unsigned int len
= 0;
604 if ((q
->available
== AV_H8SX
&& !h8300sxmode
) ||
605 (q
->available
== AV_H8S
&& !h8300smode
) ||
606 (q
->available
== AV_H8H
&& !h8300hmode
))
609 cst
[0] = cst
[1] = cst
[2] = 0;
610 reg
[0] = reg
[1] = reg
[2] = 0;
611 rdisp
[0] = rdisp
[1] = rdisp
[2] = 0;
615 op_type looking_for
= *nib
;
616 int thisnib
= data
[len
/ 2];
618 thisnib
= (len
& 1) ? (thisnib
& 0xf) : ((thisnib
>> 4) & 0xf);
619 opnum
= ((looking_for
& OP3
) ? 2 :
620 (looking_for
& DST
) ? 1 : 0);
622 if (looking_for
< 16 && looking_for
>= 0)
624 if (looking_for
!= thisnib
)
629 if (looking_for
& B31
)
631 if (!((thisnib
& 0x8) != 0))
634 looking_for
= (op_type
) (looking_for
& ~B31
);
637 else if (looking_for
& B30
)
639 if (!((thisnib
& 0x8) == 0))
642 looking_for
= (op_type
) (looking_for
& ~B30
);
645 if (looking_for
& B21
)
647 if (!((thisnib
& 0x4) != 0))
650 looking_for
= (op_type
) (looking_for
& ~B21
);
653 else if (looking_for
& B20
)
655 if (!((thisnib
& 0x4) == 0))
658 looking_for
= (op_type
) (looking_for
& ~B20
);
661 if (looking_for
& B11
)
663 if (!((thisnib
& 0x2) != 0))
666 looking_for
= (op_type
) (looking_for
& ~B11
);
669 else if (looking_for
& B10
)
671 if (!((thisnib
& 0x2) == 0))
674 looking_for
= (op_type
) (looking_for
& ~B10
);
677 if (looking_for
& B01
)
679 if (!((thisnib
& 0x1) != 0))
682 looking_for
= (op_type
) (looking_for
& ~B01
);
685 else if (looking_for
& B00
)
687 if (!((thisnib
& 0x1) == 0))
690 looking_for
= (op_type
) (looking_for
& ~B00
);
693 if (looking_for
& IGNORE
)
695 /* Hitachi has declared that IGNORE must be zero. */
699 else if ((looking_for
& MODE
) == DATA
)
701 ; /* Skip embedded data. */
703 else if ((looking_for
& MODE
) == DBIT
)
705 /* Exclude adds/subs by looking at bit 0 and 2, and
706 make sure the operand size, either w or l,
707 matches by looking at bit 1. */
708 if ((looking_for
& 7) != (thisnib
& 7))
711 cst
[opnum
] = (thisnib
& 0x8) ? 2 : 1;
713 else if ((looking_for
& MODE
) == REG
||
714 (looking_for
& MODE
) == LOWREG
||
715 (looking_for
& MODE
) == IND
||
716 (looking_for
& MODE
) == PREINC
||
717 (looking_for
& MODE
) == POSTINC
||
718 (looking_for
& MODE
) == PREDEC
||
719 (looking_for
& MODE
) == POSTDEC
)
721 reg
[opnum
] = thisnib
;
723 else if (looking_for
& CTRL
)
726 if (((looking_for
& MODE
) == CCR
&& (thisnib
!= C_CCR
)) ||
727 ((looking_for
& MODE
) == EXR
&& (thisnib
!= C_EXR
)) ||
728 ((looking_for
& MODE
) == MACH
&& (thisnib
!= C_MACH
)) ||
729 ((looking_for
& MODE
) == MACL
&& (thisnib
!= C_MACL
)) ||
730 ((looking_for
& MODE
) == VBR
&& (thisnib
!= C_VBR
)) ||
731 ((looking_for
& MODE
) == SBR
&& (thisnib
!= C_SBR
)))
733 if (((looking_for
& MODE
) == CCR_EXR
&&
734 (thisnib
!= C_CCR
&& thisnib
!= C_EXR
)) ||
735 ((looking_for
& MODE
) == VBR_SBR
&&
736 (thisnib
!= C_VBR
&& thisnib
!= C_SBR
)) ||
737 ((looking_for
& MODE
) == MACREG
&&
738 (thisnib
!= C_MACH
&& thisnib
!= C_MACL
)))
740 if (((looking_for
& MODE
) == CC_EX_VB_SB
&&
741 (thisnib
!= C_CCR
&& thisnib
!= C_EXR
&&
742 thisnib
!= C_VBR
&& thisnib
!= C_SBR
)))
745 reg
[opnum
] = thisnib
;
747 else if ((looking_for
& MODE
) == ABS
)
749 /* Absolute addresses are unsigned. */
750 switch (looking_for
& SIZE
)
753 cst
[opnum
] = UEXTCHAR (data
[len
/ 2]);
757 cst
[opnum
] = (data
[len
/ 2] << 8) + data
[len
/ 2 + 1];
761 (data
[len
/ 2 + 0] << 24) +
762 (data
[len
/ 2 + 1] << 16) +
763 (data
[len
/ 2 + 2] << 8) +
767 printf ("decode: bad size ABS: %d\n",
768 (looking_for
& SIZE
));
772 else if ((looking_for
& MODE
) == DISP
||
773 (looking_for
& MODE
) == PCREL
||
774 (looking_for
& MODE
) == INDEXB
||
775 (looking_for
& MODE
) == INDEXW
||
776 (looking_for
& MODE
) == INDEXL
)
778 switch (looking_for
& SIZE
)
781 cst
[opnum
] = thisnib
& 3;
784 cst
[opnum
] = SEXTCHAR (data
[len
/ 2]);
787 cst
[opnum
] = (data
[len
/ 2] << 8) + data
[len
/ 2 + 1];
788 cst
[opnum
] = (short) cst
[opnum
]; /* Sign extend. */
791 cst
[opnum
] = (data
[len
/ 2] << 8) + data
[len
/ 2 + 1];
795 (data
[len
/ 2 + 0] << 24) +
796 (data
[len
/ 2 + 1] << 16) +
797 (data
[len
/ 2 + 2] << 8) +
801 printf ("decode: bad size DISP/PCREL/INDEX: %d\n",
802 (looking_for
& SIZE
));
806 else if ((looking_for
& SIZE
) == L_16
||
807 (looking_for
& SIZE
) == L_16U
)
809 cst
[opnum
] = (data
[len
/ 2] << 8) + data
[len
/ 2 + 1];
810 /* Immediates are always unsigned. */
811 if ((looking_for
& SIZE
) != L_16U
&&
812 (looking_for
& MODE
) != IMM
)
813 cst
[opnum
] = (short) cst
[opnum
]; /* Sign extend. */
815 else if (looking_for
& ABSJMP
)
817 switch (looking_for
& SIZE
) {
819 cst
[opnum
] = (data
[1] << 16) | (data
[2] << 8) | (data
[3]);
823 (data
[len
/ 2 + 0] << 24) +
824 (data
[len
/ 2 + 1] << 16) +
825 (data
[len
/ 2 + 2] << 8) +
829 printf ("decode: bad size ABSJMP: %d\n",
830 (looking_for
& SIZE
));
834 else if ((looking_for
& MODE
) == MEMIND
)
836 cst
[opnum
] = data
[1];
838 else if ((looking_for
& MODE
) == VECIND
)
840 if(h8300_normal_mode
)
841 cst
[opnum
] = ((data
[1] & 0x7f) + 0x80) * 2;
843 cst
[opnum
] = ((data
[1] & 0x7f) + 0x80) * 4;
844 cst
[opnum
] += h8_get_vbr (sd
); /* Add vector base reg. */
846 else if ((looking_for
& SIZE
) == L_32
)
851 (data
[i
+ 0] << 24) |
852 (data
[i
+ 1] << 16) |
856 else if ((looking_for
& SIZE
) == L_24
)
861 (data
[i
+ 0] << 16) |
865 else if (looking_for
& DISPREG
)
867 rdisp
[opnum
] = thisnib
& 0x7;
869 else if ((looking_for
& MODE
) == KBIT
)
886 else if ((looking_for
& SIZE
) == L_8
)
888 if ((looking_for
& MODE
) == ABS
)
890 /* Will be combined with contents of SBR_REGNUM
891 by fetch (). For all modes except h8sx, this
892 will always contain the value 0xFFFFFF00. */
893 cst
[opnum
] = data
[len
/ 2] & 0xff;
897 cst
[opnum
] = data
[len
/ 2] & 0xff;
900 else if ((looking_for
& SIZE
) == L_2
)
902 cst
[opnum
] = thisnib
& 3;
904 else if ((looking_for
& SIZE
) == L_3
||
905 (looking_for
& SIZE
) == L_3NZ
)
907 cst
[opnum
] = thisnib
& 7;
908 if (cst
[opnum
] == 0 && (looking_for
& SIZE
) == L_3NZ
)
911 else if ((looking_for
& SIZE
) == L_4
)
913 cst
[opnum
] = thisnib
& 15;
915 else if ((looking_for
& SIZE
) == L_5
)
917 cst
[opnum
] = data
[len
/ 2] & 0x1f;
919 else if (looking_for
== E
)
924 /* Fill in the args. */
926 const op_type
*args
= q
->args
.nib
;
931 nargs
< 3 && *args
!= E
;
937 opnum
= ((x
& OP3
) ? 2 :
946 if ((x
& MODE
) == IMM
||
947 (x
& MODE
) == KBIT
||
950 /* Use the instruction to determine
952 p
->type
= X (OP_IMM
, OP_SIZE (q
->how
));
953 p
->literal
= cst
[opnum
];
955 else if ((x
& MODE
) == CONST_2
||
956 (x
& MODE
) == CONST_4
||
957 (x
& MODE
) == CONST_8
||
958 (x
& MODE
) == CONST_16
)
960 /* Use the instruction to determine
962 p
->type
= X (OP_IMM
, OP_SIZE (q
->how
));
964 case CONST_2
: p
->literal
= 2; break;
965 case CONST_4
: p
->literal
= 4; break;
966 case CONST_8
: p
->literal
= 8; break;
967 case CONST_16
: p
->literal
= 16; break;
970 else if ((x
& MODE
) == REG
)
972 p
->type
= X (OP_REG
, bitfrom (x
));
975 else if ((x
& MODE
) == LOWREG
)
977 p
->type
= X (OP_LOWREG
, bitfrom (x
));
980 else if ((x
& MODE
) == PREINC
)
982 /* Use the instruction to determine
984 p
->type
= X (OP_PREINC
, OP_SIZE (q
->how
));
985 p
->reg
= reg
[opnum
] & 0x7;
987 else if ((x
& MODE
) == POSTINC
)
989 /* Use the instruction to determine
991 p
->type
= X (OP_POSTINC
, OP_SIZE (q
->how
));
992 p
->reg
= reg
[opnum
] & 0x7;
994 else if ((x
& MODE
) == PREDEC
)
996 /* Use the instruction to determine
998 p
->type
= X (OP_PREDEC
, OP_SIZE (q
->how
));
999 p
->reg
= reg
[opnum
] & 0x7;
1001 else if ((x
& MODE
) == POSTDEC
)
1003 /* Use the instruction to determine
1004 the operand size. */
1005 p
->type
= X (OP_POSTDEC
, OP_SIZE (q
->how
));
1006 p
->reg
= reg
[opnum
] & 0x7;
1008 else if ((x
& MODE
) == IND
)
1010 /* Note: an indirect is transformed into
1011 a displacement of zero.
1013 /* Use the instruction to determine
1014 the operand size. */
1015 p
->type
= X (OP_DISP
, OP_SIZE (q
->how
));
1016 p
->reg
= reg
[opnum
] & 0x7;
1018 if (OP_KIND (q
->how
) == O_JSR
||
1019 OP_KIND (q
->how
) == O_JMP
)
1020 if (lvalue (sd
, p
->type
, p
->reg
, (unsigned int *)&p
->type
))
1023 else if ((x
& MODE
) == ABS
)
1025 /* Note: a 16 or 32 bit ABS is transformed into a
1026 displacement from pseudo-register ZERO_REGNUM,
1027 which is always zero. An 8 bit ABS becomes
1028 a displacement from SBR_REGNUM.
1030 /* Use the instruction to determine
1031 the operand size. */
1032 p
->type
= X (OP_DISP
, OP_SIZE (q
->how
));
1033 p
->literal
= cst
[opnum
];
1035 /* 8-bit ABS is displacement from SBR.
1036 16 and 32-bit ABS are displacement from ZERO.
1037 (SBR will always be zero except for h8/sx)
1039 if ((x
& SIZE
) == L_8
)
1040 p
->reg
= SBR_REGNUM
;
1042 p
->reg
= ZERO_REGNUM
;;
1044 else if ((x
& MODE
) == MEMIND
||
1045 (x
& MODE
) == VECIND
)
1047 /* Size doesn't matter. */
1048 p
->type
= X (OP_MEM
, SB
);
1049 p
->literal
= cst
[opnum
];
1050 if (OP_KIND (q
->how
) == O_JSR
||
1051 OP_KIND (q
->how
) == O_JMP
)
1052 if (lvalue (sd
, p
->type
, p
->reg
, (unsigned int *)&p
->type
))
1055 else if ((x
& MODE
) == PCREL
)
1057 /* Size doesn't matter. */
1058 p
->type
= X (OP_PCREL
, SB
);
1059 p
->literal
= cst
[opnum
];
1061 else if (x
& ABSJMP
)
1063 p
->type
= X (OP_IMM
, SP
);
1064 p
->literal
= cst
[opnum
];
1066 else if ((x
& MODE
) == INDEXB
)
1068 p
->type
= X (OP_INDEXB
, OP_SIZE (q
->how
));
1069 p
->literal
= cst
[opnum
];
1070 p
->reg
= rdisp
[opnum
];
1072 else if ((x
& MODE
) == INDEXW
)
1074 p
->type
= X (OP_INDEXW
, OP_SIZE (q
->how
));
1075 p
->literal
= cst
[opnum
];
1076 p
->reg
= rdisp
[opnum
];
1078 else if ((x
& MODE
) == INDEXL
)
1080 p
->type
= X (OP_INDEXL
, OP_SIZE (q
->how
));
1081 p
->literal
= cst
[opnum
];
1082 p
->reg
= rdisp
[opnum
];
1084 else if ((x
& MODE
) == DISP
)
1086 /* Yuck -- special for mova args. */
1087 if (strncmp (q
->name
, "mova", 4) == 0 &&
1090 /* Mova can have a DISP2 dest, with an
1091 INDEXB or INDEXW src. The multiplier
1092 for the displacement value is determined
1093 by the src operand, not by the insn. */
1095 switch (OP_KIND (dst
->src
.type
))
1098 p
->type
= X (OP_DISP
, SB
);
1099 p
->literal
= cst
[opnum
];
1102 p
->type
= X (OP_DISP
, SW
);
1103 p
->literal
= cst
[opnum
] * 2;
1111 p
->type
= X (OP_DISP
, OP_SIZE (q
->how
));
1112 p
->literal
= cst
[opnum
];
1113 /* DISP2 is special. */
1114 if ((x
& SIZE
) == L_2
)
1115 switch (OP_SIZE (q
->how
))
1118 case SW
: p
->literal
*= 2; break;
1119 case SL
: p
->literal
*= 4; break;
1122 p
->reg
= rdisp
[opnum
];
1129 p
->type
= X (OP_CCR
, SB
);
1132 p
->type
= X (OP_EXR
, SB
);
1135 p
->type
= X (OP_MACH
, SL
);
1138 p
->type
= X (OP_MACL
, SL
);
1141 p
->type
= X (OP_VBR
, SL
);
1144 p
->type
= X (OP_SBR
, SL
);
1148 else if ((x
& MODE
) == CCR
)
1152 else if ((x
& MODE
) == EXR
)
1157 printf ("Hmmmm 0x%x...\n", x
);
1163 /* Unary operators: treat src and dst as equivalent. */
1164 if (dst
->dst
.type
== -1)
1165 dst
->dst
= dst
->src
;
1166 if (dst
->src
.type
== -1)
1167 dst
->src
= dst
->dst
;
1169 dst
->opcode
= q
->how
;
1170 dst
->cycles
= q
->time
;
1172 /* And jsr's to these locations are turned into
1175 if (OP_KIND (dst
->opcode
) == O_JSR
)
1177 switch (dst
->src
.literal
)
1180 dst
->opcode
= O (O_SYS_OPEN
, SB
);
1183 dst
->opcode
= O (O_SYS_READ
, SB
);
1186 dst
->opcode
= O (O_SYS_WRITE
, SB
);
1189 dst
->opcode
= O (O_SYS_LSEEK
, SB
);
1192 dst
->opcode
= O (O_SYS_CLOSE
, SB
);
1195 dst
->opcode
= O (O_SYS_STAT
, SB
);
1198 dst
->opcode
= O (O_SYS_FSTAT
, SB
);
1201 dst
->opcode
= O (O_SYS_CMDLINE
, SB
);
1204 /* End of Processing for system calls. */
1207 dst
->next_pc
= addr
+ len
/ 2;
1211 printf ("Don't understand 0x%x \n", looking_for
);
1222 /* Fell off the end. */
1223 dst
->opcode
= O (O_ILL
, SB
);
1227 compile (SIM_DESC sd
, int pc
)
1231 /* Find the next cache entry to use. */
1232 idx
= h8_get_cache_top (sd
) + 1;
1233 h8_increment_compiles (sd
);
1234 if (idx
>= sd
->sim_cache_size
)
1238 h8_set_cache_top (sd
, idx
);
1240 /* Throw away its old meaning. */
1241 h8_set_cache_idx (sd
, sd
->sim_cache
[idx
].oldpc
, 0);
1243 /* Set to new address. */
1244 sd
->sim_cache
[idx
].oldpc
= pc
;
1246 /* Fill in instruction info. */
1247 decode (sd
, pc
, h8_get_memory_buf (sd
) + pc
, sd
->sim_cache
+ idx
);
1249 /* Point to new cache entry. */
1250 h8_set_cache_idx (sd
, pc
, idx
);
1254 static unsigned char *breg
[32];
1255 static unsigned short *wreg
[16];
1257 #define GET_B_REG(X) *(breg[X])
1258 #define SET_B_REG(X, Y) (*(breg[X])) = (Y)
1259 #define GET_W_REG(X) *(wreg[X])
1260 #define SET_W_REG(X, Y) (*(wreg[X])) = (Y)
1261 #define GET_L_REG(X) h8_get_reg (sd, X)
1262 #define SET_L_REG(X, Y) h8_set_reg (sd, X, Y)
1264 #define GET_MEMORY_L(X) \
1265 ((X) < memory_size \
1266 ? ((h8_get_memory (sd, (X)+0) << 24) | (h8_get_memory (sd, (X)+1) << 16) \
1267 | (h8_get_memory (sd, (X)+2) << 8) | (h8_get_memory (sd, (X)+3) << 0)) \
1268 : ((h8_get_eightbit (sd, ((X)+0) & 0xff) << 24) \
1269 | (h8_get_eightbit (sd, ((X)+1) & 0xff) << 16) \
1270 | (h8_get_eightbit (sd, ((X)+2) & 0xff) << 8) \
1271 | (h8_get_eightbit (sd, ((X)+3) & 0xff) << 0)))
1273 #define GET_MEMORY_W(X) \
1274 ((X) < memory_size \
1275 ? ((h8_get_memory (sd, (X)+0) << 8) \
1276 | (h8_get_memory (sd, (X)+1) << 0)) \
1277 : ((h8_get_eightbit (sd, ((X)+0) & 0xff) << 8) \
1278 | (h8_get_eightbit (sd, ((X)+1) & 0xff) << 0)))
1281 #define GET_MEMORY_B(X) \
1282 ((X) < memory_size ? (h8_get_memory (sd, (X))) \
1283 : (h8_get_eightbit (sd, (X) & 0xff)))
1285 #define SET_MEMORY_L(X, Y) \
1286 { register unsigned char *_p; register int __y = (Y); \
1287 _p = ((X) < memory_size ? h8_get_memory_buf (sd) + (X) : \
1288 h8_get_eightbit_buf (sd) + ((X) & 0xff)); \
1289 _p[0] = __y >> 24; _p[1] = __y >> 16; \
1290 _p[2] = __y >> 8; _p[3] = __y >> 0; \
1293 #define SET_MEMORY_W(X, Y) \
1294 { register unsigned char *_p; register int __y = (Y); \
1295 _p = ((X) < memory_size ? h8_get_memory_buf (sd) + (X) : \
1296 h8_get_eightbit_buf (sd) + ((X) & 0xff)); \
1297 _p[0] = __y >> 8; _p[1] = __y; \
1300 #define SET_MEMORY_B(X, Y) \
1301 ((X) < memory_size ? (h8_set_memory (sd, (X), (Y))) \
1302 : (h8_set_eightbit (sd, (X) & 0xff, (Y))))
1304 /* Simulate a memory fetch.
1305 Return 0 for success, -1 for failure.
1309 fetch_1 (SIM_DESC sd
, ea_type
*arg
, int *val
, int twice
)
1311 SIM_CPU
*cpu
= STATE_CPU (sd
, 0);
1313 int abs
= arg
->literal
;
1318 return -1; /* Paranoia. */
1322 /* Indexed register plus displacement mode:
1324 This new family of addressing modes are similar to OP_DISP
1325 (register plus displacement), with two differences:
1326 1) INDEXB uses only the least significant byte of the register,
1327 INDEXW uses only the least significant word, and
1328 INDEXL uses the entire register (just like OP_DISP).
1330 2) The displacement value in abs is multiplied by two
1331 for SW-sized operations, and by four for SL-size.
1333 This gives nine possible variations.
1336 case X (OP_INDEXB
, SB
):
1337 case X (OP_INDEXB
, SW
):
1338 case X (OP_INDEXB
, SL
):
1339 case X (OP_INDEXW
, SB
):
1340 case X (OP_INDEXW
, SW
):
1341 case X (OP_INDEXW
, SL
):
1342 case X (OP_INDEXL
, SB
):
1343 case X (OP_INDEXL
, SW
):
1344 case X (OP_INDEXL
, SL
):
1346 switch (OP_KIND (arg
->type
)) {
1347 case OP_INDEXB
: t
&= 0xff; break;
1348 case OP_INDEXW
: t
&= 0xffff; break;
1352 switch (OP_SIZE (arg
->type
)) {
1354 *val
= GET_MEMORY_B ((t
* 1 + abs
) & h8_get_mask (sd
));
1357 *val
= GET_MEMORY_W ((t
* 2 + abs
) & h8_get_mask (sd
));
1360 *val
= GET_MEMORY_L ((t
* 4 + abs
) & h8_get_mask (sd
));
1365 case X (OP_LOWREG
, SB
):
1366 *val
= GET_L_REG (rn
) & 0xff;
1368 case X (OP_LOWREG
, SW
):
1369 *val
= GET_L_REG (rn
) & 0xffff;
1372 case X (OP_REG
, SB
): /* Register direct, byte. */
1373 *val
= GET_B_REG (rn
);
1375 case X (OP_REG
, SW
): /* Register direct, word. */
1376 *val
= GET_W_REG (rn
);
1378 case X (OP_REG
, SL
): /* Register direct, long. */
1379 *val
= GET_L_REG (rn
);
1381 case X (OP_IMM
, SB
): /* Immediate, byte. */
1382 case X (OP_IMM
, SW
): /* Immediate, word. */
1383 case X (OP_IMM
, SL
): /* Immediate, long. */
1386 case X (OP_POSTINC
, SB
): /* Register indirect w/post-incr: byte. */
1388 r
= GET_MEMORY_B (t
& h8_get_mask (sd
));
1394 case X (OP_POSTINC
, SW
): /* Register indirect w/post-incr: word. */
1396 r
= GET_MEMORY_W (t
& h8_get_mask (sd
));
1402 case X (OP_POSTINC
, SL
): /* Register indirect w/post-incr: long. */
1404 r
= GET_MEMORY_L (t
& h8_get_mask (sd
));
1411 case X (OP_POSTDEC
, SB
): /* Register indirect w/post-decr: byte. */
1413 r
= GET_MEMORY_B (t
& h8_get_mask (sd
));
1419 case X (OP_POSTDEC
, SW
): /* Register indirect w/post-decr: word. */
1421 r
= GET_MEMORY_W (t
& h8_get_mask (sd
));
1427 case X (OP_POSTDEC
, SL
): /* Register indirect w/post-decr: long. */
1429 r
= GET_MEMORY_L (t
& h8_get_mask (sd
));
1436 case X (OP_PREDEC
, SB
): /* Register indirect w/pre-decr: byte. */
1437 t
= GET_L_REG (rn
) - 1;
1439 t
&= h8_get_mask (sd
);
1440 *val
= GET_MEMORY_B (t
);
1443 case X (OP_PREDEC
, SW
): /* Register indirect w/pre-decr: word. */
1444 t
= GET_L_REG (rn
) - 2;
1446 t
&= h8_get_mask (sd
);
1447 *val
= GET_MEMORY_W (t
);
1450 case X (OP_PREDEC
, SL
): /* Register indirect w/pre-decr: long. */
1451 t
= GET_L_REG (rn
) - 4;
1453 t
&= h8_get_mask (sd
);
1454 *val
= GET_MEMORY_L (t
);
1457 case X (OP_PREINC
, SB
): /* Register indirect w/pre-incr: byte. */
1458 t
= GET_L_REG (rn
) + 1;
1460 t
&= h8_get_mask (sd
);
1461 *val
= GET_MEMORY_B (t
);
1464 case X (OP_PREINC
, SW
): /* Register indirect w/pre-incr: long. */
1465 t
= GET_L_REG (rn
) + 2;
1467 t
&= h8_get_mask (sd
);
1468 *val
= GET_MEMORY_W (t
);
1471 case X (OP_PREINC
, SL
): /* Register indirect w/pre-incr: long. */
1472 t
= GET_L_REG (rn
) + 4;
1474 t
&= h8_get_mask (sd
);
1475 *val
= GET_MEMORY_L (t
);
1478 case X (OP_DISP
, SB
): /* Register indirect w/displacement: byte. */
1479 t
= GET_L_REG (rn
) + abs
;
1480 t
&= h8_get_mask (sd
);
1481 *val
= GET_MEMORY_B (t
);
1484 case X (OP_DISP
, SW
): /* Register indirect w/displacement: word. */
1485 t
= GET_L_REG (rn
) + abs
;
1486 t
&= h8_get_mask (sd
);
1487 *val
= GET_MEMORY_W (t
);
1490 case X (OP_DISP
, SL
): /* Register indirect w/displacement: long. */
1491 t
= GET_L_REG (rn
) + abs
;
1492 t
&= h8_get_mask (sd
);
1493 *val
=GET_MEMORY_L (t
);
1496 case X (OP_MEM
, SL
): /* Absolute memory address, long. */
1497 t
= GET_MEMORY_L (abs
);
1498 t
&= h8_get_mask (sd
);
1502 case X (OP_MEM
, SW
): /* Absolute memory address, word. */
1503 t
= GET_MEMORY_W (abs
);
1504 t
&= h8_get_mask (sd
);
1508 case X (OP_PCREL
, SB
): /* PC relative (for jump, branch etc). */
1509 case X (OP_PCREL
, SW
):
1510 case X (OP_PCREL
, SL
):
1511 case X (OP_PCREL
, SN
):
1515 case X (OP_MEM
, SB
): /* Why isn't this implemented? */
1517 sim_engine_halt (sd
, cpu
, NULL
, NULL_CIA
, sim_stopped
, SIM_SIGSEGV
);
1520 return 0; /* Success. */
1526 fetch (SIM_DESC sd
, ea_type
*arg
, int *val
)
1528 return fetch_1 (sd
, arg
, val
, 0);
1531 /* Fetch which will be followed by a store to the same location.
1532 The difference being that we don't want to do a post-increment
1533 or post-decrement at this time: we'll do it when we store. */
1536 fetch2 (SIM_DESC sd
, ea_type
*arg
, int *val
)
1538 return fetch_1 (sd
, arg
, val
, 1);
1541 /* Simulate a memory store.
1542 Return 0 for success, -1 for failure.
1546 store_1 (SIM_DESC sd
, ea_type
*arg
, int n
, int twice
)
1548 SIM_CPU
*cpu
= STATE_CPU (sd
, 0);
1550 int abs
= arg
->literal
;
1555 /* Indexed register plus displacement mode:
1557 This new family of addressing modes are similar to OP_DISP
1558 (register plus displacement), with two differences:
1559 1) INDEXB uses only the least significant byte of the register,
1560 INDEXW uses only the least significant word, and
1561 INDEXL uses the entire register (just like OP_DISP).
1563 2) The displacement value in abs is multiplied by two
1564 for SW-sized operations, and by four for SL-size.
1566 This gives nine possible variations.
1569 case X (OP_INDEXB
, SB
):
1570 case X (OP_INDEXB
, SW
):
1571 case X (OP_INDEXB
, SL
):
1572 case X (OP_INDEXW
, SB
):
1573 case X (OP_INDEXW
, SW
):
1574 case X (OP_INDEXW
, SL
):
1575 case X (OP_INDEXL
, SB
):
1576 case X (OP_INDEXL
, SW
):
1577 case X (OP_INDEXL
, SL
):
1579 switch (OP_KIND (arg
->type
)) {
1580 case OP_INDEXB
: t
&= 0xff; break;
1581 case OP_INDEXW
: t
&= 0xffff; break;
1585 switch (OP_SIZE (arg
->type
)) {
1587 SET_MEMORY_B ((t
* 1 + abs
) & h8_get_mask (sd
), n
);
1590 SET_MEMORY_W ((t
* 2 + abs
) & h8_get_mask (sd
), n
);
1593 SET_MEMORY_L ((t
* 4 + abs
) & h8_get_mask (sd
), n
);
1598 case X (OP_REG
, SB
): /* Register direct, byte. */
1601 case X (OP_REG
, SW
): /* Register direct, word. */
1604 case X (OP_REG
, SL
): /* Register direct, long. */
1608 case X (OP_PREDEC
, SB
): /* Register indirect w/pre-decr, byte. */
1613 t
&= h8_get_mask (sd
);
1614 SET_MEMORY_B (t
, n
);
1617 case X (OP_PREDEC
, SW
): /* Register indirect w/pre-decr, word. */
1622 t
&= h8_get_mask (sd
);
1623 SET_MEMORY_W (t
, n
);
1626 case X (OP_PREDEC
, SL
): /* Register indirect w/pre-decr, long. */
1631 t
&= h8_get_mask (sd
);
1632 SET_MEMORY_L (t
, n
);
1635 case X (OP_PREINC
, SB
): /* Register indirect w/pre-incr, byte. */
1640 t
&= h8_get_mask (sd
);
1641 SET_MEMORY_B (t
, n
);
1644 case X (OP_PREINC
, SW
): /* Register indirect w/pre-incr, word. */
1649 t
&= h8_get_mask (sd
);
1650 SET_MEMORY_W (t
, n
);
1653 case X (OP_PREINC
, SL
): /* Register indirect w/pre-incr, long. */
1658 t
&= h8_get_mask (sd
);
1659 SET_MEMORY_L (t
, n
);
1662 case X (OP_POSTDEC
, SB
): /* Register indirect w/post-decr, byte. */
1664 SET_L_REG (rn
, t
- 1);
1665 t
&= h8_get_mask (sd
);
1666 SET_MEMORY_B (t
, n
);
1669 case X (OP_POSTDEC
, SW
): /* Register indirect w/post-decr, word. */
1671 SET_L_REG (rn
, t
- 2);
1672 t
&= h8_get_mask (sd
);
1673 SET_MEMORY_W (t
, n
);
1676 case X (OP_POSTDEC
, SL
): /* Register indirect w/post-decr, long. */
1678 SET_L_REG (rn
, t
- 4);
1679 t
&= h8_get_mask (sd
);
1680 SET_MEMORY_L (t
, n
);
1683 case X (OP_POSTINC
, SB
): /* Register indirect w/post-incr, byte. */
1685 SET_L_REG (rn
, t
+ 1);
1686 t
&= h8_get_mask (sd
);
1687 SET_MEMORY_B (t
, n
);
1690 case X (OP_POSTINC
, SW
): /* Register indirect w/post-incr, word. */
1692 SET_L_REG (rn
, t
+ 2);
1693 t
&= h8_get_mask (sd
);
1694 SET_MEMORY_W (t
, n
);
1697 case X (OP_POSTINC
, SL
): /* Register indirect w/post-incr, long. */
1699 SET_L_REG (rn
, t
+ 4);
1700 t
&= h8_get_mask (sd
);
1701 SET_MEMORY_L (t
, n
);
1704 case X (OP_DISP
, SB
): /* Register indirect w/displacement, byte. */
1705 t
= GET_L_REG (rn
) + abs
;
1706 t
&= h8_get_mask (sd
);
1707 SET_MEMORY_B (t
, n
);
1710 case X (OP_DISP
, SW
): /* Register indirect w/displacement, word. */
1711 t
= GET_L_REG (rn
) + abs
;
1712 t
&= h8_get_mask (sd
);
1713 SET_MEMORY_W (t
, n
);
1716 case X (OP_DISP
, SL
): /* Register indirect w/displacement, long. */
1717 t
= GET_L_REG (rn
) + abs
;
1718 t
&= h8_get_mask (sd
);
1719 SET_MEMORY_L (t
, n
);
1723 case X (OP_MEM
, SB
): /* Why isn't this implemented? */
1724 case X (OP_MEM
, SW
): /* Why isn't this implemented? */
1725 case X (OP_MEM
, SL
): /* Why isn't this implemented? */
1727 sim_engine_halt (sd
, cpu
, NULL
, NULL_CIA
, sim_stopped
, SIM_SIGSEGV
);
1736 store (SIM_DESC sd
, ea_type
*arg
, int n
)
1738 return store_1 (sd
, arg
, n
, 0);
1741 /* Store which follows a fetch from the same location.
1742 The difference being that we don't want to do a pre-increment
1743 or pre-decrement at this time: it was already done when we fetched. */
1746 store2 (SIM_DESC sd
, ea_type
*arg
, int n
)
1748 return store_1 (sd
, arg
, n
, 1);
1751 /* Flag to be set whenever a new SIM_DESC object is created. */
1752 static int init_pointers_needed
= 1;
1755 init_pointers (SIM_DESC sd
)
1757 if (init_pointers_needed
)
1761 if (h8300smode
&& !h8300_normal_mode
)
1762 memory_size
= H8300S_MSIZE
;
1763 else if (h8300hmode
&& !h8300_normal_mode
)
1764 memory_size
= H8300H_MSIZE
;
1766 memory_size
= H8300_MSIZE
;
1767 /* `msize' must be a power of two. */
1768 if ((memory_size
& (memory_size
- 1)) != 0)
1772 "init_pointers: bad memory size %d, defaulting to %d.\n",
1773 memory_size
, memory_size
= H8300S_MSIZE
);
1776 if (h8_get_memory_buf (sd
))
1777 free (h8_get_memory_buf (sd
));
1778 if (h8_get_cache_idx_buf (sd
))
1779 free (h8_get_cache_idx_buf (sd
));
1780 if (h8_get_eightbit_buf (sd
))
1781 free (h8_get_eightbit_buf (sd
));
1783 h8_set_memory_buf (sd
, (unsigned char *)
1784 calloc (sizeof (char), memory_size
));
1785 h8_set_cache_idx_buf (sd
, (unsigned short *)
1786 calloc (sizeof (short), memory_size
));
1787 sd
->memory_size
= memory_size
;
1788 h8_set_eightbit_buf (sd
, (unsigned char *) calloc (sizeof (char), 256));
1790 h8_set_mask (sd
, memory_size
- 1);
1792 memset (h8_get_reg_buf (sd
), 0, sizeof (((STATE_CPU (sd
, 0))->regs
)));
1794 for (i
= 0; i
< 8; i
++)
1796 /* FIXME: rewrite using local buffer. */
1797 unsigned char *p
= (unsigned char *) (h8_get_reg_buf (sd
) + i
);
1798 unsigned char *e
= (unsigned char *) (h8_get_reg_buf (sd
) + i
+ 1);
1799 unsigned short *q
= (unsigned short *) (h8_get_reg_buf (sd
) + i
);
1800 unsigned short *u
= (unsigned short *) (h8_get_reg_buf (sd
) + i
+ 1);
1801 h8_set_reg (sd
, i
, 0x00112233);
1816 wreg
[i
] = wreg
[i
+ 8] = 0;
1830 if (wreg
[i
] == 0 || wreg
[i
+ 8] == 0)
1831 sim_io_printf (sd
, "init_pointers: internal error.\n");
1833 h8_set_reg (sd
, i
, 0);
1836 init_pointers_needed
= 0;
1838 /* Initialize the seg registers. */
1840 set_simcache_size (sd
, CSIZE
);
1844 #define OBITOP(name, f, s, op) \
1845 case O (name, SB): \
1850 if (fetch (sd, &code->dst, &ea)) \
1852 if (fetch (sd, &code->src, &tmp)) \
1854 m = 1 << (tmp & 7); \
1857 if (store (sd, &code->dst,ea)) \
1863 step_once (SIM_DESC sd
, SIM_CPU
*cpu
)
1867 int tick_start
= get_now ();
1874 int c
, nz
, v
, n
, u
, h
, ui
, intMaskBit
;
1877 host_callback
*sim_callback
= STATE_CALLBACK (sd
);
1881 pc
= h8_get_pc (sd
);
1883 /* The PC should never be odd. */
1886 sim_engine_halt (sd
, cpu
, NULL
, NULL_CIA
, sim_stopped
, SIM_SIGBUS
);
1890 /* Get Status Register (flags). */
1893 if (h8300smode
) /* Get exr. */
1895 trace
= (h8_get_exr (sd
) >> 7) & 1;
1896 intMask
= h8_get_exr (sd
) & 7;
1899 oldmask
= h8_get_mask (sd
);
1900 if (!h8300hmode
|| h8300_normal_mode
)
1901 h8_set_mask (sd
, 0xffff);
1904 unsigned short cidx
;
1908 cidx
= h8_get_cache_idx (sd
, pc
);
1909 if (cidx
== (unsigned short) -1 ||
1910 cidx
>= sd
->sim_cache_size
)
1913 code
= sd
->sim_cache
+ cidx
;
1918 printf ("%x %d %s\n", pc
, code
->opcode
,
1919 code
->op
? code
->op
->name
: "**");
1921 h8_increment_stats (sd
, code
->opcode
);
1926 cycles
+= code
->cycles
;
1930 switch (code
->opcode
)
1934 * This opcode is a fake for when we get to an
1935 * instruction which hasnt been compiled
1941 case O (O_MOVAB
, SL
):
1942 case O (O_MOVAW
, SL
):
1943 case O (O_MOVAL
, SL
):
1944 /* 1) Evaluate 2nd argument (dst).
1945 2) Mask / zero extend according to whether 1st argument (src)
1946 is INDEXB, INDEXW, or INDEXL.
1947 3) Left-shift the result by 0, 1 or 2, according to size of mova
1948 (mova/b, mova/w, mova/l).
1949 4) Add literal value of 1st argument (src).
1950 5) Store result in 3rd argument (op3).
1953 /* Alas, since this is the only instruction with 3 arguments,
1954 decode doesn't handle them very well. Some fix-up is required.
1956 a) The size of dst is determined by whether src is
1957 INDEXB or INDEXW. */
1959 if (OP_KIND (code
->src
.type
) == OP_INDEXB
)
1960 code
->dst
.type
= X (OP_KIND (code
->dst
.type
), SB
);
1961 else if (OP_KIND (code
->src
.type
) == OP_INDEXW
)
1962 code
->dst
.type
= X (OP_KIND (code
->dst
.type
), SW
);
1964 /* b) If op3 == null, then this is the short form of the insn.
1965 Dst is the dispreg of src, and op3 is the 32-bit form
1966 of the same register.
1969 if (code
->op3
.type
== 0)
1971 /* Short form: src == INDEXB/INDEXW, dst == op3 == 0.
1972 We get to compose dst and op3 as follows:
1974 op3 is a 32-bit register, ID == src.reg.
1975 dst is the same register, but 8 or 16 bits
1976 depending on whether src is INDEXB or INDEXW.
1979 code
->op3
.type
= X (OP_REG
, SL
);
1980 code
->op3
.reg
= code
->src
.reg
;
1981 code
->op3
.literal
= 0;
1983 if (OP_KIND (code
->src
.type
) == OP_INDEXB
)
1985 code
->dst
.type
= X (OP_REG
, SB
);
1986 code
->dst
.reg
= code
->op3
.reg
+ 8;
1989 code
->dst
.type
= X (OP_REG
, SW
);
1992 if (fetch (sd
, &code
->dst
, &ea
))
1995 switch (OP_KIND (code
->src
.type
)) {
1996 case OP_INDEXB
: ea
= ea
& 0xff; break;
1997 case OP_INDEXW
: ea
= ea
& 0xffff; break;
1998 case OP_INDEXL
: break;
1999 default: goto illegal
;
2002 switch (code
->opcode
) {
2003 case O (O_MOVAB
, SL
): break;
2004 case O (O_MOVAW
, SL
): ea
= ea
<< 1; break;
2005 case O (O_MOVAL
, SL
): ea
= ea
<< 2; break;
2006 default: goto illegal
;
2009 ea
= ea
+ code
->src
.literal
;
2011 if (store (sd
, &code
->op3
, ea
))
2016 case O (O_SUBX
, SB
): /* subx, extended sub */
2017 if (fetch2 (sd
, &code
->dst
, &rd
))
2019 if (fetch (sd
, &code
->src
, &ea
))
2025 case O (O_SUBX
, SW
): /* subx, extended sub */
2026 if (fetch2 (sd
, &code
->dst
, &rd
))
2028 if (fetch (sd
, &code
->src
, &ea
))
2034 case O (O_SUBX
, SL
): /* subx, extended sub */
2035 if (fetch2 (sd
, &code
->dst
, &rd
))
2037 if (fetch (sd
, &code
->src
, &ea
))
2043 case O (O_ADDX
, SB
): /* addx, extended add */
2044 if (fetch2 (sd
, &code
->dst
, &rd
))
2046 if (fetch (sd
, &code
->src
, &ea
))
2052 case O (O_ADDX
, SW
): /* addx, extended add */
2053 if (fetch2 (sd
, &code
->dst
, &rd
))
2055 if (fetch (sd
, &code
->src
, &ea
))
2061 case O (O_ADDX
, SL
): /* addx, extended add */
2062 if (fetch2 (sd
, &code
->dst
, &rd
))
2064 if (fetch (sd
, &code
->src
, &ea
))
2070 case O (O_SUB
, SB
): /* sub.b */
2071 /* Fetch rd and ea. */
2072 if (fetch (sd
, &code
->src
, &ea
) || fetch2 (sd
, &code
->dst
, &rd
))
2078 case O (O_SUB
, SW
): /* sub.w */
2079 /* Fetch rd and ea. */
2080 if (fetch (sd
, &code
->src
, &ea
) || fetch2 (sd
, &code
->dst
, &rd
))
2086 case O (O_SUB
, SL
): /* sub.l */
2087 /* Fetch rd and ea. */
2088 if (fetch (sd
, &code
->src
, &ea
) || fetch2 (sd
, &code
->dst
, &rd
))
2094 case O (O_NEG
, SB
): /* neg.b */
2096 if (fetch2 (sd
, &code
->src
, &ea
))
2103 case O (O_NEG
, SW
): /* neg.w */
2105 if (fetch2 (sd
, &code
->src
, &ea
))
2112 case O (O_NEG
, SL
): /* neg.l */
2114 if (fetch2 (sd
, &code
->src
, &ea
))
2121 case O (O_ADD
, SB
): /* add.b */
2122 if (fetch2 (sd
, &code
->dst
, &rd
))
2124 if (fetch (sd
, &code
->src
, &ea
))
2129 case O (O_ADD
, SW
): /* add.w */
2130 if (fetch2 (sd
, &code
->dst
, &rd
))
2132 if (fetch (sd
, &code
->src
, &ea
))
2137 case O (O_ADD
, SL
): /* add.l */
2138 if (fetch2 (sd
, &code
->dst
, &rd
))
2140 if (fetch (sd
, &code
->src
, &ea
))
2145 case O (O_AND
, SB
): /* and.b */
2146 /* Fetch rd and ea. */
2147 if (fetch (sd
, &code
->src
, &ea
) || fetch2 (sd
, &code
->dst
, &rd
))
2152 case O (O_AND
, SW
): /* and.w */
2153 /* Fetch rd and ea. */
2154 if (fetch (sd
, &code
->src
, &ea
) || fetch2 (sd
, &code
->dst
, &rd
))
2159 case O (O_AND
, SL
): /* and.l */
2160 /* Fetch rd and ea. */
2161 if (fetch (sd
, &code
->src
, &ea
) || fetch2 (sd
, &code
->dst
, &rd
))
2166 case O (O_OR
, SB
): /* or.b */
2167 /* Fetch rd and ea. */
2168 if (fetch (sd
, &code
->src
, &ea
) || fetch2 (sd
, &code
->dst
, &rd
))
2173 case O (O_OR
, SW
): /* or.w */
2174 /* Fetch rd and ea. */
2175 if (fetch (sd
, &code
->src
, &ea
) || fetch2 (sd
, &code
->dst
, &rd
))
2180 case O (O_OR
, SL
): /* or.l */
2181 /* Fetch rd and ea. */
2182 if (fetch (sd
, &code
->src
, &ea
) || fetch2 (sd
, &code
->dst
, &rd
))
2187 case O (O_XOR
, SB
): /* xor.b */
2188 /* Fetch rd and ea. */
2189 if (fetch (sd
, &code
->src
, &ea
) || fetch2 (sd
, &code
->dst
, &rd
))
2194 case O (O_XOR
, SW
): /* xor.w */
2195 /* Fetch rd and ea. */
2196 if (fetch (sd
, &code
->src
, &ea
) || fetch2 (sd
, &code
->dst
, &rd
))
2201 case O (O_XOR
, SL
): /* xor.l */
2202 /* Fetch rd and ea. */
2203 if (fetch (sd
, &code
->src
, &ea
) || fetch2 (sd
, &code
->dst
, &rd
))
2209 if (fetch (sd
, &code
->src
, &res
))
2211 if (store (sd
, &code
->dst
, res
))
2213 goto just_flags_log8
;
2215 if (fetch (sd
, &code
->src
, &res
))
2217 if (store (sd
, &code
->dst
, res
))
2219 goto just_flags_log16
;
2221 if (fetch (sd
, &code
->src
, &res
))
2223 if (store (sd
, &code
->dst
, res
))
2225 goto just_flags_log32
;
2227 case O (O_MOVMD
, SB
): /* movmd.b */
2234 rd
= GET_MEMORY_B (GET_L_REG (5));
2235 SET_MEMORY_B (GET_L_REG (6), rd
);
2236 SET_L_REG (5, GET_L_REG (5) + 1);
2237 SET_L_REG (6, GET_L_REG (6) + 1);
2242 case O (O_MOVMD
, SW
): /* movmd.w */
2249 rd
= GET_MEMORY_W (GET_L_REG (5));
2250 SET_MEMORY_W (GET_L_REG (6), rd
);
2251 SET_L_REG (5, GET_L_REG (5) + 2);
2252 SET_L_REG (6, GET_L_REG (6) + 2);
2257 case O (O_MOVMD
, SL
): /* movmd.l */
2264 rd
= GET_MEMORY_L (GET_L_REG (5));
2265 SET_MEMORY_L (GET_L_REG (6), rd
);
2266 SET_L_REG (5, GET_L_REG (5) + 4);
2267 SET_L_REG (6, GET_L_REG (6) + 4);
2272 case O (O_MOVSD
, SB
): /* movsd.b */
2273 /* This instruction implements strncpy, with a conditional branch.
2274 r4 contains n, r5 contains src, and r6 contains dst.
2275 The 16-bit displacement operand is added to the pc
2276 if and only if the end of string is reached before
2277 n bytes are transferred. */
2279 ea
= GET_L_REG (4) & 0xffff;
2285 rd
= GET_MEMORY_B (GET_L_REG (5));
2286 SET_MEMORY_B (GET_L_REG (6), rd
);
2287 SET_L_REG (5, GET_L_REG (5) + 1);
2288 SET_L_REG (6, GET_L_REG (6) + 1);
2295 case O (O_EEPMOV
, SB
): /* eepmov.b */
2296 case O (O_EEPMOV
, SW
): /* eepmov.w */
2297 if (h8300hmode
|| h8300smode
)
2299 register unsigned char *_src
, *_dst
;
2300 unsigned int count
= ((code
->opcode
== O (O_EEPMOV
, SW
))
2301 ? h8_get_reg (sd
, R4_REGNUM
) & 0xffff
2302 : h8_get_reg (sd
, R4_REGNUM
) & 0xff);
2304 _src
= (h8_get_reg (sd
, R5_REGNUM
) < memory_size
2305 ? h8_get_memory_buf (sd
) + h8_get_reg (sd
, R5_REGNUM
)
2306 : h8_get_eightbit_buf (sd
) +
2307 (h8_get_reg (sd
, R5_REGNUM
) & 0xff));
2308 if ((_src
+ count
) >= (h8_get_memory_buf (sd
) + memory_size
))
2310 if ((_src
+ count
) >= (h8_get_eightbit_buf (sd
) + 0x100))
2313 _dst
= (h8_get_reg (sd
, R6_REGNUM
) < memory_size
2314 ? h8_get_memory_buf (sd
) + h8_get_reg (sd
, R6_REGNUM
)
2315 : h8_get_eightbit_buf (sd
) +
2316 (h8_get_reg (sd
, R6_REGNUM
) & 0xff));
2318 if ((_dst
+ count
) >= (h8_get_memory_buf (sd
) + memory_size
))
2320 if ((_dst
+ count
) >= (h8_get_eightbit_buf (sd
) + 0x100))
2323 memcpy (_dst
, _src
, count
);
2325 h8_set_reg (sd
, R5_REGNUM
, h8_get_reg (sd
, R5_REGNUM
) + count
);
2326 h8_set_reg (sd
, R6_REGNUM
, h8_get_reg (sd
, R6_REGNUM
) + count
);
2327 h8_set_reg (sd
, R4_REGNUM
, h8_get_reg (sd
, R4_REGNUM
) &
2328 ((code
->opcode
== O (O_EEPMOV
, SW
))
2329 ? (~0xffff) : (~0xff)));
2330 cycles
+= 2 * count
;
2335 case O (O_ADDS
, SL
): /* adds (.l) */
2337 * This insn only uses register operands, but still
2338 * it would be cleaner to use fetch and store... */
2339 SET_L_REG (code
->dst
.reg
,
2340 GET_L_REG (code
->dst
.reg
)
2341 + code
->src
.literal
);
2345 case O (O_SUBS
, SL
): /* subs (.l) */
2347 * This insn only uses register operands, but still
2348 * it would be cleaner to use fetch and store... */
2349 SET_L_REG (code
->dst
.reg
,
2350 GET_L_REG (code
->dst
.reg
)
2351 - code
->src
.literal
);
2354 case O (O_CMP
, SB
): /* cmp.b */
2355 if (fetch (sd
, &code
->dst
, &rd
))
2357 if (fetch (sd
, &code
->src
, &ea
))
2361 goto just_flags_alu8
;
2363 case O (O_CMP
, SW
): /* cmp.w */
2364 if (fetch (sd
, &code
->dst
, &rd
))
2366 if (fetch (sd
, &code
->src
, &ea
))
2370 goto just_flags_alu16
;
2372 case O (O_CMP
, SL
): /* cmp.l */
2373 if (fetch (sd
, &code
->dst
, &rd
))
2375 if (fetch (sd
, &code
->src
, &ea
))
2379 goto just_flags_alu32
;
2381 case O (O_DEC
, SB
): /* dec.b */
2383 * This insn only uses register operands, but still
2384 * it would be cleaner to use fetch and store... */
2385 rd
= GET_B_REG (code
->src
.reg
);
2388 SET_B_REG (code
->src
.reg
, res
);
2389 goto just_flags_inc8
;
2391 case O (O_DEC
, SW
): /* dec.w */
2393 * This insn only uses register operands, but still
2394 * it would be cleaner to use fetch and store... */
2395 rd
= GET_W_REG (code
->dst
.reg
);
2396 ea
= -code
->src
.literal
;
2398 SET_W_REG (code
->dst
.reg
, res
);
2399 goto just_flags_inc16
;
2401 case O (O_DEC
, SL
): /* dec.l */
2403 * This insn only uses register operands, but still
2404 * it would be cleaner to use fetch and store... */
2405 rd
= GET_L_REG (code
->dst
.reg
);
2406 ea
= -code
->src
.literal
;
2408 SET_L_REG (code
->dst
.reg
, res
);
2409 goto just_flags_inc32
;
2411 case O (O_INC
, SB
): /* inc.b */
2413 * This insn only uses register operands, but still
2414 * it would be cleaner to use fetch and store... */
2415 rd
= GET_B_REG (code
->src
.reg
);
2418 SET_B_REG (code
->src
.reg
, res
);
2419 goto just_flags_inc8
;
2421 case O (O_INC
, SW
): /* inc.w */
2423 * This insn only uses register operands, but still
2424 * it would be cleaner to use fetch and store... */
2425 rd
= GET_W_REG (code
->dst
.reg
);
2426 ea
= code
->src
.literal
;
2428 SET_W_REG (code
->dst
.reg
, res
);
2429 goto just_flags_inc16
;
2431 case O (O_INC
, SL
): /* inc.l */
2433 * This insn only uses register operands, but still
2434 * it would be cleaner to use fetch and store... */
2435 rd
= GET_L_REG (code
->dst
.reg
);
2436 ea
= code
->src
.literal
;
2438 SET_L_REG (code
->dst
.reg
, res
);
2439 goto just_flags_inc32
;
2441 case O (O_LDC
, SB
): /* ldc.b */
2442 if (fetch (sd
, &code
->src
, &res
))
2446 case O (O_LDC
, SW
): /* ldc.w */
2447 if (fetch (sd
, &code
->src
, &res
))
2450 /* Word operand, value from MSB, must be shifted. */
2454 case O (O_LDC
, SL
): /* ldc.l */
2455 if (fetch (sd
, &code
->src
, &res
))
2457 switch (code
->dst
.type
) {
2458 case X (OP_SBR
, SL
):
2459 h8_set_sbr (sd
, res
);
2461 case X (OP_VBR
, SL
):
2462 h8_set_vbr (sd
, res
);
2469 case O (O_STC
, SW
): /* stc.w */
2470 case O (O_STC
, SB
): /* stc.b */
2471 if (code
->src
.type
== X (OP_CCR
, SB
))
2474 res
= h8_get_ccr (sd
);
2476 else if (code
->src
.type
== X (OP_EXR
, SB
) && h8300smode
)
2479 h8_set_exr (sd
, (trace
<< 7) | intMask
);
2480 res
= h8_get_exr (sd
);
2485 /* Word operand, value to MSB, must be shifted. */
2486 if (code
->opcode
== X (O_STC
, SW
))
2488 if (store (sd
, &code
->dst
, res
))
2491 case O (O_STC
, SL
): /* stc.l */
2492 switch (code
->src
.type
) {
2493 case X (OP_SBR
, SL
):
2494 res
= h8_get_sbr (sd
);
2496 case X (OP_VBR
, SL
):
2497 res
= h8_get_vbr (sd
);
2502 if (store (sd
, &code
->dst
, res
))
2506 case O (O_ANDC
, SB
): /* andc.b */
2507 if (code
->dst
.type
== X (OP_CCR
, SB
))
2510 rd
= h8_get_ccr (sd
);
2512 else if (code
->dst
.type
== X (OP_EXR
, SB
) && h8300smode
)
2515 h8_set_exr (sd
, (trace
<< 7) | intMask
);
2516 rd
= h8_get_exr (sd
);
2520 ea
= code
->src
.literal
;
2524 case O (O_ORC
, SB
): /* orc.b */
2525 if (code
->dst
.type
== X (OP_CCR
, SB
))
2528 rd
= h8_get_ccr (sd
);
2530 else if (code
->dst
.type
== X (OP_EXR
, SB
) && h8300smode
)
2533 h8_set_exr (sd
, (trace
<< 7) | intMask
);
2534 rd
= h8_get_exr (sd
);
2538 ea
= code
->src
.literal
;
2542 case O (O_XORC
, SB
): /* xorc.b */
2543 if (code
->dst
.type
== X (OP_CCR
, SB
))
2546 rd
= h8_get_ccr (sd
);
2548 else if (code
->dst
.type
== X (OP_EXR
, SB
) && h8300smode
)
2551 h8_set_exr (sd
, (trace
<< 7) | intMask
);
2552 rd
= h8_get_exr (sd
);
2556 ea
= code
->src
.literal
;
2560 case O (O_BRAS
, SB
): /* bra/s */
2561 /* This is basically an ordinary branch, with a delay slot. */
2562 if (fetch (sd
, &code
->src
, &res
))
2570 /* Execution continues at next instruction, but
2571 delayed_branch is set up for next cycle. */
2572 h8_set_delayed_branch (sd
, code
->next_pc
+ res
);
2576 case O (O_BRAB
, SB
): /* bra rd.b */
2577 case O (O_BRAW
, SW
): /* bra rd.w */
2578 case O (O_BRAL
, SL
): /* bra erd.l */
2579 if (fetch (sd
, &code
->src
, &rd
))
2581 switch (OP_SIZE (code
->opcode
)) {
2582 case SB
: rd
&= 0xff; break;
2583 case SW
: rd
&= 0xffff; break;
2584 case SL
: rd
&= 0xffffffff; break;
2586 pc
= code
->next_pc
+ rd
;
2589 case O (O_BRABC
, SB
): /* bra/bc, branch if bit clear */
2590 case O (O_BRABS
, SB
): /* bra/bs, branch if bit set */
2591 case O (O_BSRBC
, SB
): /* bsr/bc, call if bit clear */
2592 case O (O_BSRBS
, SB
): /* bsr/bs, call if bit set */
2593 if (fetch (sd
, &code
->dst
, &rd
) ||
2594 fetch (sd
, &code
->src
, &bit
))
2597 if (code
->opcode
== O (O_BRABC
, SB
) || /* branch if clear */
2598 code
->opcode
== O (O_BSRBC
, SB
)) /* call if clear */
2600 if ((rd
& (1 << bit
))) /* no branch */
2603 else /* branch/call if set */
2605 if (!(rd
& (1 << bit
))) /* no branch */
2609 if (fetch (sd
, &code
->op3
, &res
)) /* branch */
2611 pc
= code
->next_pc
+ res
;
2613 if (code
->opcode
== O (O_BRABC
, SB
) ||
2614 code
->opcode
== O (O_BRABS
, SB
)) /* branch */
2622 case O (O_BRA
, SB
): /* bra, branch always */
2627 case O (O_BRN
, SB
): /* brn, ;-/ branch never? */
2632 case O (O_BHI
, SB
): /* bhi */
2638 case O (O_BLS
, SB
): /* bls */
2643 case O (O_BCS
, SB
): /* bcs, branch if carry set */
2648 case O (O_BCC
, SB
): /* bcc, branch if carry clear */
2653 case O (O_BEQ
, SB
): /* beq, branch if zero set */
2657 case O (O_BGT
, SB
): /* bgt */
2658 if (((Z
|| (N
^ V
)) == 0))
2662 case O (O_BLE
, SB
): /* ble */
2663 if (((Z
|| (N
^ V
)) == 1))
2667 case O (O_BGE
, SB
): /* bge */
2671 case O (O_BLT
, SB
): /* blt */
2675 case O (O_BMI
, SB
): /* bmi */
2679 case O (O_BNE
, SB
): /* bne, branch if zero clear */
2684 case O (O_BPL
, SB
): /* bpl */
2688 case O (O_BVC
, SB
): /* bvc */
2692 case O (O_BVS
, SB
): /* bvs */
2697 /* Trap for Command Line setup. */
2698 case O (O_SYS_CMDLINE
, SB
):
2700 int i
= 0; /* Loop counter. */
2701 int j
= 0; /* Loop counter. */
2702 int ind_arg_len
= 0; /* Length of each argument. */
2703 int no_of_args
= 0; /* The no. or cmdline args. */
2704 int current_location
= 0; /* Location of string. */
2705 int old_sp
= 0; /* The Initial Stack Pointer. */
2706 int no_of_slots
= 0; /* No. of slots required on the stack
2707 for storing cmdline args. */
2708 int sp_move
= 0; /* No. of locations by which the stack needs
2710 int new_sp
= 0; /* The final stack pointer location passed
2712 int *argv_ptrs
; /* Pointers of argv strings to be stored. */
2713 int argv_ptrs_location
= 0; /* Location of pointers to cmdline
2714 args on the stack. */
2715 int char_ptr_size
= 0; /* Size of a character pointer on
2717 int addr_cmdline
= 0; /* Memory location where cmdline has
2719 int size_cmdline
= 0; /* Size of cmdline. */
2721 /* Set the address of 256 free locations where command line is
2723 addr_cmdline
= cmdline_location();
2724 h8_set_reg (sd
, 0, addr_cmdline
);
2726 /* Counting the no. of commandline arguments. */
2727 for (i
= 0; h8_get_cmdline_arg (sd
, i
) != NULL
; i
++)
2730 /* No. of arguments in the command line. */
2733 /* Current location is just a temporary variable,which we are
2734 setting to the point to the start of our commandline string. */
2735 current_location
= addr_cmdline
;
2737 /* Allocating space for storing pointers of the command line
2739 argv_ptrs
= (int *) malloc (sizeof (int) * no_of_args
);
2741 /* Setting char_ptr_size to the sizeof (char *) on the different
2743 if ((h8300hmode
|| h8300smode
) && !h8300_normal_mode
)
2752 for (i
= 0; i
< no_of_args
; i
++)
2756 /* The size of the commandline argument. */
2757 ind_arg_len
= strlen (h8_get_cmdline_arg (sd
, i
)) + 1;
2759 /* The total size of the command line string. */
2760 size_cmdline
+= ind_arg_len
;
2762 /* As we have only 256 bytes, we need to provide a graceful
2763 exit. Anyways, a program using command line arguments
2764 where we cannot store all the command line arguments
2765 given may behave unpredictably. */
2766 if (size_cmdline
>= 256)
2768 h8_set_reg (sd
, 0, 0);
2773 /* current_location points to the memory where the next
2774 commandline argument is stored. */
2775 argv_ptrs
[i
] = current_location
;
2776 for (j
= 0; j
< ind_arg_len
; j
++)
2778 SET_MEMORY_B ((current_location
+
2779 (sizeof (char) * j
)),
2780 *(h8_get_cmdline_arg (sd
, i
) +
2781 sizeof (char) * j
));
2784 /* Setting current_location to the starting of next
2786 current_location
+= ind_arg_len
;
2790 /* This is the original position of the stack pointer. */
2791 old_sp
= h8_get_reg (sd
, SP_REGNUM
);
2793 /* We need space from the stack to store the pointers to argvs. */
2794 /* As we will infringe on the stack, we need to shift the stack
2795 pointer so that the data is not overwritten. We calculate how
2796 much space is required. */
2797 sp_move
= (no_of_args
) * (char_ptr_size
);
2799 /* The final position of stack pointer, we have thus taken some
2800 space from the stack. */
2801 new_sp
= old_sp
- sp_move
;
2803 /* Temporary variable holding value where the argv pointers need
2805 argv_ptrs_location
= new_sp
;
2807 /* The argv pointers are stored at sequential locations. As per
2809 for (i
= 0; i
< no_of_args
; i
++)
2811 /* Saving the argv pointer. */
2812 if ((h8300hmode
|| h8300smode
) && !h8300_normal_mode
)
2814 SET_MEMORY_L (argv_ptrs_location
, argv_ptrs
[i
]);
2818 SET_MEMORY_W (argv_ptrs_location
, argv_ptrs
[i
]);
2821 /* The next location where the pointer to the next argv
2822 string has to be stored. */
2823 argv_ptrs_location
+= char_ptr_size
;
2826 /* Required by POSIX, Setting 0x0 at the end of the list of argv
2828 if ((h8300hmode
|| h8300smode
) && !h8300_normal_mode
)
2830 SET_MEMORY_L (old_sp
, 0x0);
2834 SET_MEMORY_W (old_sp
, 0x0);
2837 /* Freeing allocated memory. */
2839 for (i
= 0; i
<= no_of_args
; i
++)
2841 free (h8_get_cmdline_arg (sd
, i
));
2843 free (h8_get_command_line (sd
));
2845 /* The no. of argv arguments are returned in Reg 0. */
2846 h8_set_reg (sd
, 0, no_of_args
);
2847 /* The Pointer to argv in Register 1. */
2848 h8_set_reg (sd
, 1, new_sp
);
2849 /* Setting the stack pointer to the new value. */
2850 h8_set_reg (sd
, SP_REGNUM
, new_sp
);
2854 /* System call processing starts. */
2855 case O (O_SYS_OPEN
, SB
):
2857 int len
= 0; /* Length of filename. */
2858 char *filename
; /* Filename would go here. */
2859 char temp_char
; /* Temporary character */
2860 int mode
= 0; /* Mode bits for the file. */
2861 int open_return
; /* Return value of open, file descriptor. */
2862 int i
; /* Loop counter */
2863 int filename_ptr
; /* Pointer to filename in cpu memory. */
2865 /* Setting filename_ptr to first argument of open, */
2866 /* and trying to get mode. */
2867 if ((h8300sxmode
|| h8300hmode
|| h8300smode
) && !h8300_normal_mode
)
2869 filename_ptr
= GET_L_REG (0);
2870 mode
= GET_MEMORY_L (h8_get_reg (sd
, SP_REGNUM
) + 4);
2874 filename_ptr
= GET_W_REG (0);
2875 mode
= GET_MEMORY_W (h8_get_reg (sd
, SP_REGNUM
) + 2);
2878 /* Trying to find the length of the filename. */
2879 temp_char
= GET_MEMORY_B (h8_get_reg (sd
, 0));
2882 while (temp_char
!= '\0')
2884 temp_char
= GET_MEMORY_B (filename_ptr
+ len
);
2888 /* Allocating space for the filename. */
2889 filename
= (char *) malloc (sizeof (char) * len
);
2891 /* String copying the filename from memory. */
2892 for (i
= 0; i
< len
; i
++)
2894 temp_char
= GET_MEMORY_B (filename_ptr
+ i
);
2895 filename
[i
] = temp_char
;
2898 /* Callback to open and return the file descriptor. */
2899 open_return
= sim_callback
->open (sim_callback
, filename
, mode
);
2901 /* Return value in register 0. */
2902 h8_set_reg (sd
, 0, open_return
);
2904 /* Freeing memory used for filename. */
2909 case O (O_SYS_READ
, SB
):
2911 char *char_ptr
; /* Where characters read would be stored. */
2912 int fd
; /* File descriptor */
2913 int buf_size
; /* BUF_SIZE parameter in read. */
2914 int i
= 0; /* Temporary Loop counter */
2915 int read_return
= 0; /* Return value from callback to
2918 fd
= (h8300hmode
&& !h8300_normal_mode
) ? GET_L_REG (0) : GET_W_REG (0);
2919 buf_size
= (h8300hmode
&& !h8300_normal_mode
) ? GET_L_REG (2) : GET_W_REG (2);
2921 char_ptr
= (char *) malloc (sizeof (char) * buf_size
);
2923 /* Callback to read and return the no. of characters read. */
2925 sim_callback
->read (sim_callback
, fd
, char_ptr
, buf_size
);
2927 /* The characters read are stored in cpu memory. */
2928 for (i
= 0; i
< buf_size
; i
++)
2930 SET_MEMORY_B ((h8_get_reg (sd
, 1) + (sizeof (char) * i
)),
2931 *(char_ptr
+ (sizeof (char) * i
)));
2934 /* Return value in Register 0. */
2935 h8_set_reg (sd
, 0, read_return
);
2937 /* Freeing memory used as buffer. */
2942 case O (O_SYS_WRITE
, SB
):
2944 int fd
; /* File descriptor */
2945 char temp_char
; /* Temporary character */
2946 int len
; /* Length of write, Parameter II to write. */
2947 int char_ptr
; /* Character Pointer, Parameter I of write. */
2948 char *ptr
; /* Where characters to be written are stored.
2950 int write_return
; /* Return value from callback to write. */
2951 int i
= 0; /* Loop counter */
2953 fd
= (h8300hmode
&& !h8300_normal_mode
) ? GET_L_REG (0) : GET_W_REG (0);
2954 char_ptr
= (h8300hmode
&& !h8300_normal_mode
) ? GET_L_REG (1) : GET_W_REG (1);
2955 len
= (h8300hmode
&& !h8300_normal_mode
) ? GET_L_REG (2) : GET_W_REG (2);
2957 /* Allocating space for the characters to be written. */
2958 ptr
= (char *) malloc (sizeof (char) * len
);
2960 /* Fetching the characters from cpu memory. */
2961 for (i
= 0; i
< len
; i
++)
2963 temp_char
= GET_MEMORY_B (char_ptr
+ i
);
2967 /* Callback write and return the no. of characters written. */
2968 write_return
= sim_callback
->write (sim_callback
, fd
, ptr
, len
);
2970 /* Return value in Register 0. */
2971 h8_set_reg (sd
, 0, write_return
);
2973 /* Freeing memory used as buffer. */
2978 case O (O_SYS_LSEEK
, SB
):
2980 int fd
; /* File descriptor */
2981 int offset
; /* Offset */
2982 int origin
; /* Origin */
2983 int lseek_return
; /* Return value from callback to lseek. */
2985 fd
= (h8300hmode
&& !h8300_normal_mode
) ? GET_L_REG (0) : GET_W_REG (0);
2986 offset
= (h8300hmode
&& !h8300_normal_mode
) ? GET_L_REG (1) : GET_W_REG (1);
2987 origin
= (h8300hmode
&& !h8300_normal_mode
) ? GET_L_REG (2) : GET_W_REG (2);
2989 /* Callback lseek and return offset. */
2991 sim_callback
->lseek (sim_callback
, fd
, offset
, origin
);
2993 /* Return value in register 0. */
2994 h8_set_reg (sd
, 0, lseek_return
);
2998 case O (O_SYS_CLOSE
, SB
):
3000 int fd
; /* File descriptor */
3001 int close_return
; /* Return value from callback to close. */
3003 fd
= (h8300hmode
&& !h8300_normal_mode
) ? GET_L_REG (0) : GET_W_REG (0);
3005 /* Callback close and return. */
3006 close_return
= sim_callback
->close (sim_callback
, fd
);
3008 /* Return value in register 0. */
3009 h8_set_reg (sd
, 0, close_return
);
3013 case O (O_SYS_FSTAT
, SB
):
3015 int fd
; /* File descriptor */
3016 struct stat stat_rec
; /* Stat record */
3017 int fstat_return
; /* Return value from callback to stat. */
3018 int stat_ptr
; /* Pointer to stat record. */
3019 char *temp_stat_ptr
; /* Temporary stat_rec pointer. */
3021 fd
= (h8300hmode
&& !h8300_normal_mode
) ? GET_L_REG (0) : GET_W_REG (0);
3023 /* Setting stat_ptr to second argument of stat. */
3024 stat_ptr
= (h8300hmode
&& !h8300_normal_mode
) ? GET_L_REG (1) : GET_W_REG (1);
3026 /* Callback stat and return. */
3027 fstat_return
= sim_callback
->to_fstat (sim_callback
, fd
,
3030 /* Have stat_ptr point to starting of stat_rec. */
3031 temp_stat_ptr
= (char *) (&stat_rec
);
3033 /* Setting up the stat structure returned. */
3034 SET_MEMORY_W (stat_ptr
, stat_rec
.st_dev
);
3036 SET_MEMORY_W (stat_ptr
, stat_rec
.st_ino
);
3038 SET_MEMORY_L (stat_ptr
, stat_rec
.st_mode
);
3040 SET_MEMORY_W (stat_ptr
, stat_rec
.st_nlink
);
3042 SET_MEMORY_W (stat_ptr
, stat_rec
.st_uid
);
3044 SET_MEMORY_W (stat_ptr
, stat_rec
.st_gid
);
3046 SET_MEMORY_W (stat_ptr
, stat_rec
.st_rdev
);
3048 SET_MEMORY_L (stat_ptr
, stat_rec
.st_size
);
3050 SET_MEMORY_L (stat_ptr
, stat_rec
.st_atime
);
3052 SET_MEMORY_L (stat_ptr
, stat_rec
.st_mtime
);
3054 SET_MEMORY_L (stat_ptr
, stat_rec
.st_ctime
);
3056 /* Return value in register 0. */
3057 h8_set_reg (sd
, 0, fstat_return
);
3061 case O (O_SYS_STAT
, SB
):
3063 int len
= 0; /* Length of filename. */
3064 char *filename
; /* Filename would go here. */
3065 char temp_char
; /* Temporary character */
3066 int filename_ptr
; /* Pointer to filename in cpu memory. */
3067 struct stat stat_rec
; /* Stat record */
3068 int stat_return
; /* Return value from callback to stat */
3069 int stat_ptr
; /* Pointer to stat record. */
3070 char *temp_stat_ptr
; /* Temporary stat_rec pointer. */
3071 int i
= 0; /* Loop Counter */
3073 /* Setting filename_ptr to first argument of open. */
3074 filename_ptr
= (h8300hmode
&& !h8300_normal_mode
) ? GET_L_REG (0) : GET_W_REG (0);
3076 /* Trying to find the length of the filename. */
3077 temp_char
= GET_MEMORY_B (h8_get_reg (sd
, 0));
3080 while (temp_char
!= '\0')
3082 temp_char
= GET_MEMORY_B (filename_ptr
+ len
);
3086 /* Allocating space for the filename. */
3087 filename
= (char *) malloc (sizeof (char) * len
);
3089 /* String copying the filename from memory. */
3090 for (i
= 0; i
< len
; i
++)
3092 temp_char
= GET_MEMORY_B (filename_ptr
+ i
);
3093 filename
[i
] = temp_char
;
3096 /* Setting stat_ptr to second argument of stat. */
3097 /* stat_ptr = h8_get_reg (sd, 1); */
3098 stat_ptr
= (h8300hmode
&& !h8300_normal_mode
) ? GET_L_REG (1) : GET_W_REG (1);
3100 /* Callback stat and return. */
3102 sim_callback
->to_stat (sim_callback
, filename
, &stat_rec
);
3104 /* Have stat_ptr point to starting of stat_rec. */
3105 temp_stat_ptr
= (char *) (&stat_rec
);
3107 /* Freeing memory used for filename. */
3110 /* Setting up the stat structure returned. */
3111 SET_MEMORY_W (stat_ptr
, stat_rec
.st_dev
);
3113 SET_MEMORY_W (stat_ptr
, stat_rec
.st_ino
);
3115 SET_MEMORY_L (stat_ptr
, stat_rec
.st_mode
);
3117 SET_MEMORY_W (stat_ptr
, stat_rec
.st_nlink
);
3119 SET_MEMORY_W (stat_ptr
, stat_rec
.st_uid
);
3121 SET_MEMORY_W (stat_ptr
, stat_rec
.st_gid
);
3123 SET_MEMORY_W (stat_ptr
, stat_rec
.st_rdev
);
3125 SET_MEMORY_L (stat_ptr
, stat_rec
.st_size
);
3127 SET_MEMORY_L (stat_ptr
, stat_rec
.st_atime
);
3129 SET_MEMORY_L (stat_ptr
, stat_rec
.st_mtime
);
3131 SET_MEMORY_L (stat_ptr
, stat_rec
.st_ctime
);
3133 /* Return value in register 0. */
3134 h8_set_reg (sd
, 0, stat_return
);
3137 /* End of system call processing. */
3139 case O (O_NOT
, SB
): /* not.b */
3140 if (fetch2 (sd
, &code
->src
, &rd
))
3146 case O (O_NOT
, SW
): /* not.w */
3147 if (fetch2 (sd
, &code
->src
, &rd
))
3153 case O (O_NOT
, SL
): /* not.l */
3154 if (fetch2 (sd
, &code
->src
, &rd
))
3160 case O (O_SHLL
, SB
): /* shll.b */
3161 case O (O_SHLR
, SB
): /* shlr.b */
3162 if (fetch2 (sd
, &code
->dst
, &rd
))
3165 if (memcmp (&code
->src
, &code
->dst
, sizeof (code
->src
)) == 0)
3166 ea
= 1; /* unary op */
3167 else /* binary op */
3168 fetch (sd
, &code
->src
, &ea
);
3170 if (code
->opcode
== O (O_SHLL
, SB
))
3173 c
= rd
& (0x80 >> (ea
- 1));
3179 c
= rd
& (1 << (ea
- 1));
3180 rd
= (unsigned char) rd
>> ea
;
3184 case O (O_SHLL
, SW
): /* shll.w */
3185 case O (O_SHLR
, SW
): /* shlr.w */
3186 if (fetch2 (sd
, &code
->dst
, &rd
))
3189 if (memcmp (&code
->src
, &code
->dst
, sizeof (code
->src
)) == 0)
3190 ea
= 1; /* unary op */
3192 fetch (sd
, &code
->src
, &ea
);
3194 if (code
->opcode
== O (O_SHLL
, SW
))
3197 c
= rd
& (0x8000 >> (ea
- 1));
3203 c
= rd
& (1 << (ea
- 1));
3204 rd
= (unsigned short) rd
>> ea
;
3208 case O (O_SHLL
, SL
): /* shll.l */
3209 case O (O_SHLR
, SL
): /* shlr.l */
3210 if (fetch2 (sd
, &code
->dst
, &rd
))
3213 if (memcmp (&code
->src
, &code
->dst
, sizeof (code
->src
)) == 0)
3214 ea
= 1; /* unary op */
3216 fetch (sd
, &code
->src
, &ea
);
3218 if (code
->opcode
== O (O_SHLL
, SL
))
3221 c
= rd
& (0x80000000 >> (ea
- 1));
3227 c
= rd
& (1 << (ea
- 1));
3228 rd
= (unsigned int) rd
>> ea
;
3232 case O (O_SHAL
, SB
):
3233 case O (O_SHAR
, SB
):
3234 if (fetch2 (sd
, &code
->dst
, &rd
))
3237 if (code
->src
.type
== X (OP_IMM
, SB
))
3238 fetch (sd
, &code
->src
, &ea
);
3242 if (code
->opcode
== O (O_SHAL
, SB
))
3244 c
= rd
& (0x80 >> (ea
- 1));
3245 res
= rd
>> (7 - ea
);
3246 v
= ((res
& 1) && !(res
& 2))
3247 || (!(res
& 1) && (res
& 2));
3252 c
= rd
& (1 << (ea
- 1));
3254 rd
= ((signed char) rd
) >> ea
;
3258 case O (O_SHAL
, SW
):
3259 case O (O_SHAR
, SW
):
3260 if (fetch2 (sd
, &code
->dst
, &rd
))
3263 if (code
->src
.type
== X (OP_IMM
, SW
))
3264 fetch (sd
, &code
->src
, &ea
);
3268 if (code
->opcode
== O (O_SHAL
, SW
))
3270 c
= rd
& (0x8000 >> (ea
- 1));
3271 res
= rd
>> (15 - ea
);
3272 v
= ((res
& 1) && !(res
& 2))
3273 || (!(res
& 1) && (res
& 2));
3278 c
= rd
& (1 << (ea
- 1));
3280 rd
= ((signed short) rd
) >> ea
;
3284 case O (O_SHAL
, SL
):
3285 case O (O_SHAR
, SL
):
3286 if (fetch2 (sd
, &code
->dst
, &rd
))
3289 if (code
->src
.type
== X (OP_IMM
, SL
))
3290 fetch (sd
, &code
->src
, &ea
);
3294 if (code
->opcode
== O (O_SHAL
, SL
))
3296 c
= rd
& (0x80000000 >> (ea
- 1));
3297 res
= rd
>> (31 - ea
);
3298 v
= ((res
& 1) && !(res
& 2))
3299 || (!(res
& 1) && (res
& 2));
3304 c
= rd
& (1 << (ea
- 1));
3306 rd
= ((signed int) rd
) >> ea
;
3310 case O (O_ROTL
, SB
):
3311 case O (O_ROTR
, SB
):
3312 if (fetch2 (sd
, &code
->dst
, &rd
))
3315 if (code
->src
.type
== X (OP_IMM
, SB
))
3316 fetch (sd
, &code
->src
, &ea
);
3321 if (code
->opcode
== O (O_ROTL
, SB
))
3331 rd
= ((unsigned char) rd
) >> 1;
3339 case O (O_ROTL
, SW
):
3340 case O (O_ROTR
, SW
):
3341 if (fetch2 (sd
, &code
->dst
, &rd
))
3344 if (code
->src
.type
== X (OP_IMM
, SW
))
3345 fetch (sd
, &code
->src
, &ea
);
3350 if (code
->opcode
== O (O_ROTL
, SW
))
3360 rd
= ((unsigned short) rd
) >> 1;
3368 case O (O_ROTL
, SL
):
3369 case O (O_ROTR
, SL
):
3370 if (fetch2 (sd
, &code
->dst
, &rd
))
3373 if (code
->src
.type
== X (OP_IMM
, SL
))
3374 fetch (sd
, &code
->src
, &ea
);
3379 if (code
->opcode
== O (O_ROTL
, SL
))
3381 c
= rd
& 0x80000000;
3389 rd
= ((unsigned int) rd
) >> 1;
3397 case O (O_ROTXL
, SB
):
3398 case O (O_ROTXR
, SB
):
3399 if (fetch2 (sd
, &code
->dst
, &rd
))
3402 if (code
->src
.type
== X (OP_IMM
, SB
))
3403 fetch (sd
, &code
->src
, &ea
);
3408 if (code
->opcode
== O (O_ROTXL
, SB
))
3419 rd
= ((unsigned char) rd
) >> 1;
3428 case O (O_ROTXL
, SW
):
3429 case O (O_ROTXR
, SW
):
3430 if (fetch2 (sd
, &code
->dst
, &rd
))
3433 if (code
->src
.type
== X (OP_IMM
, SW
))
3434 fetch (sd
, &code
->src
, &ea
);
3439 if (code
->opcode
== O (O_ROTXL
, SW
))
3450 rd
= ((unsigned short) rd
) >> 1;
3459 case O (O_ROTXL
, SL
):
3460 case O (O_ROTXR
, SL
):
3461 if (fetch2 (sd
, &code
->dst
, &rd
))
3464 if (code
->src
.type
== X (OP_IMM
, SL
))
3465 fetch (sd
, &code
->src
, &ea
);
3470 if (code
->opcode
== O (O_ROTXL
, SL
))
3472 res
= rd
& 0x80000000;
3481 rd
= ((unsigned int) rd
) >> 1;
3492 case O (O_JMP
, SB
): /* jmp */
3494 fetch (sd
, &code
->src
, &pc
);
3499 case O (O_JSR
, SB
): /* jsr, jump to subroutine */
3501 if (fetch (sd
, &code
->src
, &pc
))
3504 tmp
= h8_get_reg (sd
, SP_REGNUM
);
3506 if (h8300hmode
&& !h8300_normal_mode
)
3509 SET_MEMORY_L (tmp
, code
->next_pc
);
3514 SET_MEMORY_W (tmp
, code
->next_pc
);
3516 h8_set_reg (sd
, SP_REGNUM
, tmp
);
3522 case O (O_BSR
, SB
): /* bsr, branch to subroutine */
3523 if (fetch (sd
, &code
->src
, &res
))
3525 pc
= code
->next_pc
+ res
;
3528 case O (O_RTE
, SN
): /* rte, return from exception */
3530 /* Pops exr and ccr before pc -- otherwise identical to rts. */
3531 tmp
= h8_get_reg (sd
, SP_REGNUM
);
3533 if (h8300smode
) /* pop exr */
3535 h8_set_exr (sd
, GET_MEMORY_L (tmp
));
3538 if (h8300hmode
&& !h8300_normal_mode
)
3540 h8_set_ccr (sd
, GET_MEMORY_L (tmp
));
3542 pc
= GET_MEMORY_L (tmp
);
3547 h8_set_ccr (sd
, GET_MEMORY_W (tmp
));
3549 pc
= GET_MEMORY_W (tmp
);
3554 h8_set_reg (sd
, SP_REGNUM
, tmp
);
3557 case O (O_RTS
, SN
): /* rts, return from subroutine */
3559 tmp
= h8_get_reg (sd
, SP_REGNUM
);
3561 if (h8300hmode
&& !h8300_normal_mode
)
3563 pc
= GET_MEMORY_L (tmp
);
3568 pc
= GET_MEMORY_W (tmp
);
3572 h8_set_reg (sd
, SP_REGNUM
, tmp
);
3575 case O (O_ILL
, SB
): /* illegal */
3576 sim_engine_halt (sd
, cpu
, NULL
, pc
, sim_stopped
, SIM_SIGILL
);
3579 case O (O_SLEEP
, SN
): /* sleep */
3580 /* Check for magic numbers in r1 and r2. */
3581 if ((h8_get_reg (sd
, R1_REGNUM
) & 0xffff) == LIBC_EXIT_MAGIC1
&&
3582 (h8_get_reg (sd
, R2_REGNUM
) & 0xffff) == LIBC_EXIT_MAGIC2
&&
3583 SIM_WIFEXITED (h8_get_reg (sd
, 0)))
3585 /* This trap comes from _exit, not from gdb. */
3586 sim_engine_halt (sd
, cpu
, NULL
, pc
, sim_exited
,
3587 SIM_WEXITSTATUS (h8_get_reg (sd
, 0)));
3590 /* Unfortunately this won't really work, because
3591 when we take a breakpoint trap, R0 has a "random",
3592 user-defined value. Don't see any immediate solution. */
3593 else if (SIM_WIFSTOPPED (h8_get_reg (sd
, 0)))
3595 /* Pass the stop signal up to gdb. */
3596 sim_engine_halt (sd
, cpu
, NULL
, pc
, sim_stopped
,
3597 SIM_WSTOPSIG (h8_get_reg (sd
, 0)));
3602 /* Treat it as a sigtrap. */
3603 sim_engine_halt (sd
, cpu
, NULL
, pc
, sim_stopped
, SIM_SIGTRAP
);
3607 case O (O_TRAPA
, SB
): /* trapa */
3608 if (fetch (sd
, &code
->src
, &res
))
3609 goto end
; /* res is vector number. */
3611 tmp
= h8_get_reg (sd
, SP_REGNUM
);
3612 if(h8300_normal_mode
)
3615 SET_MEMORY_W (tmp
, code
->next_pc
);
3617 SET_MEMORY_W (tmp
, h8_get_ccr (sd
));
3622 SET_MEMORY_L (tmp
, code
->next_pc
);
3624 SET_MEMORY_L (tmp
, h8_get_ccr (sd
));
3632 SET_MEMORY_L (tmp
, h8_get_exr (sd
));
3635 h8_set_reg (sd
, SP_REGNUM
, tmp
);
3637 if(h8300_normal_mode
)
3638 pc
= GET_MEMORY_L (0x10 + res
* 2); /* Vector addresses are 0x10,0x12,0x14 and 0x16 */
3640 pc
= GET_MEMORY_L (0x20 + res
* 4);
3644 sim_engine_halt (sd
, cpu
, NULL
, pc
, sim_stopped
, SIM_SIGTRAP
);
3647 case O (O_BSETEQ
, SB
):
3652 case O (O_BSETNE
, SB
):
3657 case O (O_BCLREQ
, SB
):
3662 case O (O_BCLRNE
, SB
):
3667 OBITOP (O_BNOT
, 1, 1, ea
^= m
); /* bnot */
3668 OBITOP (O_BTST
, 1, 0, nz
= ea
& m
); /* btst */
3670 OBITOP (O_BSET
, 1, 1, ea
|= m
); /* bset */
3672 OBITOP (O_BCLR
, 1, 1, ea
&= ~m
); /* bclr */
3673 OBITOP (O_BLD
, 1, 0, c
= ea
& m
); /* bld */
3674 OBITOP (O_BILD
, 1, 0, c
= !(ea
& m
)); /* bild */
3675 OBITOP (O_BST
, 1, 1, ea
&= ~m
;
3676 if (C
) ea
|= m
); /* bst */
3677 OBITOP (O_BIST
, 1, 1, ea
&= ~m
;
3678 if (!C
) ea
|= m
); /* bist */
3679 OBITOP (O_BSTZ
, 1, 1, ea
&= ~m
;
3680 if (Z
) ea
|= m
); /* bstz */
3681 OBITOP (O_BISTZ
, 1, 1, ea
&= ~m
;
3682 if (!Z
) ea
|= m
); /* bistz */
3683 OBITOP (O_BAND
, 1, 0, c
= (ea
& m
) && C
); /* band */
3684 OBITOP (O_BIAND
, 1, 0, c
= !(ea
& m
) && C
); /* biand */
3685 OBITOP (O_BOR
, 1, 0, c
= (ea
& m
) || C
); /* bor */
3686 OBITOP (O_BIOR
, 1, 0, c
= !(ea
& m
) || C
); /* bior */
3687 OBITOP (O_BXOR
, 1, 0, c
= ((ea
& m
) != 0)!= C
); /* bxor */
3688 OBITOP (O_BIXOR
, 1, 0, c
= !(ea
& m
) != C
); /* bixor */
3690 case O (O_BFLD
, SB
): /* bfld */
3693 if (fetch (sd
, &code
->src
, &bit
))
3698 if (fetch (sd
, &code
->dst
, &ea
))
3708 if (store (sd
, &code
->op3
, ea
))
3713 case O(O_BFST
, SB
): /* bfst */
3714 /* bitfield store */
3715 /* NOTE: the imm8 value is in dst, and the ea value
3716 (which is actually the destination) is in op3.
3717 It has to be that way, to avoid breaking the assembler. */
3719 if (fetch (sd
, &code
->dst
, &bit
)) /* imm8 */
3721 if (bit
== 0) /* noop -- nothing to do. */
3724 if (fetch (sd
, &code
->src
, &rd
)) /* reg8 src */
3727 if (fetch2 (sd
, &code
->op3
, &ea
)) /* ea dst */
3730 /* Left-shift the register data into position. */
3731 for (tmp
= bit
; !(tmp
& 1); tmp
>>= 1)
3734 /* Combine it with the neighboring bits. */
3735 ea
= (ea
& ~bit
) | (rd
& bit
);
3738 if (store2 (sd
, &code
->op3
, ea
))
3742 case O (O_CLRMAC
, SN
): /* clrmac */
3743 h8_set_mach (sd
, 0);
3744 h8_set_macl (sd
, 0);
3745 h8_set_macZ (sd
, 1);
3746 h8_set_macV (sd
, 0);
3747 h8_set_macN (sd
, 0);
3750 case O (O_STMAC
, SL
): /* stmac, 260 */
3751 switch (code
->src
.type
) {
3752 case X (OP_MACH
, SL
):
3753 res
= h8_get_mach (sd
);
3754 if (res
& 0x200) /* sign extend */
3757 case X (OP_MACL
, SL
):
3758 res
= h8_get_macl (sd
);
3760 default: goto illegal
;
3762 nz
= !h8_get_macZ (sd
);
3763 n
= h8_get_macN (sd
);
3764 v
= h8_get_macV (sd
);
3766 if (store (sd
, &code
->dst
, res
))
3771 case O (O_LDMAC
, SL
): /* ldmac, 179 */
3772 if (fetch (sd
, &code
->src
, &rd
))
3775 switch (code
->dst
.type
) {
3776 case X (OP_MACH
, SL
):
3777 rd
&= 0x3ff; /* Truncate to 10 bits */
3778 h8_set_mach (sd
, rd
);
3780 case X (OP_MACL
, SL
):
3781 h8_set_macl (sd
, rd
);
3783 default: goto illegal
;
3785 h8_set_macV (sd
, 0);
3789 if (fetch (sd
, &code
->src
, &rd
) ||
3790 fetch (sd
, &code
->dst
, &res
))
3793 /* Ye gods, this is non-portable!
3794 However, the existing mul/div code is similar. */
3795 res
= SEXTSHORT (res
) * SEXTSHORT (rd
);
3797 if (h8_get_macS (sd
)) /* Saturating mode */
3799 long long mac
= h8_get_macl (sd
);
3801 if (mac
& 0x80000000) /* sign extend */
3802 mac
|= 0xffffffff00000000LL
;
3805 if (mac
> 0x7fffffff || mac
< 0xffffffff80000000LL
)
3806 h8_set_macV (sd
, 1);
3807 h8_set_macZ (sd
, (mac
== 0));
3808 h8_set_macN (sd
, (mac
< 0));
3809 h8_set_macl (sd
, (int) mac
);
3811 else /* "Less Saturating" mode */
3813 long long mac
= h8_get_mach (sd
);
3815 mac
+= h8_get_macl (sd
);
3817 if (mac
& 0x20000000000LL
) /* sign extend */
3818 mac
|= 0xfffffc0000000000LL
;
3821 if (mac
> 0x1ffffffffffLL
||
3822 mac
< (long long) 0xfffffe0000000000LL
)
3823 h8_set_macV (sd
, 1);
3824 h8_set_macZ (sd
, (mac
== 0));
3825 h8_set_macN (sd
, (mac
< 0));
3826 h8_set_macl (sd
, (int) mac
);
3828 h8_set_mach (sd
, (int) (mac
& 0x3ff));
3832 case O (O_MULS
, SW
): /* muls.w */
3833 if (fetch (sd
, &code
->src
, &ea
) ||
3834 fetch (sd
, &code
->dst
, &rd
))
3837 ea
= SEXTSHORT (ea
);
3838 res
= SEXTSHORT (ea
* SEXTSHORT (rd
));
3842 if (store (sd
, &code
->dst
, res
))
3847 case O (O_MULS
, SL
): /* muls.l */
3848 if (fetch (sd
, &code
->src
, &ea
) ||
3849 fetch (sd
, &code
->dst
, &rd
))
3854 n
= res
& 0x80000000;
3855 nz
= res
& 0xffffffff;
3856 if (store (sd
, &code
->dst
, res
))
3860 case O (O_MULSU
, SL
): /* muls/u.l */
3861 if (fetch (sd
, &code
->src
, &ea
) ||
3862 fetch (sd
, &code
->dst
, &rd
))
3865 /* Compute upper 32 bits of the 64-bit result. */
3866 res
= (((long long) ea
) * ((long long) rd
)) >> 32;
3868 n
= res
& 0x80000000;
3869 nz
= res
& 0xffffffff;
3870 if (store (sd
, &code
->dst
, res
))
3874 case O (O_MULU
, SW
): /* mulu.w */
3875 if (fetch (sd
, &code
->src
, &ea
) ||
3876 fetch (sd
, &code
->dst
, &rd
))
3879 res
= UEXTSHORT ((UEXTSHORT (ea
) * UEXTSHORT (rd
)));
3881 /* Don't set Z or N. */
3882 if (store (sd
, &code
->dst
, res
))
3887 case O (O_MULU
, SL
): /* mulu.l */
3888 if (fetch (sd
, &code
->src
, &ea
) ||
3889 fetch (sd
, &code
->dst
, &rd
))
3894 /* Don't set Z or N. */
3895 if (store (sd
, &code
->dst
, res
))
3900 case O (O_MULUU
, SL
): /* mulu/u.l */
3901 if (fetch (sd
, &code
->src
, &ea
) ||
3902 fetch (sd
, &code
->dst
, &rd
))
3905 /* Compute upper 32 bits of the 64-bit result. */
3906 res
= (((unsigned long long) (unsigned) ea
) *
3907 ((unsigned long long) (unsigned) rd
)) >> 32;
3909 /* Don't set Z or N. */
3910 if (store (sd
, &code
->dst
, res
))
3915 case O (O_MULXS
, SB
): /* mulxs.b */
3916 if (fetch (sd
, &code
->src
, &ea
) ||
3917 fetch (sd
, &code
->dst
, &rd
))
3921 res
= ea
* SEXTCHAR (rd
);
3925 if (store (sd
, &code
->dst
, res
))
3930 case O (O_MULXS
, SW
): /* mulxs.w */
3931 if (fetch (sd
, &code
->src
, &ea
) ||
3932 fetch (sd
, &code
->dst
, &rd
))
3935 ea
= SEXTSHORT (ea
);
3936 res
= ea
* SEXTSHORT (rd
& 0xffff);
3938 n
= res
& 0x80000000;
3939 nz
= res
& 0xffffffff;
3940 if (store (sd
, &code
->dst
, res
))
3945 case O (O_MULXU
, SB
): /* mulxu.b */
3946 if (fetch (sd
, &code
->src
, &ea
) ||
3947 fetch (sd
, &code
->dst
, &rd
))
3950 res
= UEXTCHAR (ea
) * UEXTCHAR (rd
);
3952 if (store (sd
, &code
->dst
, res
))
3957 case O (O_MULXU
, SW
): /* mulxu.w */
3958 if (fetch (sd
, &code
->src
, &ea
) ||
3959 fetch (sd
, &code
->dst
, &rd
))
3962 res
= UEXTSHORT (ea
) * UEXTSHORT (rd
);
3964 if (store (sd
, &code
->dst
, res
))
3969 case O (O_TAS
, SB
): /* tas (test and set) */
3970 if (!h8300sxmode
) /* h8sx can use any register. */
3971 switch (code
->src
.reg
)
3982 if (fetch (sd
, &code
->src
, &res
))
3984 if (store (sd
, &code
->src
, res
| 0x80))
3987 goto just_flags_log8
;
3989 case O (O_DIVU
, SW
): /* divu.w */
3990 if (fetch (sd
, &code
->src
, &ea
) ||
3991 fetch (sd
, &code
->dst
, &rd
))
3997 res
= (unsigned) (UEXTSHORT (rd
) / UEXTSHORT (ea
));
4001 if (store (sd
, &code
->dst
, res
))
4005 case O (O_DIVU
, SL
): /* divu.l */
4006 if (fetch (sd
, &code
->src
, &ea
) ||
4007 fetch (sd
, &code
->dst
, &rd
))
4010 n
= ea
& 0x80000000;
4011 nz
= ea
& 0xffffffff;
4013 res
= (unsigned) rd
/ ea
;
4017 if (store (sd
, &code
->dst
, res
))
4021 case O (O_DIVS
, SW
): /* divs.w */
4022 if (fetch (sd
, &code
->src
, &ea
) ||
4023 fetch (sd
, &code
->dst
, &rd
))
4028 res
= SEXTSHORT (rd
) / SEXTSHORT (ea
);
4038 if (store (sd
, &code
->dst
, res
))
4042 case O (O_DIVS
, SL
): /* divs.l */
4043 if (fetch (sd
, &code
->src
, &ea
) ||
4044 fetch (sd
, &code
->dst
, &rd
))
4058 n
= res
& 0x80000000;
4059 if (store (sd
, &code
->dst
, res
))
4063 case O (O_DIVXU
, SB
): /* divxu.b */
4064 if (fetch (sd
, &code
->src
, &ea
) ||
4065 fetch (sd
, &code
->dst
, &rd
))
4068 rd
= UEXTSHORT (rd
);
4075 tmp
= (unsigned) rd
% ea
;
4076 res
= (unsigned) rd
/ ea
;
4084 if (store (sd
, &code
->dst
, (res
& 0xff) | (tmp
<< 8)))
4088 case O (O_DIVXU
, SW
): /* divxu.w */
4089 if (fetch (sd
, &code
->src
, &ea
) ||
4090 fetch (sd
, &code
->dst
, &rd
))
4093 ea
= UEXTSHORT (ea
);
4099 tmp
= (unsigned) rd
% ea
;
4100 res
= (unsigned) rd
/ ea
;
4108 if (store (sd
, &code
->dst
, (res
& 0xffff) | (tmp
<< 16)))
4112 case O (O_DIVXS
, SB
): /* divxs.b */
4113 if (fetch (sd
, &code
->src
, &ea
) ||
4114 fetch (sd
, &code
->dst
, &rd
))
4117 rd
= SEXTSHORT (rd
);
4122 tmp
= (int) rd
% (int) ea
;
4123 res
= (int) rd
/ (int) ea
;
4134 if (store (sd
, &code
->dst
, (res
& 0xff) | (tmp
<< 8)))
4138 case O (O_DIVXS
, SW
): /* divxs.w */
4139 if (fetch (sd
, &code
->src
, &ea
) ||
4140 fetch (sd
, &code
->dst
, &rd
))
4143 ea
= SEXTSHORT (ea
);
4147 tmp
= (int) rd
% (int) ea
;
4148 res
= (int) rd
/ (int) ea
;
4158 n
= res
& 0x80000000;
4159 if (store (sd
, &code
->dst
, (res
& 0xffff) | (tmp
<< 16)))
4163 case O (O_EXTS
, SW
): /* exts.w, signed extend */
4164 if (fetch2 (sd
, &code
->dst
, &rd
))
4166 ea
= rd
& 0x80 ? -256 : 0;
4167 res
= (rd
& 0xff) + ea
;
4170 case O (O_EXTS
, SL
): /* exts.l, signed extend */
4171 if (fetch2 (sd
, &code
->dst
, &rd
))
4173 if (code
->src
.type
== X (OP_IMM
, SL
))
4175 if (fetch (sd
, &code
->src
, &ea
))
4178 if (ea
== 2) /* exts.l #2, nn */
4180 /* Sign-extend from 8-bit to 32-bit. */
4181 ea
= rd
& 0x80 ? -256 : 0;
4182 res
= (rd
& 0xff) + ea
;
4186 /* Sign-extend from 16-bit to 32-bit. */
4187 ea
= rd
& 0x8000 ? -65536 : 0;
4188 res
= (rd
& 0xffff) + ea
;
4191 case O (O_EXTU
, SW
): /* extu.w, unsigned extend */
4192 if (fetch2 (sd
, &code
->dst
, &rd
))
4195 res
= (rd
& 0xff) + ea
;
4198 case O (O_EXTU
, SL
): /* extu.l, unsigned extend */
4199 if (fetch2 (sd
, &code
->dst
, &rd
))
4201 if (code
->src
.type
== X (OP_IMM
, SL
))
4203 if (fetch (sd
, &code
->src
, &ea
))
4206 if (ea
== 2) /* extu.l #2, nn */
4208 /* Zero-extend from 8-bit to 32-bit. */
4210 res
= (rd
& 0xff) + ea
;
4214 /* Zero-extend from 16-bit to 32-bit. */
4216 res
= (rd
& 0xffff) + ea
;
4219 case O (O_NOP
, SN
): /* nop */
4222 case O (O_STM
, SL
): /* stm, store to memory */
4224 int nregs
, firstreg
, i
;
4226 nregs
= GET_MEMORY_B (pc
+ 1);
4229 firstreg
= code
->src
.reg
;
4231 for (i
= firstreg
; i
<= firstreg
+ nregs
; i
++)
4233 h8_set_reg (sd
, SP_REGNUM
, h8_get_reg (sd
, SP_REGNUM
) - 4);
4234 SET_MEMORY_L (h8_get_reg (sd
, SP_REGNUM
), h8_get_reg (sd
, i
));
4239 case O (O_LDM
, SL
): /* ldm, load from memory */
4240 case O (O_RTEL
, SN
): /* rte/l, ldm plus rte */
4241 case O (O_RTSL
, SN
): /* rts/l, ldm plus rts */
4243 int nregs
, firstreg
, i
;
4245 nregs
= ((GET_MEMORY_B (pc
+ 1) >> 4) & 0xf);
4246 firstreg
= code
->dst
.reg
& 0xf;
4247 for (i
= firstreg
; i
>= firstreg
- nregs
; i
--)
4249 h8_set_reg (sd
, i
, GET_MEMORY_L (h8_get_reg (sd
, SP_REGNUM
)));
4250 h8_set_reg (sd
, SP_REGNUM
, h8_get_reg (sd
, SP_REGNUM
) + 4);
4253 switch (code
->opcode
) {
4254 case O (O_RTEL
, SN
):
4256 case O (O_RTSL
, SN
):
4265 /* Decimal Adjust Addition. This is for BCD arithmetic. */
4266 res
= GET_B_REG (code
->src
.reg
); /* FIXME fetch? */
4267 if (!c
&& (0 <= (res
>> 4) && (res
>> 4) <= 9) &&
4268 !h
&& (0 <= (res
& 0xf) && (res
& 0xf) <= 9))
4269 res
= res
; /* Value added == 0. */
4270 else if (!c
&& (0 <= (res
>> 4) && (res
>> 4) <= 8) &&
4271 !h
&& (10 <= (res
& 0xf) && (res
& 0xf) <= 15))
4272 res
= res
+ 0x6; /* Value added == 6. */
4273 else if (!c
&& (0 <= (res
>> 4) && (res
>> 4) <= 9) &&
4274 h
&& (0 <= (res
& 0xf) && (res
& 0xf) <= 3))
4275 res
= res
+ 0x6; /* Value added == 6. */
4276 else if (!c
&& (10 <= (res
>> 4) && (res
>> 4) <= 15) &&
4277 !h
&& (0 <= (res
& 0xf) && (res
& 0xf) <= 9))
4278 res
= res
+ 0x60; /* Value added == 60. */
4279 else if (!c
&& (9 <= (res
>> 4) && (res
>> 4) <= 15) &&
4280 !h
&& (10 <= (res
& 0xf) && (res
& 0xf) <= 15))
4281 res
= res
+ 0x66; /* Value added == 66. */
4282 else if (!c
&& (10 <= (res
>> 4) && (res
>> 4) <= 15) &&
4283 h
&& (0 <= (res
& 0xf) && (res
& 0xf) <= 3))
4284 res
= res
+ 0x66; /* Value added == 66. */
4285 else if ( c
&& (1 <= (res
>> 4) && (res
>> 4) <= 2) &&
4286 !h
&& (0 <= (res
& 0xf) && (res
& 0xf) <= 9))
4287 res
= res
+ 0x60; /* Value added == 60. */
4288 else if ( c
&& (1 <= (res
>> 4) && (res
>> 4) <= 2) &&
4289 !h
&& (10 <= (res
& 0xf) && (res
& 0xf) <= 15))
4290 res
= res
+ 0x66; /* Value added == 66. */
4291 else if (c
&& (1 <= (res
>> 4) && (res
>> 4) <= 3) &&
4292 h
&& (0 <= (res
& 0xf) && (res
& 0xf) <= 3))
4293 res
= res
+ 0x66; /* Value added == 66. */
4298 /* Decimal Adjust Subtraction. This is for BCD arithmetic. */
4299 res
= GET_B_REG (code
->src
.reg
); /* FIXME fetch, fetch2... */
4300 if (!c
&& (0 <= (res
>> 4) && (res
>> 4) <= 9) &&
4301 !h
&& (0 <= (res
& 0xf) && (res
& 0xf) <= 9))
4302 res
= res
; /* Value added == 0. */
4303 else if (!c
&& (0 <= (res
>> 4) && (res
>> 4) <= 8) &&
4304 h
&& (6 <= (res
& 0xf) && (res
& 0xf) <= 15))
4305 res
= res
+ 0xfa; /* Value added == 0xfa. */
4306 else if ( c
&& (7 <= (res
>> 4) && (res
>> 4) <= 15) &&
4307 !h
&& (0 <= (res
& 0xf) && (res
& 0xf) <= 9))
4308 res
= res
+ 0xa0; /* Value added == 0xa0. */
4309 else if (c
&& (6 <= (res
>> 4) && (res
>> 4) <= 15) &&
4310 h
&& (6 <= (res
& 0xf) && (res
& 0xf) <= 15))
4311 res
= res
+ 0x9a; /* Value added == 0x9a. */
4317 sim_engine_halt (sd
, cpu
, NULL
, pc
, sim_stopped
, SIM_SIGILL
);
4322 sim_io_printf (sd
, "sim_resume: internal error.\n");
4323 sim_engine_halt (sd
, cpu
, NULL
, pc
, sim_stopped
, SIM_SIGILL
);
4327 if (code
->dst
.type
== X (OP_CCR
, SB
) ||
4328 code
->dst
.type
== X (OP_CCR
, SW
))
4330 h8_set_ccr (sd
, res
);
4333 else if (h8300smode
&&
4334 (code
->dst
.type
== X (OP_EXR
, SB
) ||
4335 code
->dst
.type
== X (OP_EXR
, SW
)))
4337 h8_set_exr (sd
, res
);
4338 if (h8300smode
) /* Get exr. */
4340 trace
= (h8_get_exr (sd
) >> 7) & 1;
4341 intMask
= h8_get_exr (sd
) & 7;
4350 /* When a branch works */
4351 if (fetch (sd
, &code
->src
, &res
))
4353 if (res
& 1) /* bad address */
4355 pc
= code
->next_pc
+ res
;
4358 /* Set the cond codes from res */
4361 /* Set the flags after an 8 bit inc/dec operation */
4365 v
= (rd
& 0x7f) == 0x7f;
4368 /* Set the flags after an 16 bit inc/dec operation */
4372 v
= (rd
& 0x7fff) == 0x7fff;
4375 /* Set the flags after an 32 bit inc/dec operation */
4377 n
= res
& 0x80000000;
4378 nz
= res
& 0xffffffff;
4379 v
= (rd
& 0x7fffffff) == 0x7fffffff;
4383 /* Set flags after an 8 bit shift op, carry,overflow set in insn */
4386 if (store2 (sd
, &code
->dst
, rd
))
4391 /* Set flags after an 16 bit shift op, carry,overflow set in insn */
4394 if (store2 (sd
, &code
->dst
, rd
))
4399 /* Set flags after an 32 bit shift op, carry,overflow set in insn */
4400 n
= (rd
& 0x80000000);
4401 nz
= rd
& 0xffffffff;
4402 if (store2 (sd
, &code
->dst
, rd
))
4407 if (store2 (sd
, &code
->dst
, res
))
4411 /* flags after a 32bit logical operation */
4412 n
= res
& 0x80000000;
4413 nz
= res
& 0xffffffff;
4418 if (store2 (sd
, &code
->dst
, res
))
4422 /* flags after a 16bit logical operation */
4429 if (store2 (sd
, &code
->dst
, res
))
4439 if (store2 (sd
, &code
->dst
, res
))
4446 switch (code
->opcode
/ 4)
4450 v
= ((rd
& 0x80) == (ea
& 0x80)
4451 && (rd
& 0x80) != (res
& 0x80));
4456 v
= ((rd
& 0x80) != (-ea
& 0x80)
4457 && (rd
& 0x80) != (res
& 0x80));
4464 break; /* No effect on v flag. */
4469 if (store2 (sd
, &code
->dst
, res
))
4475 c
= (res
& 0x10000);
4476 switch (code
->opcode
/ 4)
4480 v
= ((rd
& 0x8000) == (ea
& 0x8000)
4481 && (rd
& 0x8000) != (res
& 0x8000));
4486 v
= ((rd
& 0x8000) != (-ea
& 0x8000)
4487 && (rd
& 0x8000) != (res
& 0x8000));
4496 if (store2 (sd
, &code
->dst
, res
))
4500 n
= res
& 0x80000000;
4501 nz
= res
& 0xffffffff;
4502 switch (code
->opcode
/ 4)
4506 v
= ((rd
& 0x80000000) == (ea
& 0x80000000)
4507 && (rd
& 0x80000000) != (res
& 0x80000000));
4508 c
= ((unsigned) res
< (unsigned) rd
) ||
4509 ((unsigned) res
< (unsigned) ea
);
4514 v
= ((rd
& 0x80000000) != (-ea
& 0x80000000)
4515 && (rd
& 0x80000000) != (res
& 0x80000000));
4516 c
= (unsigned) rd
< (unsigned) -ea
;
4519 v
= (rd
== 0x80000000);
4526 if ((res
= h8_get_delayed_branch (sd
)) != 0)
4529 h8_set_delayed_branch (sd
, 0);
4537 h8_set_ticks (sd
, h8_get_ticks (sd
) + get_now () - tick_start
);
4538 h8_set_cycles (sd
, h8_get_cycles (sd
) + cycles
);
4539 h8_set_insts (sd
, h8_get_insts (sd
) + insts
);
4544 h8_set_exr (sd
, (trace
<<7) | intMask
);
4546 h8_set_mask (sd
, oldmask
);
4550 sim_engine_run (SIM_DESC sd
,
4551 int next_cpu_nr
, /* ignore */
4552 int nr_cpus
, /* ignore */
4557 SIM_ASSERT (STATE_MAGIC (sd
) == SIM_MAGIC_NUMBER
);
4559 cpu
= STATE_CPU (sd
, 0);
4563 step_once (sd
, cpu
);
4564 if (sim_events_tick (sd
))
4565 sim_events_process (sd
);
4570 sim_write (SIM_DESC sd
, SIM_ADDR addr
, const unsigned char *buffer
, int size
)
4577 for (i
= 0; i
< size
; i
++)
4579 if (addr
< memory_size
)
4581 h8_set_memory (sd
, addr
+ i
, buffer
[i
]);
4582 h8_set_cache_idx (sd
, addr
+ i
, 0);
4586 h8_set_eightbit (sd
, (addr
+ i
) & 0xff, buffer
[i
]);
4593 sim_read (SIM_DESC sd
, SIM_ADDR addr
, unsigned char *buffer
, int size
)
4598 if (addr
< memory_size
)
4599 memcpy (buffer
, h8_get_memory_buf (sd
) + addr
, size
);
4601 memcpy (buffer
, h8_get_eightbit_buf (sd
) + (addr
& 0xff), size
);
4606 h8300_reg_store (SIM_CPU
*cpu
, int rn
, unsigned char *value
, int length
)
4611 longval
= (value
[0] << 24) | (value
[1] << 16) | (value
[2] << 8) | value
[3];
4612 shortval
= (value
[0] << 8) | (value
[1]);
4613 intval
= h8300hmode
? longval
: shortval
;
4615 init_pointers (CPU_STATE (cpu
));
4619 if(h8300_normal_mode
)
4620 cpu
->pc
= shortval
; /* PC for Normal mode is 2 bytes */
4640 cpu
->regs
[rn
] = intval
;
4645 cpu
->regs
[rn
] = longval
;
4652 h8300_reg_fetch (SIM_CPU
*cpu
, int rn
, unsigned char *buf
, int length
)
4657 init_pointers (CPU_STATE (cpu
));
4659 if (!h8300smode
&& rn
>= EXR_REGNUM
)
4694 /* In Normal mode PC is 2 byte, but other registers are 4 byte */
4695 if ((h8300hmode
|| longreg
) && !(rn
== PC_REGNUM
&& h8300_normal_mode
))
4712 set_simcache_size (SIM_DESC sd
, int n
)
4715 free (sd
->sim_cache
);
4718 sd
->sim_cache
= (decoded_inst
*) malloc (sizeof (decoded_inst
) * n
);
4719 memset (sd
->sim_cache
, 0, sizeof (decoded_inst
) * n
);
4720 sd
->sim_cache_size
= n
;
4725 sim_info (SIM_DESC sd
, int verbose
)
4727 double timetaken
= (double) h8_get_ticks (sd
) / (double) now_persec ();
4728 double virttime
= h8_get_cycles (sd
) / 10.0e6
;
4730 sim_io_printf (sd
, "\n\n#instructions executed %10d\n", h8_get_insts (sd
));
4731 sim_io_printf (sd
, "#cycles (v approximate) %10d\n", h8_get_cycles (sd
));
4732 sim_io_printf (sd
, "#real time taken %10.4f\n", timetaken
);
4733 sim_io_printf (sd
, "#virtual time taken %10.4f\n", virttime
);
4734 if (timetaken
!= 0.0)
4735 sim_io_printf (sd
, "#simulation ratio %10.4f\n", virttime
/ timetaken
);
4736 sim_io_printf (sd
, "#compiles %10d\n", h8_get_compiles (sd
));
4737 sim_io_printf (sd
, "#cache size %10d\n", sd
->sim_cache_size
);
4740 /* This to be conditional on `what' (aka `verbose'),
4741 however it was never passed as non-zero. */
4745 for (i
= 0; i
< O_LAST
; i
++)
4747 if (h8_get_stats (sd
, i
))
4748 sim_io_printf (sd
, "%d: %d\n", i
, h8_get_stats (sd
, i
));
4754 /* Indicate whether the cpu is an H8/300 or H8/300H.
4755 FLAG is non-zero for the H8/300H. */
4758 set_h8300h (unsigned long machine
)
4760 /* FIXME: Much of the code in sim_load can be moved to sim_open.
4761 This function being replaced by a sim_open:ARGV configuration
4764 h8300hmode
= h8300smode
= h8300sxmode
= h8300_normal_mode
= 0;
4766 if (machine
== bfd_mach_h8300sx
|| machine
== bfd_mach_h8300sxn
)
4769 if (machine
== bfd_mach_h8300s
|| machine
== bfd_mach_h8300sn
|| h8300sxmode
)
4772 if (machine
== bfd_mach_h8300h
|| machine
== bfd_mach_h8300hn
|| h8300smode
)
4775 if(machine
== bfd_mach_h8300hn
|| machine
== bfd_mach_h8300sn
|| machine
== bfd_mach_h8300sxn
)
4776 h8300_normal_mode
= 1;
4779 /* H8300-specific options.
4780 TODO: These really should be merged into the common model modules. */
4788 h8300_option_handler (SIM_DESC sd
, sim_cpu
*cpu ATTRIBUTE_UNUSED
, int opt
,
4789 char *arg
, int is_command ATTRIBUTE_UNUSED
)
4791 switch ((H8300_OPTIONS
) opt
)
4794 set_h8300h (bfd_mach_h8300h
);
4797 set_h8300h (bfd_mach_h8300s
);
4799 case OPTION_H8300SX
:
4800 set_h8300h (bfd_mach_h8300sx
);
4804 /* We'll actually never get here; the caller handles the error
4806 sim_io_eprintf (sd
, "Unknown option `%s'\n", arg
);
4813 static const OPTION h8300_options
[] =
4815 { {"h8300h", no_argument
, NULL
, OPTION_H8300H
},
4816 'h', NULL
, "Indicate the CPU is H8/300H",
4817 h8300_option_handler
},
4818 { {"h8300s", no_argument
, NULL
, OPTION_H8300S
},
4819 'S', NULL
, "Indicate the CPU is H8S",
4820 h8300_option_handler
},
4821 { {"h8300sx", no_argument
, NULL
, OPTION_H8300SX
},
4822 'x', NULL
, "Indicate the CPU is H8SX",
4823 h8300_option_handler
},
4824 { {NULL
, no_argument
, NULL
, 0}, '\0', NULL
, NULL
, NULL
, NULL
}
4828 h8300_pc_get (sim_cpu
*cpu
)
4834 h8300_pc_set (sim_cpu
*cpu
, sim_cia pc
)
4839 /* Cover function of sim_state_free to free the cpu buffers as well. */
4842 free_state (SIM_DESC sd
)
4844 if (STATE_MODULES (sd
) != NULL
)
4845 sim_module_uninstall (sd
);
4847 /* Fixme: free buffers in _sim_cpu. */
4848 sim_state_free (sd
);
4852 sim_open (SIM_OPEN_KIND kind
,
4853 struct host_callback_struct
*callback
,
4861 sd
= sim_state_alloc (kind
, callback
);
4863 /* The cpu data is kept in a separately allocated chunk of memory. */
4864 if (sim_cpu_alloc_all (sd
, 1, /*cgen_cpu_max_extra_bytes ()*/0) != SIM_RC_OK
)
4870 cpu
= STATE_CPU (sd
, 0);
4871 SIM_ASSERT (STATE_MAGIC (sd
) == SIM_MAGIC_NUMBER
);
4872 sim_state_initialize (sd
, cpu
);
4873 /* sim_cpu object is new, so some initialization is needed. */
4874 init_pointers_needed
= 1;
4876 if (sim_pre_argv_init (sd
, argv
[0]) != SIM_RC_OK
)
4882 if (sim_add_option_table (sd
, NULL
, h8300_options
) != SIM_RC_OK
)
4888 /* getopt will print the error message so we just have to exit if
4889 this fails. FIXME: Hmmm... in the case of gdb we need getopt
4890 to call print_filtered. */
4891 if (sim_parse_args (sd
, argv
) != SIM_RC_OK
)
4893 /* Uninstall the modules to avoid memory leaks,
4894 file descriptor leaks, etc. */
4899 /* Check for/establish the a reference program image. */
4900 if (sim_analyze_program (sd
,
4901 (STATE_PROG_ARGV (sd
) != NULL
4902 ? *STATE_PROG_ARGV (sd
)
4903 : NULL
), abfd
) != SIM_RC_OK
)
4909 /* Establish any remaining configuration options. */
4910 if (sim_config (sd
) != SIM_RC_OK
)
4916 if (sim_post_argv_init (sd
) != SIM_RC_OK
)
4918 /* Uninstall the modules to avoid memory leaks,
4919 file descriptor leaks, etc. */
4924 /* CPU specific initialization. */
4925 for (i
= 0; i
< MAX_NR_PROCESSORS
; ++i
)
4927 SIM_CPU
*cpu
= STATE_CPU (sd
, i
);
4929 CPU_REG_FETCH (cpu
) = h8300_reg_fetch
;
4930 CPU_REG_STORE (cpu
) = h8300_reg_store
;
4931 CPU_PC_FETCH (cpu
) = h8300_pc_get
;
4932 CPU_PC_STORE (cpu
) = h8300_pc_set
;
4935 /* sim_hw_configure (sd); */
4937 /* FIXME: Much of the code in sim_load can be moved here. */
4942 /* Called by gdb to load a program into memory. */
4945 sim_load (SIM_DESC sd
, const char *prog
, bfd
*abfd
, int from_tty
)
4949 /* FIXME: The code below that sets a specific variant of the H8/300
4950 being simulated should be moved to sim_open(). */
4952 /* See if the file is for the H8/300 or H8/300H. */
4953 /* ??? This may not be the most efficient way. The z8k simulator
4954 does this via a different mechanism (INIT_EXTRA_SYMTAB_INFO). */
4958 prog_bfd
= bfd_openr (prog
, NULL
);
4959 if (prog_bfd
!= NULL
)
4961 /* Set the cpu type. We ignore failure from bfd_check_format
4962 and bfd_openr as sim_load_file checks too. */
4963 if (bfd_check_format (prog_bfd
, bfd_object
))
4965 set_h8300h (bfd_get_mach (prog_bfd
));
4969 /* If we're using gdb attached to the simulator, then we have to
4970 reallocate memory for the simulator.
4972 When gdb first starts, it calls fetch_registers (among other
4973 functions), which in turn calls init_pointers, which allocates
4976 The problem is when we do that, we don't know whether we're
4977 debugging an H8/300 or H8/300H program.
4979 This is the first point at which we can make that determination,
4980 so we just reallocate memory now; this will also allow us to handle
4981 switching between H8/300 and H8/300H programs without exiting
4984 if (h8300smode
&& !h8300_normal_mode
)
4985 memory_size
= H8300S_MSIZE
;
4986 else if (h8300hmode
&& !h8300_normal_mode
)
4987 memory_size
= H8300H_MSIZE
;
4989 memory_size
= H8300_MSIZE
;
4991 if (h8_get_memory_buf (sd
))
4992 free (h8_get_memory_buf (sd
));
4993 if (h8_get_cache_idx_buf (sd
))
4994 free (h8_get_cache_idx_buf (sd
));
4995 if (h8_get_eightbit_buf (sd
))
4996 free (h8_get_eightbit_buf (sd
));
4998 h8_set_memory_buf (sd
, (unsigned char *)
4999 calloc (sizeof (char), memory_size
));
5000 h8_set_cache_idx_buf (sd
, (unsigned short *)
5001 calloc (sizeof (short), memory_size
));
5002 sd
->memory_size
= memory_size
;
5003 h8_set_eightbit_buf (sd
, (unsigned char *) calloc (sizeof (char), 256));
5005 /* `msize' must be a power of two. */
5006 if ((memory_size
& (memory_size
- 1)) != 0)
5008 sim_io_printf (sd
, "sim_load: bad memory size.\n");
5011 h8_set_mask (sd
, memory_size
- 1);
5013 if (sim_load_file (sd
, STATE_MY_NAME (sd
), STATE_CALLBACK (sd
), prog
,
5014 prog_bfd
, STATE_OPEN_KIND (sd
) == SIM_OPEN_DEBUG
,
5018 /* Close the bfd if we opened it. */
5019 if (abfd
== NULL
&& prog_bfd
!= NULL
)
5020 bfd_close (prog_bfd
);
5024 /* Close the bfd if we opened it. */
5025 if (abfd
== NULL
&& prog_bfd
!= NULL
)
5026 bfd_close (prog_bfd
);
5031 sim_create_inferior (SIM_DESC sd
, struct bfd
*abfd
, char **argv
, char **env
)
5038 h8_set_pc (sd
, bfd_get_start_address (abfd
));
5042 /* Command Line support. */
5045 /* Counting the no. of commandline arguments. */
5046 for (no_of_args
= 0; argv
[no_of_args
] != NULL
; no_of_args
++)
5049 /* Allocating memory for the argv pointers. */
5050 h8_set_command_line (sd
, (char **) malloc ((sizeof (char *))
5051 * (no_of_args
+ 1)));
5053 for (i
= 0; i
< no_of_args
; i
++)
5055 /* Copying the argument string. */
5056 h8_set_cmdline_arg (sd
, i
, (char *) strdup (argv
[i
]));
5058 h8_set_cmdline_arg (sd
, i
, NULL
);