sim/igen/igen.h

   1 /* The IGEN simulator generator for GDB, the GNU Debugger.
   2
   3    Copyright 2002, 2007, 2008, 2009, 2010 Free Software Foundation, Inc.
   4
   5    Contributed by Andrew Cagney.
   6
   7    This file is part of GDB.
   8
   9    This program is free software; you can redistribute it and/or modify
  10    it under the terms of the GNU General Public License as published by
  11    the Free Software Foundation; either version 3 of the License, or
  12    (at your option) any later version.
  13
  14    This program is distributed in the hope that it will be useful,
  15    but WITHOUT ANY WARRANTY; without even the implied warranty of
  16    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17    GNU General Public License for more details.
  18
  19    You should have received a copy of the GNU General Public License
  20    along with this program.  If not, see <http://www.gnu.org/licenses/>.  */
  21
  22
  23 /* code-generation options: */
  24
  25 typedef enum
  26 {
  27
  28   /* Transfer control to an instructions semantic code using the the
  29      standard call/return mechanism */
  30
  31   generate_calls,
  32
  33   /* Transfer control to an instructions semantic code using
  34      (computed) goto's instead of the more conventional call/return
  35      mechanism */
  36
  37   generate_jumps,
  38
  39 }
  40 igen_code;
  41
  42 typedef enum
  43 {
  44   nia_is_cia_plus_one,
  45   nia_is_void,
  46   nia_is_invalid,
  47 }
  48 igen_nia;
  49
  50
  51
  52 typedef struct _igen_gen_options igen_gen_options;
  53 struct _igen_gen_options
  54 {
  55   int direct_access;
  56   int semantic_icache;
  57   int insn_in_icache;
  58   int conditional_issue;
  59   int slot_verification;
  60   int delayed_branch;
  61
  62   /* If zeroing a register, which one? */
  63   int zero_reg;
  64   int zero_reg_nr;
  65
  66   /* should multiple simulators be generated? */
  67   int multi_sim;
  68
  69   /* name of the default multi-sim model */
  70   char *default_model;
  71
  72   /* should the simulator support multi word instructions and if so,
  73      what is the max nr of words. */
  74   int multi_word;
  75
  76   /* SMP?  Should the generated code include SMP support (>0) and if
  77      so, for how many processors? */
  78   int smp;
  79
  80   /* how should the next instruction address be computed? */
  81   igen_nia nia;
  82
  83   /* nr of instructions in the decoded instruction cache */
  84   int icache;
  85   int icache_size;
  86
  87   /* see above */
  88   igen_code code;
  89 };
  90
  91
  92 typedef struct _igen_trace_options igen_trace_options;
  93 struct _igen_trace_options
  94 {
  95   int rule_selection;
  96   int rule_rejection;
  97   int insn_insertion;
  98   int insn_expansion;
  99   int entries;
 100   int combine;
 101 };
 102
 103 typedef struct _igen_name
 104 {
 105   char *u;
 106   char *l;
 107 }
 108 igen_name;
 109 typedef struct _igen_module
 110 {
 111   igen_name prefix;
 112   igen_name suffix;
 113 }
 114 igen_module;
 115
 116 typedef struct _igen_module_options
 117 {
 118   igen_module global;
 119   igen_module engine;
 120   igen_module icache;
 121   igen_module idecode;
 122   igen_module itable;
 123   igen_module semantics;
 124   igen_module support;
 125 }
 126 igen_module_options;
 127
 128 typedef struct _igen_decode_options igen_decode_options;
 129 struct _igen_decode_options
 130 {
 131
 132   /* Combine tables?  Should the generator make a second pass through
 133      each generated table looking for any sub-entries that contain the
 134      same instructions.  Those entries being merged into a single
 135      table */
 136   int combine;
 137
 138   /* Instruction expansion? Should the semantic code for each
 139      instruction, when the oportunity arrises, be expanded according
 140      to the variable opcode files that the instruction decode process
 141      renders constant */
 142   int duplicate;
 143
 144   /* Treat reserved fields as constant (zero) instead of ignoring
 145      their value when determining decode tables */
 146   int zero_reserved;
 147
 148   /* Convert any padded switch rules into goto_switch */
 149   int switch_as_goto;
 150
 151   /* Force all tables to be generated with this lookup mechanism */
 152   char *overriding_gen;
 153 };
 154
 155
 156 typedef struct _igen_warn_options igen_warn_options;
 157 struct _igen_warn_options
 158 {
 159
 160   /* Issue warning about discarded instructions */
 161   int discard;
 162
 163   /* Issue warning about invalid instruction widths */
 164   int width;
 165
 166   /* Issue warning about unimplemented instructions */
 167   int unimplemented;
 168
 169 };
 170
 171
 172
 173 typedef struct _igen_options igen_options;
 174 struct _igen_options
 175 {
 176
 177   /* What does the instruction look like - bit ordering, size, widths or
 178      offesets */
 179   int hi_bit_nr;
 180   int insn_bit_size;
 181   int insn_specifying_widths;
 182
 183   /* what should global names be prefixed with? */
 184   igen_module_options module;
 185
 186   /* See above for options and flags */
 187   igen_gen_options gen;
 188
 189   /* See above for trace options */
 190   igen_trace_options trace;
 191
 192   /* See above for include options */
 193   table_include *include;
 194
 195   /* See above for decode options */
 196   igen_decode_options decode;
 197
 198   /* Filter set to be used on the flag field of the instruction table */
 199   filter *flags_filter;
 200
 201   /* See above for warn options */
 202   igen_warn_options warn;
 203
 204   /* Be more picky about the input */
 205   error_func (*warning);
 206
 207   /* Model (processor) set - like flags_filter. Used to select the
 208      specific ISA within a processor family. */
 209   filter *model_filter;
 210
 211   /* Format name set */
 212   filter *format_name_filter;
 213 };
 214
 215 extern igen_options options;
 216
 217 /* default options - hopefully backward compatible */
 218 #define INIT_OPTIONS() \
 219 do { \
 220   memset (&options, 0, sizeof options); \
 221   memset (&options.warn, -1, sizeof (options.warn)); \
 222   options.hi_bit_nr = 0; \
 223   options.insn_bit_size = default_insn_bit_size; \
 224   options.insn_specifying_widths = 0; \
 225   options.module.global.prefix.u = ""; \
 226   options.module.global.prefix.l = ""; \
 227   /* the prefixes */ \
 228   options.module.engine = options.module.global; \
 229   options.module.icache = options.module.global; \
 230   options.module.idecode = options.module.global; \
 231   options.module.itable = options.module.global; \
 232   options.module.semantics = options.module.global; \
 233   options.module.support = options.module.global; \
 234   /* the suffixes */ \
 235   options.module.engine.suffix.l = "engine"; \
 236   options.module.engine.suffix.u = "ENGINE"; \
 237   options.module.icache.suffix.l = "icache"; \
 238   options.module.icache.suffix.u = "ICACHE"; \
 239   options.module.idecode.suffix.l = "idecode"; \
 240   options.module.idecode.suffix.u = "IDECODE"; \
 241   options.module.itable.suffix.l = "itable"; \
 242   options.module.itable.suffix.u = "ITABLE"; \
 243   options.module.semantics.suffix.l = "semantics"; \
 244   options.module.semantics.suffix.u = "SEMANTICS"; \
 245   options.module.support.suffix.l = "support"; \
 246   options.module.support.suffix.u = "SUPPORT"; \
 247   /* misc stuff */ \
 248   options.gen.code = generate_calls; \
 249   options.gen.icache_size = 1024; \
 250   options.warning = warning; \
 251 } while (0)