sim/lm32/cpu.h

   1 /* CPU family header for lm32bf.
   2
   3 THIS FILE IS MACHINE GENERATED WITH CGEN.
   4
   5 Copyright 1996-2014 Free Software Foundation, Inc.
   6
   7 This file is part of the GNU simulators.
   8
   9    This file is free software; you can redistribute it and/or modify
  10    it under the terms of the GNU General Public License as published by
  11    the Free Software Foundation; either version 3, or (at your option)
  12    any later version.
  13
  14    It is distributed in the hope that it will be useful, but WITHOUT
  15    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  16    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  17    License for more details.
  18
  19    You should have received a copy of the GNU General Public License along
  20    with this program; if not, see <http://www.gnu.org/licenses/>.
  21
  22 */
  23
  24 #ifndef CPU_LM32BF_H
  25 #define CPU_LM32BF_H
  26
  27 /* Maximum number of instructions that are fetched at a time.
  28    This is for LIW type instructions sets (e.g. m32r).  */
  29 #define MAX_LIW_INSNS 1
  30
  31 /* Maximum number of instructions that can be executed in parallel.  */
  32 #define MAX_PARALLEL_INSNS 1
  33
  34 /* The size of an "int" needed to hold an instruction word.
  35    This is usually 32 bits, but some architectures needs 64 bits.  */
  36 typedef CGEN_INSN_INT CGEN_INSN_WORD;
  37
  38 #include "cgen-engine.h"
  39
  40 /* CPU state information.  */
  41 typedef struct {
  42   /* Hardware elements.  */
  43   struct {
  44   /* Program counter */
  45   USI h_pc;
  46 #define GET_H_PC() CPU (h_pc)
  47 #define SET_H_PC(x) (CPU (h_pc) = (x))
  48   /* General purpose registers */
  49   SI h_gr[32];
  50 #define GET_H_GR(a1) CPU (h_gr)[a1]
  51 #define SET_H_GR(a1, x) (CPU (h_gr)[a1] = (x))
  52   /* Control and status registers */
  53   SI h_csr[32];
  54 #define GET_H_CSR(a1) CPU (h_csr)[a1]
  55 #define SET_H_CSR(a1, x) (CPU (h_csr)[a1] = (x))
  56   } hardware;
  57 #define CPU_CGEN_HW(cpu) (& (cpu)->cpu_data.hardware)
  58 } LM32BF_CPU_DATA;
  59
  60 /* Cover fns for register access.  */
  61 USI lm32bf_h_pc_get (SIM_CPU *);
  62 void lm32bf_h_pc_set (SIM_CPU *, USI);
  63 SI lm32bf_h_gr_get (SIM_CPU *, UINT);
  64 void lm32bf_h_gr_set (SIM_CPU *, UINT, SI);
  65 SI lm32bf_h_csr_get (SIM_CPU *, UINT);
  66 void lm32bf_h_csr_set (SIM_CPU *, UINT, SI);
  67
  68 /* These must be hand-written.  */
  69 extern CPUREG_FETCH_FN lm32bf_fetch_register;
  70 extern CPUREG_STORE_FN lm32bf_store_register;
  71
  72 typedef struct {
  73   int empty;
  74 } MODEL_LM32_DATA;
  75
  76 /* Instruction argument buffer.  */
  77
  78 union sem_fields {
  79   struct { /* no operands */
  80     int empty;
  81   } sfmt_empty;
  82   struct { /*  */
  83     IADDR i_call;
  84   } sfmt_bi;
  85   struct { /*  */
  86     UINT f_csr;
  87     UINT f_r1;
  88   } sfmt_wcsr;
  89   struct { /*  */
  90     UINT f_csr;
  91     UINT f_r2;
  92   } sfmt_rcsr;
  93   struct { /*  */
  94     IADDR i_branch;
  95     UINT f_r0;
  96     UINT f_r1;
  97   } sfmt_be;
  98   struct { /*  */
  99     UINT f_r0;
 100     UINT f_r1;
 101     UINT f_uimm;
 102   } sfmt_andi;
 103   struct { /*  */
 104     INT f_imm;
 105     UINT f_r0;
 106     UINT f_r1;
 107   } sfmt_addi;
 108   struct { /*  */
 109     UINT f_r0;
 110     UINT f_r1;
 111     UINT f_r2;
 112     UINT f_user;
 113   } sfmt_user;
 114 #if WITH_SCACHE_PBB
 115   /* Writeback handler.  */
 116   struct {
 117     /* Pointer to argbuf entry for insn whose results need writing back.  */
 118     const struct argbuf *abuf;
 119   } write;
 120   /* x-before handler */
 121   struct {
 122     /*const SCACHE *insns[MAX_PARALLEL_INSNS];*/
 123     int first_p;
 124   } before;
 125   /* x-after handler */
 126   struct {
 127     int empty;
 128   } after;
 129   /* This entry is used to terminate each pbb.  */
 130   struct {
 131     /* Number of insns in pbb.  */
 132     int insn_count;
 133     /* Next pbb to execute.  */
 134     SCACHE *next;
 135     SCACHE *branch_target;
 136   } chain;
 137 #endif
 138 };
 139
 140 /* The ARGBUF struct.  */
 141 struct argbuf {
 142   /* These are the baseclass definitions.  */
 143   IADDR addr;
 144   const IDESC *idesc;
 145   char trace_p;
 146   char profile_p;
 147   /* ??? Temporary hack for skip insns.  */
 148   char skip_count;
 149   char unused;
 150   /* cpu specific data follows */
 151   union sem semantic;
 152   int written;
 153   union sem_fields fields;
 154 };
 155
 156 /* A cached insn.
 157
 158    ??? SCACHE used to contain more than just argbuf.  We could delete the
 159    type entirely and always just use ARGBUF, but for future concerns and as
 160    a level of abstraction it is left in.  */
 161
 162 struct scache {
 163   struct argbuf argbuf;
 164 };
 165
 166 /* Macros to simplify extraction, reading and semantic code.
 167    These define and assign the local vars that contain the insn's fields.  */
 168
 169 #define EXTRACT_IFMT_EMPTY_VARS \
 170   unsigned int length;
 171 #define EXTRACT_IFMT_EMPTY_CODE \
 172   length = 0; \
 173
 174 #define EXTRACT_IFMT_ADD_VARS \
 175   UINT f_opcode; \
 176   UINT f_r0; \
 177   UINT f_r1; \
 178   UINT f_r2; \
 179   UINT f_resv0; \
 180   unsigned int length;
 181 #define EXTRACT_IFMT_ADD_CODE \
 182   length = 4; \
 183   f_opcode = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \
 184   f_r0 = EXTRACT_LSB0_UINT (insn, 32, 25, 5); \
 185   f_r1 = EXTRACT_LSB0_UINT (insn, 32, 20, 5); \
 186   f_r2 = EXTRACT_LSB0_UINT (insn, 32, 15, 5); \
 187   f_resv0 = EXTRACT_LSB0_UINT (insn, 32, 10, 11); \
 188
 189 #define EXTRACT_IFMT_ADDI_VARS \
 190   UINT f_opcode; \
 191   UINT f_r0; \
 192   UINT f_r1; \
 193   INT f_imm; \
 194   unsigned int length;
 195 #define EXTRACT_IFMT_ADDI_CODE \
 196   length = 4; \
 197   f_opcode = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \
 198   f_r0 = EXTRACT_LSB0_UINT (insn, 32, 25, 5); \
 199   f_r1 = EXTRACT_LSB0_UINT (insn, 32, 20, 5); \
 200   f_imm = EXTRACT_LSB0_SINT (insn, 32, 15, 16); \
 201
 202 #define EXTRACT_IFMT_ANDI_VARS \
 203   UINT f_opcode; \
 204   UINT f_r0; \
 205   UINT f_r1; \
 206   UINT f_uimm; \
 207   unsigned int length;
 208 #define EXTRACT_IFMT_ANDI_CODE \
 209   length = 4; \
 210   f_opcode = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \
 211   f_r0 = EXTRACT_LSB0_UINT (insn, 32, 25, 5); \
 212   f_r1 = EXTRACT_LSB0_UINT (insn, 32, 20, 5); \
 213   f_uimm = EXTRACT_LSB0_UINT (insn, 32, 15, 16); \
 214
 215 #define EXTRACT_IFMT_ANDHII_VARS \
 216   UINT f_opcode; \
 217   UINT f_r0; \
 218   UINT f_r1; \
 219   UINT f_uimm; \
 220   unsigned int length;
 221 #define EXTRACT_IFMT_ANDHII_CODE \
 222   length = 4; \
 223   f_opcode = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \
 224   f_r0 = EXTRACT_LSB0_UINT (insn, 32, 25, 5); \
 225   f_r1 = EXTRACT_LSB0_UINT (insn, 32, 20, 5); \
 226   f_uimm = EXTRACT_LSB0_UINT (insn, 32, 15, 16); \
 227
 228 #define EXTRACT_IFMT_B_VARS \
 229   UINT f_opcode; \
 230   UINT f_r0; \
 231   UINT f_r1; \
 232   UINT f_r2; \
 233   UINT f_resv0; \
 234   unsigned int length;
 235 #define EXTRACT_IFMT_B_CODE \
 236   length = 4; \
 237   f_opcode = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \
 238   f_r0 = EXTRACT_LSB0_UINT (insn, 32, 25, 5); \
 239   f_r1 = EXTRACT_LSB0_UINT (insn, 32, 20, 5); \
 240   f_r2 = EXTRACT_LSB0_UINT (insn, 32, 15, 5); \
 241   f_resv0 = EXTRACT_LSB0_UINT (insn, 32, 10, 11); \
 242
 243 #define EXTRACT_IFMT_BI_VARS \
 244   UINT f_opcode; \
 245   SI f_call; \
 246   unsigned int length;
 247 #define EXTRACT_IFMT_BI_CODE \
 248   length = 4; \
 249   f_opcode = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \
 250   f_call = ((pc) + (((SI) (((EXTRACT_LSB0_SINT (insn, 32, 25, 26)) << (6))) >> (4)))); \
 251
 252 #define EXTRACT_IFMT_BE_VARS \
 253   UINT f_opcode; \
 254   UINT f_r0; \
 255   UINT f_r1; \
 256   SI f_branch; \
 257   unsigned int length;
 258 #define EXTRACT_IFMT_BE_CODE \
 259   length = 4; \
 260   f_opcode = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \
 261   f_r0 = EXTRACT_LSB0_UINT (insn, 32, 25, 5); \
 262   f_r1 = EXTRACT_LSB0_UINT (insn, 32, 20, 5); \
 263   f_branch = ((pc) + (((SI) (((EXTRACT_LSB0_SINT (insn, 32, 15, 16)) << (16))) >> (14)))); \
 264
 265 #define EXTRACT_IFMT_ORI_VARS \
 266   UINT f_opcode; \
 267   UINT f_r0; \
 268   UINT f_r1; \
 269   UINT f_uimm; \
 270   unsigned int length;
 271 #define EXTRACT_IFMT_ORI_CODE \
 272   length = 4; \
 273   f_opcode = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \
 274   f_r0 = EXTRACT_LSB0_UINT (insn, 32, 25, 5); \
 275   f_r1 = EXTRACT_LSB0_UINT (insn, 32, 20, 5); \
 276   f_uimm = EXTRACT_LSB0_UINT (insn, 32, 15, 16); \
 277
 278 #define EXTRACT_IFMT_RCSR_VARS \
 279   UINT f_opcode; \
 280   UINT f_csr; \
 281   UINT f_r1; \
 282   UINT f_r2; \
 283   UINT f_resv0; \
 284   unsigned int length;
 285 #define EXTRACT_IFMT_RCSR_CODE \
 286   length = 4; \
 287   f_opcode = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \
 288   f_csr = EXTRACT_LSB0_UINT (insn, 32, 25, 5); \
 289   f_r1 = EXTRACT_LSB0_UINT (insn, 32, 20, 5); \
 290   f_r2 = EXTRACT_LSB0_UINT (insn, 32, 15, 5); \
 291   f_resv0 = EXTRACT_LSB0_UINT (insn, 32, 10, 11); \
 292
 293 #define EXTRACT_IFMT_SEXTB_VARS \
 294   UINT f_opcode; \
 295   UINT f_r0; \
 296   UINT f_r1; \
 297   UINT f_r2; \
 298   UINT f_resv0; \
 299   unsigned int length;
 300 #define EXTRACT_IFMT_SEXTB_CODE \
 301   length = 4; \
 302   f_opcode = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \
 303   f_r0 = EXTRACT_LSB0_UINT (insn, 32, 25, 5); \
 304   f_r1 = EXTRACT_LSB0_UINT (insn, 32, 20, 5); \
 305   f_r2 = EXTRACT_LSB0_UINT (insn, 32, 15, 5); \
 306   f_resv0 = EXTRACT_LSB0_UINT (insn, 32, 10, 11); \
 307
 308 #define EXTRACT_IFMT_USER_VARS \
 309   UINT f_opcode; \
 310   UINT f_r0; \
 311   UINT f_r1; \
 312   UINT f_r2; \
 313   UINT f_user; \
 314   unsigned int length;
 315 #define EXTRACT_IFMT_USER_CODE \
 316   length = 4; \
 317   f_opcode = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \
 318   f_r0 = EXTRACT_LSB0_UINT (insn, 32, 25, 5); \
 319   f_r1 = EXTRACT_LSB0_UINT (insn, 32, 20, 5); \
 320   f_r2 = EXTRACT_LSB0_UINT (insn, 32, 15, 5); \
 321   f_user = EXTRACT_LSB0_UINT (insn, 32, 10, 11); \
 322
 323 #define EXTRACT_IFMT_WCSR_VARS \
 324   UINT f_opcode; \
 325   UINT f_csr; \
 326   UINT f_r1; \
 327   UINT f_r2; \
 328   UINT f_resv0; \
 329   unsigned int length;
 330 #define EXTRACT_IFMT_WCSR_CODE \
 331   length = 4; \
 332   f_opcode = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \
 333   f_csr = EXTRACT_LSB0_UINT (insn, 32, 25, 5); \
 334   f_r1 = EXTRACT_LSB0_UINT (insn, 32, 20, 5); \
 335   f_r2 = EXTRACT_LSB0_UINT (insn, 32, 15, 5); \
 336   f_resv0 = EXTRACT_LSB0_UINT (insn, 32, 10, 11); \
 337
 338 #define EXTRACT_IFMT_BREAK_VARS \
 339   UINT f_opcode; \
 340   UINT f_exception; \
 341   unsigned int length;
 342 #define EXTRACT_IFMT_BREAK_CODE \
 343   length = 4; \
 344   f_opcode = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \
 345   f_exception = EXTRACT_LSB0_UINT (insn, 32, 25, 26); \
 346
 347 /* Collection of various things for the trace handler to use.  */
 348
 349 typedef struct trace_record {
 350   IADDR pc;
 351   /* FIXME:wip */
 352 } TRACE_RECORD;
 353
 354 #endif /* CPU_LM32BF_H */