sim/m32r/Makefile.in

   1 # Makefile template for Configure for the m32r simulator
   2 # Copyright (C) 1996, 1997, 1998 Free Software Foundation, Inc.
   3 # Contributed by Cygnus Support.
   4 #
   5 # This file is part of GDB, the GNU debugger.
   6 #
   7 # This program is free software; you can redistribute it and/or modify
   8 # it under the terms of the GNU General Public License as published by
   9 # the Free Software Foundation; either version 2 of the License, or
  10 # (at your option) any later version.
  11 #
  12 # This program is distributed in the hope that it will be useful,
  13 # but WITHOUT ANY WARRANTY; without even the implied warranty of
  14 # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15 # GNU General Public License for more details.
  16 #
  17 # You should have received a copy of the GNU General Public License along
  18 # with this program; if not, write to the Free Software Foundation, Inc.,
  19 # 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  20
  21 ## COMMON_PRE_CONFIG_FRAG
  22
  23 M32R_OBJS = m32r.o decode.o extract.o sem.o model.o mloop.o
  24 # start-sanitize-m32rx
  25 M32RX_OBJS = m32rx.o decodex.o modelx.o mloopx.o
  26 # end-sanitize-m32rx
  27
  28 SIM_OBJS = \
  29         $(SIM_NEW_COMMON_OBJS) \
  30         sim-hload.o sim-hrw.o sim-engine.o sim-model.o sim-reason.o \
  31         cgen-utils.o cgen-trace.o cgen-scache.o \
  32         sim-if.o arch.o \
  33         $(M32R_OBJS)
  34
  35 # Extra headers included by sim-main.h.
  36 SIM_EXTRA_DEPS = \
  37         $(srcdir)/../common/cgen-types.h \
  38         $(srcdir)/../common/cgen-sim.h \
  39         $(srcdir)/../common/cgen-trace.h \
  40         arch.h cpuall.h m32r-sim.h
  41
  42 SIM_EXTRA_CFLAGS =
  43
  44 SIM_RUN_OBJS = nrun.o
  45 SIM_EXTRA_CLEAN = m32r-clean
  46
  47 ## COMMON_POST_CONFIG_FRAG
  48
  49 arch = m32r
  50
  51 MAIN_INCLUDE_DEPS = \
  52         sim-main.h \
  53         $(srcdir)/../common/sim-config.h \
  54         $(srcdir)/../common/sim-base.h \
  55         $(srcdir)/../common/sim-basics.h \
  56         $(srcdir)/../common/sim-module.h \
  57         $(srcdir)/../common/sim-trace.h \
  58         $(srcdir)/../common/sim-profile.h \
  59         tconfig.h
  60 INCLUDE_DEPS = $(MAIN_INCLUDE_DEPS) $(SIM_EXTRA_DEPS) cpu-sim.h
  61 OPS_INCLUDE_DEPS = \
  62         $(srcdir)/../common/cgen-mem.h \
  63         $(srcdir)/../common/cgen-ops.h
  64
  65 sim-if.o: sim-if.c $(INCLUDE_DEPS) $(srcdir)/../common/sim-core.h
  66 m32r.o: m32r.c $(INCLUDE_DEPS) $(OPS_INCLUDE_DEPS)
  67
  68 arch.o: arch.c $(INCLUDE_DEPS) cpu-opc.h
  69
  70 # M32R objs
  71
  72 # FIXME: Use of `mono' is wip.
  73 mloop.c: $(srcdir)/../common/genmloop.sh mloop.in Makefile
  74         rm -f mloop.c
  75         $(SHELL) $(srcdir)/../common/genmloop.sh $(SHELL) -mono -scache -fast m32r $(srcdir)/mloop.in | sed -e 's/@cpu@/m32r/' -e 's/@CPU@/M32R/' >mloop.c
  76 mloop.o: mloop.c sem-switch.c $(INCLUDE_DEPS) $(OPS_INCLUDE_DEPS) cpu.h
  77
  78 decode.o: decode.c decode.h $(INCLUDE_DEPS) $(OPS_INCLUDE_DEPS) cpu-opc.h cpu.h
  79 extract.o: extract.c decode.h $(INCLUDE_DEPS) $(OPS_INCLUDE_DEPS) cpu.h
  80 sem.o: sem.c decode.h $(INCLUDE_DEPS) $(OPS_INCLUDE_DEPS) cpu.h
  81 model.o: model.c $(INCLUDE_DEPS) cpu-opc.h cpu.h
  82
  83 # wip
  84 #extr-cache.o: extract.c $(INCLUDE_DEPS) $(OPS_INCLUDE_DEPS)
  85 #       $(CC) -c $(srcdir)/extract.c -o extr-cache.o -DSCACHE_P $(ALL_CFLAGS)
  86 sem-cache.o: sem.c decode.h $(INCLUDE_DEPS) $(OPS_INCLUDE_DEPS) cpu.h
  87         $(CC) -c $(srcdir)/sem.c -o sem-cache.o -DSCACHE_P $(ALL_CFLAGS)
  88
  89 # start-sanitize-m32rx
  90 # M32RX objs
  91
  92 # FIXME: Use of `mono' is wip.
  93 mloopx.c: $(srcdir)/../common/genmloop.sh mloopx.in Makefile
  94         rm -f mloopx.c
  95         $(SHELL) $(srcdir)/../common/genmloop.sh $(SHELL) -mono -no-scache -no-fast -parallel m32r $(srcdir)/mloopx.in | sed -e 's/@cpu@/m32rx/' -e 's/@CPU@/M32RX/' >mloopx.c
  96 mloopx.o: mloopx.c readx.c semx-switch.c $(INCLUDE_DEPS) $(OPS_INCLUDE_DEPS) cpux.h
  97
  98 decodex.o: decodex.c decodex.h $(INCLUDE_DEPS) $(OPS_INCLUDE_DEPS) cpu-opc.h cpux.h
  99 extractx.o: extractx.c decodex.h $(INCLUDE_DEPS) $(OPS_INCLUDE_DEPS) cpux.h
 100 semx.o: semx.c decodex.h $(INCLUDE_DEPS) $(OPS_INCLUDE_DEPS) cpux.h
 101 modelx.o: modelx.c $(INCLUDE_DEPS) cpu-opc.h cpux.h
 102
 103 # wip
 104 #extr-cache.o: extract.c $(INCLUDE_DEPS) $(OPS_INCLUDE_DEPS)
 105 #       $(CC) -c $(srcdir)/extract.c -o extr-cache.o -DSCACHE_P $(ALL_CFLAGS)
 106 semx-cache.o: semx.c decode.h $(INCLUDE_DEPS) $(OPS_INCLUDE_DEPS) cpux.h
 107         $(CC) -c $(srcdir)/semx.c -o semx-cache.o -DSCACHE_P $(ALL_CFLAGS)
 108 # end-sanitize-m32rx
 109
 110 m32r-clean:
 111         rm -f mloop.c stamp-arch stamp-cpu stamp-decode
 112 # start-sanitize-m32rx
 113         rm -f mloopx.c stamp-xcpu stamp-xdecode
 114 # end-sanitize-m32rx
 115         rm -f tmp-*
 116
 117 # start-sanitize-cygnus
 118 # cgen support
 119 # For now, require developers to configure with --enable-maintainer-mode.
 120 # ??? Do we need to use a different option?
 121
 122 stamp-arch: $(CGEN_MAIN_SCM) $(srccgen)/m32r.cpu
 123         $(MAKE) cgen-arch
 124         touch stamp-arch
 125 arch.h arch.c cpuall.h: @MAINT@ stamp-arch
 126         @true
 127
 128 stamp-cpu: $(CGEN_MAIN_SCM) $(CGEN_CPU_SCM) $(srccgen)/m32r.cpu
 129         $(MAKE) cgen-cpu cpu=m32r mach=m32r SUFFIX= FLAGS="with-scache,with-profile fn" EXTRAFILES="$(CGEN_CPU_EXTR) $(CGEN_CPU_SEM) $(CGEN_CPU_SEMSW)"
 130         touch stamp-cpu
 131 cpu.h extract.c sem.c sem-switch.c model.c: @MAINT@ stamp-cpu
 132         @true
 133
 134 stamp-decode: $(CGEN_MAIN_SCM) $(CGEN_DECODE_SCM) $(srccgen)/m32r.cpu
 135         $(MAKE) cgen-decode cpu=m32r mach=m32r SUFFIX= FLAGS="with-scache,with-profile fn"
 136         touch stamp-decode
 137 decode.h decode.c: @MAINT@ stamp-decode
 138         @true
 139 # start-sanitize-cygnus
 140
 141 # start-sanitize-m32rx
 142 stamp-xcpu: $(CGEN_MAIN_SCM) $(CGEN_CPU_SCM) $(srccgen)/m32r.cpu
 143         $(MAKE) cgen-cpu cpu=m32rx mach=m32rx SUFFIX=x FLAGS="" EXTRAFILES="$(CGEN_CPU_READ) $(CGEN_CPU_SEMSW)"
 144         touch stamp-xcpu
 145 cpux.h readx.c semx-switch.c modelx.c: @MAINT@ stamp-xcpu
 146         @true
 147
 148 stamp-xdecode: $(CGEN_MAIN_SCM) $(CGEN_DECODE_SCM) $(srccgen)/m32r.cpu
 149         $(MAKE) cgen-decode cpu=m32rx mach=m32rx SUFFIX=x
 150         touch stamp-xdecode
 151 decodex.h decodex.c: @MAINT@ stamp-xdecode
 152         @true
 153 # end-sanitize-m32rx