sim/m32r/cpu.h

   1 /* CPU family header for m32rbf.
   2
   3 THIS FILE IS MACHINE GENERATED WITH CGEN.
   4
   5 Copyright (C) 1996, 1997, 1998, 1999 Free Software Foundation, Inc.
   6
   7 This file is part of the GNU Simulators.
   8
   9 This program is free software; you can redistribute it and/or modify
  10 it under the terms of the GNU General Public License as published by
  11 the Free Software Foundation; either version 2, or (at your option)
  12 any later version.
  13
  14 This program is distributed in the hope that it will be useful,
  15 but WITHOUT ANY WARRANTY; without even the implied warranty of
  16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17 GNU General Public License for more details.
  18
  19 You should have received a copy of the GNU General Public License along
  20 with this program; if not, write to the Free Software Foundation, Inc.,
  21 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  22
  23 */
  24
  25 #ifndef CPU_M32RBF_H
  26 #define CPU_M32RBF_H
  27
  28 /* Maximum number of instructions that are fetched at a time.
  29    This is for LIW type instructions sets (e.g. m32r).  */
  30 #define MAX_LIW_INSNS 2
  31
  32 /* Maximum number of instructions that can be executed in parallel.  */
  33 #define MAX_PARALLEL_INSNS 1
  34
  35 /* CPU state information.  */
  36 typedef struct {
  37   /* Hardware elements.  */
  38   struct {
  39   /* program counter */
  40   USI h_pc;
  41 #define GET_H_PC() CPU (h_pc)
  42 #define SET_H_PC(x) (CPU (h_pc) = (x))
  43   /* general registers */
  44   SI h_gr[16];
  45 #define GET_H_GR(a1) CPU (h_gr)[a1]
  46 #define SET_H_GR(a1, x) (CPU (h_gr)[a1] = (x))
  47   /* control registers */
  48   USI h_cr[16];
  49 /* GET_H_CR macro user-written */
  50 /* SET_H_CR macro user-written */
  51   /* accumulator */
  52   DI h_accum;
  53 /* GET_H_ACCUM macro user-written */
  54 /* SET_H_ACCUM macro user-written */
  55   /* condition bit */
  56   BI h_cond;
  57 #define GET_H_COND() CPU (h_cond)
  58 #define SET_H_COND(x) (CPU (h_cond) = (x))
  59   /* psw part of psw */
  60   UQI h_psw;
  61 /* GET_H_PSW macro user-written */
  62 /* SET_H_PSW macro user-written */
  63   /* backup psw */
  64   UQI h_bpsw;
  65 #define GET_H_BPSW() CPU (h_bpsw)
  66 #define SET_H_BPSW(x) (CPU (h_bpsw) = (x))
  67   /* backup bpsw */
  68   UQI h_bbpsw;
  69 #define GET_H_BBPSW() CPU (h_bbpsw)
  70 #define SET_H_BBPSW(x) (CPU (h_bbpsw) = (x))
  71   /* lock */
  72   BI h_lock;
  73 #define GET_H_LOCK() CPU (h_lock)
  74 #define SET_H_LOCK(x) (CPU (h_lock) = (x))
  75   } hardware;
  76 #define CPU_CGEN_HW(cpu) (& (cpu)->cpu_data.hardware)
  77 } M32RBF_CPU_DATA;
  78
  79 /* Cover fns for register access.  */
  80 USI m32rbf_h_pc_get (SIM_CPU *);
  81 void m32rbf_h_pc_set (SIM_CPU *, USI);
  82 SI m32rbf_h_gr_get (SIM_CPU *, UINT);
  83 void m32rbf_h_gr_set (SIM_CPU *, UINT, SI);
  84 USI m32rbf_h_cr_get (SIM_CPU *, UINT);
  85 void m32rbf_h_cr_set (SIM_CPU *, UINT, USI);
  86 DI m32rbf_h_accum_get (SIM_CPU *);
  87 void m32rbf_h_accum_set (SIM_CPU *, DI);
  88 DI m32rbf_h_accums_get (SIM_CPU *, UINT);
  89 void m32rbf_h_accums_set (SIM_CPU *, UINT, DI);
  90 BI m32rbf_h_cond_get (SIM_CPU *);
  91 void m32rbf_h_cond_set (SIM_CPU *, BI);
  92 UQI m32rbf_h_psw_get (SIM_CPU *);
  93 void m32rbf_h_psw_set (SIM_CPU *, UQI);
  94 UQI m32rbf_h_bpsw_get (SIM_CPU *);
  95 void m32rbf_h_bpsw_set (SIM_CPU *, UQI);
  96 UQI m32rbf_h_bbpsw_get (SIM_CPU *);
  97 void m32rbf_h_bbpsw_set (SIM_CPU *, UQI);
  98 BI m32rbf_h_lock_get (SIM_CPU *);
  99 void m32rbf_h_lock_set (SIM_CPU *, BI);
 100
 101 /* These must be hand-written.  */
 102 extern CPUREG_FETCH_FN m32rbf_fetch_register;
 103 extern CPUREG_STORE_FN m32rbf_store_register;
 104
 105 typedef struct {
 106   UINT h_gr;
 107 } MODEL_M32R_D_DATA;
 108
 109 typedef struct {
 110   int empty;
 111 } MODEL_TEST_DATA;
 112
 113 union sem_fields {
 114     struct { /* empty sformat for unspecified field list */
 115       int empty;
 116     } fmt_empty;
 117     struct { /* e.g. add $dr,$sr */
 118       SI * i_dr;
 119       SI * i_sr;
 120       unsigned char in_dr;
 121       unsigned char in_sr;
 122       unsigned char out_dr;
 123     } fmt_add;
 124     struct { /* e.g. add3 $dr,$sr,$hash$slo16 */
 125       INT f_simm16;
 126       SI * i_sr;
 127       SI * i_dr;
 128       unsigned char in_sr;
 129       unsigned char out_dr;
 130     } fmt_add3;
 131     struct { /* e.g. and3 $dr,$sr,$uimm16 */
 132       UINT f_uimm16;
 133       SI * i_sr;
 134       SI * i_dr;
 135       unsigned char in_sr;
 136       unsigned char out_dr;
 137     } fmt_and3;
 138     struct { /* e.g. or3 $dr,$sr,$hash$ulo16 */
 139       UINT f_uimm16;
 140       SI * i_sr;
 141       SI * i_dr;
 142       unsigned char in_sr;
 143       unsigned char out_dr;
 144     } fmt_or3;
 145     struct { /* e.g. addi $dr,$simm8 */
 146       INT f_simm8;
 147       SI * i_dr;
 148       unsigned char in_dr;
 149       unsigned char out_dr;
 150     } fmt_addi;
 151     struct { /* e.g. addv $dr,$sr */
 152       SI * i_dr;
 153       SI * i_sr;
 154       unsigned char in_dr;
 155       unsigned char in_sr;
 156       unsigned char out_dr;
 157     } fmt_addv;
 158     struct { /* e.g. addv3 $dr,$sr,$simm16 */
 159       INT f_simm16;
 160       SI * i_sr;
 161       SI * i_dr;
 162       unsigned char in_sr;
 163       unsigned char out_dr;
 164     } fmt_addv3;
 165     struct { /* e.g. addx $dr,$sr */
 166       SI * i_dr;
 167       SI * i_sr;
 168       unsigned char in_dr;
 169       unsigned char in_sr;
 170       unsigned char out_dr;
 171     } fmt_addx;
 172     struct { /* e.g. cmp $src1,$src2 */
 173       SI * i_src1;
 174       SI * i_src2;
 175       unsigned char in_src1;
 176       unsigned char in_src2;
 177     } fmt_cmp;
 178     struct { /* e.g. cmpi $src2,$simm16 */
 179       INT f_simm16;
 180       SI * i_src2;
 181       unsigned char in_src2;
 182     } fmt_cmpi;
 183     struct { /* e.g. div $dr,$sr */
 184       SI * i_dr;
 185       SI * i_sr;
 186       unsigned char in_dr;
 187       unsigned char in_sr;
 188       unsigned char out_dr;
 189     } fmt_div;
 190     struct { /* e.g. ld $dr,@$sr */
 191       SI * i_sr;
 192       SI * i_dr;
 193       unsigned char in_sr;
 194       unsigned char out_dr;
 195     } fmt_ld;
 196     struct { /* e.g. ld $dr,@($slo16,$sr) */
 197       INT f_simm16;
 198       SI * i_sr;
 199       SI * i_dr;
 200       unsigned char in_sr;
 201       unsigned char out_dr;
 202     } fmt_ld_d;
 203     struct { /* e.g. ldb $dr,@$sr */
 204       SI * i_sr;
 205       SI * i_dr;
 206       unsigned char in_sr;
 207       unsigned char out_dr;
 208     } fmt_ldb;
 209     struct { /* e.g. ldb $dr,@($slo16,$sr) */
 210       INT f_simm16;
 211       SI * i_sr;
 212       SI * i_dr;
 213       unsigned char in_sr;
 214       unsigned char out_dr;
 215     } fmt_ldb_d;
 216     struct { /* e.g. ldh $dr,@$sr */
 217       SI * i_sr;
 218       SI * i_dr;
 219       unsigned char in_sr;
 220       unsigned char out_dr;
 221     } fmt_ldh;
 222     struct { /* e.g. ldh $dr,@($slo16,$sr) */
 223       INT f_simm16;
 224       SI * i_sr;
 225       SI * i_dr;
 226       unsigned char in_sr;
 227       unsigned char out_dr;
 228     } fmt_ldh_d;
 229     struct { /* e.g. ld $dr,@$sr+ */
 230       SI * i_sr;
 231       SI * i_dr;
 232       unsigned char in_sr;
 233       unsigned char out_dr;
 234       unsigned char out_sr;
 235     } fmt_ld_plus;
 236     struct { /* e.g. ld24 $dr,$uimm24 */
 237       ADDR i_uimm24;
 238       SI * i_dr;
 239       unsigned char out_dr;
 240     } fmt_ld24;
 241     struct { /* e.g. ldi8 $dr,$simm8 */
 242       INT f_simm8;
 243       SI * i_dr;
 244       unsigned char out_dr;
 245     } fmt_ldi8;
 246     struct { /* e.g. ldi16 $dr,$hash$slo16 */
 247       INT f_simm16;
 248       SI * i_dr;
 249       unsigned char out_dr;
 250     } fmt_ldi16;
 251     struct { /* e.g. lock $dr,@$sr */
 252       SI * i_sr;
 253       SI * i_dr;
 254       unsigned char in_sr;
 255       unsigned char out_dr;
 256     } fmt_lock;
 257     struct { /* e.g. machi $src1,$src2 */
 258       SI * i_src1;
 259       SI * i_src2;
 260       unsigned char in_src1;
 261       unsigned char in_src2;
 262     } fmt_machi;
 263     struct { /* e.g. mulhi $src1,$src2 */
 264       SI * i_src1;
 265       SI * i_src2;
 266       unsigned char in_src1;
 267       unsigned char in_src2;
 268     } fmt_mulhi;
 269     struct { /* e.g. mv $dr,$sr */
 270       SI * i_sr;
 271       SI * i_dr;
 272       unsigned char in_sr;
 273       unsigned char out_dr;
 274     } fmt_mv;
 275     struct { /* e.g. mvfachi $dr */
 276       SI * i_dr;
 277       unsigned char out_dr;
 278     } fmt_mvfachi;
 279     struct { /* e.g. mvfc $dr,$scr */
 280       UINT f_r2;
 281       SI * i_dr;
 282       unsigned char out_dr;
 283     } fmt_mvfc;
 284     struct { /* e.g. mvtachi $src1 */
 285       SI * i_src1;
 286       unsigned char in_src1;
 287     } fmt_mvtachi;
 288     struct { /* e.g. mvtc $sr,$dcr */
 289       UINT f_r1;
 290       SI * i_sr;
 291       unsigned char in_sr;
 292     } fmt_mvtc;
 293     struct { /* e.g. nop */
 294       int empty;
 295     } fmt_nop;
 296     struct { /* e.g. rac */
 297       int empty;
 298     } fmt_rac;
 299     struct { /* e.g. seth $dr,$hash$hi16 */
 300       UINT f_hi16;
 301       SI * i_dr;
 302       unsigned char out_dr;
 303     } fmt_seth;
 304     struct { /* e.g. sll3 $dr,$sr,$simm16 */
 305       INT f_simm16;
 306       SI * i_sr;
 307       SI * i_dr;
 308       unsigned char in_sr;
 309       unsigned char out_dr;
 310     } fmt_sll3;
 311     struct { /* e.g. slli $dr,$uimm5 */
 312       UINT f_uimm5;
 313       SI * i_dr;
 314       unsigned char in_dr;
 315       unsigned char out_dr;
 316     } fmt_slli;
 317     struct { /* e.g. st $src1,@$src2 */
 318       SI * i_src1;
 319       SI * i_src2;
 320       unsigned char in_src1;
 321       unsigned char in_src2;
 322     } fmt_st;
 323     struct { /* e.g. st $src1,@($slo16,$src2) */
 324       INT f_simm16;
 325       SI * i_src1;
 326       SI * i_src2;
 327       unsigned char in_src1;
 328       unsigned char in_src2;
 329     } fmt_st_d;
 330     struct { /* e.g. stb $src1,@$src2 */
 331       SI * i_src1;
 332       SI * i_src2;
 333       unsigned char in_src1;
 334       unsigned char in_src2;
 335     } fmt_stb;
 336     struct { /* e.g. stb $src1,@($slo16,$src2) */
 337       INT f_simm16;
 338       SI * i_src1;
 339       SI * i_src2;
 340       unsigned char in_src1;
 341       unsigned char in_src2;
 342     } fmt_stb_d;
 343     struct { /* e.g. sth $src1,@$src2 */
 344       SI * i_src1;
 345       SI * i_src2;
 346       unsigned char in_src1;
 347       unsigned char in_src2;
 348     } fmt_sth;
 349     struct { /* e.g. sth $src1,@($slo16,$src2) */
 350       INT f_simm16;
 351       SI * i_src1;
 352       SI * i_src2;
 353       unsigned char in_src1;
 354       unsigned char in_src2;
 355     } fmt_sth_d;
 356     struct { /* e.g. st $src1,@+$src2 */
 357       SI * i_src1;
 358       SI * i_src2;
 359       unsigned char in_src1;
 360       unsigned char in_src2;
 361       unsigned char out_src2;
 362     } fmt_st_plus;
 363     struct { /* e.g. unlock $src1,@$src2 */
 364       SI * i_src1;
 365       SI * i_src2;
 366       unsigned char in_src1;
 367       unsigned char in_src2;
 368     } fmt_unlock;
 369   /* cti insns, kept separately so addr_cache is in fixed place */
 370   struct {
 371     union {
 372     struct { /* e.g. bc.s $disp8 */
 373       IADDR i_disp8;
 374     } fmt_bc8;
 375     struct { /* e.g. bc.l $disp24 */
 376       IADDR i_disp24;
 377     } fmt_bc24;
 378     struct { /* e.g. beq $src1,$src2,$disp16 */
 379       IADDR i_disp16;
 380       SI * i_src1;
 381       SI * i_src2;
 382       unsigned char in_src1;
 383       unsigned char in_src2;
 384     } fmt_beq;
 385     struct { /* e.g. beqz $src2,$disp16 */
 386       IADDR i_disp16;
 387       SI * i_src2;
 388       unsigned char in_src2;
 389     } fmt_beqz;
 390     struct { /* e.g. bl.s $disp8 */
 391       IADDR i_disp8;
 392       unsigned char out_h_gr_14;
 393     } fmt_bl8;
 394     struct { /* e.g. bl.l $disp24 */
 395       IADDR i_disp24;
 396       unsigned char out_h_gr_14;
 397     } fmt_bl24;
 398     struct { /* e.g. bra.s $disp8 */
 399       IADDR i_disp8;
 400     } fmt_bra8;
 401     struct { /* e.g. bra.l $disp24 */
 402       IADDR i_disp24;
 403     } fmt_bra24;
 404     struct { /* e.g. jl $sr */
 405       SI * i_sr;
 406       unsigned char in_sr;
 407       unsigned char out_h_gr_14;
 408     } fmt_jl;
 409     struct { /* e.g. jmp $sr */
 410       SI * i_sr;
 411       unsigned char in_sr;
 412     } fmt_jmp;
 413     struct { /* e.g. rte */
 414       int empty;
 415     } fmt_rte;
 416     struct { /* e.g. trap $uimm4 */
 417       UINT f_uimm4;
 418     } fmt_trap;
 419     } fields;
 420 #if WITH_SCACHE_PBB
 421     SEM_PC addr_cache;
 422 #endif
 423   } cti;
 424 #if WITH_SCACHE_PBB
 425   /* Writeback handler.  */
 426   struct {
 427     /* Pointer to argbuf entry for insn whose results need writing back.  */
 428     const struct argbuf *abuf;
 429   } write;
 430   /* x-before handler */
 431   struct {
 432     /*const SCACHE *insns[MAX_PARALLEL_INSNS];*/
 433     int first_p;
 434   } before;
 435   /* x-after handler */
 436   struct {
 437     int empty;
 438   } after;
 439   /* This entry is used to terminate each pbb.  */
 440   struct {
 441     /* Number of insns in pbb.  */
 442     int insn_count;
 443     /* Next pbb to execute.  */
 444     SCACHE *next;
 445   } chain;
 446 #endif
 447 };
 448
 449 /* The ARGBUF struct.  */
 450 struct argbuf {
 451   /* These are the baseclass definitions.  */
 452   IADDR addr;
 453   const IDESC *idesc;
 454   char trace_p;
 455   char profile_p;
 456   /* cpu specific data follows */
 457   union sem semantic;
 458   int written;
 459   union sem_fields fields;
 460 };
 461
 462 /* A cached insn.
 463
 464    ??? SCACHE used to contain more than just argbuf.  We could delete the
 465    type entirely and always just use ARGBUF, but for future concerns and as
 466    a level of abstraction it is left in.  */
 467
 468 struct scache {
 469   struct argbuf argbuf;
 470 };
 471
 472 /* Macros to simplify extraction, reading and semantic code.
 473    These define and assign the local vars that contain the insn's fields.  */
 474
 475 #define EXTRACT_IFMT_EMPTY_VARS \
 476   /* Instruction fields.  */ \
 477   unsigned int length;
 478 #define EXTRACT_IFMT_EMPTY_CODE \
 479   length = 0; \
 480
 481 #define EXTRACT_IFMT_ADD_VARS \
 482   /* Instruction fields.  */ \
 483   UINT f_op1; \
 484   UINT f_r1; \
 485   UINT f_op2; \
 486   UINT f_r2; \
 487   unsigned int length;
 488 #define EXTRACT_IFMT_ADD_CODE \
 489   length = 2; \
 490   f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
 491   f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
 492   f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
 493   f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
 494
 495 #define EXTRACT_IFMT_ADD3_VARS \
 496   /* Instruction fields.  */ \
 497   UINT f_op1; \
 498   UINT f_r1; \
 499   UINT f_op2; \
 500   UINT f_r2; \
 501   INT f_simm16; \
 502   unsigned int length;
 503 #define EXTRACT_IFMT_ADD3_CODE \
 504   length = 4; \
 505   f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
 506   f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
 507   f_op2 = EXTRACT_UINT (insn, 32, 8, 4); \
 508   f_r2 = EXTRACT_UINT (insn, 32, 12, 4); \
 509   f_simm16 = EXTRACT_INT (insn, 32, 16, 16); \
 510
 511 #define EXTRACT_IFMT_AND3_VARS \
 512   /* Instruction fields.  */ \
 513   UINT f_op1; \
 514   UINT f_r1; \
 515   UINT f_op2; \
 516   UINT f_r2; \
 517   UINT f_uimm16; \
 518   unsigned int length;
 519 #define EXTRACT_IFMT_AND3_CODE \
 520   length = 4; \
 521   f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
 522   f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
 523   f_op2 = EXTRACT_UINT (insn, 32, 8, 4); \
 524   f_r2 = EXTRACT_UINT (insn, 32, 12, 4); \
 525   f_uimm16 = EXTRACT_UINT (insn, 32, 16, 16); \
 526
 527 #define EXTRACT_IFMT_OR3_VARS \
 528   /* Instruction fields.  */ \
 529   UINT f_op1; \
 530   UINT f_r1; \
 531   UINT f_op2; \
 532   UINT f_r2; \
 533   UINT f_uimm16; \
 534   unsigned int length;
 535 #define EXTRACT_IFMT_OR3_CODE \
 536   length = 4; \
 537   f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
 538   f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
 539   f_op2 = EXTRACT_UINT (insn, 32, 8, 4); \
 540   f_r2 = EXTRACT_UINT (insn, 32, 12, 4); \
 541   f_uimm16 = EXTRACT_UINT (insn, 32, 16, 16); \
 542
 543 #define EXTRACT_IFMT_ADDI_VARS \
 544   /* Instruction fields.  */ \
 545   UINT f_op1; \
 546   UINT f_r1; \
 547   INT f_simm8; \
 548   unsigned int length;
 549 #define EXTRACT_IFMT_ADDI_CODE \
 550   length = 2; \
 551   f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
 552   f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
 553   f_simm8 = EXTRACT_INT (insn, 16, 8, 8); \
 554
 555 #define EXTRACT_IFMT_ADDV3_VARS \
 556   /* Instruction fields.  */ \
 557   UINT f_op1; \
 558   UINT f_r1; \
 559   UINT f_op2; \
 560   UINT f_r2; \
 561   INT f_simm16; \
 562   unsigned int length;
 563 #define EXTRACT_IFMT_ADDV3_CODE \
 564   length = 4; \
 565   f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
 566   f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
 567   f_op2 = EXTRACT_UINT (insn, 32, 8, 4); \
 568   f_r2 = EXTRACT_UINT (insn, 32, 12, 4); \
 569   f_simm16 = EXTRACT_INT (insn, 32, 16, 16); \
 570
 571 #define EXTRACT_IFMT_BC8_VARS \
 572   /* Instruction fields.  */ \
 573   UINT f_op1; \
 574   UINT f_r1; \
 575   SI f_disp8; \
 576   unsigned int length;
 577 #define EXTRACT_IFMT_BC8_CODE \
 578   length = 2; \
 579   f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
 580   f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
 581   f_disp8 = ((((EXTRACT_INT (insn, 16, 8, 8)) << (2))) + (((pc) & (-4)))); \
 582
 583 #define EXTRACT_IFMT_BC24_VARS \
 584   /* Instruction fields.  */ \
 585   UINT f_op1; \
 586   UINT f_r1; \
 587   SI f_disp24; \
 588   unsigned int length;
 589 #define EXTRACT_IFMT_BC24_CODE \
 590   length = 4; \
 591   f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
 592   f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
 593   f_disp24 = ((((EXTRACT_INT (insn, 32, 8, 24)) << (2))) + (pc)); \
 594
 595 #define EXTRACT_IFMT_BEQ_VARS \
 596   /* Instruction fields.  */ \
 597   UINT f_op1; \
 598   UINT f_r1; \
 599   UINT f_op2; \
 600   UINT f_r2; \
 601   SI f_disp16; \
 602   unsigned int length;
 603 #define EXTRACT_IFMT_BEQ_CODE \
 604   length = 4; \
 605   f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
 606   f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
 607   f_op2 = EXTRACT_UINT (insn, 32, 8, 4); \
 608   f_r2 = EXTRACT_UINT (insn, 32, 12, 4); \
 609   f_disp16 = ((((EXTRACT_INT (insn, 32, 16, 16)) << (2))) + (pc)); \
 610
 611 #define EXTRACT_IFMT_BEQZ_VARS \
 612   /* Instruction fields.  */ \
 613   UINT f_op1; \
 614   UINT f_r1; \
 615   UINT f_op2; \
 616   UINT f_r2; \
 617   SI f_disp16; \
 618   unsigned int length;
 619 #define EXTRACT_IFMT_BEQZ_CODE \
 620   length = 4; \
 621   f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
 622   f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
 623   f_op2 = EXTRACT_UINT (insn, 32, 8, 4); \
 624   f_r2 = EXTRACT_UINT (insn, 32, 12, 4); \
 625   f_disp16 = ((((EXTRACT_INT (insn, 32, 16, 16)) << (2))) + (pc)); \
 626
 627 #define EXTRACT_IFMT_CMP_VARS \
 628   /* Instruction fields.  */ \
 629   UINT f_op1; \
 630   UINT f_r1; \
 631   UINT f_op2; \
 632   UINT f_r2; \
 633   unsigned int length;
 634 #define EXTRACT_IFMT_CMP_CODE \
 635   length = 2; \
 636   f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
 637   f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
 638   f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
 639   f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
 640
 641 #define EXTRACT_IFMT_CMPI_VARS \
 642   /* Instruction fields.  */ \
 643   UINT f_op1; \
 644   UINT f_r1; \
 645   UINT f_op2; \
 646   UINT f_r2; \
 647   INT f_simm16; \
 648   unsigned int length;
 649 #define EXTRACT_IFMT_CMPI_CODE \
 650   length = 4; \
 651   f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
 652   f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
 653   f_op2 = EXTRACT_UINT (insn, 32, 8, 4); \
 654   f_r2 = EXTRACT_UINT (insn, 32, 12, 4); \
 655   f_simm16 = EXTRACT_INT (insn, 32, 16, 16); \
 656
 657 #define EXTRACT_IFMT_DIV_VARS \
 658   /* Instruction fields.  */ \
 659   UINT f_op1; \
 660   UINT f_r1; \
 661   UINT f_op2; \
 662   UINT f_r2; \
 663   INT f_simm16; \
 664   unsigned int length;
 665 #define EXTRACT_IFMT_DIV_CODE \
 666   length = 4; \
 667   f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
 668   f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
 669   f_op2 = EXTRACT_UINT (insn, 32, 8, 4); \
 670   f_r2 = EXTRACT_UINT (insn, 32, 12, 4); \
 671   f_simm16 = EXTRACT_INT (insn, 32, 16, 16); \
 672
 673 #define EXTRACT_IFMT_JL_VARS \
 674   /* Instruction fields.  */ \
 675   UINT f_op1; \
 676   UINT f_r1; \
 677   UINT f_op2; \
 678   UINT f_r2; \
 679   unsigned int length;
 680 #define EXTRACT_IFMT_JL_CODE \
 681   length = 2; \
 682   f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
 683   f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
 684   f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
 685   f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
 686
 687 #define EXTRACT_IFMT_LD24_VARS \
 688   /* Instruction fields.  */ \
 689   UINT f_op1; \
 690   UINT f_r1; \
 691   UINT f_uimm24; \
 692   unsigned int length;
 693 #define EXTRACT_IFMT_LD24_CODE \
 694   length = 4; \
 695   f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
 696   f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
 697   f_uimm24 = EXTRACT_UINT (insn, 32, 8, 24); \
 698
 699 #define EXTRACT_IFMT_LDI16_VARS \
 700   /* Instruction fields.  */ \
 701   UINT f_op1; \
 702   UINT f_r1; \
 703   UINT f_op2; \
 704   UINT f_r2; \
 705   INT f_simm16; \
 706   unsigned int length;
 707 #define EXTRACT_IFMT_LDI16_CODE \
 708   length = 4; \
 709   f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
 710   f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
 711   f_op2 = EXTRACT_UINT (insn, 32, 8, 4); \
 712   f_r2 = EXTRACT_UINT (insn, 32, 12, 4); \
 713   f_simm16 = EXTRACT_INT (insn, 32, 16, 16); \
 714
 715 #define EXTRACT_IFMT_MVFACHI_VARS \
 716   /* Instruction fields.  */ \
 717   UINT f_op1; \
 718   UINT f_r1; \
 719   UINT f_op2; \
 720   UINT f_r2; \
 721   unsigned int length;
 722 #define EXTRACT_IFMT_MVFACHI_CODE \
 723   length = 2; \
 724   f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
 725   f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
 726   f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
 727   f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
 728
 729 #define EXTRACT_IFMT_MVFC_VARS \
 730   /* Instruction fields.  */ \
 731   UINT f_op1; \
 732   UINT f_r1; \
 733   UINT f_op2; \
 734   UINT f_r2; \
 735   unsigned int length;
 736 #define EXTRACT_IFMT_MVFC_CODE \
 737   length = 2; \
 738   f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
 739   f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
 740   f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
 741   f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
 742
 743 #define EXTRACT_IFMT_MVTACHI_VARS \
 744   /* Instruction fields.  */ \
 745   UINT f_op1; \
 746   UINT f_r1; \
 747   UINT f_op2; \
 748   UINT f_r2; \
 749   unsigned int length;
 750 #define EXTRACT_IFMT_MVTACHI_CODE \
 751   length = 2; \
 752   f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
 753   f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
 754   f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
 755   f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
 756
 757 #define EXTRACT_IFMT_MVTC_VARS \
 758   /* Instruction fields.  */ \
 759   UINT f_op1; \
 760   UINT f_r1; \
 761   UINT f_op2; \
 762   UINT f_r2; \
 763   unsigned int length;
 764 #define EXTRACT_IFMT_MVTC_CODE \
 765   length = 2; \
 766   f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
 767   f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
 768   f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
 769   f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
 770
 771 #define EXTRACT_IFMT_NOP_VARS \
 772   /* Instruction fields.  */ \
 773   UINT f_op1; \
 774   UINT f_r1; \
 775   UINT f_op2; \
 776   UINT f_r2; \
 777   unsigned int length;
 778 #define EXTRACT_IFMT_NOP_CODE \
 779   length = 2; \
 780   f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
 781   f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
 782   f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
 783   f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
 784
 785 #define EXTRACT_IFMT_SETH_VARS \
 786   /* Instruction fields.  */ \
 787   UINT f_op1; \
 788   UINT f_r1; \
 789   UINT f_op2; \
 790   UINT f_r2; \
 791   UINT f_hi16; \
 792   unsigned int length;
 793 #define EXTRACT_IFMT_SETH_CODE \
 794   length = 4; \
 795   f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
 796   f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
 797   f_op2 = EXTRACT_UINT (insn, 32, 8, 4); \
 798   f_r2 = EXTRACT_UINT (insn, 32, 12, 4); \
 799   f_hi16 = EXTRACT_UINT (insn, 32, 16, 16); \
 800
 801 #define EXTRACT_IFMT_SLLI_VARS \
 802   /* Instruction fields.  */ \
 803   UINT f_op1; \
 804   UINT f_r1; \
 805   UINT f_shift_op2; \
 806   UINT f_uimm5; \
 807   unsigned int length;
 808 #define EXTRACT_IFMT_SLLI_CODE \
 809   length = 2; \
 810   f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
 811   f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
 812   f_shift_op2 = EXTRACT_UINT (insn, 16, 8, 3); \
 813   f_uimm5 = EXTRACT_UINT (insn, 16, 11, 5); \
 814
 815 #define EXTRACT_IFMT_ST_D_VARS \
 816   /* Instruction fields.  */ \
 817   UINT f_op1; \
 818   UINT f_r1; \
 819   UINT f_op2; \
 820   UINT f_r2; \
 821   INT f_simm16; \
 822   unsigned int length;
 823 #define EXTRACT_IFMT_ST_D_CODE \
 824   length = 4; \
 825   f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
 826   f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
 827   f_op2 = EXTRACT_UINT (insn, 32, 8, 4); \
 828   f_r2 = EXTRACT_UINT (insn, 32, 12, 4); \
 829   f_simm16 = EXTRACT_INT (insn, 32, 16, 16); \
 830
 831 #define EXTRACT_IFMT_TRAP_VARS \
 832   /* Instruction fields.  */ \
 833   UINT f_op1; \
 834   UINT f_r1; \
 835   UINT f_op2; \
 836   UINT f_uimm4; \
 837   unsigned int length;
 838 #define EXTRACT_IFMT_TRAP_CODE \
 839   length = 2; \
 840   f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
 841   f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
 842   f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
 843   f_uimm4 = EXTRACT_UINT (insn, 16, 12, 4); \
 844
 845 /* Collection of various things for the trace handler to use.  */
 846
 847 typedef struct trace_record {
 848   IADDR pc;
 849   /* FIXME:wip */
 850 } TRACE_RECORD;
 851
 852 #endif /* CPU_M32RBF_H */