1 /* Simulator instruction decoder for m32rbf.
3 THIS FILE IS MACHINE GENERATED WITH CGEN.
5 Copyright (C) 1996, 1997, 1998, 1999 Free Software Foundation, Inc.
7 This file is part of the GNU Simulators.
9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 2, or (at your option)
14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License along
20 with this program; if not, write to the Free Software Foundation, Inc.,
21 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
25 #define WANT_CPU m32rbf
26 #define WANT_CPU_M32RBF
29 #include "sim-assert.h"
31 /* FIXME: Need to review choices for the following. */
33 #if WITH_SEM_SWITCH_FULL
36 #define FULL(fn) CONCAT3 (m32rbf,_sem_,fn) ,
40 #if WITH_SEM_SWITCH_FAST
43 #define FAST(fn) CONCAT3 (m32rbf,_semf_,fn) , /* f for fast */
49 /* The instruction descriptor array.
50 This is computed at runtime. Space for it is not malloc'd to save a
51 teensy bit of cpu in the decoder. Moving it to malloc space is trivial
52 but won't be done until necessary (we don't currently support the runtime
53 addition of instructions nor an SMP machine with different cpus). */
54 static IDESC m32rbf_insn_data
[M32RBF_INSN_MAX
];
56 /* The INSN_ prefix is not here and is instead part of the `insn' argument
57 to avoid collisions with header files (e.g. `AND' in ansidecl.h). */
58 #define IDX(insn) CONCAT2 (M32RBF_,insn)
59 #define TYPE(insn) CONCAT2 (M32R_,insn)
61 /* Commas between elements are contained in the macros.
62 Some of these are conditionally compiled out. */
64 static const struct insn_sem m32rbf_insn_sem
[] =
66 { VIRTUAL_INSN_X_INVALID
, IDX (INSN_X_INVALID
), FULL (x_invalid
) FAST (x_invalid
) },
67 { VIRTUAL_INSN_X_AFTER
, IDX (INSN_X_AFTER
), FULL (x_after
) FAST (x_after
) },
68 { VIRTUAL_INSN_X_BEFORE
, IDX (INSN_X_BEFORE
), FULL (x_before
) FAST (x_before
) },
69 { VIRTUAL_INSN_X_CTI_CHAIN
, IDX (INSN_X_CTI_CHAIN
), FULL (x_cti_chain
) FAST (x_cti_chain
) },
70 { VIRTUAL_INSN_X_CHAIN
, IDX (INSN_X_CHAIN
), FULL (x_chain
) FAST (x_chain
) },
71 { VIRTUAL_INSN_X_BEGIN
, IDX (INSN_X_BEGIN
), FULL (x_begin
) FAST (x_begin
) },
72 { TYPE (INSN_ADD
), IDX (INSN_ADD
), FULL (add
) FAST (add
) },
73 { TYPE (INSN_ADD3
), IDX (INSN_ADD3
), FULL (add3
) FAST (add3
) },
74 { TYPE (INSN_AND
), IDX (INSN_AND
), FULL (and) FAST (and) },
75 { TYPE (INSN_AND3
), IDX (INSN_AND3
), FULL (and3
) FAST (and3
) },
76 { TYPE (INSN_OR
), IDX (INSN_OR
), FULL (or) FAST (or) },
77 { TYPE (INSN_OR3
), IDX (INSN_OR3
), FULL (or3
) FAST (or3
) },
78 { TYPE (INSN_XOR
), IDX (INSN_XOR
), FULL (xor) FAST (xor) },
79 { TYPE (INSN_XOR3
), IDX (INSN_XOR3
), FULL (xor3
) FAST (xor3
) },
80 { TYPE (INSN_ADDI
), IDX (INSN_ADDI
), FULL (addi
) FAST (addi
) },
81 { TYPE (INSN_ADDV
), IDX (INSN_ADDV
), FULL (addv
) FAST (addv
) },
82 { TYPE (INSN_ADDV3
), IDX (INSN_ADDV3
), FULL (addv3
) FAST (addv3
) },
83 { TYPE (INSN_ADDX
), IDX (INSN_ADDX
), FULL (addx
) FAST (addx
) },
84 { TYPE (INSN_BC8
), IDX (INSN_BC8
), FULL (bc8
) FAST (bc8
) },
85 { TYPE (INSN_BC24
), IDX (INSN_BC24
), FULL (bc24
) FAST (bc24
) },
86 { TYPE (INSN_BEQ
), IDX (INSN_BEQ
), FULL (beq
) FAST (beq
) },
87 { TYPE (INSN_BEQZ
), IDX (INSN_BEQZ
), FULL (beqz
) FAST (beqz
) },
88 { TYPE (INSN_BGEZ
), IDX (INSN_BGEZ
), FULL (bgez
) FAST (bgez
) },
89 { TYPE (INSN_BGTZ
), IDX (INSN_BGTZ
), FULL (bgtz
) FAST (bgtz
) },
90 { TYPE (INSN_BLEZ
), IDX (INSN_BLEZ
), FULL (blez
) FAST (blez
) },
91 { TYPE (INSN_BLTZ
), IDX (INSN_BLTZ
), FULL (bltz
) FAST (bltz
) },
92 { TYPE (INSN_BNEZ
), IDX (INSN_BNEZ
), FULL (bnez
) FAST (bnez
) },
93 { TYPE (INSN_BL8
), IDX (INSN_BL8
), FULL (bl8
) FAST (bl8
) },
94 { TYPE (INSN_BL24
), IDX (INSN_BL24
), FULL (bl24
) FAST (bl24
) },
95 { TYPE (INSN_BNC8
), IDX (INSN_BNC8
), FULL (bnc8
) FAST (bnc8
) },
96 { TYPE (INSN_BNC24
), IDX (INSN_BNC24
), FULL (bnc24
) FAST (bnc24
) },
97 { TYPE (INSN_BNE
), IDX (INSN_BNE
), FULL (bne
) FAST (bne
) },
98 { TYPE (INSN_BRA8
), IDX (INSN_BRA8
), FULL (bra8
) FAST (bra8
) },
99 { TYPE (INSN_BRA24
), IDX (INSN_BRA24
), FULL (bra24
) FAST (bra24
) },
100 { TYPE (INSN_CMP
), IDX (INSN_CMP
), FULL (cmp
) FAST (cmp
) },
101 { TYPE (INSN_CMPI
), IDX (INSN_CMPI
), FULL (cmpi
) FAST (cmpi
) },
102 { TYPE (INSN_CMPU
), IDX (INSN_CMPU
), FULL (cmpu
) FAST (cmpu
) },
103 { TYPE (INSN_CMPUI
), IDX (INSN_CMPUI
), FULL (cmpui
) FAST (cmpui
) },
104 { TYPE (INSN_DIV
), IDX (INSN_DIV
), FULL (div
) FAST (div
) },
105 { TYPE (INSN_DIVU
), IDX (INSN_DIVU
), FULL (divu
) FAST (divu
) },
106 { TYPE (INSN_REM
), IDX (INSN_REM
), FULL (rem
) FAST (rem
) },
107 { TYPE (INSN_REMU
), IDX (INSN_REMU
), FULL (remu
) FAST (remu
) },
108 { TYPE (INSN_JL
), IDX (INSN_JL
), FULL (jl
) FAST (jl
) },
109 { TYPE (INSN_JMP
), IDX (INSN_JMP
), FULL (jmp
) FAST (jmp
) },
110 { TYPE (INSN_LD
), IDX (INSN_LD
), FULL (ld
) FAST (ld
) },
111 { TYPE (INSN_LD_D
), IDX (INSN_LD_D
), FULL (ld_d
) FAST (ld_d
) },
112 { TYPE (INSN_LDB
), IDX (INSN_LDB
), FULL (ldb
) FAST (ldb
) },
113 { TYPE (INSN_LDB_D
), IDX (INSN_LDB_D
), FULL (ldb_d
) FAST (ldb_d
) },
114 { TYPE (INSN_LDH
), IDX (INSN_LDH
), FULL (ldh
) FAST (ldh
) },
115 { TYPE (INSN_LDH_D
), IDX (INSN_LDH_D
), FULL (ldh_d
) FAST (ldh_d
) },
116 { TYPE (INSN_LDUB
), IDX (INSN_LDUB
), FULL (ldub
) FAST (ldub
) },
117 { TYPE (INSN_LDUB_D
), IDX (INSN_LDUB_D
), FULL (ldub_d
) FAST (ldub_d
) },
118 { TYPE (INSN_LDUH
), IDX (INSN_LDUH
), FULL (lduh
) FAST (lduh
) },
119 { TYPE (INSN_LDUH_D
), IDX (INSN_LDUH_D
), FULL (lduh_d
) FAST (lduh_d
) },
120 { TYPE (INSN_LD_PLUS
), IDX (INSN_LD_PLUS
), FULL (ld_plus
) FAST (ld_plus
) },
121 { TYPE (INSN_LD24
), IDX (INSN_LD24
), FULL (ld24
) FAST (ld24
) },
122 { TYPE (INSN_LDI8
), IDX (INSN_LDI8
), FULL (ldi8
) FAST (ldi8
) },
123 { TYPE (INSN_LDI16
), IDX (INSN_LDI16
), FULL (ldi16
) FAST (ldi16
) },
124 { TYPE (INSN_LOCK
), IDX (INSN_LOCK
), FULL (lock
) FAST (lock
) },
125 { TYPE (INSN_MACHI
), IDX (INSN_MACHI
), FULL (machi
) FAST (machi
) },
126 { TYPE (INSN_MACLO
), IDX (INSN_MACLO
), FULL (maclo
) FAST (maclo
) },
127 { TYPE (INSN_MACWHI
), IDX (INSN_MACWHI
), FULL (macwhi
) FAST (macwhi
) },
128 { TYPE (INSN_MACWLO
), IDX (INSN_MACWLO
), FULL (macwlo
) FAST (macwlo
) },
129 { TYPE (INSN_MUL
), IDX (INSN_MUL
), FULL (mul
) FAST (mul
) },
130 { TYPE (INSN_MULHI
), IDX (INSN_MULHI
), FULL (mulhi
) FAST (mulhi
) },
131 { TYPE (INSN_MULLO
), IDX (INSN_MULLO
), FULL (mullo
) FAST (mullo
) },
132 { TYPE (INSN_MULWHI
), IDX (INSN_MULWHI
), FULL (mulwhi
) FAST (mulwhi
) },
133 { TYPE (INSN_MULWLO
), IDX (INSN_MULWLO
), FULL (mulwlo
) FAST (mulwlo
) },
134 { TYPE (INSN_MV
), IDX (INSN_MV
), FULL (mv
) FAST (mv
) },
135 { TYPE (INSN_MVFACHI
), IDX (INSN_MVFACHI
), FULL (mvfachi
) FAST (mvfachi
) },
136 { TYPE (INSN_MVFACLO
), IDX (INSN_MVFACLO
), FULL (mvfaclo
) FAST (mvfaclo
) },
137 { TYPE (INSN_MVFACMI
), IDX (INSN_MVFACMI
), FULL (mvfacmi
) FAST (mvfacmi
) },
138 { TYPE (INSN_MVFC
), IDX (INSN_MVFC
), FULL (mvfc
) FAST (mvfc
) },
139 { TYPE (INSN_MVTACHI
), IDX (INSN_MVTACHI
), FULL (mvtachi
) FAST (mvtachi
) },
140 { TYPE (INSN_MVTACLO
), IDX (INSN_MVTACLO
), FULL (mvtaclo
) FAST (mvtaclo
) },
141 { TYPE (INSN_MVTC
), IDX (INSN_MVTC
), FULL (mvtc
) FAST (mvtc
) },
142 { TYPE (INSN_NEG
), IDX (INSN_NEG
), FULL (neg
) FAST (neg
) },
143 { TYPE (INSN_NOP
), IDX (INSN_NOP
), FULL (nop
) FAST (nop
) },
144 { TYPE (INSN_NOT
), IDX (INSN_NOT
), FULL (not) FAST (not) },
145 { TYPE (INSN_RAC
), IDX (INSN_RAC
), FULL (rac
) FAST (rac
) },
146 { TYPE (INSN_RACH
), IDX (INSN_RACH
), FULL (rach
) FAST (rach
) },
147 { TYPE (INSN_RTE
), IDX (INSN_RTE
), FULL (rte
) FAST (rte
) },
148 { TYPE (INSN_SETH
), IDX (INSN_SETH
), FULL (seth
) FAST (seth
) },
149 { TYPE (INSN_SLL
), IDX (INSN_SLL
), FULL (sll
) FAST (sll
) },
150 { TYPE (INSN_SLL3
), IDX (INSN_SLL3
), FULL (sll3
) FAST (sll3
) },
151 { TYPE (INSN_SLLI
), IDX (INSN_SLLI
), FULL (slli
) FAST (slli
) },
152 { TYPE (INSN_SRA
), IDX (INSN_SRA
), FULL (sra
) FAST (sra
) },
153 { TYPE (INSN_SRA3
), IDX (INSN_SRA3
), FULL (sra3
) FAST (sra3
) },
154 { TYPE (INSN_SRAI
), IDX (INSN_SRAI
), FULL (srai
) FAST (srai
) },
155 { TYPE (INSN_SRL
), IDX (INSN_SRL
), FULL (srl
) FAST (srl
) },
156 { TYPE (INSN_SRL3
), IDX (INSN_SRL3
), FULL (srl3
) FAST (srl3
) },
157 { TYPE (INSN_SRLI
), IDX (INSN_SRLI
), FULL (srli
) FAST (srli
) },
158 { TYPE (INSN_ST
), IDX (INSN_ST
), FULL (st
) FAST (st
) },
159 { TYPE (INSN_ST_D
), IDX (INSN_ST_D
), FULL (st_d
) FAST (st_d
) },
160 { TYPE (INSN_STB
), IDX (INSN_STB
), FULL (stb
) FAST (stb
) },
161 { TYPE (INSN_STB_D
), IDX (INSN_STB_D
), FULL (stb_d
) FAST (stb_d
) },
162 { TYPE (INSN_STH
), IDX (INSN_STH
), FULL (sth
) FAST (sth
) },
163 { TYPE (INSN_STH_D
), IDX (INSN_STH_D
), FULL (sth_d
) FAST (sth_d
) },
164 { TYPE (INSN_ST_PLUS
), IDX (INSN_ST_PLUS
), FULL (st_plus
) FAST (st_plus
) },
165 { TYPE (INSN_ST_MINUS
), IDX (INSN_ST_MINUS
), FULL (st_minus
) FAST (st_minus
) },
166 { TYPE (INSN_SUB
), IDX (INSN_SUB
), FULL (sub
) FAST (sub
) },
167 { TYPE (INSN_SUBV
), IDX (INSN_SUBV
), FULL (subv
) FAST (subv
) },
168 { TYPE (INSN_SUBX
), IDX (INSN_SUBX
), FULL (subx
) FAST (subx
) },
169 { TYPE (INSN_TRAP
), IDX (INSN_TRAP
), FULL (trap
) FAST (trap
) },
170 { TYPE (INSN_UNLOCK
), IDX (INSN_UNLOCK
), FULL (unlock
) FAST (unlock
) },
173 static const struct insn_sem m32rbf_insn_sem_invalid
=
175 VIRTUAL_INSN_X_INVALID
, IDX (INSN_X_INVALID
), FULL (x_invalid
) FAST (x_invalid
)
181 /* Initialize an IDESC from the compile-time computable parts. */
184 init_idesc (SIM_CPU
*cpu
, IDESC
*id
, const struct insn_sem
*t
)
186 const CGEN_INSN
*insn_table
= CGEN_CPU_INSN_TABLE (CPU_CPU_DESC (cpu
))->init_entries
;
189 if ((int) t
->type
<= 0)
190 id
->idata
= & cgen_virtual_insn_table
[- (int) t
->type
];
192 id
->idata
= & insn_table
[t
->type
];
193 id
->attrs
= CGEN_INSN_ATTRS (id
->idata
);
194 /* Oh my god, a magic number. */
195 id
->length
= CGEN_INSN_BITSIZE (id
->idata
) / 8;
196 #if ! WITH_SEM_SWITCH_FULL
197 id
->sem_full
= t
->sem_full
;
199 #if WITH_FAST && ! WITH_SEM_SWITCH_FAST
200 id
->sem_fast
= t
->sem_fast
;
202 #if WITH_PROFILE_MODEL_P
203 id
->timing
= & MODEL_TIMING (CPU_MODEL (cpu
)) [t
->index
];
205 SIM_DESC sd
= CPU_STATE (cpu
);
206 SIM_ASSERT (t
->index
== id
->timing
->num
);
211 /* Initialize the instruction descriptor table. */
214 m32rbf_init_idesc_table (SIM_CPU
*cpu
)
217 const struct insn_sem
*t
,*tend
;
218 int tabsize
= M32RBF_INSN_MAX
;
219 IDESC
*table
= m32rbf_insn_data
;
221 memset (table
, 0, tabsize
* sizeof (IDESC
));
223 /* First set all entries to the `invalid insn'. */
224 t
= & m32rbf_insn_sem_invalid
;
225 for (id
= table
, tabend
= table
+ tabsize
; id
< tabend
; ++id
)
226 init_idesc (cpu
, id
, t
);
228 /* Now fill in the values for the chosen cpu. */
229 for (t
= m32rbf_insn_sem
, tend
= t
+ sizeof (m32rbf_insn_sem
) / sizeof (*t
);
232 init_idesc (cpu
, & table
[t
->index
], t
);
235 /* Link the IDESC table into the cpu. */
236 CPU_IDESC (cpu
) = table
;
239 /* Enum declaration for all instruction semantic formats. */
241 FMT_EMPTY
, FMT_ADD
, FMT_ADD3
, FMT_AND3
242 , FMT_OR3
, FMT_ADDI
, FMT_ADDV
, FMT_ADDV3
243 , FMT_ADDX
, FMT_BC8
, FMT_BC24
, FMT_BEQ
244 , FMT_BEQZ
, FMT_BL8
, FMT_BL24
, FMT_BRA8
245 , FMT_BRA24
, FMT_CMP
, FMT_CMPI
, FMT_DIV
246 , FMT_JL
, FMT_JMP
, FMT_LD
, FMT_LD_D
247 , FMT_LDB
, FMT_LDB_D
, FMT_LDH
, FMT_LDH_D
248 , FMT_LD_PLUS
, FMT_LD24
, FMT_LDI8
, FMT_LDI16
249 , FMT_LOCK
, FMT_MACHI
, FMT_MULHI
, FMT_MV
250 , FMT_MVFACHI
, FMT_MVFC
, FMT_MVTACHI
, FMT_MVTC
251 , FMT_NOP
, FMT_RAC
, FMT_RTE
, FMT_SETH
252 , FMT_SLL3
, FMT_SLLI
, FMT_ST
, FMT_ST_D
253 , FMT_STB
, FMT_STB_D
, FMT_STH
, FMT_STH_D
254 , FMT_ST_PLUS
, FMT_TRAP
, FMT_UNLOCK
257 /* The decoder uses this to record insns and direct extraction handling. */
268 /* Macro to go from decode phase to extraction phase. */
271 #define GOTO_EXTRACT(id) goto *(id)->sfmt
273 #define GOTO_EXTRACT(id) goto extract
276 /* The decoder needs a slightly different computed goto switch control. */
278 #define DECODE_SWITCH(N, X) goto *labels_##N[X];
280 #define DECODE_SWITCH(N, X) switch (X)
283 /* Given an instruction, return a pointer to its IDESC entry. */
286 m32rbf_decode (SIM_CPU
*current_cpu
, IADDR pc
,
287 CGEN_INSN_INT base_insn
, CGEN_INSN_INT entire_insn
,
290 /* Result of decoder, used by extractor. */
291 const DECODE_DESC
*idecode
;
293 /* First decode the instruction. */
296 #define I(insn) & m32rbf_insn_data[CONCAT2 (M32RBF_,insn)]
298 #define E(fmt) && case_ex_##fmt
302 CGEN_INSN_INT insn
= base_insn
;
303 static const DECODE_DESC idecode_invalid
= { I (INSN_X_INVALID
), E (FMT_EMPTY
) };
307 static const void *labels_0
[256] = {
308 && default_0
, && default_0
, && default_0
, && default_0
,
309 && default_0
, && default_0
, && default_0
, && default_0
,
310 && default_0
, && default_0
, && default_0
, && default_0
,
311 && default_0
, && default_0
, && default_0
, && default_0
,
312 && default_0
, && default_0
, && default_0
, && default_0
,
313 && default_0
, && default_0
, && default_0
, && default_0
,
314 && default_0
, && default_0
, && default_0
, && default_0
,
315 && case_0_28
, && default_0
, && default_0
, && default_0
,
316 && default_0
, && default_0
, && default_0
, && default_0
,
317 && default_0
, && default_0
, && default_0
, && default_0
,
318 && default_0
, && default_0
, && default_0
, && default_0
,
319 && default_0
, && default_0
, && default_0
, && default_0
,
320 && default_0
, && default_0
, && default_0
, && default_0
,
321 && default_0
, && default_0
, && default_0
, && default_0
,
322 && default_0
, && default_0
, && default_0
, && default_0
,
323 && default_0
, && default_0
, && default_0
, && default_0
,
324 && default_0
, && default_0
, && default_0
, && default_0
,
325 && default_0
, && default_0
, && default_0
, && default_0
,
326 && default_0
, && default_0
, && default_0
, && default_0
,
327 && default_0
, && default_0
, && default_0
, && default_0
,
328 && default_0
, && default_0
, && default_0
, && default_0
,
329 && default_0
, && default_0
, && default_0
, && case_0_87
,
330 && default_0
, && default_0
, && default_0
, && default_0
,
331 && default_0
, && default_0
, && default_0
, && case_0_95
,
332 && default_0
, && default_0
, && default_0
, && default_0
,
333 && default_0
, && default_0
, && default_0
, && default_0
,
334 && default_0
, && default_0
, && default_0
, && default_0
,
335 && default_0
, && default_0
, && default_0
, && default_0
,
336 && case_0_112
, && case_0_113
, && case_0_114
, && case_0_115
,
337 && case_0_116
, && case_0_117
, && case_0_118
, && case_0_119
,
338 && case_0_120
, && case_0_121
, && case_0_122
, && case_0_123
,
339 && case_0_124
, && case_0_125
, && case_0_126
, && case_0_127
,
340 && default_0
, && default_0
, && default_0
, && default_0
,
341 && default_0
, && default_0
, && default_0
, && default_0
,
342 && default_0
, && default_0
, && default_0
, && default_0
,
343 && default_0
, && default_0
, && default_0
, && default_0
,
344 && default_0
, && default_0
, && default_0
, && default_0
,
345 && default_0
, && default_0
, && default_0
, && default_0
,
346 && default_0
, && default_0
, && default_0
, && default_0
,
347 && default_0
, && default_0
, && default_0
, && default_0
,
348 && default_0
, && default_0
, && default_0
, && default_0
,
349 && default_0
, && default_0
, && default_0
, && default_0
,
350 && default_0
, && default_0
, && default_0
, && default_0
,
351 && default_0
, && default_0
, && default_0
, && default_0
,
352 && default_0
, && default_0
, && default_0
, && default_0
,
353 && default_0
, && default_0
, && default_0
, && default_0
,
354 && default_0
, && default_0
, && default_0
, && default_0
,
355 && default_0
, && default_0
, && default_0
, && default_0
,
356 && default_0
, && default_0
, && default_0
, && default_0
,
357 && default_0
, && default_0
, && default_0
, && default_0
,
358 && default_0
, && default_0
, && default_0
, && default_0
,
359 && default_0
, && default_0
, && default_0
, && default_0
,
360 && default_0
, && default_0
, && default_0
, && default_0
,
361 && default_0
, && default_0
, && default_0
, && default_0
,
362 && default_0
, && default_0
, && default_0
, && default_0
,
363 && default_0
, && default_0
, && default_0
, && default_0
,
364 && default_0
, && default_0
, && default_0
, && default_0
,
365 && default_0
, && default_0
, && default_0
, && default_0
,
366 && default_0
, && default_0
, && default_0
, && default_0
,
367 && default_0
, && default_0
, && default_0
, && default_0
,
368 && case_0_240
, && case_0_241
, && case_0_242
, && case_0_243
,
369 && case_0_244
, && case_0_245
, && case_0_246
, && case_0_247
,
370 && case_0_248
, && case_0_249
, && case_0_250
, && case_0_251
,
371 && case_0_252
, && case_0_253
, && case_0_254
, && case_0_255
,
374 static const DECODE_DESC insns
[256] = {
375 { I (INSN_SUBV
), E (FMT_ADDV
) }, { I (INSN_SUBX
), E (FMT_ADDX
) },
376 { I (INSN_SUB
), E (FMT_ADD
) }, { I (INSN_NEG
), E (FMT_MV
) },
377 { I (INSN_CMP
), E (FMT_CMP
) }, { I (INSN_CMPU
), E (FMT_CMP
) },
378 { I (INSN_X_INVALID
), E (FMT_EMPTY
) }, { I (INSN_X_INVALID
), E (FMT_EMPTY
) },
379 { I (INSN_ADDV
), E (FMT_ADDV
) }, { I (INSN_ADDX
), E (FMT_ADDX
) },
380 { I (INSN_ADD
), E (FMT_ADD
) }, { I (INSN_NOT
), E (FMT_MV
) },
381 { I (INSN_AND
), E (FMT_ADD
) }, { I (INSN_XOR
), E (FMT_ADD
) },
382 { I (INSN_OR
), E (FMT_ADD
) }, { I (INSN_X_INVALID
), E (FMT_EMPTY
) },
383 { I (INSN_SRL
), E (FMT_ADD
) }, { I (INSN_X_INVALID
), E (FMT_EMPTY
) },
384 { I (INSN_SRA
), E (FMT_ADD
) }, { I (INSN_X_INVALID
), E (FMT_EMPTY
) },
385 { I (INSN_SLL
), E (FMT_ADD
) }, { I (INSN_X_INVALID
), E (FMT_EMPTY
) },
386 { I (INSN_MUL
), E (FMT_ADD
) }, { I (INSN_X_INVALID
), E (FMT_EMPTY
) },
387 { I (INSN_MV
), E (FMT_MV
) }, { I (INSN_MVFC
), E (FMT_MVFC
) },
388 { I (INSN_MVTC
), E (FMT_MVTC
) }, { I (INSN_X_INVALID
), E (FMT_EMPTY
) },
389 { 0 }, { I (INSN_RTE
), E (FMT_RTE
) },
390 { I (INSN_X_INVALID
), E (FMT_EMPTY
) }, { I (INSN_TRAP
), E (FMT_TRAP
) },
391 { I (INSN_STB
), E (FMT_STB
) }, { I (INSN_X_INVALID
), E (FMT_EMPTY
) },
392 { I (INSN_STH
), E (FMT_STH
) }, { I (INSN_X_INVALID
), E (FMT_EMPTY
) },
393 { I (INSN_ST
), E (FMT_ST
) }, { I (INSN_UNLOCK
), E (FMT_UNLOCK
) },
394 { I (INSN_ST_PLUS
), E (FMT_ST_PLUS
) }, { I (INSN_ST_MINUS
), E (FMT_ST_PLUS
) },
395 { I (INSN_LDB
), E (FMT_LDB
) }, { I (INSN_LDUB
), E (FMT_LDB
) },
396 { I (INSN_LDH
), E (FMT_LDH
) }, { I (INSN_LDUH
), E (FMT_LDH
) },
397 { I (INSN_LD
), E (FMT_LD
) }, { I (INSN_LOCK
), E (FMT_LOCK
) },
398 { I (INSN_LD_PLUS
), E (FMT_LD_PLUS
) }, { I (INSN_X_INVALID
), E (FMT_EMPTY
) },
399 { I (INSN_MULHI
), E (FMT_MULHI
) }, { I (INSN_MULLO
), E (FMT_MULHI
) },
400 { I (INSN_MULWHI
), E (FMT_MULHI
) }, { I (INSN_MULWLO
), E (FMT_MULHI
) },
401 { I (INSN_MACHI
), E (FMT_MACHI
) }, { I (INSN_MACLO
), E (FMT_MACHI
) },
402 { I (INSN_MACWHI
), E (FMT_MACHI
) }, { I (INSN_MACWLO
), E (FMT_MACHI
) },
403 { I (INSN_X_INVALID
), E (FMT_EMPTY
) }, { I (INSN_X_INVALID
), E (FMT_EMPTY
) },
404 { I (INSN_X_INVALID
), E (FMT_EMPTY
) }, { I (INSN_X_INVALID
), E (FMT_EMPTY
) },
405 { I (INSN_X_INVALID
), E (FMT_EMPTY
) }, { I (INSN_X_INVALID
), E (FMT_EMPTY
) },
406 { I (INSN_X_INVALID
), E (FMT_EMPTY
) }, { I (INSN_X_INVALID
), E (FMT_EMPTY
) },
407 { I (INSN_ADDI
), E (FMT_ADDI
) }, { I (INSN_ADDI
), E (FMT_ADDI
) },
408 { I (INSN_ADDI
), E (FMT_ADDI
) }, { I (INSN_ADDI
), E (FMT_ADDI
) },
409 { I (INSN_ADDI
), E (FMT_ADDI
) }, { I (INSN_ADDI
), E (FMT_ADDI
) },
410 { I (INSN_ADDI
), E (FMT_ADDI
) }, { I (INSN_ADDI
), E (FMT_ADDI
) },
411 { I (INSN_ADDI
), E (FMT_ADDI
) }, { I (INSN_ADDI
), E (FMT_ADDI
) },
412 { I (INSN_ADDI
), E (FMT_ADDI
) }, { I (INSN_ADDI
), E (FMT_ADDI
) },
413 { I (INSN_ADDI
), E (FMT_ADDI
) }, { I (INSN_ADDI
), E (FMT_ADDI
) },
414 { I (INSN_ADDI
), E (FMT_ADDI
) }, { I (INSN_ADDI
), E (FMT_ADDI
) },
415 { I (INSN_SRLI
), E (FMT_SLLI
) }, { I (INSN_SRLI
), E (FMT_SLLI
) },
416 { I (INSN_SRAI
), E (FMT_SLLI
) }, { I (INSN_SRAI
), E (FMT_SLLI
) },
417 { I (INSN_SLLI
), E (FMT_SLLI
) }, { I (INSN_SLLI
), E (FMT_SLLI
) },
418 { I (INSN_X_INVALID
), E (FMT_EMPTY
) }, { 0 },
419 { I (INSN_RACH
), E (FMT_RAC
) }, { I (INSN_RAC
), E (FMT_RAC
) },
420 { I (INSN_X_INVALID
), E (FMT_EMPTY
) }, { I (INSN_X_INVALID
), E (FMT_EMPTY
) },
421 { I (INSN_X_INVALID
), E (FMT_EMPTY
) }, { I (INSN_X_INVALID
), E (FMT_EMPTY
) },
422 { I (INSN_X_INVALID
), E (FMT_EMPTY
) }, { 0 },
423 { I (INSN_LDI8
), E (FMT_LDI8
) }, { I (INSN_LDI8
), E (FMT_LDI8
) },
424 { I (INSN_LDI8
), E (FMT_LDI8
) }, { I (INSN_LDI8
), E (FMT_LDI8
) },
425 { I (INSN_LDI8
), E (FMT_LDI8
) }, { I (INSN_LDI8
), E (FMT_LDI8
) },
426 { I (INSN_LDI8
), E (FMT_LDI8
) }, { I (INSN_LDI8
), E (FMT_LDI8
) },
427 { I (INSN_LDI8
), E (FMT_LDI8
) }, { I (INSN_LDI8
), E (FMT_LDI8
) },
428 { I (INSN_LDI8
), E (FMT_LDI8
) }, { I (INSN_LDI8
), E (FMT_LDI8
) },
429 { I (INSN_LDI8
), E (FMT_LDI8
) }, { I (INSN_LDI8
), E (FMT_LDI8
) },
430 { I (INSN_LDI8
), E (FMT_LDI8
) }, { I (INSN_LDI8
), E (FMT_LDI8
) },
439 { I (INSN_X_INVALID
), E (FMT_EMPTY
) }, { I (INSN_X_INVALID
), E (FMT_EMPTY
) },
440 { I (INSN_X_INVALID
), E (FMT_EMPTY
) }, { I (INSN_X_INVALID
), E (FMT_EMPTY
) },
441 { I (INSN_CMPI
), E (FMT_CMPI
) }, { I (INSN_CMPUI
), E (FMT_CMPI
) },
442 { I (INSN_X_INVALID
), E (FMT_EMPTY
) }, { I (INSN_X_INVALID
), E (FMT_EMPTY
) },
443 { I (INSN_ADDV3
), E (FMT_ADDV3
) }, { I (INSN_X_INVALID
), E (FMT_EMPTY
) },
444 { I (INSN_ADD3
), E (FMT_ADD3
) }, { I (INSN_X_INVALID
), E (FMT_EMPTY
) },
445 { I (INSN_AND3
), E (FMT_AND3
) }, { I (INSN_XOR3
), E (FMT_AND3
) },
446 { I (INSN_OR3
), E (FMT_OR3
) }, { I (INSN_X_INVALID
), E (FMT_EMPTY
) },
447 { I (INSN_DIV
), E (FMT_DIV
) }, { I (INSN_DIVU
), E (FMT_DIV
) },
448 { I (INSN_REM
), E (FMT_DIV
) }, { I (INSN_REMU
), E (FMT_DIV
) },
449 { I (INSN_X_INVALID
), E (FMT_EMPTY
) }, { I (INSN_X_INVALID
), E (FMT_EMPTY
) },
450 { I (INSN_X_INVALID
), E (FMT_EMPTY
) }, { I (INSN_X_INVALID
), E (FMT_EMPTY
) },
451 { I (INSN_SRL3
), E (FMT_SLL3
) }, { I (INSN_X_INVALID
), E (FMT_EMPTY
) },
452 { I (INSN_SRA3
), E (FMT_SLL3
) }, { I (INSN_X_INVALID
), E (FMT_EMPTY
) },
453 { I (INSN_SLL3
), E (FMT_SLL3
) }, { I (INSN_X_INVALID
), E (FMT_EMPTY
) },
454 { I (INSN_X_INVALID
), E (FMT_EMPTY
) }, { I (INSN_LDI16
), E (FMT_LDI16
) },
455 { I (INSN_STB_D
), E (FMT_STB_D
) }, { I (INSN_X_INVALID
), E (FMT_EMPTY
) },
456 { I (INSN_STH_D
), E (FMT_STH_D
) }, { I (INSN_X_INVALID
), E (FMT_EMPTY
) },
457 { I (INSN_ST_D
), E (FMT_ST_D
) }, { I (INSN_X_INVALID
), E (FMT_EMPTY
) },
458 { I (INSN_X_INVALID
), E (FMT_EMPTY
) }, { I (INSN_X_INVALID
), E (FMT_EMPTY
) },
459 { I (INSN_LDB_D
), E (FMT_LDB_D
) }, { I (INSN_LDUB_D
), E (FMT_LDB_D
) },
460 { I (INSN_LDH_D
), E (FMT_LDH_D
) }, { I (INSN_LDUH_D
), E (FMT_LDH_D
) },
461 { I (INSN_LD_D
), E (FMT_LD_D
) }, { I (INSN_X_INVALID
), E (FMT_EMPTY
) },
462 { I (INSN_X_INVALID
), E (FMT_EMPTY
) }, { I (INSN_X_INVALID
), E (FMT_EMPTY
) },
463 { I (INSN_BEQ
), E (FMT_BEQ
) }, { I (INSN_BNE
), E (FMT_BEQ
) },
464 { I (INSN_X_INVALID
), E (FMT_EMPTY
) }, { I (INSN_X_INVALID
), E (FMT_EMPTY
) },
465 { I (INSN_X_INVALID
), E (FMT_EMPTY
) }, { I (INSN_X_INVALID
), E (FMT_EMPTY
) },
466 { I (INSN_X_INVALID
), E (FMT_EMPTY
) }, { I (INSN_X_INVALID
), E (FMT_EMPTY
) },
467 { I (INSN_BEQZ
), E (FMT_BEQZ
) }, { I (INSN_BNEZ
), E (FMT_BEQZ
) },
468 { I (INSN_BLTZ
), E (FMT_BEQZ
) }, { I (INSN_BGEZ
), E (FMT_BEQZ
) },
469 { I (INSN_BLEZ
), E (FMT_BEQZ
) }, { I (INSN_BGTZ
), E (FMT_BEQZ
) },
470 { I (INSN_X_INVALID
), E (FMT_EMPTY
) }, { I (INSN_X_INVALID
), E (FMT_EMPTY
) },
471 { I (INSN_X_INVALID
), E (FMT_EMPTY
) }, { I (INSN_X_INVALID
), E (FMT_EMPTY
) },
472 { I (INSN_X_INVALID
), E (FMT_EMPTY
) }, { I (INSN_X_INVALID
), E (FMT_EMPTY
) },
473 { I (INSN_X_INVALID
), E (FMT_EMPTY
) }, { I (INSN_X_INVALID
), E (FMT_EMPTY
) },
474 { I (INSN_X_INVALID
), E (FMT_EMPTY
) }, { I (INSN_X_INVALID
), E (FMT_EMPTY
) },
475 { I (INSN_X_INVALID
), E (FMT_EMPTY
) }, { I (INSN_X_INVALID
), E (FMT_EMPTY
) },
476 { I (INSN_X_INVALID
), E (FMT_EMPTY
) }, { I (INSN_X_INVALID
), E (FMT_EMPTY
) },
477 { I (INSN_X_INVALID
), E (FMT_EMPTY
) }, { I (INSN_X_INVALID
), E (FMT_EMPTY
) },
478 { I (INSN_X_INVALID
), E (FMT_EMPTY
) }, { I (INSN_X_INVALID
), E (FMT_EMPTY
) },
479 { I (INSN_X_INVALID
), E (FMT_EMPTY
) }, { I (INSN_X_INVALID
), E (FMT_EMPTY
) },
480 { I (INSN_X_INVALID
), E (FMT_EMPTY
) }, { I (INSN_X_INVALID
), E (FMT_EMPTY
) },
481 { I (INSN_X_INVALID
), E (FMT_EMPTY
) }, { I (INSN_X_INVALID
), E (FMT_EMPTY
) },
482 { I (INSN_X_INVALID
), E (FMT_EMPTY
) }, { I (INSN_X_INVALID
), E (FMT_EMPTY
) },
483 { I (INSN_X_INVALID
), E (FMT_EMPTY
) }, { I (INSN_X_INVALID
), E (FMT_EMPTY
) },
484 { I (INSN_X_INVALID
), E (FMT_EMPTY
) }, { I (INSN_X_INVALID
), E (FMT_EMPTY
) },
485 { I (INSN_SETH
), E (FMT_SETH
) }, { I (INSN_X_INVALID
), E (FMT_EMPTY
) },
486 { I (INSN_X_INVALID
), E (FMT_EMPTY
) }, { I (INSN_X_INVALID
), E (FMT_EMPTY
) },
487 { I (INSN_LD24
), E (FMT_LD24
) }, { I (INSN_LD24
), E (FMT_LD24
) },
488 { I (INSN_LD24
), E (FMT_LD24
) }, { I (INSN_LD24
), E (FMT_LD24
) },
489 { I (INSN_LD24
), E (FMT_LD24
) }, { I (INSN_LD24
), E (FMT_LD24
) },
490 { I (INSN_LD24
), E (FMT_LD24
) }, { I (INSN_LD24
), E (FMT_LD24
) },
491 { I (INSN_LD24
), E (FMT_LD24
) }, { I (INSN_LD24
), E (FMT_LD24
) },
492 { I (INSN_LD24
), E (FMT_LD24
) }, { I (INSN_LD24
), E (FMT_LD24
) },
493 { I (INSN_LD24
), E (FMT_LD24
) }, { I (INSN_LD24
), E (FMT_LD24
) },
494 { I (INSN_LD24
), E (FMT_LD24
) }, { I (INSN_LD24
), E (FMT_LD24
) },
505 val
= (((insn
>> 8) & (15 << 4)) | ((insn
>> 4) & (15 << 0)));
506 DECODE_SWITCH (0, val
)
510 static const DECODE_DESC insns
[16] = {
511 { I (INSN_X_INVALID
), E (FMT_EMPTY
) }, { I (INSN_X_INVALID
), E (FMT_EMPTY
) },
512 { I (INSN_X_INVALID
), E (FMT_EMPTY
) }, { I (INSN_X_INVALID
), E (FMT_EMPTY
) },
513 { I (INSN_X_INVALID
), E (FMT_EMPTY
) }, { I (INSN_X_INVALID
), E (FMT_EMPTY
) },
514 { I (INSN_X_INVALID
), E (FMT_EMPTY
) }, { I (INSN_X_INVALID
), E (FMT_EMPTY
) },
515 { I (INSN_X_INVALID
), E (FMT_EMPTY
) }, { I (INSN_X_INVALID
), E (FMT_EMPTY
) },
516 { I (INSN_X_INVALID
), E (FMT_EMPTY
) }, { I (INSN_X_INVALID
), E (FMT_EMPTY
) },
517 { I (INSN_X_INVALID
), E (FMT_EMPTY
) }, { I (INSN_X_INVALID
), E (FMT_EMPTY
) },
518 { I (INSN_JL
), E (FMT_JL
) }, { I (INSN_JMP
), E (FMT_JMP
) },
520 unsigned int val
= (((insn
>> 8) & (15 << 0)));
521 idecode
= &insns
[val
];
522 GOTO_EXTRACT (idecode
);
526 static const DECODE_DESC insns
[16] = {
527 { I (INSN_MVTACHI
), E (FMT_MVTACHI
) }, { I (INSN_MVTACLO
), E (FMT_MVTACHI
) },
528 { I (INSN_X_INVALID
), E (FMT_EMPTY
) }, { I (INSN_X_INVALID
), E (FMT_EMPTY
) },
529 { I (INSN_X_INVALID
), E (FMT_EMPTY
) }, { I (INSN_X_INVALID
), E (FMT_EMPTY
) },
530 { I (INSN_X_INVALID
), E (FMT_EMPTY
) }, { I (INSN_X_INVALID
), E (FMT_EMPTY
) },
531 { I (INSN_X_INVALID
), E (FMT_EMPTY
) }, { I (INSN_X_INVALID
), E (FMT_EMPTY
) },
532 { I (INSN_X_INVALID
), E (FMT_EMPTY
) }, { I (INSN_X_INVALID
), E (FMT_EMPTY
) },
533 { I (INSN_X_INVALID
), E (FMT_EMPTY
) }, { I (INSN_X_INVALID
), E (FMT_EMPTY
) },
534 { I (INSN_X_INVALID
), E (FMT_EMPTY
) }, { I (INSN_X_INVALID
), E (FMT_EMPTY
) },
536 unsigned int val
= (((insn
>> 0) & (15 << 0)));
537 idecode
= &insns
[val
];
538 GOTO_EXTRACT (idecode
);
542 static const DECODE_DESC insns
[16] = {
543 { I (INSN_MVFACHI
), E (FMT_MVFACHI
) }, { I (INSN_MVFACLO
), E (FMT_MVFACHI
) },
544 { I (INSN_MVFACMI
), E (FMT_MVFACHI
) }, { I (INSN_X_INVALID
), E (FMT_EMPTY
) },
545 { I (INSN_X_INVALID
), E (FMT_EMPTY
) }, { I (INSN_X_INVALID
), E (FMT_EMPTY
) },
546 { I (INSN_X_INVALID
), E (FMT_EMPTY
) }, { I (INSN_X_INVALID
), E (FMT_EMPTY
) },
547 { I (INSN_X_INVALID
), E (FMT_EMPTY
) }, { I (INSN_X_INVALID
), E (FMT_EMPTY
) },
548 { I (INSN_X_INVALID
), E (FMT_EMPTY
) }, { I (INSN_X_INVALID
), E (FMT_EMPTY
) },
549 { I (INSN_X_INVALID
), E (FMT_EMPTY
) }, { I (INSN_X_INVALID
), E (FMT_EMPTY
) },
550 { I (INSN_X_INVALID
), E (FMT_EMPTY
) }, { I (INSN_X_INVALID
), E (FMT_EMPTY
) },
552 unsigned int val
= (((insn
>> 0) & (15 << 0)));
553 idecode
= &insns
[val
];
554 GOTO_EXTRACT (idecode
);
558 static const DECODE_DESC insns
[16] = {
559 { I (INSN_NOP
), E (FMT_NOP
) }, { I (INSN_X_INVALID
), E (FMT_EMPTY
) },
560 { I (INSN_X_INVALID
), E (FMT_EMPTY
) }, { I (INSN_X_INVALID
), E (FMT_EMPTY
) },
561 { I (INSN_X_INVALID
), E (FMT_EMPTY
) }, { I (INSN_X_INVALID
), E (FMT_EMPTY
) },
562 { I (INSN_X_INVALID
), E (FMT_EMPTY
) }, { I (INSN_X_INVALID
), E (FMT_EMPTY
) },
563 { I (INSN_X_INVALID
), E (FMT_EMPTY
) }, { I (INSN_X_INVALID
), E (FMT_EMPTY
) },
564 { I (INSN_X_INVALID
), E (FMT_EMPTY
) }, { I (INSN_X_INVALID
), E (FMT_EMPTY
) },
565 { I (INSN_BC8
), E (FMT_BC8
) }, { I (INSN_BNC8
), E (FMT_BC8
) },
566 { I (INSN_BL8
), E (FMT_BL8
) }, { I (INSN_BRA8
), E (FMT_BRA8
) },
568 unsigned int val
= (((insn
>> 8) & (15 << 0)));
569 idecode
= &insns
[val
];
570 GOTO_EXTRACT (idecode
);
572 CASE (0, 113) : /* fall through */
573 CASE (0, 114) : /* fall through */
574 CASE (0, 115) : /* fall through */
575 CASE (0, 116) : /* fall through */
576 CASE (0, 117) : /* fall through */
577 CASE (0, 118) : /* fall through */
578 CASE (0, 119) : /* fall through */
579 CASE (0, 120) : /* fall through */
580 CASE (0, 121) : /* fall through */
581 CASE (0, 122) : /* fall through */
582 CASE (0, 123) : /* fall through */
583 CASE (0, 124) : /* fall through */
584 CASE (0, 125) : /* fall through */
585 CASE (0, 126) : /* fall through */
588 static const DECODE_DESC insns
[16] = {
589 { I (INSN_X_INVALID
), E (FMT_EMPTY
) }, { I (INSN_X_INVALID
), E (FMT_EMPTY
) },
590 { I (INSN_X_INVALID
), E (FMT_EMPTY
) }, { I (INSN_X_INVALID
), E (FMT_EMPTY
) },
591 { I (INSN_X_INVALID
), E (FMT_EMPTY
) }, { I (INSN_X_INVALID
), E (FMT_EMPTY
) },
592 { I (INSN_X_INVALID
), E (FMT_EMPTY
) }, { I (INSN_X_INVALID
), E (FMT_EMPTY
) },
593 { I (INSN_X_INVALID
), E (FMT_EMPTY
) }, { I (INSN_X_INVALID
), E (FMT_EMPTY
) },
594 { I (INSN_X_INVALID
), E (FMT_EMPTY
) }, { I (INSN_X_INVALID
), E (FMT_EMPTY
) },
595 { I (INSN_BC8
), E (FMT_BC8
) }, { I (INSN_BNC8
), E (FMT_BC8
) },
596 { I (INSN_BL8
), E (FMT_BL8
) }, { I (INSN_BRA8
), E (FMT_BRA8
) },
598 unsigned int val
= (((insn
>> 8) & (15 << 0)));
599 idecode
= &insns
[val
];
600 GOTO_EXTRACT (idecode
);
602 CASE (0, 240) : /* fall through */
603 CASE (0, 241) : /* fall through */
604 CASE (0, 242) : /* fall through */
605 CASE (0, 243) : /* fall through */
606 CASE (0, 244) : /* fall through */
607 CASE (0, 245) : /* fall through */
608 CASE (0, 246) : /* fall through */
609 CASE (0, 247) : /* fall through */
610 CASE (0, 248) : /* fall through */
611 CASE (0, 249) : /* fall through */
612 CASE (0, 250) : /* fall through */
613 CASE (0, 251) : /* fall through */
614 CASE (0, 252) : /* fall through */
615 CASE (0, 253) : /* fall through */
616 CASE (0, 254) : /* fall through */
619 static const DECODE_DESC insns
[16] = {
620 { I (INSN_X_INVALID
), E (FMT_EMPTY
) }, { I (INSN_X_INVALID
), E (FMT_EMPTY
) },
621 { I (INSN_X_INVALID
), E (FMT_EMPTY
) }, { I (INSN_X_INVALID
), E (FMT_EMPTY
) },
622 { I (INSN_X_INVALID
), E (FMT_EMPTY
) }, { I (INSN_X_INVALID
), E (FMT_EMPTY
) },
623 { I (INSN_X_INVALID
), E (FMT_EMPTY
) }, { I (INSN_X_INVALID
), E (FMT_EMPTY
) },
624 { I (INSN_X_INVALID
), E (FMT_EMPTY
) }, { I (INSN_X_INVALID
), E (FMT_EMPTY
) },
625 { I (INSN_X_INVALID
), E (FMT_EMPTY
) }, { I (INSN_X_INVALID
), E (FMT_EMPTY
) },
626 { I (INSN_BC24
), E (FMT_BC24
) }, { I (INSN_BNC24
), E (FMT_BC24
) },
627 { I (INSN_BL24
), E (FMT_BL24
) }, { I (INSN_BRA24
), E (FMT_BRA24
) },
629 unsigned int val
= (((insn
>> 8) & (15 << 0)));
630 idecode
= &insns
[val
];
631 GOTO_EXTRACT (idecode
);
634 idecode
= &insns
[val
];
635 GOTO_EXTRACT (idecode
);
643 /* The instruction has been decoded, now extract the fields. */
648 switch (idecode
->sfmt
)
652 CASE (ex
, FMT_EMPTY
) :
654 CGEN_INSN_INT insn
= entire_insn
;
655 #define FLD(f) abuf->fields.fmt_empty.f
656 EXTRACT_IFMT_EMPTY_VARS
/* */
658 EXTRACT_IFMT_EMPTY_CODE
660 /* Record the fields for the semantic handler. */
661 TRACE_EXTRACT (current_cpu
, abuf
, (current_cpu
, pc
, "fmt_empty", (char *) 0));
669 CGEN_INSN_INT insn
= entire_insn
;
670 #define FLD(f) abuf->fields.fmt_add.f
671 EXTRACT_IFMT_ADD_VARS
/* f-op1 f-r1 f-op2 f-r2 */
673 EXTRACT_IFMT_ADD_CODE
675 /* Record the fields for the semantic handler. */
676 FLD (i_dr
) = & CPU (h_gr
)[f_r1
];
677 FLD (i_sr
) = & CPU (h_gr
)[f_r2
];
678 TRACE_EXTRACT (current_cpu
, abuf
, (current_cpu
, pc
, "fmt_add", "dr 0x%x", 'x', f_r1
, "sr 0x%x", 'x', f_r2
, (char *) 0));
680 #if WITH_PROFILE_MODEL_P
681 /* Record the fields for profiling. */
682 if (PROFILE_MODEL_P (current_cpu
))
693 CASE (ex
, FMT_ADD3
) :
695 CGEN_INSN_INT insn
= entire_insn
;
696 #define FLD(f) abuf->fields.fmt_add3.f
697 EXTRACT_IFMT_ADD3_VARS
/* f-op1 f-r1 f-op2 f-r2 f-simm16 */
699 EXTRACT_IFMT_ADD3_CODE
701 /* Record the fields for the semantic handler. */
702 FLD (f_simm16
) = f_simm16
;
703 FLD (i_sr
) = & CPU (h_gr
)[f_r2
];
704 FLD (i_dr
) = & CPU (h_gr
)[f_r1
];
705 TRACE_EXTRACT (current_cpu
, abuf
, (current_cpu
, pc
, "fmt_add3", "f_simm16 0x%x", 'x', f_simm16
, "sr 0x%x", 'x', f_r2
, "dr 0x%x", 'x', f_r1
, (char *) 0));
707 #if WITH_PROFILE_MODEL_P
708 /* Record the fields for profiling. */
709 if (PROFILE_MODEL_P (current_cpu
))
719 CASE (ex
, FMT_AND3
) :
721 CGEN_INSN_INT insn
= entire_insn
;
722 #define FLD(f) abuf->fields.fmt_and3.f
723 EXTRACT_IFMT_AND3_VARS
/* f-op1 f-r1 f-op2 f-r2 f-uimm16 */
725 EXTRACT_IFMT_AND3_CODE
727 /* Record the fields for the semantic handler. */
728 FLD (f_uimm16
) = f_uimm16
;
729 FLD (i_sr
) = & CPU (h_gr
)[f_r2
];
730 FLD (i_dr
) = & CPU (h_gr
)[f_r1
];
731 TRACE_EXTRACT (current_cpu
, abuf
, (current_cpu
, pc
, "fmt_and3", "f_uimm16 0x%x", 'x', f_uimm16
, "sr 0x%x", 'x', f_r2
, "dr 0x%x", 'x', f_r1
, (char *) 0));
733 #if WITH_PROFILE_MODEL_P
734 /* Record the fields for profiling. */
735 if (PROFILE_MODEL_P (current_cpu
))
747 CGEN_INSN_INT insn
= entire_insn
;
748 #define FLD(f) abuf->fields.fmt_or3.f
749 EXTRACT_IFMT_OR3_VARS
/* f-op1 f-r1 f-op2 f-r2 f-uimm16 */
751 EXTRACT_IFMT_OR3_CODE
753 /* Record the fields for the semantic handler. */
754 FLD (f_uimm16
) = f_uimm16
;
755 FLD (i_sr
) = & CPU (h_gr
)[f_r2
];
756 FLD (i_dr
) = & CPU (h_gr
)[f_r1
];
757 TRACE_EXTRACT (current_cpu
, abuf
, (current_cpu
, pc
, "fmt_or3", "f_uimm16 0x%x", 'x', f_uimm16
, "sr 0x%x", 'x', f_r2
, "dr 0x%x", 'x', f_r1
, (char *) 0));
759 #if WITH_PROFILE_MODEL_P
760 /* Record the fields for profiling. */
761 if (PROFILE_MODEL_P (current_cpu
))
771 CASE (ex
, FMT_ADDI
) :
773 CGEN_INSN_INT insn
= entire_insn
;
774 #define FLD(f) abuf->fields.fmt_addi.f
775 EXTRACT_IFMT_ADDI_VARS
/* f-op1 f-r1 f-simm8 */
777 EXTRACT_IFMT_ADDI_CODE
779 /* Record the fields for the semantic handler. */
780 FLD (f_simm8
) = f_simm8
;
781 FLD (i_dr
) = & CPU (h_gr
)[f_r1
];
782 TRACE_EXTRACT (current_cpu
, abuf
, (current_cpu
, pc
, "fmt_addi", "f_simm8 0x%x", 'x', f_simm8
, "dr 0x%x", 'x', f_r1
, (char *) 0));
784 #if WITH_PROFILE_MODEL_P
785 /* Record the fields for profiling. */
786 if (PROFILE_MODEL_P (current_cpu
))
796 CASE (ex
, FMT_ADDV
) :
798 CGEN_INSN_INT insn
= entire_insn
;
799 #define FLD(f) abuf->fields.fmt_addv.f
800 EXTRACT_IFMT_ADD_VARS
/* f-op1 f-r1 f-op2 f-r2 */
802 EXTRACT_IFMT_ADD_CODE
804 /* Record the fields for the semantic handler. */
805 FLD (i_dr
) = & CPU (h_gr
)[f_r1
];
806 FLD (i_sr
) = & CPU (h_gr
)[f_r2
];
807 TRACE_EXTRACT (current_cpu
, abuf
, (current_cpu
, pc
, "fmt_addv", "dr 0x%x", 'x', f_r1
, "sr 0x%x", 'x', f_r2
, (char *) 0));
809 #if WITH_PROFILE_MODEL_P
810 /* Record the fields for profiling. */
811 if (PROFILE_MODEL_P (current_cpu
))
822 CASE (ex
, FMT_ADDV3
) :
824 CGEN_INSN_INT insn
= entire_insn
;
825 #define FLD(f) abuf->fields.fmt_addv3.f
826 EXTRACT_IFMT_ADDV3_VARS
/* f-op1 f-r1 f-op2 f-r2 f-simm16 */
828 EXTRACT_IFMT_ADDV3_CODE
830 /* Record the fields for the semantic handler. */
831 FLD (f_simm16
) = f_simm16
;
832 FLD (i_sr
) = & CPU (h_gr
)[f_r2
];
833 FLD (i_dr
) = & CPU (h_gr
)[f_r1
];
834 TRACE_EXTRACT (current_cpu
, abuf
, (current_cpu
, pc
, "fmt_addv3", "f_simm16 0x%x", 'x', f_simm16
, "sr 0x%x", 'x', f_r2
, "dr 0x%x", 'x', f_r1
, (char *) 0));
836 #if WITH_PROFILE_MODEL_P
837 /* Record the fields for profiling. */
838 if (PROFILE_MODEL_P (current_cpu
))
848 CASE (ex
, FMT_ADDX
) :
850 CGEN_INSN_INT insn
= entire_insn
;
851 #define FLD(f) abuf->fields.fmt_addx.f
852 EXTRACT_IFMT_ADD_VARS
/* f-op1 f-r1 f-op2 f-r2 */
854 EXTRACT_IFMT_ADD_CODE
856 /* Record the fields for the semantic handler. */
857 FLD (i_dr
) = & CPU (h_gr
)[f_r1
];
858 FLD (i_sr
) = & CPU (h_gr
)[f_r2
];
859 TRACE_EXTRACT (current_cpu
, abuf
, (current_cpu
, pc
, "fmt_addx", "dr 0x%x", 'x', f_r1
, "sr 0x%x", 'x', f_r2
, (char *) 0));
861 #if WITH_PROFILE_MODEL_P
862 /* Record the fields for profiling. */
863 if (PROFILE_MODEL_P (current_cpu
))
876 CGEN_INSN_INT insn
= entire_insn
;
877 #define FLD(f) abuf->fields.cti.fields.fmt_bc8.f
878 EXTRACT_IFMT_BC8_VARS
/* f-op1 f-r1 f-disp8 */
880 EXTRACT_IFMT_BC8_CODE
882 /* Record the fields for the semantic handler. */
883 FLD (i_disp8
) = f_disp8
;
884 SEM_BRANCH_INIT_EXTRACT (abuf
);
885 TRACE_EXTRACT (current_cpu
, abuf
, (current_cpu
, pc
, "fmt_bc8", "disp8 0x%x", 'x', f_disp8
, (char *) 0));
887 #if WITH_PROFILE_MODEL_P
888 /* Record the fields for profiling. */
889 if (PROFILE_MODEL_P (current_cpu
))
897 CASE (ex
, FMT_BC24
) :
899 CGEN_INSN_INT insn
= entire_insn
;
900 #define FLD(f) abuf->fields.cti.fields.fmt_bc24.f
901 EXTRACT_IFMT_BC24_VARS
/* f-op1 f-r1 f-disp24 */
903 EXTRACT_IFMT_BC24_CODE
905 /* Record the fields for the semantic handler. */
906 FLD (i_disp24
) = f_disp24
;
907 SEM_BRANCH_INIT_EXTRACT (abuf
);
908 TRACE_EXTRACT (current_cpu
, abuf
, (current_cpu
, pc
, "fmt_bc24", "disp24 0x%x", 'x', f_disp24
, (char *) 0));
910 #if WITH_PROFILE_MODEL_P
911 /* Record the fields for profiling. */
912 if (PROFILE_MODEL_P (current_cpu
))
922 CGEN_INSN_INT insn
= entire_insn
;
923 #define FLD(f) abuf->fields.cti.fields.fmt_beq.f
924 EXTRACT_IFMT_BEQ_VARS
/* f-op1 f-r1 f-op2 f-r2 f-disp16 */
926 EXTRACT_IFMT_BEQ_CODE
928 /* Record the fields for the semantic handler. */
929 FLD (i_disp16
) = f_disp16
;
930 FLD (i_src1
) = & CPU (h_gr
)[f_r1
];
931 FLD (i_src2
) = & CPU (h_gr
)[f_r2
];
932 SEM_BRANCH_INIT_EXTRACT (abuf
);
933 TRACE_EXTRACT (current_cpu
, abuf
, (current_cpu
, pc
, "fmt_beq", "disp16 0x%x", 'x', f_disp16
, "src1 0x%x", 'x', f_r1
, "src2 0x%x", 'x', f_r2
, (char *) 0));
935 #if WITH_PROFILE_MODEL_P
936 /* Record the fields for profiling. */
937 if (PROFILE_MODEL_P (current_cpu
))
939 FLD (in_src1
) = f_r1
;
940 FLD (in_src2
) = f_r2
;
947 CASE (ex
, FMT_BEQZ
) :
949 CGEN_INSN_INT insn
= entire_insn
;
950 #define FLD(f) abuf->fields.cti.fields.fmt_beqz.f
951 EXTRACT_IFMT_BEQZ_VARS
/* f-op1 f-r1 f-op2 f-r2 f-disp16 */
953 EXTRACT_IFMT_BEQZ_CODE
955 /* Record the fields for the semantic handler. */
956 FLD (i_disp16
) = f_disp16
;
957 FLD (i_src2
) = & CPU (h_gr
)[f_r2
];
958 SEM_BRANCH_INIT_EXTRACT (abuf
);
959 TRACE_EXTRACT (current_cpu
, abuf
, (current_cpu
, pc
, "fmt_beqz", "disp16 0x%x", 'x', f_disp16
, "src2 0x%x", 'x', f_r2
, (char *) 0));
961 #if WITH_PROFILE_MODEL_P
962 /* Record the fields for profiling. */
963 if (PROFILE_MODEL_P (current_cpu
))
965 FLD (in_src2
) = f_r2
;
974 CGEN_INSN_INT insn
= entire_insn
;
975 #define FLD(f) abuf->fields.cti.fields.fmt_bl8.f
976 EXTRACT_IFMT_BC8_VARS
/* f-op1 f-r1 f-disp8 */
978 EXTRACT_IFMT_BC8_CODE
980 /* Record the fields for the semantic handler. */
981 FLD (i_disp8
) = f_disp8
;
982 SEM_BRANCH_INIT_EXTRACT (abuf
);
983 TRACE_EXTRACT (current_cpu
, abuf
, (current_cpu
, pc
, "fmt_bl8", "disp8 0x%x", 'x', f_disp8
, (char *) 0));
985 #if WITH_PROFILE_MODEL_P
986 /* Record the fields for profiling. */
987 if (PROFILE_MODEL_P (current_cpu
))
989 FLD (out_h_gr_14
) = 14;
996 CASE (ex
, FMT_BL24
) :
998 CGEN_INSN_INT insn
= entire_insn
;
999 #define FLD(f) abuf->fields.cti.fields.fmt_bl24.f
1000 EXTRACT_IFMT_BC24_VARS
/* f-op1 f-r1 f-disp24 */
1002 EXTRACT_IFMT_BC24_CODE
1004 /* Record the fields for the semantic handler. */
1005 FLD (i_disp24
) = f_disp24
;
1006 SEM_BRANCH_INIT_EXTRACT (abuf
);
1007 TRACE_EXTRACT (current_cpu
, abuf
, (current_cpu
, pc
, "fmt_bl24", "disp24 0x%x", 'x', f_disp24
, (char *) 0));
1009 #if WITH_PROFILE_MODEL_P
1010 /* Record the fields for profiling. */
1011 if (PROFILE_MODEL_P (current_cpu
))
1013 FLD (out_h_gr_14
) = 14;
1020 CASE (ex
, FMT_BRA8
) :
1022 CGEN_INSN_INT insn
= entire_insn
;
1023 #define FLD(f) abuf->fields.cti.fields.fmt_bra8.f
1024 EXTRACT_IFMT_BC8_VARS
/* f-op1 f-r1 f-disp8 */
1026 EXTRACT_IFMT_BC8_CODE
1028 /* Record the fields for the semantic handler. */
1029 FLD (i_disp8
) = f_disp8
;
1030 SEM_BRANCH_INIT_EXTRACT (abuf
);
1031 TRACE_EXTRACT (current_cpu
, abuf
, (current_cpu
, pc
, "fmt_bra8", "disp8 0x%x", 'x', f_disp8
, (char *) 0));
1033 #if WITH_PROFILE_MODEL_P
1034 /* Record the fields for profiling. */
1035 if (PROFILE_MODEL_P (current_cpu
))
1043 CASE (ex
, FMT_BRA24
) :
1045 CGEN_INSN_INT insn
= entire_insn
;
1046 #define FLD(f) abuf->fields.cti.fields.fmt_bra24.f
1047 EXTRACT_IFMT_BC24_VARS
/* f-op1 f-r1 f-disp24 */
1049 EXTRACT_IFMT_BC24_CODE
1051 /* Record the fields for the semantic handler. */
1052 FLD (i_disp24
) = f_disp24
;
1053 SEM_BRANCH_INIT_EXTRACT (abuf
);
1054 TRACE_EXTRACT (current_cpu
, abuf
, (current_cpu
, pc
, "fmt_bra24", "disp24 0x%x", 'x', f_disp24
, (char *) 0));
1056 #if WITH_PROFILE_MODEL_P
1057 /* Record the fields for profiling. */
1058 if (PROFILE_MODEL_P (current_cpu
))
1066 CASE (ex
, FMT_CMP
) :
1068 CGEN_INSN_INT insn
= entire_insn
;
1069 #define FLD(f) abuf->fields.fmt_cmp.f
1070 EXTRACT_IFMT_CMP_VARS
/* f-op1 f-r1 f-op2 f-r2 */
1072 EXTRACT_IFMT_CMP_CODE
1074 /* Record the fields for the semantic handler. */
1075 FLD (i_src1
) = & CPU (h_gr
)[f_r1
];
1076 FLD (i_src2
) = & CPU (h_gr
)[f_r2
];
1077 TRACE_EXTRACT (current_cpu
, abuf
, (current_cpu
, pc
, "fmt_cmp", "src1 0x%x", 'x', f_r1
, "src2 0x%x", 'x', f_r2
, (char *) 0));
1079 #if WITH_PROFILE_MODEL_P
1080 /* Record the fields for profiling. */
1081 if (PROFILE_MODEL_P (current_cpu
))
1083 FLD (in_src1
) = f_r1
;
1084 FLD (in_src2
) = f_r2
;
1091 CASE (ex
, FMT_CMPI
) :
1093 CGEN_INSN_INT insn
= entire_insn
;
1094 #define FLD(f) abuf->fields.fmt_cmpi.f
1095 EXTRACT_IFMT_CMPI_VARS
/* f-op1 f-r1 f-op2 f-r2 f-simm16 */
1097 EXTRACT_IFMT_CMPI_CODE
1099 /* Record the fields for the semantic handler. */
1100 FLD (f_simm16
) = f_simm16
;
1101 FLD (i_src2
) = & CPU (h_gr
)[f_r2
];
1102 TRACE_EXTRACT (current_cpu
, abuf
, (current_cpu
, pc
, "fmt_cmpi", "f_simm16 0x%x", 'x', f_simm16
, "src2 0x%x", 'x', f_r2
, (char *) 0));
1104 #if WITH_PROFILE_MODEL_P
1105 /* Record the fields for profiling. */
1106 if (PROFILE_MODEL_P (current_cpu
))
1108 FLD (in_src2
) = f_r2
;
1115 CASE (ex
, FMT_DIV
) :
1117 CGEN_INSN_INT insn
= entire_insn
;
1118 #define FLD(f) abuf->fields.fmt_div.f
1119 EXTRACT_IFMT_DIV_VARS
/* f-op1 f-r1 f-op2 f-r2 f-simm16 */
1121 EXTRACT_IFMT_DIV_CODE
1123 /* Record the fields for the semantic handler. */
1124 FLD (i_dr
) = & CPU (h_gr
)[f_r1
];
1125 FLD (i_sr
) = & CPU (h_gr
)[f_r2
];
1126 TRACE_EXTRACT (current_cpu
, abuf
, (current_cpu
, pc
, "fmt_div", "dr 0x%x", 'x', f_r1
, "sr 0x%x", 'x', f_r2
, (char *) 0));
1128 #if WITH_PROFILE_MODEL_P
1129 /* Record the fields for profiling. */
1130 if (PROFILE_MODEL_P (current_cpu
))
1134 FLD (out_dr
) = f_r1
;
1143 CGEN_INSN_INT insn
= entire_insn
;
1144 #define FLD(f) abuf->fields.cti.fields.fmt_jl.f
1145 EXTRACT_IFMT_JL_VARS
/* f-op1 f-r1 f-op2 f-r2 */
1147 EXTRACT_IFMT_JL_CODE
1149 /* Record the fields for the semantic handler. */
1150 FLD (i_sr
) = & CPU (h_gr
)[f_r2
];
1151 SEM_BRANCH_INIT_EXTRACT (abuf
);
1152 TRACE_EXTRACT (current_cpu
, abuf
, (current_cpu
, pc
, "fmt_jl", "sr 0x%x", 'x', f_r2
, (char *) 0));
1154 #if WITH_PROFILE_MODEL_P
1155 /* Record the fields for profiling. */
1156 if (PROFILE_MODEL_P (current_cpu
))
1159 FLD (out_h_gr_14
) = 14;
1166 CASE (ex
, FMT_JMP
) :
1168 CGEN_INSN_INT insn
= entire_insn
;
1169 #define FLD(f) abuf->fields.cti.fields.fmt_jmp.f
1170 EXTRACT_IFMT_JL_VARS
/* f-op1 f-r1 f-op2 f-r2 */
1172 EXTRACT_IFMT_JL_CODE
1174 /* Record the fields for the semantic handler. */
1175 FLD (i_sr
) = & CPU (h_gr
)[f_r2
];
1176 SEM_BRANCH_INIT_EXTRACT (abuf
);
1177 TRACE_EXTRACT (current_cpu
, abuf
, (current_cpu
, pc
, "fmt_jmp", "sr 0x%x", 'x', f_r2
, (char *) 0));
1179 #if WITH_PROFILE_MODEL_P
1180 /* Record the fields for profiling. */
1181 if (PROFILE_MODEL_P (current_cpu
))
1192 CGEN_INSN_INT insn
= entire_insn
;
1193 #define FLD(f) abuf->fields.fmt_ld.f
1194 EXTRACT_IFMT_ADD_VARS
/* f-op1 f-r1 f-op2 f-r2 */
1196 EXTRACT_IFMT_ADD_CODE
1198 /* Record the fields for the semantic handler. */
1199 FLD (i_sr
) = & CPU (h_gr
)[f_r2
];
1200 FLD (i_dr
) = & CPU (h_gr
)[f_r1
];
1201 TRACE_EXTRACT (current_cpu
, abuf
, (current_cpu
, pc
, "fmt_ld", "sr 0x%x", 'x', f_r2
, "dr 0x%x", 'x', f_r1
, (char *) 0));
1203 #if WITH_PROFILE_MODEL_P
1204 /* Record the fields for profiling. */
1205 if (PROFILE_MODEL_P (current_cpu
))
1208 FLD (out_dr
) = f_r1
;
1215 CASE (ex
, FMT_LD_D
) :
1217 CGEN_INSN_INT insn
= entire_insn
;
1218 #define FLD(f) abuf->fields.fmt_ld_d.f
1219 EXTRACT_IFMT_ADD3_VARS
/* f-op1 f-r1 f-op2 f-r2 f-simm16 */
1221 EXTRACT_IFMT_ADD3_CODE
1223 /* Record the fields for the semantic handler. */
1224 FLD (f_simm16
) = f_simm16
;
1225 FLD (i_sr
) = & CPU (h_gr
)[f_r2
];
1226 FLD (i_dr
) = & CPU (h_gr
)[f_r1
];
1227 TRACE_EXTRACT (current_cpu
, abuf
, (current_cpu
, pc
, "fmt_ld_d", "f_simm16 0x%x", 'x', f_simm16
, "sr 0x%x", 'x', f_r2
, "dr 0x%x", 'x', f_r1
, (char *) 0));
1229 #if WITH_PROFILE_MODEL_P
1230 /* Record the fields for profiling. */
1231 if (PROFILE_MODEL_P (current_cpu
))
1234 FLD (out_dr
) = f_r1
;
1241 CASE (ex
, FMT_LDB
) :
1243 CGEN_INSN_INT insn
= entire_insn
;
1244 #define FLD(f) abuf->fields.fmt_ldb.f
1245 EXTRACT_IFMT_ADD_VARS
/* f-op1 f-r1 f-op2 f-r2 */
1247 EXTRACT_IFMT_ADD_CODE
1249 /* Record the fields for the semantic handler. */
1250 FLD (i_sr
) = & CPU (h_gr
)[f_r2
];
1251 FLD (i_dr
) = & CPU (h_gr
)[f_r1
];
1252 TRACE_EXTRACT (current_cpu
, abuf
, (current_cpu
, pc
, "fmt_ldb", "sr 0x%x", 'x', f_r2
, "dr 0x%x", 'x', f_r1
, (char *) 0));
1254 #if WITH_PROFILE_MODEL_P
1255 /* Record the fields for profiling. */
1256 if (PROFILE_MODEL_P (current_cpu
))
1259 FLD (out_dr
) = f_r1
;
1266 CASE (ex
, FMT_LDB_D
) :
1268 CGEN_INSN_INT insn
= entire_insn
;
1269 #define FLD(f) abuf->fields.fmt_ldb_d.f
1270 EXTRACT_IFMT_ADD3_VARS
/* f-op1 f-r1 f-op2 f-r2 f-simm16 */
1272 EXTRACT_IFMT_ADD3_CODE
1274 /* Record the fields for the semantic handler. */
1275 FLD (f_simm16
) = f_simm16
;
1276 FLD (i_sr
) = & CPU (h_gr
)[f_r2
];
1277 FLD (i_dr
) = & CPU (h_gr
)[f_r1
];
1278 TRACE_EXTRACT (current_cpu
, abuf
, (current_cpu
, pc
, "fmt_ldb_d", "f_simm16 0x%x", 'x', f_simm16
, "sr 0x%x", 'x', f_r2
, "dr 0x%x", 'x', f_r1
, (char *) 0));
1280 #if WITH_PROFILE_MODEL_P
1281 /* Record the fields for profiling. */
1282 if (PROFILE_MODEL_P (current_cpu
))
1285 FLD (out_dr
) = f_r1
;
1292 CASE (ex
, FMT_LDH
) :
1294 CGEN_INSN_INT insn
= entire_insn
;
1295 #define FLD(f) abuf->fields.fmt_ldh.f
1296 EXTRACT_IFMT_ADD_VARS
/* f-op1 f-r1 f-op2 f-r2 */
1298 EXTRACT_IFMT_ADD_CODE
1300 /* Record the fields for the semantic handler. */
1301 FLD (i_sr
) = & CPU (h_gr
)[f_r2
];
1302 FLD (i_dr
) = & CPU (h_gr
)[f_r1
];
1303 TRACE_EXTRACT (current_cpu
, abuf
, (current_cpu
, pc
, "fmt_ldh", "sr 0x%x", 'x', f_r2
, "dr 0x%x", 'x', f_r1
, (char *) 0));
1305 #if WITH_PROFILE_MODEL_P
1306 /* Record the fields for profiling. */
1307 if (PROFILE_MODEL_P (current_cpu
))
1310 FLD (out_dr
) = f_r1
;
1317 CASE (ex
, FMT_LDH_D
) :
1319 CGEN_INSN_INT insn
= entire_insn
;
1320 #define FLD(f) abuf->fields.fmt_ldh_d.f
1321 EXTRACT_IFMT_ADD3_VARS
/* f-op1 f-r1 f-op2 f-r2 f-simm16 */
1323 EXTRACT_IFMT_ADD3_CODE
1325 /* Record the fields for the semantic handler. */
1326 FLD (f_simm16
) = f_simm16
;
1327 FLD (i_sr
) = & CPU (h_gr
)[f_r2
];
1328 FLD (i_dr
) = & CPU (h_gr
)[f_r1
];
1329 TRACE_EXTRACT (current_cpu
, abuf
, (current_cpu
, pc
, "fmt_ldh_d", "f_simm16 0x%x", 'x', f_simm16
, "sr 0x%x", 'x', f_r2
, "dr 0x%x", 'x', f_r1
, (char *) 0));
1331 #if WITH_PROFILE_MODEL_P
1332 /* Record the fields for profiling. */
1333 if (PROFILE_MODEL_P (current_cpu
))
1336 FLD (out_dr
) = f_r1
;
1343 CASE (ex
, FMT_LD_PLUS
) :
1345 CGEN_INSN_INT insn
= entire_insn
;
1346 #define FLD(f) abuf->fields.fmt_ld_plus.f
1347 EXTRACT_IFMT_ADD_VARS
/* f-op1 f-r1 f-op2 f-r2 */
1349 EXTRACT_IFMT_ADD_CODE
1351 /* Record the fields for the semantic handler. */
1352 FLD (i_sr
) = & CPU (h_gr
)[f_r2
];
1353 FLD (i_dr
) = & CPU (h_gr
)[f_r1
];
1354 TRACE_EXTRACT (current_cpu
, abuf
, (current_cpu
, pc
, "fmt_ld_plus", "sr 0x%x", 'x', f_r2
, "dr 0x%x", 'x', f_r1
, (char *) 0));
1356 #if WITH_PROFILE_MODEL_P
1357 /* Record the fields for profiling. */
1358 if (PROFILE_MODEL_P (current_cpu
))
1361 FLD (out_dr
) = f_r1
;
1362 FLD (out_sr
) = f_r2
;
1369 CASE (ex
, FMT_LD24
) :
1371 CGEN_INSN_INT insn
= entire_insn
;
1372 #define FLD(f) abuf->fields.fmt_ld24.f
1373 EXTRACT_IFMT_LD24_VARS
/* f-op1 f-r1 f-uimm24 */
1375 EXTRACT_IFMT_LD24_CODE
1377 /* Record the fields for the semantic handler. */
1378 FLD (i_uimm24
) = f_uimm24
;
1379 FLD (i_dr
) = & CPU (h_gr
)[f_r1
];
1380 TRACE_EXTRACT (current_cpu
, abuf
, (current_cpu
, pc
, "fmt_ld24", "uimm24 0x%x", 'x', f_uimm24
, "dr 0x%x", 'x', f_r1
, (char *) 0));
1382 #if WITH_PROFILE_MODEL_P
1383 /* Record the fields for profiling. */
1384 if (PROFILE_MODEL_P (current_cpu
))
1386 FLD (out_dr
) = f_r1
;
1393 CASE (ex
, FMT_LDI8
) :
1395 CGEN_INSN_INT insn
= entire_insn
;
1396 #define FLD(f) abuf->fields.fmt_ldi8.f
1397 EXTRACT_IFMT_ADDI_VARS
/* f-op1 f-r1 f-simm8 */
1399 EXTRACT_IFMT_ADDI_CODE
1401 /* Record the fields for the semantic handler. */
1402 FLD (f_simm8
) = f_simm8
;
1403 FLD (i_dr
) = & CPU (h_gr
)[f_r1
];
1404 TRACE_EXTRACT (current_cpu
, abuf
, (current_cpu
, pc
, "fmt_ldi8", "f_simm8 0x%x", 'x', f_simm8
, "dr 0x%x", 'x', f_r1
, (char *) 0));
1406 #if WITH_PROFILE_MODEL_P
1407 /* Record the fields for profiling. */
1408 if (PROFILE_MODEL_P (current_cpu
))
1410 FLD (out_dr
) = f_r1
;
1417 CASE (ex
, FMT_LDI16
) :
1419 CGEN_INSN_INT insn
= entire_insn
;
1420 #define FLD(f) abuf->fields.fmt_ldi16.f
1421 EXTRACT_IFMT_LDI16_VARS
/* f-op1 f-r1 f-op2 f-r2 f-simm16 */
1423 EXTRACT_IFMT_LDI16_CODE
1425 /* Record the fields for the semantic handler. */
1426 FLD (f_simm16
) = f_simm16
;
1427 FLD (i_dr
) = & CPU (h_gr
)[f_r1
];
1428 TRACE_EXTRACT (current_cpu
, abuf
, (current_cpu
, pc
, "fmt_ldi16", "f_simm16 0x%x", 'x', f_simm16
, "dr 0x%x", 'x', f_r1
, (char *) 0));
1430 #if WITH_PROFILE_MODEL_P
1431 /* Record the fields for profiling. */
1432 if (PROFILE_MODEL_P (current_cpu
))
1434 FLD (out_dr
) = f_r1
;
1441 CASE (ex
, FMT_LOCK
) :
1443 CGEN_INSN_INT insn
= entire_insn
;
1444 #define FLD(f) abuf->fields.fmt_lock.f
1445 EXTRACT_IFMT_ADD_VARS
/* f-op1 f-r1 f-op2 f-r2 */
1447 EXTRACT_IFMT_ADD_CODE
1449 /* Record the fields for the semantic handler. */
1450 FLD (i_sr
) = & CPU (h_gr
)[f_r2
];
1451 FLD (i_dr
) = & CPU (h_gr
)[f_r1
];
1452 TRACE_EXTRACT (current_cpu
, abuf
, (current_cpu
, pc
, "fmt_lock", "sr 0x%x", 'x', f_r2
, "dr 0x%x", 'x', f_r1
, (char *) 0));
1454 #if WITH_PROFILE_MODEL_P
1455 /* Record the fields for profiling. */
1456 if (PROFILE_MODEL_P (current_cpu
))
1459 FLD (out_dr
) = f_r1
;
1466 CASE (ex
, FMT_MACHI
) :
1468 CGEN_INSN_INT insn
= entire_insn
;
1469 #define FLD(f) abuf->fields.fmt_machi.f
1470 EXTRACT_IFMT_CMP_VARS
/* f-op1 f-r1 f-op2 f-r2 */
1472 EXTRACT_IFMT_CMP_CODE
1474 /* Record the fields for the semantic handler. */
1475 FLD (i_src1
) = & CPU (h_gr
)[f_r1
];
1476 FLD (i_src2
) = & CPU (h_gr
)[f_r2
];
1477 TRACE_EXTRACT (current_cpu
, abuf
, (current_cpu
, pc
, "fmt_machi", "src1 0x%x", 'x', f_r1
, "src2 0x%x", 'x', f_r2
, (char *) 0));
1479 #if WITH_PROFILE_MODEL_P
1480 /* Record the fields for profiling. */
1481 if (PROFILE_MODEL_P (current_cpu
))
1483 FLD (in_src1
) = f_r1
;
1484 FLD (in_src2
) = f_r2
;
1491 CASE (ex
, FMT_MULHI
) :
1493 CGEN_INSN_INT insn
= entire_insn
;
1494 #define FLD(f) abuf->fields.fmt_mulhi.f
1495 EXTRACT_IFMT_CMP_VARS
/* f-op1 f-r1 f-op2 f-r2 */
1497 EXTRACT_IFMT_CMP_CODE
1499 /* Record the fields for the semantic handler. */
1500 FLD (i_src1
) = & CPU (h_gr
)[f_r1
];
1501 FLD (i_src2
) = & CPU (h_gr
)[f_r2
];
1502 TRACE_EXTRACT (current_cpu
, abuf
, (current_cpu
, pc
, "fmt_mulhi", "src1 0x%x", 'x', f_r1
, "src2 0x%x", 'x', f_r2
, (char *) 0));
1504 #if WITH_PROFILE_MODEL_P
1505 /* Record the fields for profiling. */
1506 if (PROFILE_MODEL_P (current_cpu
))
1508 FLD (in_src1
) = f_r1
;
1509 FLD (in_src2
) = f_r2
;
1518 CGEN_INSN_INT insn
= entire_insn
;
1519 #define FLD(f) abuf->fields.fmt_mv.f
1520 EXTRACT_IFMT_ADD_VARS
/* f-op1 f-r1 f-op2 f-r2 */
1522 EXTRACT_IFMT_ADD_CODE
1524 /* Record the fields for the semantic handler. */
1525 FLD (i_sr
) = & CPU (h_gr
)[f_r2
];
1526 FLD (i_dr
) = & CPU (h_gr
)[f_r1
];
1527 TRACE_EXTRACT (current_cpu
, abuf
, (current_cpu
, pc
, "fmt_mv", "sr 0x%x", 'x', f_r2
, "dr 0x%x", 'x', f_r1
, (char *) 0));
1529 #if WITH_PROFILE_MODEL_P
1530 /* Record the fields for profiling. */
1531 if (PROFILE_MODEL_P (current_cpu
))
1534 FLD (out_dr
) = f_r1
;
1541 CASE (ex
, FMT_MVFACHI
) :
1543 CGEN_INSN_INT insn
= entire_insn
;
1544 #define FLD(f) abuf->fields.fmt_mvfachi.f
1545 EXTRACT_IFMT_MVFACHI_VARS
/* f-op1 f-r1 f-op2 f-r2 */
1547 EXTRACT_IFMT_MVFACHI_CODE
1549 /* Record the fields for the semantic handler. */
1550 FLD (i_dr
) = & CPU (h_gr
)[f_r1
];
1551 TRACE_EXTRACT (current_cpu
, abuf
, (current_cpu
, pc
, "fmt_mvfachi", "dr 0x%x", 'x', f_r1
, (char *) 0));
1553 #if WITH_PROFILE_MODEL_P
1554 /* Record the fields for profiling. */
1555 if (PROFILE_MODEL_P (current_cpu
))
1557 FLD (out_dr
) = f_r1
;
1564 CASE (ex
, FMT_MVFC
) :
1566 CGEN_INSN_INT insn
= entire_insn
;
1567 #define FLD(f) abuf->fields.fmt_mvfc.f
1568 EXTRACT_IFMT_MVFC_VARS
/* f-op1 f-r1 f-op2 f-r2 */
1570 EXTRACT_IFMT_MVFC_CODE
1572 /* Record the fields for the semantic handler. */
1574 FLD (i_dr
) = & CPU (h_gr
)[f_r1
];
1575 TRACE_EXTRACT (current_cpu
, abuf
, (current_cpu
, pc
, "fmt_mvfc", "f_r2 0x%x", 'x', f_r2
, "dr 0x%x", 'x', f_r1
, (char *) 0));
1577 #if WITH_PROFILE_MODEL_P
1578 /* Record the fields for profiling. */
1579 if (PROFILE_MODEL_P (current_cpu
))
1581 FLD (out_dr
) = f_r1
;
1588 CASE (ex
, FMT_MVTACHI
) :
1590 CGEN_INSN_INT insn
= entire_insn
;
1591 #define FLD(f) abuf->fields.fmt_mvtachi.f
1592 EXTRACT_IFMT_MVTACHI_VARS
/* f-op1 f-r1 f-op2 f-r2 */
1594 EXTRACT_IFMT_MVTACHI_CODE
1596 /* Record the fields for the semantic handler. */
1597 FLD (i_src1
) = & CPU (h_gr
)[f_r1
];
1598 TRACE_EXTRACT (current_cpu
, abuf
, (current_cpu
, pc
, "fmt_mvtachi", "src1 0x%x", 'x', f_r1
, (char *) 0));
1600 #if WITH_PROFILE_MODEL_P
1601 /* Record the fields for profiling. */
1602 if (PROFILE_MODEL_P (current_cpu
))
1604 FLD (in_src1
) = f_r1
;
1611 CASE (ex
, FMT_MVTC
) :
1613 CGEN_INSN_INT insn
= entire_insn
;
1614 #define FLD(f) abuf->fields.fmt_mvtc.f
1615 EXTRACT_IFMT_MVTC_VARS
/* f-op1 f-r1 f-op2 f-r2 */
1617 EXTRACT_IFMT_MVTC_CODE
1619 /* Record the fields for the semantic handler. */
1621 FLD (i_sr
) = & CPU (h_gr
)[f_r2
];
1622 TRACE_EXTRACT (current_cpu
, abuf
, (current_cpu
, pc
, "fmt_mvtc", "f_r1 0x%x", 'x', f_r1
, "sr 0x%x", 'x', f_r2
, (char *) 0));
1624 #if WITH_PROFILE_MODEL_P
1625 /* Record the fields for profiling. */
1626 if (PROFILE_MODEL_P (current_cpu
))
1635 CASE (ex
, FMT_NOP
) :
1637 CGEN_INSN_INT insn
= entire_insn
;
1638 #define FLD(f) abuf->fields.fmt_nop.f
1639 EXTRACT_IFMT_NOP_VARS
/* f-op1 f-r1 f-op2 f-r2 */
1641 EXTRACT_IFMT_NOP_CODE
1643 /* Record the fields for the semantic handler. */
1644 TRACE_EXTRACT (current_cpu
, abuf
, (current_cpu
, pc
, "fmt_nop", (char *) 0));
1650 CASE (ex
, FMT_RAC
) :
1652 CGEN_INSN_INT insn
= entire_insn
;
1653 #define FLD(f) abuf->fields.fmt_rac.f
1654 EXTRACT_IFMT_NOP_VARS
/* f-op1 f-r1 f-op2 f-r2 */
1656 EXTRACT_IFMT_NOP_CODE
1658 /* Record the fields for the semantic handler. */
1659 TRACE_EXTRACT (current_cpu
, abuf
, (current_cpu
, pc
, "fmt_rac", (char *) 0));
1665 CASE (ex
, FMT_RTE
) :
1667 CGEN_INSN_INT insn
= entire_insn
;
1668 #define FLD(f) abuf->fields.cti.fields.fmt_rte.f
1669 EXTRACT_IFMT_NOP_VARS
/* f-op1 f-r1 f-op2 f-r2 */
1671 EXTRACT_IFMT_NOP_CODE
1673 /* Record the fields for the semantic handler. */
1674 SEM_BRANCH_INIT_EXTRACT (abuf
);
1675 TRACE_EXTRACT (current_cpu
, abuf
, (current_cpu
, pc
, "fmt_rte", (char *) 0));
1677 #if WITH_PROFILE_MODEL_P
1678 /* Record the fields for profiling. */
1679 if (PROFILE_MODEL_P (current_cpu
))
1687 CASE (ex
, FMT_SETH
) :
1689 CGEN_INSN_INT insn
= entire_insn
;
1690 #define FLD(f) abuf->fields.fmt_seth.f
1691 EXTRACT_IFMT_SETH_VARS
/* f-op1 f-r1 f-op2 f-r2 f-hi16 */
1693 EXTRACT_IFMT_SETH_CODE
1695 /* Record the fields for the semantic handler. */
1696 FLD (f_hi16
) = f_hi16
;
1697 FLD (i_dr
) = & CPU (h_gr
)[f_r1
];
1698 TRACE_EXTRACT (current_cpu
, abuf
, (current_cpu
, pc
, "fmt_seth", "f_hi16 0x%x", 'x', f_hi16
, "dr 0x%x", 'x', f_r1
, (char *) 0));
1700 #if WITH_PROFILE_MODEL_P
1701 /* Record the fields for profiling. */
1702 if (PROFILE_MODEL_P (current_cpu
))
1704 FLD (out_dr
) = f_r1
;
1711 CASE (ex
, FMT_SLL3
) :
1713 CGEN_INSN_INT insn
= entire_insn
;
1714 #define FLD(f) abuf->fields.fmt_sll3.f
1715 EXTRACT_IFMT_ADDV3_VARS
/* f-op1 f-r1 f-op2 f-r2 f-simm16 */
1717 EXTRACT_IFMT_ADDV3_CODE
1719 /* Record the fields for the semantic handler. */
1720 FLD (f_simm16
) = f_simm16
;
1721 FLD (i_sr
) = & CPU (h_gr
)[f_r2
];
1722 FLD (i_dr
) = & CPU (h_gr
)[f_r1
];
1723 TRACE_EXTRACT (current_cpu
, abuf
, (current_cpu
, pc
, "fmt_sll3", "f_simm16 0x%x", 'x', f_simm16
, "sr 0x%x", 'x', f_r2
, "dr 0x%x", 'x', f_r1
, (char *) 0));
1725 #if WITH_PROFILE_MODEL_P
1726 /* Record the fields for profiling. */
1727 if (PROFILE_MODEL_P (current_cpu
))
1730 FLD (out_dr
) = f_r1
;
1737 CASE (ex
, FMT_SLLI
) :
1739 CGEN_INSN_INT insn
= entire_insn
;
1740 #define FLD(f) abuf->fields.fmt_slli.f
1741 EXTRACT_IFMT_SLLI_VARS
/* f-op1 f-r1 f-shift-op2 f-uimm5 */
1743 EXTRACT_IFMT_SLLI_CODE
1745 /* Record the fields for the semantic handler. */
1746 FLD (f_uimm5
) = f_uimm5
;
1747 FLD (i_dr
) = & CPU (h_gr
)[f_r1
];
1748 TRACE_EXTRACT (current_cpu
, abuf
, (current_cpu
, pc
, "fmt_slli", "f_uimm5 0x%x", 'x', f_uimm5
, "dr 0x%x", 'x', f_r1
, (char *) 0));
1750 #if WITH_PROFILE_MODEL_P
1751 /* Record the fields for profiling. */
1752 if (PROFILE_MODEL_P (current_cpu
))
1755 FLD (out_dr
) = f_r1
;
1764 CGEN_INSN_INT insn
= entire_insn
;
1765 #define FLD(f) abuf->fields.fmt_st.f
1766 EXTRACT_IFMT_CMP_VARS
/* f-op1 f-r1 f-op2 f-r2 */
1768 EXTRACT_IFMT_CMP_CODE
1770 /* Record the fields for the semantic handler. */
1771 FLD (i_src1
) = & CPU (h_gr
)[f_r1
];
1772 FLD (i_src2
) = & CPU (h_gr
)[f_r2
];
1773 TRACE_EXTRACT (current_cpu
, abuf
, (current_cpu
, pc
, "fmt_st", "src1 0x%x", 'x', f_r1
, "src2 0x%x", 'x', f_r2
, (char *) 0));
1775 #if WITH_PROFILE_MODEL_P
1776 /* Record the fields for profiling. */
1777 if (PROFILE_MODEL_P (current_cpu
))
1779 FLD (in_src1
) = f_r1
;
1780 FLD (in_src2
) = f_r2
;
1787 CASE (ex
, FMT_ST_D
) :
1789 CGEN_INSN_INT insn
= entire_insn
;
1790 #define FLD(f) abuf->fields.fmt_st_d.f
1791 EXTRACT_IFMT_ST_D_VARS
/* f-op1 f-r1 f-op2 f-r2 f-simm16 */
1793 EXTRACT_IFMT_ST_D_CODE
1795 /* Record the fields for the semantic handler. */
1796 FLD (f_simm16
) = f_simm16
;
1797 FLD (i_src1
) = & CPU (h_gr
)[f_r1
];
1798 FLD (i_src2
) = & CPU (h_gr
)[f_r2
];
1799 TRACE_EXTRACT (current_cpu
, abuf
, (current_cpu
, pc
, "fmt_st_d", "f_simm16 0x%x", 'x', f_simm16
, "src1 0x%x", 'x', f_r1
, "src2 0x%x", 'x', f_r2
, (char *) 0));
1801 #if WITH_PROFILE_MODEL_P
1802 /* Record the fields for profiling. */
1803 if (PROFILE_MODEL_P (current_cpu
))
1805 FLD (in_src1
) = f_r1
;
1806 FLD (in_src2
) = f_r2
;
1813 CASE (ex
, FMT_STB
) :
1815 CGEN_INSN_INT insn
= entire_insn
;
1816 #define FLD(f) abuf->fields.fmt_stb.f
1817 EXTRACT_IFMT_CMP_VARS
/* f-op1 f-r1 f-op2 f-r2 */
1819 EXTRACT_IFMT_CMP_CODE
1821 /* Record the fields for the semantic handler. */
1822 FLD (i_src1
) = & CPU (h_gr
)[f_r1
];
1823 FLD (i_src2
) = & CPU (h_gr
)[f_r2
];
1824 TRACE_EXTRACT (current_cpu
, abuf
, (current_cpu
, pc
, "fmt_stb", "src1 0x%x", 'x', f_r1
, "src2 0x%x", 'x', f_r2
, (char *) 0));
1826 #if WITH_PROFILE_MODEL_P
1827 /* Record the fields for profiling. */
1828 if (PROFILE_MODEL_P (current_cpu
))
1830 FLD (in_src1
) = f_r1
;
1831 FLD (in_src2
) = f_r2
;
1838 CASE (ex
, FMT_STB_D
) :
1840 CGEN_INSN_INT insn
= entire_insn
;
1841 #define FLD(f) abuf->fields.fmt_stb_d.f
1842 EXTRACT_IFMT_ST_D_VARS
/* f-op1 f-r1 f-op2 f-r2 f-simm16 */
1844 EXTRACT_IFMT_ST_D_CODE
1846 /* Record the fields for the semantic handler. */
1847 FLD (f_simm16
) = f_simm16
;
1848 FLD (i_src1
) = & CPU (h_gr
)[f_r1
];
1849 FLD (i_src2
) = & CPU (h_gr
)[f_r2
];
1850 TRACE_EXTRACT (current_cpu
, abuf
, (current_cpu
, pc
, "fmt_stb_d", "f_simm16 0x%x", 'x', f_simm16
, "src1 0x%x", 'x', f_r1
, "src2 0x%x", 'x', f_r2
, (char *) 0));
1852 #if WITH_PROFILE_MODEL_P
1853 /* Record the fields for profiling. */
1854 if (PROFILE_MODEL_P (current_cpu
))
1856 FLD (in_src1
) = f_r1
;
1857 FLD (in_src2
) = f_r2
;
1864 CASE (ex
, FMT_STH
) :
1866 CGEN_INSN_INT insn
= entire_insn
;
1867 #define FLD(f) abuf->fields.fmt_sth.f
1868 EXTRACT_IFMT_CMP_VARS
/* f-op1 f-r1 f-op2 f-r2 */
1870 EXTRACT_IFMT_CMP_CODE
1872 /* Record the fields for the semantic handler. */
1873 FLD (i_src1
) = & CPU (h_gr
)[f_r1
];
1874 FLD (i_src2
) = & CPU (h_gr
)[f_r2
];
1875 TRACE_EXTRACT (current_cpu
, abuf
, (current_cpu
, pc
, "fmt_sth", "src1 0x%x", 'x', f_r1
, "src2 0x%x", 'x', f_r2
, (char *) 0));
1877 #if WITH_PROFILE_MODEL_P
1878 /* Record the fields for profiling. */
1879 if (PROFILE_MODEL_P (current_cpu
))
1881 FLD (in_src1
) = f_r1
;
1882 FLD (in_src2
) = f_r2
;
1889 CASE (ex
, FMT_STH_D
) :
1891 CGEN_INSN_INT insn
= entire_insn
;
1892 #define FLD(f) abuf->fields.fmt_sth_d.f
1893 EXTRACT_IFMT_ST_D_VARS
/* f-op1 f-r1 f-op2 f-r2 f-simm16 */
1895 EXTRACT_IFMT_ST_D_CODE
1897 /* Record the fields for the semantic handler. */
1898 FLD (f_simm16
) = f_simm16
;
1899 FLD (i_src1
) = & CPU (h_gr
)[f_r1
];
1900 FLD (i_src2
) = & CPU (h_gr
)[f_r2
];
1901 TRACE_EXTRACT (current_cpu
, abuf
, (current_cpu
, pc
, "fmt_sth_d", "f_simm16 0x%x", 'x', f_simm16
, "src1 0x%x", 'x', f_r1
, "src2 0x%x", 'x', f_r2
, (char *) 0));
1903 #if WITH_PROFILE_MODEL_P
1904 /* Record the fields for profiling. */
1905 if (PROFILE_MODEL_P (current_cpu
))
1907 FLD (in_src1
) = f_r1
;
1908 FLD (in_src2
) = f_r2
;
1915 CASE (ex
, FMT_ST_PLUS
) :
1917 CGEN_INSN_INT insn
= entire_insn
;
1918 #define FLD(f) abuf->fields.fmt_st_plus.f
1919 EXTRACT_IFMT_CMP_VARS
/* f-op1 f-r1 f-op2 f-r2 */
1921 EXTRACT_IFMT_CMP_CODE
1923 /* Record the fields for the semantic handler. */
1924 FLD (i_src1
) = & CPU (h_gr
)[f_r1
];
1925 FLD (i_src2
) = & CPU (h_gr
)[f_r2
];
1926 TRACE_EXTRACT (current_cpu
, abuf
, (current_cpu
, pc
, "fmt_st_plus", "src1 0x%x", 'x', f_r1
, "src2 0x%x", 'x', f_r2
, (char *) 0));
1928 #if WITH_PROFILE_MODEL_P
1929 /* Record the fields for profiling. */
1930 if (PROFILE_MODEL_P (current_cpu
))
1932 FLD (in_src1
) = f_r1
;
1933 FLD (in_src2
) = f_r2
;
1934 FLD (out_src2
) = f_r2
;
1941 CASE (ex
, FMT_TRAP
) :
1943 CGEN_INSN_INT insn
= entire_insn
;
1944 #define FLD(f) abuf->fields.cti.fields.fmt_trap.f
1945 EXTRACT_IFMT_TRAP_VARS
/* f-op1 f-r1 f-op2 f-uimm4 */
1947 EXTRACT_IFMT_TRAP_CODE
1949 /* Record the fields for the semantic handler. */
1950 FLD (f_uimm4
) = f_uimm4
;
1951 SEM_BRANCH_INIT_EXTRACT (abuf
);
1952 TRACE_EXTRACT (current_cpu
, abuf
, (current_cpu
, pc
, "fmt_trap", "f_uimm4 0x%x", 'x', f_uimm4
, (char *) 0));
1954 #if WITH_PROFILE_MODEL_P
1955 /* Record the fields for profiling. */
1956 if (PROFILE_MODEL_P (current_cpu
))
1964 CASE (ex
, FMT_UNLOCK
) :
1966 CGEN_INSN_INT insn
= entire_insn
;
1967 #define FLD(f) abuf->fields.fmt_unlock.f
1968 EXTRACT_IFMT_CMP_VARS
/* f-op1 f-r1 f-op2 f-r2 */
1970 EXTRACT_IFMT_CMP_CODE
1972 /* Record the fields for the semantic handler. */
1973 FLD (i_src1
) = & CPU (h_gr
)[f_r1
];
1974 FLD (i_src2
) = & CPU (h_gr
)[f_r2
];
1975 TRACE_EXTRACT (current_cpu
, abuf
, (current_cpu
, pc
, "fmt_unlock", "src1 0x%x", 'x', f_r1
, "src2 0x%x", 'x', f_r2
, (char *) 0));
1977 #if WITH_PROFILE_MODEL_P
1978 /* Record the fields for profiling. */
1979 if (PROFILE_MODEL_P (current_cpu
))
1981 FLD (in_src1
) = f_r1
;
1982 FLD (in_src2
) = f_r2
;
1995 return idecode
->idesc
;
projects / thirdparty / binutils-gdb.git / blob