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[thirdparty/binutils-gdb.git] / sim / m32r / decode2.c
1 /* Simulator instruction decoder for m32r2f.
2
3 THIS FILE IS MACHINE GENERATED WITH CGEN.
4
5 Copyright 1996-2018 Free Software Foundation, Inc.
6
7 This file is part of the GNU simulators.
8
9 This file is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 3, or (at your option)
12 any later version.
13
14 It is distributed in the hope that it will be useful, but WITHOUT
15 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
16 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
17 License for more details.
18
19 You should have received a copy of the GNU General Public License along
20 with this program; if not, see <http://www.gnu.org/licenses/>.
21
22 */
23
24 #define WANT_CPU m32r2f
25 #define WANT_CPU_M32R2F
26
27 #include "sim-main.h"
28 #include "sim-assert.h"
29
30 /* Insn can't be executed in parallel.
31 Or is that "do NOt Pass to Air defense Radar"? :-) */
32 #define NOPAR (-1)
33
34 /* The instruction descriptor array.
35 This is computed at runtime. Space for it is not malloc'd to save a
36 teensy bit of cpu in the decoder. Moving it to malloc space is trivial
37 but won't be done until necessary (we don't currently support the runtime
38 addition of instructions nor an SMP machine with different cpus). */
39 static IDESC m32r2f_insn_data[M32R2F_INSN__MAX];
40
41 /* Commas between elements are contained in the macros.
42 Some of these are conditionally compiled out. */
43
44 static const struct insn_sem m32r2f_insn_sem[] =
45 {
46 { VIRTUAL_INSN_X_INVALID, M32R2F_INSN_X_INVALID, M32R2F_SFMT_EMPTY, NOPAR, NOPAR },
47 { VIRTUAL_INSN_X_AFTER, M32R2F_INSN_X_AFTER, M32R2F_SFMT_EMPTY, NOPAR, NOPAR },
48 { VIRTUAL_INSN_X_BEFORE, M32R2F_INSN_X_BEFORE, M32R2F_SFMT_EMPTY, NOPAR, NOPAR },
49 { VIRTUAL_INSN_X_CTI_CHAIN, M32R2F_INSN_X_CTI_CHAIN, M32R2F_SFMT_EMPTY, NOPAR, NOPAR },
50 { VIRTUAL_INSN_X_CHAIN, M32R2F_INSN_X_CHAIN, M32R2F_SFMT_EMPTY, NOPAR, NOPAR },
51 { VIRTUAL_INSN_X_BEGIN, M32R2F_INSN_X_BEGIN, M32R2F_SFMT_EMPTY, NOPAR, NOPAR },
52 { M32R_INSN_ADD, M32R2F_INSN_ADD, M32R2F_SFMT_ADD, M32R2F_INSN_PAR_ADD, M32R2F_INSN_WRITE_ADD },
53 { M32R_INSN_ADD3, M32R2F_INSN_ADD3, M32R2F_SFMT_ADD3, NOPAR, NOPAR },
54 { M32R_INSN_AND, M32R2F_INSN_AND, M32R2F_SFMT_ADD, M32R2F_INSN_PAR_AND, M32R2F_INSN_WRITE_AND },
55 { M32R_INSN_AND3, M32R2F_INSN_AND3, M32R2F_SFMT_AND3, NOPAR, NOPAR },
56 { M32R_INSN_OR, M32R2F_INSN_OR, M32R2F_SFMT_ADD, M32R2F_INSN_PAR_OR, M32R2F_INSN_WRITE_OR },
57 { M32R_INSN_OR3, M32R2F_INSN_OR3, M32R2F_SFMT_OR3, NOPAR, NOPAR },
58 { M32R_INSN_XOR, M32R2F_INSN_XOR, M32R2F_SFMT_ADD, M32R2F_INSN_PAR_XOR, M32R2F_INSN_WRITE_XOR },
59 { M32R_INSN_XOR3, M32R2F_INSN_XOR3, M32R2F_SFMT_AND3, NOPAR, NOPAR },
60 { M32R_INSN_ADDI, M32R2F_INSN_ADDI, M32R2F_SFMT_ADDI, M32R2F_INSN_PAR_ADDI, M32R2F_INSN_WRITE_ADDI },
61 { M32R_INSN_ADDV, M32R2F_INSN_ADDV, M32R2F_SFMT_ADDV, M32R2F_INSN_PAR_ADDV, M32R2F_INSN_WRITE_ADDV },
62 { M32R_INSN_ADDV3, M32R2F_INSN_ADDV3, M32R2F_SFMT_ADDV3, NOPAR, NOPAR },
63 { M32R_INSN_ADDX, M32R2F_INSN_ADDX, M32R2F_SFMT_ADDX, M32R2F_INSN_PAR_ADDX, M32R2F_INSN_WRITE_ADDX },
64 { M32R_INSN_BC8, M32R2F_INSN_BC8, M32R2F_SFMT_BC8, M32R2F_INSN_PAR_BC8, M32R2F_INSN_WRITE_BC8 },
65 { M32R_INSN_BC24, M32R2F_INSN_BC24, M32R2F_SFMT_BC24, NOPAR, NOPAR },
66 { M32R_INSN_BEQ, M32R2F_INSN_BEQ, M32R2F_SFMT_BEQ, NOPAR, NOPAR },
67 { M32R_INSN_BEQZ, M32R2F_INSN_BEQZ, M32R2F_SFMT_BEQZ, NOPAR, NOPAR },
68 { M32R_INSN_BGEZ, M32R2F_INSN_BGEZ, M32R2F_SFMT_BEQZ, NOPAR, NOPAR },
69 { M32R_INSN_BGTZ, M32R2F_INSN_BGTZ, M32R2F_SFMT_BEQZ, NOPAR, NOPAR },
70 { M32R_INSN_BLEZ, M32R2F_INSN_BLEZ, M32R2F_SFMT_BEQZ, NOPAR, NOPAR },
71 { M32R_INSN_BLTZ, M32R2F_INSN_BLTZ, M32R2F_SFMT_BEQZ, NOPAR, NOPAR },
72 { M32R_INSN_BNEZ, M32R2F_INSN_BNEZ, M32R2F_SFMT_BEQZ, NOPAR, NOPAR },
73 { M32R_INSN_BL8, M32R2F_INSN_BL8, M32R2F_SFMT_BL8, M32R2F_INSN_PAR_BL8, M32R2F_INSN_WRITE_BL8 },
74 { M32R_INSN_BL24, M32R2F_INSN_BL24, M32R2F_SFMT_BL24, NOPAR, NOPAR },
75 { M32R_INSN_BCL8, M32R2F_INSN_BCL8, M32R2F_SFMT_BCL8, M32R2F_INSN_PAR_BCL8, M32R2F_INSN_WRITE_BCL8 },
76 { M32R_INSN_BCL24, M32R2F_INSN_BCL24, M32R2F_SFMT_BCL24, NOPAR, NOPAR },
77 { M32R_INSN_BNC8, M32R2F_INSN_BNC8, M32R2F_SFMT_BC8, M32R2F_INSN_PAR_BNC8, M32R2F_INSN_WRITE_BNC8 },
78 { M32R_INSN_BNC24, M32R2F_INSN_BNC24, M32R2F_SFMT_BC24, NOPAR, NOPAR },
79 { M32R_INSN_BNE, M32R2F_INSN_BNE, M32R2F_SFMT_BEQ, NOPAR, NOPAR },
80 { M32R_INSN_BRA8, M32R2F_INSN_BRA8, M32R2F_SFMT_BRA8, M32R2F_INSN_PAR_BRA8, M32R2F_INSN_WRITE_BRA8 },
81 { M32R_INSN_BRA24, M32R2F_INSN_BRA24, M32R2F_SFMT_BRA24, NOPAR, NOPAR },
82 { M32R_INSN_BNCL8, M32R2F_INSN_BNCL8, M32R2F_SFMT_BCL8, M32R2F_INSN_PAR_BNCL8, M32R2F_INSN_WRITE_BNCL8 },
83 { M32R_INSN_BNCL24, M32R2F_INSN_BNCL24, M32R2F_SFMT_BCL24, NOPAR, NOPAR },
84 { M32R_INSN_CMP, M32R2F_INSN_CMP, M32R2F_SFMT_CMP, M32R2F_INSN_PAR_CMP, M32R2F_INSN_WRITE_CMP },
85 { M32R_INSN_CMPI, M32R2F_INSN_CMPI, M32R2F_SFMT_CMPI, NOPAR, NOPAR },
86 { M32R_INSN_CMPU, M32R2F_INSN_CMPU, M32R2F_SFMT_CMP, M32R2F_INSN_PAR_CMPU, M32R2F_INSN_WRITE_CMPU },
87 { M32R_INSN_CMPUI, M32R2F_INSN_CMPUI, M32R2F_SFMT_CMPI, NOPAR, NOPAR },
88 { M32R_INSN_CMPEQ, M32R2F_INSN_CMPEQ, M32R2F_SFMT_CMP, M32R2F_INSN_PAR_CMPEQ, M32R2F_INSN_WRITE_CMPEQ },
89 { M32R_INSN_CMPZ, M32R2F_INSN_CMPZ, M32R2F_SFMT_CMPZ, M32R2F_INSN_PAR_CMPZ, M32R2F_INSN_WRITE_CMPZ },
90 { M32R_INSN_DIV, M32R2F_INSN_DIV, M32R2F_SFMT_DIV, NOPAR, NOPAR },
91 { M32R_INSN_DIVU, M32R2F_INSN_DIVU, M32R2F_SFMT_DIV, NOPAR, NOPAR },
92 { M32R_INSN_REM, M32R2F_INSN_REM, M32R2F_SFMT_DIV, NOPAR, NOPAR },
93 { M32R_INSN_REMU, M32R2F_INSN_REMU, M32R2F_SFMT_DIV, NOPAR, NOPAR },
94 { M32R_INSN_REMH, M32R2F_INSN_REMH, M32R2F_SFMT_DIV, NOPAR, NOPAR },
95 { M32R_INSN_REMUH, M32R2F_INSN_REMUH, M32R2F_SFMT_DIV, NOPAR, NOPAR },
96 { M32R_INSN_REMB, M32R2F_INSN_REMB, M32R2F_SFMT_DIV, NOPAR, NOPAR },
97 { M32R_INSN_REMUB, M32R2F_INSN_REMUB, M32R2F_SFMT_DIV, NOPAR, NOPAR },
98 { M32R_INSN_DIVUH, M32R2F_INSN_DIVUH, M32R2F_SFMT_DIV, NOPAR, NOPAR },
99 { M32R_INSN_DIVB, M32R2F_INSN_DIVB, M32R2F_SFMT_DIV, NOPAR, NOPAR },
100 { M32R_INSN_DIVUB, M32R2F_INSN_DIVUB, M32R2F_SFMT_DIV, NOPAR, NOPAR },
101 { M32R_INSN_DIVH, M32R2F_INSN_DIVH, M32R2F_SFMT_DIV, NOPAR, NOPAR },
102 { M32R_INSN_JC, M32R2F_INSN_JC, M32R2F_SFMT_JC, M32R2F_INSN_PAR_JC, M32R2F_INSN_WRITE_JC },
103 { M32R_INSN_JNC, M32R2F_INSN_JNC, M32R2F_SFMT_JC, M32R2F_INSN_PAR_JNC, M32R2F_INSN_WRITE_JNC },
104 { M32R_INSN_JL, M32R2F_INSN_JL, M32R2F_SFMT_JL, M32R2F_INSN_PAR_JL, M32R2F_INSN_WRITE_JL },
105 { M32R_INSN_JMP, M32R2F_INSN_JMP, M32R2F_SFMT_JMP, M32R2F_INSN_PAR_JMP, M32R2F_INSN_WRITE_JMP },
106 { M32R_INSN_LD, M32R2F_INSN_LD, M32R2F_SFMT_LD, M32R2F_INSN_PAR_LD, M32R2F_INSN_WRITE_LD },
107 { M32R_INSN_LD_D, M32R2F_INSN_LD_D, M32R2F_SFMT_LD_D, NOPAR, NOPAR },
108 { M32R_INSN_LDB, M32R2F_INSN_LDB, M32R2F_SFMT_LDB, M32R2F_INSN_PAR_LDB, M32R2F_INSN_WRITE_LDB },
109 { M32R_INSN_LDB_D, M32R2F_INSN_LDB_D, M32R2F_SFMT_LDB_D, NOPAR, NOPAR },
110 { M32R_INSN_LDH, M32R2F_INSN_LDH, M32R2F_SFMT_LDH, M32R2F_INSN_PAR_LDH, M32R2F_INSN_WRITE_LDH },
111 { M32R_INSN_LDH_D, M32R2F_INSN_LDH_D, M32R2F_SFMT_LDH_D, NOPAR, NOPAR },
112 { M32R_INSN_LDUB, M32R2F_INSN_LDUB, M32R2F_SFMT_LDB, M32R2F_INSN_PAR_LDUB, M32R2F_INSN_WRITE_LDUB },
113 { M32R_INSN_LDUB_D, M32R2F_INSN_LDUB_D, M32R2F_SFMT_LDB_D, NOPAR, NOPAR },
114 { M32R_INSN_LDUH, M32R2F_INSN_LDUH, M32R2F_SFMT_LDH, M32R2F_INSN_PAR_LDUH, M32R2F_INSN_WRITE_LDUH },
115 { M32R_INSN_LDUH_D, M32R2F_INSN_LDUH_D, M32R2F_SFMT_LDH_D, NOPAR, NOPAR },
116 { M32R_INSN_LD_PLUS, M32R2F_INSN_LD_PLUS, M32R2F_SFMT_LD_PLUS, M32R2F_INSN_PAR_LD_PLUS, M32R2F_INSN_WRITE_LD_PLUS },
117 { M32R_INSN_LD24, M32R2F_INSN_LD24, M32R2F_SFMT_LD24, NOPAR, NOPAR },
118 { M32R_INSN_LDI8, M32R2F_INSN_LDI8, M32R2F_SFMT_LDI8, M32R2F_INSN_PAR_LDI8, M32R2F_INSN_WRITE_LDI8 },
119 { M32R_INSN_LDI16, M32R2F_INSN_LDI16, M32R2F_SFMT_LDI16, NOPAR, NOPAR },
120 { M32R_INSN_LOCK, M32R2F_INSN_LOCK, M32R2F_SFMT_LOCK, M32R2F_INSN_PAR_LOCK, M32R2F_INSN_WRITE_LOCK },
121 { M32R_INSN_MACHI_A, M32R2F_INSN_MACHI_A, M32R2F_SFMT_MACHI_A, M32R2F_INSN_PAR_MACHI_A, M32R2F_INSN_WRITE_MACHI_A },
122 { M32R_INSN_MACLO_A, M32R2F_INSN_MACLO_A, M32R2F_SFMT_MACHI_A, M32R2F_INSN_PAR_MACLO_A, M32R2F_INSN_WRITE_MACLO_A },
123 { M32R_INSN_MACWHI_A, M32R2F_INSN_MACWHI_A, M32R2F_SFMT_MACHI_A, M32R2F_INSN_PAR_MACWHI_A, M32R2F_INSN_WRITE_MACWHI_A },
124 { M32R_INSN_MACWLO_A, M32R2F_INSN_MACWLO_A, M32R2F_SFMT_MACHI_A, M32R2F_INSN_PAR_MACWLO_A, M32R2F_INSN_WRITE_MACWLO_A },
125 { M32R_INSN_MUL, M32R2F_INSN_MUL, M32R2F_SFMT_ADD, M32R2F_INSN_PAR_MUL, M32R2F_INSN_WRITE_MUL },
126 { M32R_INSN_MULHI_A, M32R2F_INSN_MULHI_A, M32R2F_SFMT_MULHI_A, M32R2F_INSN_PAR_MULHI_A, M32R2F_INSN_WRITE_MULHI_A },
127 { M32R_INSN_MULLO_A, M32R2F_INSN_MULLO_A, M32R2F_SFMT_MULHI_A, M32R2F_INSN_PAR_MULLO_A, M32R2F_INSN_WRITE_MULLO_A },
128 { M32R_INSN_MULWHI_A, M32R2F_INSN_MULWHI_A, M32R2F_SFMT_MULHI_A, M32R2F_INSN_PAR_MULWHI_A, M32R2F_INSN_WRITE_MULWHI_A },
129 { M32R_INSN_MULWLO_A, M32R2F_INSN_MULWLO_A, M32R2F_SFMT_MULHI_A, M32R2F_INSN_PAR_MULWLO_A, M32R2F_INSN_WRITE_MULWLO_A },
130 { M32R_INSN_MV, M32R2F_INSN_MV, M32R2F_SFMT_MV, M32R2F_INSN_PAR_MV, M32R2F_INSN_WRITE_MV },
131 { M32R_INSN_MVFACHI_A, M32R2F_INSN_MVFACHI_A, M32R2F_SFMT_MVFACHI_A, M32R2F_INSN_PAR_MVFACHI_A, M32R2F_INSN_WRITE_MVFACHI_A },
132 { M32R_INSN_MVFACLO_A, M32R2F_INSN_MVFACLO_A, M32R2F_SFMT_MVFACHI_A, M32R2F_INSN_PAR_MVFACLO_A, M32R2F_INSN_WRITE_MVFACLO_A },
133 { M32R_INSN_MVFACMI_A, M32R2F_INSN_MVFACMI_A, M32R2F_SFMT_MVFACHI_A, M32R2F_INSN_PAR_MVFACMI_A, M32R2F_INSN_WRITE_MVFACMI_A },
134 { M32R_INSN_MVFC, M32R2F_INSN_MVFC, M32R2F_SFMT_MVFC, M32R2F_INSN_PAR_MVFC, M32R2F_INSN_WRITE_MVFC },
135 { M32R_INSN_MVTACHI_A, M32R2F_INSN_MVTACHI_A, M32R2F_SFMT_MVTACHI_A, M32R2F_INSN_PAR_MVTACHI_A, M32R2F_INSN_WRITE_MVTACHI_A },
136 { M32R_INSN_MVTACLO_A, M32R2F_INSN_MVTACLO_A, M32R2F_SFMT_MVTACHI_A, M32R2F_INSN_PAR_MVTACLO_A, M32R2F_INSN_WRITE_MVTACLO_A },
137 { M32R_INSN_MVTC, M32R2F_INSN_MVTC, M32R2F_SFMT_MVTC, M32R2F_INSN_PAR_MVTC, M32R2F_INSN_WRITE_MVTC },
138 { M32R_INSN_NEG, M32R2F_INSN_NEG, M32R2F_SFMT_MV, M32R2F_INSN_PAR_NEG, M32R2F_INSN_WRITE_NEG },
139 { M32R_INSN_NOP, M32R2F_INSN_NOP, M32R2F_SFMT_NOP, M32R2F_INSN_PAR_NOP, M32R2F_INSN_WRITE_NOP },
140 { M32R_INSN_NOT, M32R2F_INSN_NOT, M32R2F_SFMT_MV, M32R2F_INSN_PAR_NOT, M32R2F_INSN_WRITE_NOT },
141 { M32R_INSN_RAC_DSI, M32R2F_INSN_RAC_DSI, M32R2F_SFMT_RAC_DSI, M32R2F_INSN_PAR_RAC_DSI, M32R2F_INSN_WRITE_RAC_DSI },
142 { M32R_INSN_RACH_DSI, M32R2F_INSN_RACH_DSI, M32R2F_SFMT_RAC_DSI, M32R2F_INSN_PAR_RACH_DSI, M32R2F_INSN_WRITE_RACH_DSI },
143 { M32R_INSN_RTE, M32R2F_INSN_RTE, M32R2F_SFMT_RTE, M32R2F_INSN_PAR_RTE, M32R2F_INSN_WRITE_RTE },
144 { M32R_INSN_SETH, M32R2F_INSN_SETH, M32R2F_SFMT_SETH, NOPAR, NOPAR },
145 { M32R_INSN_SLL, M32R2F_INSN_SLL, M32R2F_SFMT_ADD, M32R2F_INSN_PAR_SLL, M32R2F_INSN_WRITE_SLL },
146 { M32R_INSN_SLL3, M32R2F_INSN_SLL3, M32R2F_SFMT_SLL3, NOPAR, NOPAR },
147 { M32R_INSN_SLLI, M32R2F_INSN_SLLI, M32R2F_SFMT_SLLI, M32R2F_INSN_PAR_SLLI, M32R2F_INSN_WRITE_SLLI },
148 { M32R_INSN_SRA, M32R2F_INSN_SRA, M32R2F_SFMT_ADD, M32R2F_INSN_PAR_SRA, M32R2F_INSN_WRITE_SRA },
149 { M32R_INSN_SRA3, M32R2F_INSN_SRA3, M32R2F_SFMT_SLL3, NOPAR, NOPAR },
150 { M32R_INSN_SRAI, M32R2F_INSN_SRAI, M32R2F_SFMT_SLLI, M32R2F_INSN_PAR_SRAI, M32R2F_INSN_WRITE_SRAI },
151 { M32R_INSN_SRL, M32R2F_INSN_SRL, M32R2F_SFMT_ADD, M32R2F_INSN_PAR_SRL, M32R2F_INSN_WRITE_SRL },
152 { M32R_INSN_SRL3, M32R2F_INSN_SRL3, M32R2F_SFMT_SLL3, NOPAR, NOPAR },
153 { M32R_INSN_SRLI, M32R2F_INSN_SRLI, M32R2F_SFMT_SLLI, M32R2F_INSN_PAR_SRLI, M32R2F_INSN_WRITE_SRLI },
154 { M32R_INSN_ST, M32R2F_INSN_ST, M32R2F_SFMT_ST, M32R2F_INSN_PAR_ST, M32R2F_INSN_WRITE_ST },
155 { M32R_INSN_ST_D, M32R2F_INSN_ST_D, M32R2F_SFMT_ST_D, NOPAR, NOPAR },
156 { M32R_INSN_STB, M32R2F_INSN_STB, M32R2F_SFMT_STB, M32R2F_INSN_PAR_STB, M32R2F_INSN_WRITE_STB },
157 { M32R_INSN_STB_D, M32R2F_INSN_STB_D, M32R2F_SFMT_STB_D, NOPAR, NOPAR },
158 { M32R_INSN_STH, M32R2F_INSN_STH, M32R2F_SFMT_STH, M32R2F_INSN_PAR_STH, M32R2F_INSN_WRITE_STH },
159 { M32R_INSN_STH_D, M32R2F_INSN_STH_D, M32R2F_SFMT_STH_D, NOPAR, NOPAR },
160 { M32R_INSN_ST_PLUS, M32R2F_INSN_ST_PLUS, M32R2F_SFMT_ST_PLUS, M32R2F_INSN_PAR_ST_PLUS, M32R2F_INSN_WRITE_ST_PLUS },
161 { M32R_INSN_STH_PLUS, M32R2F_INSN_STH_PLUS, M32R2F_SFMT_STH_PLUS, M32R2F_INSN_PAR_STH_PLUS, M32R2F_INSN_WRITE_STH_PLUS },
162 { M32R_INSN_STB_PLUS, M32R2F_INSN_STB_PLUS, M32R2F_SFMT_STB_PLUS, M32R2F_INSN_PAR_STB_PLUS, M32R2F_INSN_WRITE_STB_PLUS },
163 { M32R_INSN_ST_MINUS, M32R2F_INSN_ST_MINUS, M32R2F_SFMT_ST_PLUS, M32R2F_INSN_PAR_ST_MINUS, M32R2F_INSN_WRITE_ST_MINUS },
164 { M32R_INSN_SUB, M32R2F_INSN_SUB, M32R2F_SFMT_ADD, M32R2F_INSN_PAR_SUB, M32R2F_INSN_WRITE_SUB },
165 { M32R_INSN_SUBV, M32R2F_INSN_SUBV, M32R2F_SFMT_ADDV, M32R2F_INSN_PAR_SUBV, M32R2F_INSN_WRITE_SUBV },
166 { M32R_INSN_SUBX, M32R2F_INSN_SUBX, M32R2F_SFMT_ADDX, M32R2F_INSN_PAR_SUBX, M32R2F_INSN_WRITE_SUBX },
167 { M32R_INSN_TRAP, M32R2F_INSN_TRAP, M32R2F_SFMT_TRAP, M32R2F_INSN_PAR_TRAP, M32R2F_INSN_WRITE_TRAP },
168 { M32R_INSN_UNLOCK, M32R2F_INSN_UNLOCK, M32R2F_SFMT_UNLOCK, M32R2F_INSN_PAR_UNLOCK, M32R2F_INSN_WRITE_UNLOCK },
169 { M32R_INSN_SATB, M32R2F_INSN_SATB, M32R2F_SFMT_SATB, NOPAR, NOPAR },
170 { M32R_INSN_SATH, M32R2F_INSN_SATH, M32R2F_SFMT_SATB, NOPAR, NOPAR },
171 { M32R_INSN_SAT, M32R2F_INSN_SAT, M32R2F_SFMT_SAT, NOPAR, NOPAR },
172 { M32R_INSN_PCMPBZ, M32R2F_INSN_PCMPBZ, M32R2F_SFMT_CMPZ, M32R2F_INSN_PAR_PCMPBZ, M32R2F_INSN_WRITE_PCMPBZ },
173 { M32R_INSN_SADD, M32R2F_INSN_SADD, M32R2F_SFMT_SADD, M32R2F_INSN_PAR_SADD, M32R2F_INSN_WRITE_SADD },
174 { M32R_INSN_MACWU1, M32R2F_INSN_MACWU1, M32R2F_SFMT_MACWU1, M32R2F_INSN_PAR_MACWU1, M32R2F_INSN_WRITE_MACWU1 },
175 { M32R_INSN_MSBLO, M32R2F_INSN_MSBLO, M32R2F_SFMT_MSBLO, M32R2F_INSN_PAR_MSBLO, M32R2F_INSN_WRITE_MSBLO },
176 { M32R_INSN_MULWU1, M32R2F_INSN_MULWU1, M32R2F_SFMT_MULWU1, M32R2F_INSN_PAR_MULWU1, M32R2F_INSN_WRITE_MULWU1 },
177 { M32R_INSN_MACLH1, M32R2F_INSN_MACLH1, M32R2F_SFMT_MACWU1, M32R2F_INSN_PAR_MACLH1, M32R2F_INSN_WRITE_MACLH1 },
178 { M32R_INSN_SC, M32R2F_INSN_SC, M32R2F_SFMT_SC, M32R2F_INSN_PAR_SC, M32R2F_INSN_WRITE_SC },
179 { M32R_INSN_SNC, M32R2F_INSN_SNC, M32R2F_SFMT_SC, M32R2F_INSN_PAR_SNC, M32R2F_INSN_WRITE_SNC },
180 { M32R_INSN_CLRPSW, M32R2F_INSN_CLRPSW, M32R2F_SFMT_CLRPSW, M32R2F_INSN_PAR_CLRPSW, M32R2F_INSN_WRITE_CLRPSW },
181 { M32R_INSN_SETPSW, M32R2F_INSN_SETPSW, M32R2F_SFMT_SETPSW, M32R2F_INSN_PAR_SETPSW, M32R2F_INSN_WRITE_SETPSW },
182 { M32R_INSN_BSET, M32R2F_INSN_BSET, M32R2F_SFMT_BSET, NOPAR, NOPAR },
183 { M32R_INSN_BCLR, M32R2F_INSN_BCLR, M32R2F_SFMT_BSET, NOPAR, NOPAR },
184 { M32R_INSN_BTST, M32R2F_INSN_BTST, M32R2F_SFMT_BTST, M32R2F_INSN_PAR_BTST, M32R2F_INSN_WRITE_BTST },
185 };
186
187 static const struct insn_sem m32r2f_insn_sem_invalid =
188 {
189 VIRTUAL_INSN_X_INVALID, M32R2F_INSN_X_INVALID, M32R2F_SFMT_EMPTY, NOPAR, NOPAR
190 };
191
192 /* Initialize an IDESC from the compile-time computable parts. */
193
194 static INLINE void
195 init_idesc (SIM_CPU *cpu, IDESC *id, const struct insn_sem *t)
196 {
197 const CGEN_INSN *insn_table = CGEN_CPU_INSN_TABLE (CPU_CPU_DESC (cpu))->init_entries;
198
199 id->num = t->index;
200 id->sfmt = t->sfmt;
201 if ((int) t->type <= 0)
202 id->idata = & cgen_virtual_insn_table[- (int) t->type];
203 else
204 id->idata = & insn_table[t->type];
205 id->attrs = CGEN_INSN_ATTRS (id->idata);
206 /* Oh my god, a magic number. */
207 id->length = CGEN_INSN_BITSIZE (id->idata) / 8;
208
209 #if WITH_PROFILE_MODEL_P
210 id->timing = & MODEL_TIMING (CPU_MODEL (cpu)) [t->index];
211 {
212 SIM_DESC sd = CPU_STATE (cpu);
213 SIM_ASSERT (t->index == id->timing->num);
214 }
215 #endif
216
217 /* Semantic pointers are initialized elsewhere. */
218 }
219
220 /* Initialize the instruction descriptor table. */
221
222 void
223 m32r2f_init_idesc_table (SIM_CPU *cpu)
224 {
225 IDESC *id,*tabend;
226 const struct insn_sem *t,*tend;
227 int tabsize = M32R2F_INSN__MAX;
228 IDESC *table = m32r2f_insn_data;
229
230 memset (table, 0, tabsize * sizeof (IDESC));
231
232 /* First set all entries to the `invalid insn'. */
233 t = & m32r2f_insn_sem_invalid;
234 for (id = table, tabend = table + tabsize; id < tabend; ++id)
235 init_idesc (cpu, id, t);
236
237 /* Now fill in the values for the chosen cpu. */
238 for (t = m32r2f_insn_sem, tend = t + ARRAY_SIZE (m32r2f_insn_sem);
239 t != tend; ++t)
240 {
241 init_idesc (cpu, & table[t->index], t);
242 if (t->par_index != NOPAR)
243 {
244 init_idesc (cpu, &table[t->par_index], t);
245 table[t->index].par_idesc = &table[t->par_index];
246 }
247 if (t->par_index != NOPAR)
248 {
249 init_idesc (cpu, &table[t->write_index], t);
250 table[t->par_index].par_idesc = &table[t->write_index];
251 }
252 }
253
254 /* Link the IDESC table into the cpu. */
255 CPU_IDESC (cpu) = table;
256 }
257
258 /* Given an instruction, return a pointer to its IDESC entry. */
259
260 const IDESC *
261 m32r2f_decode (SIM_CPU *current_cpu, IADDR pc,
262 CGEN_INSN_WORD base_insn, CGEN_INSN_WORD entire_insn,
263 ARGBUF *abuf)
264 {
265 /* Result of decoder. */
266 M32R2F_INSN_TYPE itype;
267
268 {
269 CGEN_INSN_WORD insn = base_insn;
270
271 {
272 unsigned int val = (((insn >> 8) & (15 << 4)) | ((insn >> 4) & (15 << 0)));
273 switch (val)
274 {
275 case 0 : itype = M32R2F_INSN_SUBV; goto extract_sfmt_addv;
276 case 1 : itype = M32R2F_INSN_SUBX; goto extract_sfmt_addx;
277 case 2 : itype = M32R2F_INSN_SUB; goto extract_sfmt_add;
278 case 3 : itype = M32R2F_INSN_NEG; goto extract_sfmt_mv;
279 case 4 : itype = M32R2F_INSN_CMP; goto extract_sfmt_cmp;
280 case 5 : itype = M32R2F_INSN_CMPU; goto extract_sfmt_cmp;
281 case 6 : itype = M32R2F_INSN_CMPEQ; goto extract_sfmt_cmp;
282 case 7 :
283 {
284 unsigned int val = (((insn >> 8) & (3 << 0)));
285 switch (val)
286 {
287 case 0 :
288 if ((entire_insn & 0xfff0) == 0x70)
289 { itype = M32R2F_INSN_CMPZ; goto extract_sfmt_cmpz; }
290 itype = M32R2F_INSN_X_INVALID; goto extract_sfmt_empty;
291 case 3 :
292 if ((entire_insn & 0xfff0) == 0x370)
293 { itype = M32R2F_INSN_PCMPBZ; goto extract_sfmt_cmpz; }
294 itype = M32R2F_INSN_X_INVALID; goto extract_sfmt_empty;
295 default : itype = M32R2F_INSN_X_INVALID; goto extract_sfmt_empty;
296 }
297 }
298 case 8 : itype = M32R2F_INSN_ADDV; goto extract_sfmt_addv;
299 case 9 : itype = M32R2F_INSN_ADDX; goto extract_sfmt_addx;
300 case 10 : itype = M32R2F_INSN_ADD; goto extract_sfmt_add;
301 case 11 : itype = M32R2F_INSN_NOT; goto extract_sfmt_mv;
302 case 12 : itype = M32R2F_INSN_AND; goto extract_sfmt_add;
303 case 13 : itype = M32R2F_INSN_XOR; goto extract_sfmt_add;
304 case 14 : itype = M32R2F_INSN_OR; goto extract_sfmt_add;
305 case 15 :
306 if ((entire_insn & 0xf8f0) == 0xf0)
307 { itype = M32R2F_INSN_BTST; goto extract_sfmt_btst; }
308 itype = M32R2F_INSN_X_INVALID; goto extract_sfmt_empty;
309 case 16 : itype = M32R2F_INSN_SRL; goto extract_sfmt_add;
310 case 18 : itype = M32R2F_INSN_SRA; goto extract_sfmt_add;
311 case 20 : itype = M32R2F_INSN_SLL; goto extract_sfmt_add;
312 case 22 : itype = M32R2F_INSN_MUL; goto extract_sfmt_add;
313 case 24 : itype = M32R2F_INSN_MV; goto extract_sfmt_mv;
314 case 25 : itype = M32R2F_INSN_MVFC; goto extract_sfmt_mvfc;
315 case 26 : itype = M32R2F_INSN_MVTC; goto extract_sfmt_mvtc;
316 case 28 :
317 {
318 unsigned int val = (((insn >> 8) & (3 << 0)));
319 switch (val)
320 {
321 case 0 :
322 if ((entire_insn & 0xfff0) == 0x1cc0)
323 { itype = M32R2F_INSN_JC; goto extract_sfmt_jc; }
324 itype = M32R2F_INSN_X_INVALID; goto extract_sfmt_empty;
325 case 1 :
326 if ((entire_insn & 0xfff0) == 0x1dc0)
327 { itype = M32R2F_INSN_JNC; goto extract_sfmt_jc; }
328 itype = M32R2F_INSN_X_INVALID; goto extract_sfmt_empty;
329 case 2 :
330 if ((entire_insn & 0xfff0) == 0x1ec0)
331 { itype = M32R2F_INSN_JL; goto extract_sfmt_jl; }
332 itype = M32R2F_INSN_X_INVALID; goto extract_sfmt_empty;
333 case 3 :
334 if ((entire_insn & 0xfff0) == 0x1fc0)
335 { itype = M32R2F_INSN_JMP; goto extract_sfmt_jmp; }
336 itype = M32R2F_INSN_X_INVALID; goto extract_sfmt_empty;
337 default : itype = M32R2F_INSN_X_INVALID; goto extract_sfmt_empty;
338 }
339 }
340 case 29 :
341 if ((entire_insn & 0xffff) == 0x10d6)
342 { itype = M32R2F_INSN_RTE; goto extract_sfmt_rte; }
343 itype = M32R2F_INSN_X_INVALID; goto extract_sfmt_empty;
344 case 31 :
345 if ((entire_insn & 0xfff0) == 0x10f0)
346 { itype = M32R2F_INSN_TRAP; goto extract_sfmt_trap; }
347 itype = M32R2F_INSN_X_INVALID; goto extract_sfmt_empty;
348 case 32 : itype = M32R2F_INSN_STB; goto extract_sfmt_stb;
349 case 33 : itype = M32R2F_INSN_STB_PLUS; goto extract_sfmt_stb_plus;
350 case 34 : itype = M32R2F_INSN_STH; goto extract_sfmt_sth;
351 case 35 : itype = M32R2F_INSN_STH_PLUS; goto extract_sfmt_sth_plus;
352 case 36 : itype = M32R2F_INSN_ST; goto extract_sfmt_st;
353 case 37 : itype = M32R2F_INSN_UNLOCK; goto extract_sfmt_unlock;
354 case 38 : itype = M32R2F_INSN_ST_PLUS; goto extract_sfmt_st_plus;
355 case 39 : itype = M32R2F_INSN_ST_MINUS; goto extract_sfmt_st_plus;
356 case 40 : itype = M32R2F_INSN_LDB; goto extract_sfmt_ldb;
357 case 41 : itype = M32R2F_INSN_LDUB; goto extract_sfmt_ldb;
358 case 42 : itype = M32R2F_INSN_LDH; goto extract_sfmt_ldh;
359 case 43 : itype = M32R2F_INSN_LDUH; goto extract_sfmt_ldh;
360 case 44 : itype = M32R2F_INSN_LD; goto extract_sfmt_ld;
361 case 45 : itype = M32R2F_INSN_LOCK; goto extract_sfmt_lock;
362 case 46 : itype = M32R2F_INSN_LD_PLUS; goto extract_sfmt_ld_plus;
363 case 48 : /* fall through */
364 case 56 : itype = M32R2F_INSN_MULHI_A; goto extract_sfmt_mulhi_a;
365 case 49 : /* fall through */
366 case 57 : itype = M32R2F_INSN_MULLO_A; goto extract_sfmt_mulhi_a;
367 case 50 : /* fall through */
368 case 58 : itype = M32R2F_INSN_MULWHI_A; goto extract_sfmt_mulhi_a;
369 case 51 : /* fall through */
370 case 59 : itype = M32R2F_INSN_MULWLO_A; goto extract_sfmt_mulhi_a;
371 case 52 : /* fall through */
372 case 60 : itype = M32R2F_INSN_MACHI_A; goto extract_sfmt_machi_a;
373 case 53 : /* fall through */
374 case 61 : itype = M32R2F_INSN_MACLO_A; goto extract_sfmt_machi_a;
375 case 54 : /* fall through */
376 case 62 : itype = M32R2F_INSN_MACWHI_A; goto extract_sfmt_machi_a;
377 case 55 : /* fall through */
378 case 63 : itype = M32R2F_INSN_MACWLO_A; goto extract_sfmt_machi_a;
379 case 64 : /* fall through */
380 case 65 : /* fall through */
381 case 66 : /* fall through */
382 case 67 : /* fall through */
383 case 68 : /* fall through */
384 case 69 : /* fall through */
385 case 70 : /* fall through */
386 case 71 : /* fall through */
387 case 72 : /* fall through */
388 case 73 : /* fall through */
389 case 74 : /* fall through */
390 case 75 : /* fall through */
391 case 76 : /* fall through */
392 case 77 : /* fall through */
393 case 78 : /* fall through */
394 case 79 : itype = M32R2F_INSN_ADDI; goto extract_sfmt_addi;
395 case 80 : /* fall through */
396 case 81 : itype = M32R2F_INSN_SRLI; goto extract_sfmt_slli;
397 case 82 : /* fall through */
398 case 83 : itype = M32R2F_INSN_SRAI; goto extract_sfmt_slli;
399 case 84 : /* fall through */
400 case 85 : itype = M32R2F_INSN_SLLI; goto extract_sfmt_slli;
401 case 87 :
402 {
403 unsigned int val = (((insn >> 0) & (1 << 0)));
404 switch (val)
405 {
406 case 0 :
407 if ((entire_insn & 0xf0f3) == 0x5070)
408 { itype = M32R2F_INSN_MVTACHI_A; goto extract_sfmt_mvtachi_a; }
409 itype = M32R2F_INSN_X_INVALID; goto extract_sfmt_empty;
410 case 1 :
411 if ((entire_insn & 0xf0f3) == 0x5071)
412 { itype = M32R2F_INSN_MVTACLO_A; goto extract_sfmt_mvtachi_a; }
413 itype = M32R2F_INSN_X_INVALID; goto extract_sfmt_empty;
414 default : itype = M32R2F_INSN_X_INVALID; goto extract_sfmt_empty;
415 }
416 }
417 case 88 :
418 if ((entire_insn & 0xf3f2) == 0x5080)
419 { itype = M32R2F_INSN_RACH_DSI; goto extract_sfmt_rac_dsi; }
420 itype = M32R2F_INSN_X_INVALID; goto extract_sfmt_empty;
421 case 89 :
422 if ((entire_insn & 0xf3f2) == 0x5090)
423 { itype = M32R2F_INSN_RAC_DSI; goto extract_sfmt_rac_dsi; }
424 itype = M32R2F_INSN_X_INVALID; goto extract_sfmt_empty;
425 case 90 : itype = M32R2F_INSN_MULWU1; goto extract_sfmt_mulwu1;
426 case 91 : itype = M32R2F_INSN_MACWU1; goto extract_sfmt_macwu1;
427 case 92 : itype = M32R2F_INSN_MACLH1; goto extract_sfmt_macwu1;
428 case 93 : itype = M32R2F_INSN_MSBLO; goto extract_sfmt_msblo;
429 case 94 :
430 if ((entire_insn & 0xffff) == 0x50e4)
431 { itype = M32R2F_INSN_SADD; goto extract_sfmt_sadd; }
432 itype = M32R2F_INSN_X_INVALID; goto extract_sfmt_empty;
433 case 95 :
434 {
435 unsigned int val = (((insn >> 0) & (3 << 0)));
436 switch (val)
437 {
438 case 0 : itype = M32R2F_INSN_MVFACHI_A; goto extract_sfmt_mvfachi_a;
439 case 1 : itype = M32R2F_INSN_MVFACLO_A; goto extract_sfmt_mvfachi_a;
440 case 2 : itype = M32R2F_INSN_MVFACMI_A; goto extract_sfmt_mvfachi_a;
441 default : itype = M32R2F_INSN_X_INVALID; goto extract_sfmt_empty;
442 }
443 }
444 case 96 : /* fall through */
445 case 97 : /* fall through */
446 case 98 : /* fall through */
447 case 99 : /* fall through */
448 case 100 : /* fall through */
449 case 101 : /* fall through */
450 case 102 : /* fall through */
451 case 103 : /* fall through */
452 case 104 : /* fall through */
453 case 105 : /* fall through */
454 case 106 : /* fall through */
455 case 107 : /* fall through */
456 case 108 : /* fall through */
457 case 109 : /* fall through */
458 case 110 : /* fall through */
459 case 111 : itype = M32R2F_INSN_LDI8; goto extract_sfmt_ldi8;
460 case 112 :
461 {
462 unsigned int val = (((insn >> 7) & (15 << 1)) | ((insn >> 0) & (1 << 0)));
463 switch (val)
464 {
465 case 0 :
466 if ((entire_insn & 0xffff) == 0x7000)
467 { itype = M32R2F_INSN_NOP; goto extract_sfmt_nop; }
468 itype = M32R2F_INSN_X_INVALID; goto extract_sfmt_empty;
469 case 2 : /* fall through */
470 case 3 : itype = M32R2F_INSN_SETPSW; goto extract_sfmt_setpsw;
471 case 4 : /* fall through */
472 case 5 : itype = M32R2F_INSN_CLRPSW; goto extract_sfmt_clrpsw;
473 case 9 :
474 if ((entire_insn & 0xffff) == 0x7401)
475 { itype = M32R2F_INSN_SC; goto extract_sfmt_sc; }
476 itype = M32R2F_INSN_X_INVALID; goto extract_sfmt_empty;
477 case 11 :
478 if ((entire_insn & 0xffff) == 0x7501)
479 { itype = M32R2F_INSN_SNC; goto extract_sfmt_sc; }
480 itype = M32R2F_INSN_X_INVALID; goto extract_sfmt_empty;
481 case 16 : /* fall through */
482 case 17 : itype = M32R2F_INSN_BCL8; goto extract_sfmt_bcl8;
483 case 18 : /* fall through */
484 case 19 : itype = M32R2F_INSN_BNCL8; goto extract_sfmt_bcl8;
485 case 24 : /* fall through */
486 case 25 : itype = M32R2F_INSN_BC8; goto extract_sfmt_bc8;
487 case 26 : /* fall through */
488 case 27 : itype = M32R2F_INSN_BNC8; goto extract_sfmt_bc8;
489 case 28 : /* fall through */
490 case 29 : itype = M32R2F_INSN_BL8; goto extract_sfmt_bl8;
491 case 30 : /* fall through */
492 case 31 : itype = M32R2F_INSN_BRA8; goto extract_sfmt_bra8;
493 default : itype = M32R2F_INSN_X_INVALID; goto extract_sfmt_empty;
494 }
495 }
496 case 113 : /* fall through */
497 case 114 : /* fall through */
498 case 115 : /* fall through */
499 case 116 : /* fall through */
500 case 117 : /* fall through */
501 case 118 : /* fall through */
502 case 119 : /* fall through */
503 case 120 : /* fall through */
504 case 121 : /* fall through */
505 case 122 : /* fall through */
506 case 123 : /* fall through */
507 case 124 : /* fall through */
508 case 125 : /* fall through */
509 case 126 : /* fall through */
510 case 127 :
511 {
512 unsigned int val = (((insn >> 8) & (15 << 0)));
513 switch (val)
514 {
515 case 1 : itype = M32R2F_INSN_SETPSW; goto extract_sfmt_setpsw;
516 case 2 : itype = M32R2F_INSN_CLRPSW; goto extract_sfmt_clrpsw;
517 case 8 : itype = M32R2F_INSN_BCL8; goto extract_sfmt_bcl8;
518 case 9 : itype = M32R2F_INSN_BNCL8; goto extract_sfmt_bcl8;
519 case 12 : itype = M32R2F_INSN_BC8; goto extract_sfmt_bc8;
520 case 13 : itype = M32R2F_INSN_BNC8; goto extract_sfmt_bc8;
521 case 14 : itype = M32R2F_INSN_BL8; goto extract_sfmt_bl8;
522 case 15 : itype = M32R2F_INSN_BRA8; goto extract_sfmt_bra8;
523 default : itype = M32R2F_INSN_X_INVALID; goto extract_sfmt_empty;
524 }
525 }
526 case 132 :
527 if ((entire_insn & 0xfff00000) == 0x80400000)
528 { itype = M32R2F_INSN_CMPI; goto extract_sfmt_cmpi; }
529 itype = M32R2F_INSN_X_INVALID; goto extract_sfmt_empty;
530 case 133 :
531 if ((entire_insn & 0xfff00000) == 0x80500000)
532 { itype = M32R2F_INSN_CMPUI; goto extract_sfmt_cmpi; }
533 itype = M32R2F_INSN_X_INVALID; goto extract_sfmt_empty;
534 case 134 :
535 {
536 unsigned int val = (((entire_insn >> 8) & (3 << 0)));
537 switch (val)
538 {
539 case 0 :
540 if ((entire_insn & 0xf0f0ffff) == 0x80600000)
541 { itype = M32R2F_INSN_SAT; goto extract_sfmt_sat; }
542 itype = M32R2F_INSN_X_INVALID; goto extract_sfmt_empty;
543 case 2 :
544 if ((entire_insn & 0xf0f0ffff) == 0x80600200)
545 { itype = M32R2F_INSN_SATH; goto extract_sfmt_satb; }
546 itype = M32R2F_INSN_X_INVALID; goto extract_sfmt_empty;
547 case 3 :
548 if ((entire_insn & 0xf0f0ffff) == 0x80600300)
549 { itype = M32R2F_INSN_SATB; goto extract_sfmt_satb; }
550 itype = M32R2F_INSN_X_INVALID; goto extract_sfmt_empty;
551 default : itype = M32R2F_INSN_X_INVALID; goto extract_sfmt_empty;
552 }
553 }
554 case 136 : itype = M32R2F_INSN_ADDV3; goto extract_sfmt_addv3;
555 case 138 : itype = M32R2F_INSN_ADD3; goto extract_sfmt_add3;
556 case 140 : itype = M32R2F_INSN_AND3; goto extract_sfmt_and3;
557 case 141 : itype = M32R2F_INSN_XOR3; goto extract_sfmt_and3;
558 case 142 : itype = M32R2F_INSN_OR3; goto extract_sfmt_or3;
559 case 144 :
560 {
561 unsigned int val = (((entire_insn >> 3) & (3 << 0)));
562 switch (val)
563 {
564 case 0 :
565 if ((entire_insn & 0xf0f0ffff) == 0x90000000)
566 { itype = M32R2F_INSN_DIV; goto extract_sfmt_div; }
567 itype = M32R2F_INSN_X_INVALID; goto extract_sfmt_empty;
568 case 2 :
569 if ((entire_insn & 0xf0f0ffff) == 0x90000010)
570 { itype = M32R2F_INSN_DIVH; goto extract_sfmt_div; }
571 itype = M32R2F_INSN_X_INVALID; goto extract_sfmt_empty;
572 case 3 :
573 if ((entire_insn & 0xf0f0ffff) == 0x90000018)
574 { itype = M32R2F_INSN_DIVB; goto extract_sfmt_div; }
575 itype = M32R2F_INSN_X_INVALID; goto extract_sfmt_empty;
576 default : itype = M32R2F_INSN_X_INVALID; goto extract_sfmt_empty;
577 }
578 }
579 case 145 :
580 {
581 unsigned int val = (((entire_insn >> 3) & (3 << 0)));
582 switch (val)
583 {
584 case 0 :
585 if ((entire_insn & 0xf0f0ffff) == 0x90100000)
586 { itype = M32R2F_INSN_DIVU; goto extract_sfmt_div; }
587 itype = M32R2F_INSN_X_INVALID; goto extract_sfmt_empty;
588 case 2 :
589 if ((entire_insn & 0xf0f0ffff) == 0x90100010)
590 { itype = M32R2F_INSN_DIVUH; goto extract_sfmt_div; }
591 itype = M32R2F_INSN_X_INVALID; goto extract_sfmt_empty;
592 case 3 :
593 if ((entire_insn & 0xf0f0ffff) == 0x90100018)
594 { itype = M32R2F_INSN_DIVUB; goto extract_sfmt_div; }
595 itype = M32R2F_INSN_X_INVALID; goto extract_sfmt_empty;
596 default : itype = M32R2F_INSN_X_INVALID; goto extract_sfmt_empty;
597 }
598 }
599 case 146 :
600 {
601 unsigned int val = (((entire_insn >> 3) & (3 << 0)));
602 switch (val)
603 {
604 case 0 :
605 if ((entire_insn & 0xf0f0ffff) == 0x90200000)
606 { itype = M32R2F_INSN_REM; goto extract_sfmt_div; }
607 itype = M32R2F_INSN_X_INVALID; goto extract_sfmt_empty;
608 case 2 :
609 if ((entire_insn & 0xf0f0ffff) == 0x90200010)
610 { itype = M32R2F_INSN_REMH; goto extract_sfmt_div; }
611 itype = M32R2F_INSN_X_INVALID; goto extract_sfmt_empty;
612 case 3 :
613 if ((entire_insn & 0xf0f0ffff) == 0x90200018)
614 { itype = M32R2F_INSN_REMB; goto extract_sfmt_div; }
615 itype = M32R2F_INSN_X_INVALID; goto extract_sfmt_empty;
616 default : itype = M32R2F_INSN_X_INVALID; goto extract_sfmt_empty;
617 }
618 }
619 case 147 :
620 {
621 unsigned int val = (((entire_insn >> 3) & (3 << 0)));
622 switch (val)
623 {
624 case 0 :
625 if ((entire_insn & 0xf0f0ffff) == 0x90300000)
626 { itype = M32R2F_INSN_REMU; goto extract_sfmt_div; }
627 itype = M32R2F_INSN_X_INVALID; goto extract_sfmt_empty;
628 case 2 :
629 if ((entire_insn & 0xf0f0ffff) == 0x90300010)
630 { itype = M32R2F_INSN_REMUH; goto extract_sfmt_div; }
631 itype = M32R2F_INSN_X_INVALID; goto extract_sfmt_empty;
632 case 3 :
633 if ((entire_insn & 0xf0f0ffff) == 0x90300018)
634 { itype = M32R2F_INSN_REMUB; goto extract_sfmt_div; }
635 itype = M32R2F_INSN_X_INVALID; goto extract_sfmt_empty;
636 default : itype = M32R2F_INSN_X_INVALID; goto extract_sfmt_empty;
637 }
638 }
639 case 152 : itype = M32R2F_INSN_SRL3; goto extract_sfmt_sll3;
640 case 154 : itype = M32R2F_INSN_SRA3; goto extract_sfmt_sll3;
641 case 156 : itype = M32R2F_INSN_SLL3; goto extract_sfmt_sll3;
642 case 159 :
643 if ((entire_insn & 0xf0ff0000) == 0x90f00000)
644 { itype = M32R2F_INSN_LDI16; goto extract_sfmt_ldi16; }
645 itype = M32R2F_INSN_X_INVALID; goto extract_sfmt_empty;
646 case 160 : itype = M32R2F_INSN_STB_D; goto extract_sfmt_stb_d;
647 case 162 : itype = M32R2F_INSN_STH_D; goto extract_sfmt_sth_d;
648 case 164 : itype = M32R2F_INSN_ST_D; goto extract_sfmt_st_d;
649 case 166 :
650 if ((entire_insn & 0xf8f00000) == 0xa0600000)
651 { itype = M32R2F_INSN_BSET; goto extract_sfmt_bset; }
652 itype = M32R2F_INSN_X_INVALID; goto extract_sfmt_empty;
653 case 167 :
654 if ((entire_insn & 0xf8f00000) == 0xa0700000)
655 { itype = M32R2F_INSN_BCLR; goto extract_sfmt_bset; }
656 itype = M32R2F_INSN_X_INVALID; goto extract_sfmt_empty;
657 case 168 : itype = M32R2F_INSN_LDB_D; goto extract_sfmt_ldb_d;
658 case 169 : itype = M32R2F_INSN_LDUB_D; goto extract_sfmt_ldb_d;
659 case 170 : itype = M32R2F_INSN_LDH_D; goto extract_sfmt_ldh_d;
660 case 171 : itype = M32R2F_INSN_LDUH_D; goto extract_sfmt_ldh_d;
661 case 172 : itype = M32R2F_INSN_LD_D; goto extract_sfmt_ld_d;
662 case 176 : itype = M32R2F_INSN_BEQ; goto extract_sfmt_beq;
663 case 177 : itype = M32R2F_INSN_BNE; goto extract_sfmt_beq;
664 case 184 :
665 if ((entire_insn & 0xfff00000) == 0xb0800000)
666 { itype = M32R2F_INSN_BEQZ; goto extract_sfmt_beqz; }
667 itype = M32R2F_INSN_X_INVALID; goto extract_sfmt_empty;
668 case 185 :
669 if ((entire_insn & 0xfff00000) == 0xb0900000)
670 { itype = M32R2F_INSN_BNEZ; goto extract_sfmt_beqz; }
671 itype = M32R2F_INSN_X_INVALID; goto extract_sfmt_empty;
672 case 186 :
673 if ((entire_insn & 0xfff00000) == 0xb0a00000)
674 { itype = M32R2F_INSN_BLTZ; goto extract_sfmt_beqz; }
675 itype = M32R2F_INSN_X_INVALID; goto extract_sfmt_empty;
676 case 187 :
677 if ((entire_insn & 0xfff00000) == 0xb0b00000)
678 { itype = M32R2F_INSN_BGEZ; goto extract_sfmt_beqz; }
679 itype = M32R2F_INSN_X_INVALID; goto extract_sfmt_empty;
680 case 188 :
681 if ((entire_insn & 0xfff00000) == 0xb0c00000)
682 { itype = M32R2F_INSN_BLEZ; goto extract_sfmt_beqz; }
683 itype = M32R2F_INSN_X_INVALID; goto extract_sfmt_empty;
684 case 189 :
685 if ((entire_insn & 0xfff00000) == 0xb0d00000)
686 { itype = M32R2F_INSN_BGTZ; goto extract_sfmt_beqz; }
687 itype = M32R2F_INSN_X_INVALID; goto extract_sfmt_empty;
688 case 220 :
689 if ((entire_insn & 0xf0ff0000) == 0xd0c00000)
690 { itype = M32R2F_INSN_SETH; goto extract_sfmt_seth; }
691 itype = M32R2F_INSN_X_INVALID; goto extract_sfmt_empty;
692 case 224 : /* fall through */
693 case 225 : /* fall through */
694 case 226 : /* fall through */
695 case 227 : /* fall through */
696 case 228 : /* fall through */
697 case 229 : /* fall through */
698 case 230 : /* fall through */
699 case 231 : /* fall through */
700 case 232 : /* fall through */
701 case 233 : /* fall through */
702 case 234 : /* fall through */
703 case 235 : /* fall through */
704 case 236 : /* fall through */
705 case 237 : /* fall through */
706 case 238 : /* fall through */
707 case 239 : itype = M32R2F_INSN_LD24; goto extract_sfmt_ld24;
708 case 240 : /* fall through */
709 case 241 : /* fall through */
710 case 242 : /* fall through */
711 case 243 : /* fall through */
712 case 244 : /* fall through */
713 case 245 : /* fall through */
714 case 246 : /* fall through */
715 case 247 : /* fall through */
716 case 248 : /* fall through */
717 case 249 : /* fall through */
718 case 250 : /* fall through */
719 case 251 : /* fall through */
720 case 252 : /* fall through */
721 case 253 : /* fall through */
722 case 254 : /* fall through */
723 case 255 :
724 {
725 unsigned int val = (((insn >> 8) & (7 << 0)));
726 switch (val)
727 {
728 case 0 :
729 if ((entire_insn & 0xff000000) == 0xf8000000)
730 { itype = M32R2F_INSN_BCL24; goto extract_sfmt_bcl24; }
731 itype = M32R2F_INSN_X_INVALID; goto extract_sfmt_empty;
732 case 1 :
733 if ((entire_insn & 0xff000000) == 0xf9000000)
734 { itype = M32R2F_INSN_BNCL24; goto extract_sfmt_bcl24; }
735 itype = M32R2F_INSN_X_INVALID; goto extract_sfmt_empty;
736 case 4 :
737 if ((entire_insn & 0xff000000) == 0xfc000000)
738 { itype = M32R2F_INSN_BC24; goto extract_sfmt_bc24; }
739 itype = M32R2F_INSN_X_INVALID; goto extract_sfmt_empty;
740 case 5 :
741 if ((entire_insn & 0xff000000) == 0xfd000000)
742 { itype = M32R2F_INSN_BNC24; goto extract_sfmt_bc24; }
743 itype = M32R2F_INSN_X_INVALID; goto extract_sfmt_empty;
744 case 6 :
745 if ((entire_insn & 0xff000000) == 0xfe000000)
746 { itype = M32R2F_INSN_BL24; goto extract_sfmt_bl24; }
747 itype = M32R2F_INSN_X_INVALID; goto extract_sfmt_empty;
748 case 7 :
749 if ((entire_insn & 0xff000000) == 0xff000000)
750 { itype = M32R2F_INSN_BRA24; goto extract_sfmt_bra24; }
751 itype = M32R2F_INSN_X_INVALID; goto extract_sfmt_empty;
752 default : itype = M32R2F_INSN_X_INVALID; goto extract_sfmt_empty;
753 }
754 }
755 default : itype = M32R2F_INSN_X_INVALID; goto extract_sfmt_empty;
756 }
757 }
758 }
759
760 /* The instruction has been decoded, now extract the fields. */
761
762 extract_sfmt_empty:
763 {
764 const IDESC *idesc = &m32r2f_insn_data[itype];
765 #define FLD(f) abuf->fields.sfmt_empty.f
766
767
768 /* Record the fields for the semantic handler. */
769 CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_empty", (char *) 0));
770
771 #undef FLD
772 return idesc;
773 }
774
775 extract_sfmt_add:
776 {
777 const IDESC *idesc = &m32r2f_insn_data[itype];
778 CGEN_INSN_WORD insn = entire_insn;
779 #define FLD(f) abuf->fields.sfmt_add.f
780 UINT f_r1;
781 UINT f_r2;
782
783 f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4);
784 f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4);
785
786 /* Record the fields for the semantic handler. */
787 FLD (f_r1) = f_r1;
788 FLD (f_r2) = f_r2;
789 FLD (i_dr) = & CPU (h_gr)[f_r1];
790 FLD (i_sr) = & CPU (h_gr)[f_r2];
791 CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_add", "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, (char *) 0));
792
793 #if WITH_PROFILE_MODEL_P
794 /* Record the fields for profiling. */
795 if (PROFILE_MODEL_P (current_cpu))
796 {
797 FLD (in_dr) = f_r1;
798 FLD (in_sr) = f_r2;
799 FLD (out_dr) = f_r1;
800 }
801 #endif
802 #undef FLD
803 return idesc;
804 }
805
806 extract_sfmt_add3:
807 {
808 const IDESC *idesc = &m32r2f_insn_data[itype];
809 CGEN_INSN_WORD insn = entire_insn;
810 #define FLD(f) abuf->fields.sfmt_add3.f
811 UINT f_r1;
812 UINT f_r2;
813 INT f_simm16;
814
815 f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4);
816 f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4);
817 f_simm16 = EXTRACT_MSB0_SINT (insn, 32, 16, 16);
818
819 /* Record the fields for the semantic handler. */
820 FLD (f_simm16) = f_simm16;
821 FLD (f_r2) = f_r2;
822 FLD (f_r1) = f_r1;
823 FLD (i_sr) = & CPU (h_gr)[f_r2];
824 FLD (i_dr) = & CPU (h_gr)[f_r1];
825 CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_add3", "f_simm16 0x%x", 'x', f_simm16, "f_r2 0x%x", 'x', f_r2, "f_r1 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0));
826
827 #if WITH_PROFILE_MODEL_P
828 /* Record the fields for profiling. */
829 if (PROFILE_MODEL_P (current_cpu))
830 {
831 FLD (in_sr) = f_r2;
832 FLD (out_dr) = f_r1;
833 }
834 #endif
835 #undef FLD
836 return idesc;
837 }
838
839 extract_sfmt_and3:
840 {
841 const IDESC *idesc = &m32r2f_insn_data[itype];
842 CGEN_INSN_WORD insn = entire_insn;
843 #define FLD(f) abuf->fields.sfmt_and3.f
844 UINT f_r1;
845 UINT f_r2;
846 UINT f_uimm16;
847
848 f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4);
849 f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4);
850 f_uimm16 = EXTRACT_MSB0_UINT (insn, 32, 16, 16);
851
852 /* Record the fields for the semantic handler. */
853 FLD (f_r2) = f_r2;
854 FLD (f_uimm16) = f_uimm16;
855 FLD (f_r1) = f_r1;
856 FLD (i_sr) = & CPU (h_gr)[f_r2];
857 FLD (i_dr) = & CPU (h_gr)[f_r1];
858 CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_and3", "f_r2 0x%x", 'x', f_r2, "f_uimm16 0x%x", 'x', f_uimm16, "f_r1 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0));
859
860 #if WITH_PROFILE_MODEL_P
861 /* Record the fields for profiling. */
862 if (PROFILE_MODEL_P (current_cpu))
863 {
864 FLD (in_sr) = f_r2;
865 FLD (out_dr) = f_r1;
866 }
867 #endif
868 #undef FLD
869 return idesc;
870 }
871
872 extract_sfmt_or3:
873 {
874 const IDESC *idesc = &m32r2f_insn_data[itype];
875 CGEN_INSN_WORD insn = entire_insn;
876 #define FLD(f) abuf->fields.sfmt_and3.f
877 UINT f_r1;
878 UINT f_r2;
879 UINT f_uimm16;
880
881 f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4);
882 f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4);
883 f_uimm16 = EXTRACT_MSB0_UINT (insn, 32, 16, 16);
884
885 /* Record the fields for the semantic handler. */
886 FLD (f_r2) = f_r2;
887 FLD (f_uimm16) = f_uimm16;
888 FLD (f_r1) = f_r1;
889 FLD (i_sr) = & CPU (h_gr)[f_r2];
890 FLD (i_dr) = & CPU (h_gr)[f_r1];
891 CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_or3", "f_r2 0x%x", 'x', f_r2, "f_uimm16 0x%x", 'x', f_uimm16, "f_r1 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0));
892
893 #if WITH_PROFILE_MODEL_P
894 /* Record the fields for profiling. */
895 if (PROFILE_MODEL_P (current_cpu))
896 {
897 FLD (in_sr) = f_r2;
898 FLD (out_dr) = f_r1;
899 }
900 #endif
901 #undef FLD
902 return idesc;
903 }
904
905 extract_sfmt_addi:
906 {
907 const IDESC *idesc = &m32r2f_insn_data[itype];
908 CGEN_INSN_WORD insn = entire_insn;
909 #define FLD(f) abuf->fields.sfmt_addi.f
910 UINT f_r1;
911 INT f_simm8;
912
913 f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4);
914 f_simm8 = EXTRACT_MSB0_SINT (insn, 16, 8, 8);
915
916 /* Record the fields for the semantic handler. */
917 FLD (f_r1) = f_r1;
918 FLD (f_simm8) = f_simm8;
919 FLD (i_dr) = & CPU (h_gr)[f_r1];
920 CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_addi", "f_r1 0x%x", 'x', f_r1, "f_simm8 0x%x", 'x', f_simm8, "dr 0x%x", 'x', f_r1, (char *) 0));
921
922 #if WITH_PROFILE_MODEL_P
923 /* Record the fields for profiling. */
924 if (PROFILE_MODEL_P (current_cpu))
925 {
926 FLD (in_dr) = f_r1;
927 FLD (out_dr) = f_r1;
928 }
929 #endif
930 #undef FLD
931 return idesc;
932 }
933
934 extract_sfmt_addv:
935 {
936 const IDESC *idesc = &m32r2f_insn_data[itype];
937 CGEN_INSN_WORD insn = entire_insn;
938 #define FLD(f) abuf->fields.sfmt_add.f
939 UINT f_r1;
940 UINT f_r2;
941
942 f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4);
943 f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4);
944
945 /* Record the fields for the semantic handler. */
946 FLD (f_r1) = f_r1;
947 FLD (f_r2) = f_r2;
948 FLD (i_dr) = & CPU (h_gr)[f_r1];
949 FLD (i_sr) = & CPU (h_gr)[f_r2];
950 CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_addv", "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, (char *) 0));
951
952 #if WITH_PROFILE_MODEL_P
953 /* Record the fields for profiling. */
954 if (PROFILE_MODEL_P (current_cpu))
955 {
956 FLD (in_dr) = f_r1;
957 FLD (in_sr) = f_r2;
958 FLD (out_dr) = f_r1;
959 }
960 #endif
961 #undef FLD
962 return idesc;
963 }
964
965 extract_sfmt_addv3:
966 {
967 const IDESC *idesc = &m32r2f_insn_data[itype];
968 CGEN_INSN_WORD insn = entire_insn;
969 #define FLD(f) abuf->fields.sfmt_add3.f
970 UINT f_r1;
971 UINT f_r2;
972 INT f_simm16;
973
974 f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4);
975 f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4);
976 f_simm16 = EXTRACT_MSB0_SINT (insn, 32, 16, 16);
977
978 /* Record the fields for the semantic handler. */
979 FLD (f_simm16) = f_simm16;
980 FLD (f_r2) = f_r2;
981 FLD (f_r1) = f_r1;
982 FLD (i_sr) = & CPU (h_gr)[f_r2];
983 FLD (i_dr) = & CPU (h_gr)[f_r1];
984 CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_addv3", "f_simm16 0x%x", 'x', f_simm16, "f_r2 0x%x", 'x', f_r2, "f_r1 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0));
985
986 #if WITH_PROFILE_MODEL_P
987 /* Record the fields for profiling. */
988 if (PROFILE_MODEL_P (current_cpu))
989 {
990 FLD (in_sr) = f_r2;
991 FLD (out_dr) = f_r1;
992 }
993 #endif
994 #undef FLD
995 return idesc;
996 }
997
998 extract_sfmt_addx:
999 {
1000 const IDESC *idesc = &m32r2f_insn_data[itype];
1001 CGEN_INSN_WORD insn = entire_insn;
1002 #define FLD(f) abuf->fields.sfmt_add.f
1003 UINT f_r1;
1004 UINT f_r2;
1005
1006 f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4);
1007 f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4);
1008
1009 /* Record the fields for the semantic handler. */
1010 FLD (f_r1) = f_r1;
1011 FLD (f_r2) = f_r2;
1012 FLD (i_dr) = & CPU (h_gr)[f_r1];
1013 FLD (i_sr) = & CPU (h_gr)[f_r2];
1014 CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_addx", "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, (char *) 0));
1015
1016 #if WITH_PROFILE_MODEL_P
1017 /* Record the fields for profiling. */
1018 if (PROFILE_MODEL_P (current_cpu))
1019 {
1020 FLD (in_dr) = f_r1;
1021 FLD (in_sr) = f_r2;
1022 FLD (out_dr) = f_r1;
1023 }
1024 #endif
1025 #undef FLD
1026 return idesc;
1027 }
1028
1029 extract_sfmt_bc8:
1030 {
1031 const IDESC *idesc = &m32r2f_insn_data[itype];
1032 CGEN_INSN_WORD insn = entire_insn;
1033 #define FLD(f) abuf->fields.sfmt_bl8.f
1034 SI f_disp8;
1035
1036 f_disp8 = ((((EXTRACT_MSB0_SINT (insn, 16, 8, 8)) << (2))) + (((pc) & (-4))));
1037
1038 /* Record the fields for the semantic handler. */
1039 FLD (i_disp8) = f_disp8;
1040 CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_bc8", "disp8 0x%x", 'x', f_disp8, (char *) 0));
1041
1042 #if WITH_PROFILE_MODEL_P
1043 /* Record the fields for profiling. */
1044 if (PROFILE_MODEL_P (current_cpu))
1045 {
1046 }
1047 #endif
1048 #undef FLD
1049 return idesc;
1050 }
1051
1052 extract_sfmt_bc24:
1053 {
1054 const IDESC *idesc = &m32r2f_insn_data[itype];
1055 CGEN_INSN_WORD insn = entire_insn;
1056 #define FLD(f) abuf->fields.sfmt_bl24.f
1057 SI f_disp24;
1058
1059 f_disp24 = ((((EXTRACT_MSB0_SINT (insn, 32, 8, 24)) << (2))) + (pc));
1060
1061 /* Record the fields for the semantic handler. */
1062 FLD (i_disp24) = f_disp24;
1063 CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_bc24", "disp24 0x%x", 'x', f_disp24, (char *) 0));
1064
1065 #if WITH_PROFILE_MODEL_P
1066 /* Record the fields for profiling. */
1067 if (PROFILE_MODEL_P (current_cpu))
1068 {
1069 }
1070 #endif
1071 #undef FLD
1072 return idesc;
1073 }
1074
1075 extract_sfmt_beq:
1076 {
1077 const IDESC *idesc = &m32r2f_insn_data[itype];
1078 CGEN_INSN_WORD insn = entire_insn;
1079 #define FLD(f) abuf->fields.sfmt_beq.f
1080 UINT f_r1;
1081 UINT f_r2;
1082 SI f_disp16;
1083
1084 f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4);
1085 f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4);
1086 f_disp16 = ((((EXTRACT_MSB0_SINT (insn, 32, 16, 16)) << (2))) + (pc));
1087
1088 /* Record the fields for the semantic handler. */
1089 FLD (f_r1) = f_r1;
1090 FLD (f_r2) = f_r2;
1091 FLD (i_disp16) = f_disp16;
1092 FLD (i_src1) = & CPU (h_gr)[f_r1];
1093 FLD (i_src2) = & CPU (h_gr)[f_r2];
1094 CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_beq", "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "disp16 0x%x", 'x', f_disp16, "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0));
1095
1096 #if WITH_PROFILE_MODEL_P
1097 /* Record the fields for profiling. */
1098 if (PROFILE_MODEL_P (current_cpu))
1099 {
1100 FLD (in_src1) = f_r1;
1101 FLD (in_src2) = f_r2;
1102 }
1103 #endif
1104 #undef FLD
1105 return idesc;
1106 }
1107
1108 extract_sfmt_beqz:
1109 {
1110 const IDESC *idesc = &m32r2f_insn_data[itype];
1111 CGEN_INSN_WORD insn = entire_insn;
1112 #define FLD(f) abuf->fields.sfmt_beq.f
1113 UINT f_r2;
1114 SI f_disp16;
1115
1116 f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4);
1117 f_disp16 = ((((EXTRACT_MSB0_SINT (insn, 32, 16, 16)) << (2))) + (pc));
1118
1119 /* Record the fields for the semantic handler. */
1120 FLD (f_r2) = f_r2;
1121 FLD (i_disp16) = f_disp16;
1122 FLD (i_src2) = & CPU (h_gr)[f_r2];
1123 CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_beqz", "f_r2 0x%x", 'x', f_r2, "disp16 0x%x", 'x', f_disp16, "src2 0x%x", 'x', f_r2, (char *) 0));
1124
1125 #if WITH_PROFILE_MODEL_P
1126 /* Record the fields for profiling. */
1127 if (PROFILE_MODEL_P (current_cpu))
1128 {
1129 FLD (in_src2) = f_r2;
1130 }
1131 #endif
1132 #undef FLD
1133 return idesc;
1134 }
1135
1136 extract_sfmt_bl8:
1137 {
1138 const IDESC *idesc = &m32r2f_insn_data[itype];
1139 CGEN_INSN_WORD insn = entire_insn;
1140 #define FLD(f) abuf->fields.sfmt_bl8.f
1141 SI f_disp8;
1142
1143 f_disp8 = ((((EXTRACT_MSB0_SINT (insn, 16, 8, 8)) << (2))) + (((pc) & (-4))));
1144
1145 /* Record the fields for the semantic handler. */
1146 FLD (i_disp8) = f_disp8;
1147 CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_bl8", "disp8 0x%x", 'x', f_disp8, (char *) 0));
1148
1149 #if WITH_PROFILE_MODEL_P
1150 /* Record the fields for profiling. */
1151 if (PROFILE_MODEL_P (current_cpu))
1152 {
1153 FLD (out_h_gr_SI_14) = 14;
1154 }
1155 #endif
1156 #undef FLD
1157 return idesc;
1158 }
1159
1160 extract_sfmt_bl24:
1161 {
1162 const IDESC *idesc = &m32r2f_insn_data[itype];
1163 CGEN_INSN_WORD insn = entire_insn;
1164 #define FLD(f) abuf->fields.sfmt_bl24.f
1165 SI f_disp24;
1166
1167 f_disp24 = ((((EXTRACT_MSB0_SINT (insn, 32, 8, 24)) << (2))) + (pc));
1168
1169 /* Record the fields for the semantic handler. */
1170 FLD (i_disp24) = f_disp24;
1171 CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_bl24", "disp24 0x%x", 'x', f_disp24, (char *) 0));
1172
1173 #if WITH_PROFILE_MODEL_P
1174 /* Record the fields for profiling. */
1175 if (PROFILE_MODEL_P (current_cpu))
1176 {
1177 FLD (out_h_gr_SI_14) = 14;
1178 }
1179 #endif
1180 #undef FLD
1181 return idesc;
1182 }
1183
1184 extract_sfmt_bcl8:
1185 {
1186 const IDESC *idesc = &m32r2f_insn_data[itype];
1187 CGEN_INSN_WORD insn = entire_insn;
1188 #define FLD(f) abuf->fields.sfmt_bl8.f
1189 SI f_disp8;
1190
1191 f_disp8 = ((((EXTRACT_MSB0_SINT (insn, 16, 8, 8)) << (2))) + (((pc) & (-4))));
1192
1193 /* Record the fields for the semantic handler. */
1194 FLD (i_disp8) = f_disp8;
1195 CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_bcl8", "disp8 0x%x", 'x', f_disp8, (char *) 0));
1196
1197 #if WITH_PROFILE_MODEL_P
1198 /* Record the fields for profiling. */
1199 if (PROFILE_MODEL_P (current_cpu))
1200 {
1201 FLD (out_h_gr_SI_14) = 14;
1202 }
1203 #endif
1204 #undef FLD
1205 return idesc;
1206 }
1207
1208 extract_sfmt_bcl24:
1209 {
1210 const IDESC *idesc = &m32r2f_insn_data[itype];
1211 CGEN_INSN_WORD insn = entire_insn;
1212 #define FLD(f) abuf->fields.sfmt_bl24.f
1213 SI f_disp24;
1214
1215 f_disp24 = ((((EXTRACT_MSB0_SINT (insn, 32, 8, 24)) << (2))) + (pc));
1216
1217 /* Record the fields for the semantic handler. */
1218 FLD (i_disp24) = f_disp24;
1219 CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_bcl24", "disp24 0x%x", 'x', f_disp24, (char *) 0));
1220
1221 #if WITH_PROFILE_MODEL_P
1222 /* Record the fields for profiling. */
1223 if (PROFILE_MODEL_P (current_cpu))
1224 {
1225 FLD (out_h_gr_SI_14) = 14;
1226 }
1227 #endif
1228 #undef FLD
1229 return idesc;
1230 }
1231
1232 extract_sfmt_bra8:
1233 {
1234 const IDESC *idesc = &m32r2f_insn_data[itype];
1235 CGEN_INSN_WORD insn = entire_insn;
1236 #define FLD(f) abuf->fields.sfmt_bl8.f
1237 SI f_disp8;
1238
1239 f_disp8 = ((((EXTRACT_MSB0_SINT (insn, 16, 8, 8)) << (2))) + (((pc) & (-4))));
1240
1241 /* Record the fields for the semantic handler. */
1242 FLD (i_disp8) = f_disp8;
1243 CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_bra8", "disp8 0x%x", 'x', f_disp8, (char *) 0));
1244
1245 #if WITH_PROFILE_MODEL_P
1246 /* Record the fields for profiling. */
1247 if (PROFILE_MODEL_P (current_cpu))
1248 {
1249 }
1250 #endif
1251 #undef FLD
1252 return idesc;
1253 }
1254
1255 extract_sfmt_bra24:
1256 {
1257 const IDESC *idesc = &m32r2f_insn_data[itype];
1258 CGEN_INSN_WORD insn = entire_insn;
1259 #define FLD(f) abuf->fields.sfmt_bl24.f
1260 SI f_disp24;
1261
1262 f_disp24 = ((((EXTRACT_MSB0_SINT (insn, 32, 8, 24)) << (2))) + (pc));
1263
1264 /* Record the fields for the semantic handler. */
1265 FLD (i_disp24) = f_disp24;
1266 CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_bra24", "disp24 0x%x", 'x', f_disp24, (char *) 0));
1267
1268 #if WITH_PROFILE_MODEL_P
1269 /* Record the fields for profiling. */
1270 if (PROFILE_MODEL_P (current_cpu))
1271 {
1272 }
1273 #endif
1274 #undef FLD
1275 return idesc;
1276 }
1277
1278 extract_sfmt_cmp:
1279 {
1280 const IDESC *idesc = &m32r2f_insn_data[itype];
1281 CGEN_INSN_WORD insn = entire_insn;
1282 #define FLD(f) abuf->fields.sfmt_st_plus.f
1283 UINT f_r1;
1284 UINT f_r2;
1285
1286 f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4);
1287 f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4);
1288
1289 /* Record the fields for the semantic handler. */
1290 FLD (f_r1) = f_r1;
1291 FLD (f_r2) = f_r2;
1292 FLD (i_src1) = & CPU (h_gr)[f_r1];
1293 FLD (i_src2) = & CPU (h_gr)[f_r2];
1294 CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_cmp", "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0));
1295
1296 #if WITH_PROFILE_MODEL_P
1297 /* Record the fields for profiling. */
1298 if (PROFILE_MODEL_P (current_cpu))
1299 {
1300 FLD (in_src1) = f_r1;
1301 FLD (in_src2) = f_r2;
1302 }
1303 #endif
1304 #undef FLD
1305 return idesc;
1306 }
1307
1308 extract_sfmt_cmpi:
1309 {
1310 const IDESC *idesc = &m32r2f_insn_data[itype];
1311 CGEN_INSN_WORD insn = entire_insn;
1312 #define FLD(f) abuf->fields.sfmt_st_d.f
1313 UINT f_r2;
1314 INT f_simm16;
1315
1316 f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4);
1317 f_simm16 = EXTRACT_MSB0_SINT (insn, 32, 16, 16);
1318
1319 /* Record the fields for the semantic handler. */
1320 FLD (f_simm16) = f_simm16;
1321 FLD (f_r2) = f_r2;
1322 FLD (i_src2) = & CPU (h_gr)[f_r2];
1323 CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_cmpi", "f_simm16 0x%x", 'x', f_simm16, "f_r2 0x%x", 'x', f_r2, "src2 0x%x", 'x', f_r2, (char *) 0));
1324
1325 #if WITH_PROFILE_MODEL_P
1326 /* Record the fields for profiling. */
1327 if (PROFILE_MODEL_P (current_cpu))
1328 {
1329 FLD (in_src2) = f_r2;
1330 }
1331 #endif
1332 #undef FLD
1333 return idesc;
1334 }
1335
1336 extract_sfmt_cmpz:
1337 {
1338 const IDESC *idesc = &m32r2f_insn_data[itype];
1339 CGEN_INSN_WORD insn = entire_insn;
1340 #define FLD(f) abuf->fields.sfmt_st_plus.f
1341 UINT f_r2;
1342
1343 f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4);
1344
1345 /* Record the fields for the semantic handler. */
1346 FLD (f_r2) = f_r2;
1347 FLD (i_src2) = & CPU (h_gr)[f_r2];
1348 CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_cmpz", "f_r2 0x%x", 'x', f_r2, "src2 0x%x", 'x', f_r2, (char *) 0));
1349
1350 #if WITH_PROFILE_MODEL_P
1351 /* Record the fields for profiling. */
1352 if (PROFILE_MODEL_P (current_cpu))
1353 {
1354 FLD (in_src2) = f_r2;
1355 }
1356 #endif
1357 #undef FLD
1358 return idesc;
1359 }
1360
1361 extract_sfmt_div:
1362 {
1363 const IDESC *idesc = &m32r2f_insn_data[itype];
1364 CGEN_INSN_WORD insn = entire_insn;
1365 #define FLD(f) abuf->fields.sfmt_add.f
1366 UINT f_r1;
1367 UINT f_r2;
1368
1369 f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4);
1370 f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4);
1371
1372 /* Record the fields for the semantic handler. */
1373 FLD (f_r1) = f_r1;
1374 FLD (f_r2) = f_r2;
1375 FLD (i_dr) = & CPU (h_gr)[f_r1];
1376 FLD (i_sr) = & CPU (h_gr)[f_r2];
1377 CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_div", "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, (char *) 0));
1378
1379 #if WITH_PROFILE_MODEL_P
1380 /* Record the fields for profiling. */
1381 if (PROFILE_MODEL_P (current_cpu))
1382 {
1383 FLD (in_dr) = f_r1;
1384 FLD (in_sr) = f_r2;
1385 FLD (out_dr) = f_r1;
1386 }
1387 #endif
1388 #undef FLD
1389 return idesc;
1390 }
1391
1392 extract_sfmt_jc:
1393 {
1394 const IDESC *idesc = &m32r2f_insn_data[itype];
1395 CGEN_INSN_WORD insn = entire_insn;
1396 #define FLD(f) abuf->fields.sfmt_jl.f
1397 UINT f_r2;
1398
1399 f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4);
1400
1401 /* Record the fields for the semantic handler. */
1402 FLD (f_r2) = f_r2;
1403 FLD (i_sr) = & CPU (h_gr)[f_r2];
1404 CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_jc", "f_r2 0x%x", 'x', f_r2, "sr 0x%x", 'x', f_r2, (char *) 0));
1405
1406 #if WITH_PROFILE_MODEL_P
1407 /* Record the fields for profiling. */
1408 if (PROFILE_MODEL_P (current_cpu))
1409 {
1410 FLD (in_sr) = f_r2;
1411 }
1412 #endif
1413 #undef FLD
1414 return idesc;
1415 }
1416
1417 extract_sfmt_jl:
1418 {
1419 const IDESC *idesc = &m32r2f_insn_data[itype];
1420 CGEN_INSN_WORD insn = entire_insn;
1421 #define FLD(f) abuf->fields.sfmt_jl.f
1422 UINT f_r2;
1423
1424 f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4);
1425
1426 /* Record the fields for the semantic handler. */
1427 FLD (f_r2) = f_r2;
1428 FLD (i_sr) = & CPU (h_gr)[f_r2];
1429 CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_jl", "f_r2 0x%x", 'x', f_r2, "sr 0x%x", 'x', f_r2, (char *) 0));
1430
1431 #if WITH_PROFILE_MODEL_P
1432 /* Record the fields for profiling. */
1433 if (PROFILE_MODEL_P (current_cpu))
1434 {
1435 FLD (in_sr) = f_r2;
1436 FLD (out_h_gr_SI_14) = 14;
1437 }
1438 #endif
1439 #undef FLD
1440 return idesc;
1441 }
1442
1443 extract_sfmt_jmp:
1444 {
1445 const IDESC *idesc = &m32r2f_insn_data[itype];
1446 CGEN_INSN_WORD insn = entire_insn;
1447 #define FLD(f) abuf->fields.sfmt_jl.f
1448 UINT f_r2;
1449
1450 f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4);
1451
1452 /* Record the fields for the semantic handler. */
1453 FLD (f_r2) = f_r2;
1454 FLD (i_sr) = & CPU (h_gr)[f_r2];
1455 CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_jmp", "f_r2 0x%x", 'x', f_r2, "sr 0x%x", 'x', f_r2, (char *) 0));
1456
1457 #if WITH_PROFILE_MODEL_P
1458 /* Record the fields for profiling. */
1459 if (PROFILE_MODEL_P (current_cpu))
1460 {
1461 FLD (in_sr) = f_r2;
1462 }
1463 #endif
1464 #undef FLD
1465 return idesc;
1466 }
1467
1468 extract_sfmt_ld:
1469 {
1470 const IDESC *idesc = &m32r2f_insn_data[itype];
1471 CGEN_INSN_WORD insn = entire_insn;
1472 #define FLD(f) abuf->fields.sfmt_ld_plus.f
1473 UINT f_r1;
1474 UINT f_r2;
1475
1476 f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4);
1477 f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4);
1478
1479 /* Record the fields for the semantic handler. */
1480 FLD (f_r2) = f_r2;
1481 FLD (f_r1) = f_r1;
1482 FLD (i_sr) = & CPU (h_gr)[f_r2];
1483 FLD (i_dr) = & CPU (h_gr)[f_r1];
1484 CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ld", "f_r2 0x%x", 'x', f_r2, "f_r1 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0));
1485
1486 #if WITH_PROFILE_MODEL_P
1487 /* Record the fields for profiling. */
1488 if (PROFILE_MODEL_P (current_cpu))
1489 {
1490 FLD (in_sr) = f_r2;
1491 FLD (out_dr) = f_r1;
1492 }
1493 #endif
1494 #undef FLD
1495 return idesc;
1496 }
1497
1498 extract_sfmt_ld_d:
1499 {
1500 const IDESC *idesc = &m32r2f_insn_data[itype];
1501 CGEN_INSN_WORD insn = entire_insn;
1502 #define FLD(f) abuf->fields.sfmt_add3.f
1503 UINT f_r1;
1504 UINT f_r2;
1505 INT f_simm16;
1506
1507 f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4);
1508 f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4);
1509 f_simm16 = EXTRACT_MSB0_SINT (insn, 32, 16, 16);
1510
1511 /* Record the fields for the semantic handler. */
1512 FLD (f_simm16) = f_simm16;
1513 FLD (f_r2) = f_r2;
1514 FLD (f_r1) = f_r1;
1515 FLD (i_sr) = & CPU (h_gr)[f_r2];
1516 FLD (i_dr) = & CPU (h_gr)[f_r1];
1517 CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ld_d", "f_simm16 0x%x", 'x', f_simm16, "f_r2 0x%x", 'x', f_r2, "f_r1 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0));
1518
1519 #if WITH_PROFILE_MODEL_P
1520 /* Record the fields for profiling. */
1521 if (PROFILE_MODEL_P (current_cpu))
1522 {
1523 FLD (in_sr) = f_r2;
1524 FLD (out_dr) = f_r1;
1525 }
1526 #endif
1527 #undef FLD
1528 return idesc;
1529 }
1530
1531 extract_sfmt_ldb:
1532 {
1533 const IDESC *idesc = &m32r2f_insn_data[itype];
1534 CGEN_INSN_WORD insn = entire_insn;
1535 #define FLD(f) abuf->fields.sfmt_ld_plus.f
1536 UINT f_r1;
1537 UINT f_r2;
1538
1539 f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4);
1540 f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4);
1541
1542 /* Record the fields for the semantic handler. */
1543 FLD (f_r2) = f_r2;
1544 FLD (f_r1) = f_r1;
1545 FLD (i_sr) = & CPU (h_gr)[f_r2];
1546 FLD (i_dr) = & CPU (h_gr)[f_r1];
1547 CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ldb", "f_r2 0x%x", 'x', f_r2, "f_r1 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0));
1548
1549 #if WITH_PROFILE_MODEL_P
1550 /* Record the fields for profiling. */
1551 if (PROFILE_MODEL_P (current_cpu))
1552 {
1553 FLD (in_sr) = f_r2;
1554 FLD (out_dr) = f_r1;
1555 }
1556 #endif
1557 #undef FLD
1558 return idesc;
1559 }
1560
1561 extract_sfmt_ldb_d:
1562 {
1563 const IDESC *idesc = &m32r2f_insn_data[itype];
1564 CGEN_INSN_WORD insn = entire_insn;
1565 #define FLD(f) abuf->fields.sfmt_add3.f
1566 UINT f_r1;
1567 UINT f_r2;
1568 INT f_simm16;
1569
1570 f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4);
1571 f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4);
1572 f_simm16 = EXTRACT_MSB0_SINT (insn, 32, 16, 16);
1573
1574 /* Record the fields for the semantic handler. */
1575 FLD (f_simm16) = f_simm16;
1576 FLD (f_r2) = f_r2;
1577 FLD (f_r1) = f_r1;
1578 FLD (i_sr) = & CPU (h_gr)[f_r2];
1579 FLD (i_dr) = & CPU (h_gr)[f_r1];
1580 CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ldb_d", "f_simm16 0x%x", 'x', f_simm16, "f_r2 0x%x", 'x', f_r2, "f_r1 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0));
1581
1582 #if WITH_PROFILE_MODEL_P
1583 /* Record the fields for profiling. */
1584 if (PROFILE_MODEL_P (current_cpu))
1585 {
1586 FLD (in_sr) = f_r2;
1587 FLD (out_dr) = f_r1;
1588 }
1589 #endif
1590 #undef FLD
1591 return idesc;
1592 }
1593
1594 extract_sfmt_ldh:
1595 {
1596 const IDESC *idesc = &m32r2f_insn_data[itype];
1597 CGEN_INSN_WORD insn = entire_insn;
1598 #define FLD(f) abuf->fields.sfmt_ld_plus.f
1599 UINT f_r1;
1600 UINT f_r2;
1601
1602 f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4);
1603 f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4);
1604
1605 /* Record the fields for the semantic handler. */
1606 FLD (f_r2) = f_r2;
1607 FLD (f_r1) = f_r1;
1608 FLD (i_sr) = & CPU (h_gr)[f_r2];
1609 FLD (i_dr) = & CPU (h_gr)[f_r1];
1610 CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ldh", "f_r2 0x%x", 'x', f_r2, "f_r1 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0));
1611
1612 #if WITH_PROFILE_MODEL_P
1613 /* Record the fields for profiling. */
1614 if (PROFILE_MODEL_P (current_cpu))
1615 {
1616 FLD (in_sr) = f_r2;
1617 FLD (out_dr) = f_r1;
1618 }
1619 #endif
1620 #undef FLD
1621 return idesc;
1622 }
1623
1624 extract_sfmt_ldh_d:
1625 {
1626 const IDESC *idesc = &m32r2f_insn_data[itype];
1627 CGEN_INSN_WORD insn = entire_insn;
1628 #define FLD(f) abuf->fields.sfmt_add3.f
1629 UINT f_r1;
1630 UINT f_r2;
1631 INT f_simm16;
1632
1633 f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4);
1634 f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4);
1635 f_simm16 = EXTRACT_MSB0_SINT (insn, 32, 16, 16);
1636
1637 /* Record the fields for the semantic handler. */
1638 FLD (f_simm16) = f_simm16;
1639 FLD (f_r2) = f_r2;
1640 FLD (f_r1) = f_r1;
1641 FLD (i_sr) = & CPU (h_gr)[f_r2];
1642 FLD (i_dr) = & CPU (h_gr)[f_r1];
1643 CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ldh_d", "f_simm16 0x%x", 'x', f_simm16, "f_r2 0x%x", 'x', f_r2, "f_r1 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0));
1644
1645 #if WITH_PROFILE_MODEL_P
1646 /* Record the fields for profiling. */
1647 if (PROFILE_MODEL_P (current_cpu))
1648 {
1649 FLD (in_sr) = f_r2;
1650 FLD (out_dr) = f_r1;
1651 }
1652 #endif
1653 #undef FLD
1654 return idesc;
1655 }
1656
1657 extract_sfmt_ld_plus:
1658 {
1659 const IDESC *idesc = &m32r2f_insn_data[itype];
1660 CGEN_INSN_WORD insn = entire_insn;
1661 #define FLD(f) abuf->fields.sfmt_ld_plus.f
1662 UINT f_r1;
1663 UINT f_r2;
1664
1665 f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4);
1666 f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4);
1667
1668 /* Record the fields for the semantic handler. */
1669 FLD (f_r2) = f_r2;
1670 FLD (f_r1) = f_r1;
1671 FLD (i_sr) = & CPU (h_gr)[f_r2];
1672 FLD (i_dr) = & CPU (h_gr)[f_r1];
1673 CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ld_plus", "f_r2 0x%x", 'x', f_r2, "f_r1 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0));
1674
1675 #if WITH_PROFILE_MODEL_P
1676 /* Record the fields for profiling. */
1677 if (PROFILE_MODEL_P (current_cpu))
1678 {
1679 FLD (in_sr) = f_r2;
1680 FLD (out_dr) = f_r1;
1681 FLD (out_sr) = f_r2;
1682 }
1683 #endif
1684 #undef FLD
1685 return idesc;
1686 }
1687
1688 extract_sfmt_ld24:
1689 {
1690 const IDESC *idesc = &m32r2f_insn_data[itype];
1691 CGEN_INSN_WORD insn = entire_insn;
1692 #define FLD(f) abuf->fields.sfmt_ld24.f
1693 UINT f_r1;
1694 UINT f_uimm24;
1695
1696 f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4);
1697 f_uimm24 = EXTRACT_MSB0_UINT (insn, 32, 8, 24);
1698
1699 /* Record the fields for the semantic handler. */
1700 FLD (f_r1) = f_r1;
1701 FLD (i_uimm24) = f_uimm24;
1702 FLD (i_dr) = & CPU (h_gr)[f_r1];
1703 CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ld24", "f_r1 0x%x", 'x', f_r1, "uimm24 0x%x", 'x', f_uimm24, "dr 0x%x", 'x', f_r1, (char *) 0));
1704
1705 #if WITH_PROFILE_MODEL_P
1706 /* Record the fields for profiling. */
1707 if (PROFILE_MODEL_P (current_cpu))
1708 {
1709 FLD (out_dr) = f_r1;
1710 }
1711 #endif
1712 #undef FLD
1713 return idesc;
1714 }
1715
1716 extract_sfmt_ldi8:
1717 {
1718 const IDESC *idesc = &m32r2f_insn_data[itype];
1719 CGEN_INSN_WORD insn = entire_insn;
1720 #define FLD(f) abuf->fields.sfmt_addi.f
1721 UINT f_r1;
1722 INT f_simm8;
1723
1724 f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4);
1725 f_simm8 = EXTRACT_MSB0_SINT (insn, 16, 8, 8);
1726
1727 /* Record the fields for the semantic handler. */
1728 FLD (f_simm8) = f_simm8;
1729 FLD (f_r1) = f_r1;
1730 FLD (i_dr) = & CPU (h_gr)[f_r1];
1731 CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ldi8", "f_simm8 0x%x", 'x', f_simm8, "f_r1 0x%x", 'x', f_r1, "dr 0x%x", 'x', f_r1, (char *) 0));
1732
1733 #if WITH_PROFILE_MODEL_P
1734 /* Record the fields for profiling. */
1735 if (PROFILE_MODEL_P (current_cpu))
1736 {
1737 FLD (out_dr) = f_r1;
1738 }
1739 #endif
1740 #undef FLD
1741 return idesc;
1742 }
1743
1744 extract_sfmt_ldi16:
1745 {
1746 const IDESC *idesc = &m32r2f_insn_data[itype];
1747 CGEN_INSN_WORD insn = entire_insn;
1748 #define FLD(f) abuf->fields.sfmt_add3.f
1749 UINT f_r1;
1750 INT f_simm16;
1751
1752 f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4);
1753 f_simm16 = EXTRACT_MSB0_SINT (insn, 32, 16, 16);
1754
1755 /* Record the fields for the semantic handler. */
1756 FLD (f_simm16) = f_simm16;
1757 FLD (f_r1) = f_r1;
1758 FLD (i_dr) = & CPU (h_gr)[f_r1];
1759 CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ldi16", "f_simm16 0x%x", 'x', f_simm16, "f_r1 0x%x", 'x', f_r1, "dr 0x%x", 'x', f_r1, (char *) 0));
1760
1761 #if WITH_PROFILE_MODEL_P
1762 /* Record the fields for profiling. */
1763 if (PROFILE_MODEL_P (current_cpu))
1764 {
1765 FLD (out_dr) = f_r1;
1766 }
1767 #endif
1768 #undef FLD
1769 return idesc;
1770 }
1771
1772 extract_sfmt_lock:
1773 {
1774 const IDESC *idesc = &m32r2f_insn_data[itype];
1775 CGEN_INSN_WORD insn = entire_insn;
1776 #define FLD(f) abuf->fields.sfmt_ld_plus.f
1777 UINT f_r1;
1778 UINT f_r2;
1779
1780 f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4);
1781 f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4);
1782
1783 /* Record the fields for the semantic handler. */
1784 FLD (f_r2) = f_r2;
1785 FLD (f_r1) = f_r1;
1786 FLD (i_sr) = & CPU (h_gr)[f_r2];
1787 FLD (i_dr) = & CPU (h_gr)[f_r1];
1788 CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_lock", "f_r2 0x%x", 'x', f_r2, "f_r1 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0));
1789
1790 #if WITH_PROFILE_MODEL_P
1791 /* Record the fields for profiling. */
1792 if (PROFILE_MODEL_P (current_cpu))
1793 {
1794 FLD (in_sr) = f_r2;
1795 FLD (out_dr) = f_r1;
1796 }
1797 #endif
1798 #undef FLD
1799 return idesc;
1800 }
1801
1802 extract_sfmt_machi_a:
1803 {
1804 const IDESC *idesc = &m32r2f_insn_data[itype];
1805 CGEN_INSN_WORD insn = entire_insn;
1806 #define FLD(f) abuf->fields.sfmt_machi_a.f
1807 UINT f_r1;
1808 UINT f_acc;
1809 UINT f_r2;
1810
1811 f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4);
1812 f_acc = EXTRACT_MSB0_UINT (insn, 16, 8, 1);
1813 f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4);
1814
1815 /* Record the fields for the semantic handler. */
1816 FLD (f_acc) = f_acc;
1817 FLD (f_r1) = f_r1;
1818 FLD (f_r2) = f_r2;
1819 FLD (i_src1) = & CPU (h_gr)[f_r1];
1820 FLD (i_src2) = & CPU (h_gr)[f_r2];
1821 CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_machi_a", "f_acc 0x%x", 'x', f_acc, "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0));
1822
1823 #if WITH_PROFILE_MODEL_P
1824 /* Record the fields for profiling. */
1825 if (PROFILE_MODEL_P (current_cpu))
1826 {
1827 FLD (in_src1) = f_r1;
1828 FLD (in_src2) = f_r2;
1829 }
1830 #endif
1831 #undef FLD
1832 return idesc;
1833 }
1834
1835 extract_sfmt_mulhi_a:
1836 {
1837 const IDESC *idesc = &m32r2f_insn_data[itype];
1838 CGEN_INSN_WORD insn = entire_insn;
1839 #define FLD(f) abuf->fields.sfmt_machi_a.f
1840 UINT f_r1;
1841 UINT f_acc;
1842 UINT f_r2;
1843
1844 f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4);
1845 f_acc = EXTRACT_MSB0_UINT (insn, 16, 8, 1);
1846 f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4);
1847
1848 /* Record the fields for the semantic handler. */
1849 FLD (f_r1) = f_r1;
1850 FLD (f_r2) = f_r2;
1851 FLD (f_acc) = f_acc;
1852 FLD (i_src1) = & CPU (h_gr)[f_r1];
1853 FLD (i_src2) = & CPU (h_gr)[f_r2];
1854 CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_mulhi_a", "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "f_acc 0x%x", 'x', f_acc, "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0));
1855
1856 #if WITH_PROFILE_MODEL_P
1857 /* Record the fields for profiling. */
1858 if (PROFILE_MODEL_P (current_cpu))
1859 {
1860 FLD (in_src1) = f_r1;
1861 FLD (in_src2) = f_r2;
1862 }
1863 #endif
1864 #undef FLD
1865 return idesc;
1866 }
1867
1868 extract_sfmt_mv:
1869 {
1870 const IDESC *idesc = &m32r2f_insn_data[itype];
1871 CGEN_INSN_WORD insn = entire_insn;
1872 #define FLD(f) abuf->fields.sfmt_ld_plus.f
1873 UINT f_r1;
1874 UINT f_r2;
1875
1876 f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4);
1877 f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4);
1878
1879 /* Record the fields for the semantic handler. */
1880 FLD (f_r2) = f_r2;
1881 FLD (f_r1) = f_r1;
1882 FLD (i_sr) = & CPU (h_gr)[f_r2];
1883 FLD (i_dr) = & CPU (h_gr)[f_r1];
1884 CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_mv", "f_r2 0x%x", 'x', f_r2, "f_r1 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0));
1885
1886 #if WITH_PROFILE_MODEL_P
1887 /* Record the fields for profiling. */
1888 if (PROFILE_MODEL_P (current_cpu))
1889 {
1890 FLD (in_sr) = f_r2;
1891 FLD (out_dr) = f_r1;
1892 }
1893 #endif
1894 #undef FLD
1895 return idesc;
1896 }
1897
1898 extract_sfmt_mvfachi_a:
1899 {
1900 const IDESC *idesc = &m32r2f_insn_data[itype];
1901 CGEN_INSN_WORD insn = entire_insn;
1902 #define FLD(f) abuf->fields.sfmt_mvfachi_a.f
1903 UINT f_r1;
1904 UINT f_accs;
1905
1906 f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4);
1907 f_accs = EXTRACT_MSB0_UINT (insn, 16, 12, 2);
1908
1909 /* Record the fields for the semantic handler. */
1910 FLD (f_accs) = f_accs;
1911 FLD (f_r1) = f_r1;
1912 FLD (i_dr) = & CPU (h_gr)[f_r1];
1913 CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_mvfachi_a", "f_accs 0x%x", 'x', f_accs, "f_r1 0x%x", 'x', f_r1, "dr 0x%x", 'x', f_r1, (char *) 0));
1914
1915 #if WITH_PROFILE_MODEL_P
1916 /* Record the fields for profiling. */
1917 if (PROFILE_MODEL_P (current_cpu))
1918 {
1919 FLD (out_dr) = f_r1;
1920 }
1921 #endif
1922 #undef FLD
1923 return idesc;
1924 }
1925
1926 extract_sfmt_mvfc:
1927 {
1928 const IDESC *idesc = &m32r2f_insn_data[itype];
1929 CGEN_INSN_WORD insn = entire_insn;
1930 #define FLD(f) abuf->fields.sfmt_ld_plus.f
1931 UINT f_r1;
1932 UINT f_r2;
1933
1934 f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4);
1935 f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4);
1936
1937 /* Record the fields for the semantic handler. */
1938 FLD (f_r2) = f_r2;
1939 FLD (f_r1) = f_r1;
1940 FLD (i_dr) = & CPU (h_gr)[f_r1];
1941 CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_mvfc", "f_r2 0x%x", 'x', f_r2, "f_r1 0x%x", 'x', f_r1, "dr 0x%x", 'x', f_r1, (char *) 0));
1942
1943 #if WITH_PROFILE_MODEL_P
1944 /* Record the fields for profiling. */
1945 if (PROFILE_MODEL_P (current_cpu))
1946 {
1947 FLD (out_dr) = f_r1;
1948 }
1949 #endif
1950 #undef FLD
1951 return idesc;
1952 }
1953
1954 extract_sfmt_mvtachi_a:
1955 {
1956 const IDESC *idesc = &m32r2f_insn_data[itype];
1957 CGEN_INSN_WORD insn = entire_insn;
1958 #define FLD(f) abuf->fields.sfmt_mvtachi_a.f
1959 UINT f_r1;
1960 UINT f_accs;
1961
1962 f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4);
1963 f_accs = EXTRACT_MSB0_UINT (insn, 16, 12, 2);
1964
1965 /* Record the fields for the semantic handler. */
1966 FLD (f_accs) = f_accs;
1967 FLD (f_r1) = f_r1;
1968 FLD (i_src1) = & CPU (h_gr)[f_r1];
1969 CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_mvtachi_a", "f_accs 0x%x", 'x', f_accs, "f_r1 0x%x", 'x', f_r1, "src1 0x%x", 'x', f_r1, (char *) 0));
1970
1971 #if WITH_PROFILE_MODEL_P
1972 /* Record the fields for profiling. */
1973 if (PROFILE_MODEL_P (current_cpu))
1974 {
1975 FLD (in_src1) = f_r1;
1976 }
1977 #endif
1978 #undef FLD
1979 return idesc;
1980 }
1981
1982 extract_sfmt_mvtc:
1983 {
1984 const IDESC *idesc = &m32r2f_insn_data[itype];
1985 CGEN_INSN_WORD insn = entire_insn;
1986 #define FLD(f) abuf->fields.sfmt_ld_plus.f
1987 UINT f_r1;
1988 UINT f_r2;
1989
1990 f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4);
1991 f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4);
1992
1993 /* Record the fields for the semantic handler. */
1994 FLD (f_r2) = f_r2;
1995 FLD (f_r1) = f_r1;
1996 FLD (i_sr) = & CPU (h_gr)[f_r2];
1997 CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_mvtc", "f_r2 0x%x", 'x', f_r2, "f_r1 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, (char *) 0));
1998
1999 #if WITH_PROFILE_MODEL_P
2000 /* Record the fields for profiling. */
2001 if (PROFILE_MODEL_P (current_cpu))
2002 {
2003 FLD (in_sr) = f_r2;
2004 }
2005 #endif
2006 #undef FLD
2007 return idesc;
2008 }
2009
2010 extract_sfmt_nop:
2011 {
2012 const IDESC *idesc = &m32r2f_insn_data[itype];
2013 #define FLD(f) abuf->fields.sfmt_empty.f
2014
2015
2016 /* Record the fields for the semantic handler. */
2017 CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_nop", (char *) 0));
2018
2019 #undef FLD
2020 return idesc;
2021 }
2022
2023 extract_sfmt_rac_dsi:
2024 {
2025 const IDESC *idesc = &m32r2f_insn_data[itype];
2026 CGEN_INSN_WORD insn = entire_insn;
2027 #define FLD(f) abuf->fields.sfmt_rac_dsi.f
2028 UINT f_accd;
2029 UINT f_accs;
2030 SI f_imm1;
2031
2032 f_accd = EXTRACT_MSB0_UINT (insn, 16, 4, 2);
2033 f_accs = EXTRACT_MSB0_UINT (insn, 16, 12, 2);
2034 f_imm1 = ((EXTRACT_MSB0_UINT (insn, 16, 15, 1)) + (1));
2035
2036 /* Record the fields for the semantic handler. */
2037 FLD (f_accs) = f_accs;
2038 FLD (f_imm1) = f_imm1;
2039 FLD (f_accd) = f_accd;
2040 CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_rac_dsi", "f_accs 0x%x", 'x', f_accs, "f_imm1 0x%x", 'x', f_imm1, "f_accd 0x%x", 'x', f_accd, (char *) 0));
2041
2042 #undef FLD
2043 return idesc;
2044 }
2045
2046 extract_sfmt_rte:
2047 {
2048 const IDESC *idesc = &m32r2f_insn_data[itype];
2049 #define FLD(f) abuf->fields.sfmt_empty.f
2050
2051
2052 /* Record the fields for the semantic handler. */
2053 CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_rte", (char *) 0));
2054
2055 #if WITH_PROFILE_MODEL_P
2056 /* Record the fields for profiling. */
2057 if (PROFILE_MODEL_P (current_cpu))
2058 {
2059 }
2060 #endif
2061 #undef FLD
2062 return idesc;
2063 }
2064
2065 extract_sfmt_seth:
2066 {
2067 const IDESC *idesc = &m32r2f_insn_data[itype];
2068 CGEN_INSN_WORD insn = entire_insn;
2069 #define FLD(f) abuf->fields.sfmt_seth.f
2070 UINT f_r1;
2071 UINT f_hi16;
2072
2073 f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4);
2074 f_hi16 = EXTRACT_MSB0_UINT (insn, 32, 16, 16);
2075
2076 /* Record the fields for the semantic handler. */
2077 FLD (f_hi16) = f_hi16;
2078 FLD (f_r1) = f_r1;
2079 FLD (i_dr) = & CPU (h_gr)[f_r1];
2080 CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_seth", "f_hi16 0x%x", 'x', f_hi16, "f_r1 0x%x", 'x', f_r1, "dr 0x%x", 'x', f_r1, (char *) 0));
2081
2082 #if WITH_PROFILE_MODEL_P
2083 /* Record the fields for profiling. */
2084 if (PROFILE_MODEL_P (current_cpu))
2085 {
2086 FLD (out_dr) = f_r1;
2087 }
2088 #endif
2089 #undef FLD
2090 return idesc;
2091 }
2092
2093 extract_sfmt_sll3:
2094 {
2095 const IDESC *idesc = &m32r2f_insn_data[itype];
2096 CGEN_INSN_WORD insn = entire_insn;
2097 #define FLD(f) abuf->fields.sfmt_add3.f
2098 UINT f_r1;
2099 UINT f_r2;
2100 INT f_simm16;
2101
2102 f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4);
2103 f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4);
2104 f_simm16 = EXTRACT_MSB0_SINT (insn, 32, 16, 16);
2105
2106 /* Record the fields for the semantic handler. */
2107 FLD (f_simm16) = f_simm16;
2108 FLD (f_r2) = f_r2;
2109 FLD (f_r1) = f_r1;
2110 FLD (i_sr) = & CPU (h_gr)[f_r2];
2111 FLD (i_dr) = & CPU (h_gr)[f_r1];
2112 CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_sll3", "f_simm16 0x%x", 'x', f_simm16, "f_r2 0x%x", 'x', f_r2, "f_r1 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0));
2113
2114 #if WITH_PROFILE_MODEL_P
2115 /* Record the fields for profiling. */
2116 if (PROFILE_MODEL_P (current_cpu))
2117 {
2118 FLD (in_sr) = f_r2;
2119 FLD (out_dr) = f_r1;
2120 }
2121 #endif
2122 #undef FLD
2123 return idesc;
2124 }
2125
2126 extract_sfmt_slli:
2127 {
2128 const IDESC *idesc = &m32r2f_insn_data[itype];
2129 CGEN_INSN_WORD insn = entire_insn;
2130 #define FLD(f) abuf->fields.sfmt_slli.f
2131 UINT f_r1;
2132 UINT f_uimm5;
2133
2134 f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4);
2135 f_uimm5 = EXTRACT_MSB0_UINT (insn, 16, 11, 5);
2136
2137 /* Record the fields for the semantic handler. */
2138 FLD (f_r1) = f_r1;
2139 FLD (f_uimm5) = f_uimm5;
2140 FLD (i_dr) = & CPU (h_gr)[f_r1];
2141 CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_slli", "f_r1 0x%x", 'x', f_r1, "f_uimm5 0x%x", 'x', f_uimm5, "dr 0x%x", 'x', f_r1, (char *) 0));
2142
2143 #if WITH_PROFILE_MODEL_P
2144 /* Record the fields for profiling. */
2145 if (PROFILE_MODEL_P (current_cpu))
2146 {
2147 FLD (in_dr) = f_r1;
2148 FLD (out_dr) = f_r1;
2149 }
2150 #endif
2151 #undef FLD
2152 return idesc;
2153 }
2154
2155 extract_sfmt_st:
2156 {
2157 const IDESC *idesc = &m32r2f_insn_data[itype];
2158 CGEN_INSN_WORD insn = entire_insn;
2159 #define FLD(f) abuf->fields.sfmt_st_plus.f
2160 UINT f_r1;
2161 UINT f_r2;
2162
2163 f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4);
2164 f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4);
2165
2166 /* Record the fields for the semantic handler. */
2167 FLD (f_r1) = f_r1;
2168 FLD (f_r2) = f_r2;
2169 FLD (i_src1) = & CPU (h_gr)[f_r1];
2170 FLD (i_src2) = & CPU (h_gr)[f_r2];
2171 CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_st", "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0));
2172
2173 #if WITH_PROFILE_MODEL_P
2174 /* Record the fields for profiling. */
2175 if (PROFILE_MODEL_P (current_cpu))
2176 {
2177 FLD (in_src1) = f_r1;
2178 FLD (in_src2) = f_r2;
2179 }
2180 #endif
2181 #undef FLD
2182 return idesc;
2183 }
2184
2185 extract_sfmt_st_d:
2186 {
2187 const IDESC *idesc = &m32r2f_insn_data[itype];
2188 CGEN_INSN_WORD insn = entire_insn;
2189 #define FLD(f) abuf->fields.sfmt_st_d.f
2190 UINT f_r1;
2191 UINT f_r2;
2192 INT f_simm16;
2193
2194 f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4);
2195 f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4);
2196 f_simm16 = EXTRACT_MSB0_SINT (insn, 32, 16, 16);
2197
2198 /* Record the fields for the semantic handler. */
2199 FLD (f_simm16) = f_simm16;
2200 FLD (f_r1) = f_r1;
2201 FLD (f_r2) = f_r2;
2202 FLD (i_src1) = & CPU (h_gr)[f_r1];
2203 FLD (i_src2) = & CPU (h_gr)[f_r2];
2204 CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_st_d", "f_simm16 0x%x", 'x', f_simm16, "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0));
2205
2206 #if WITH_PROFILE_MODEL_P
2207 /* Record the fields for profiling. */
2208 if (PROFILE_MODEL_P (current_cpu))
2209 {
2210 FLD (in_src1) = f_r1;
2211 FLD (in_src2) = f_r2;
2212 }
2213 #endif
2214 #undef FLD
2215 return idesc;
2216 }
2217
2218 extract_sfmt_stb:
2219 {
2220 const IDESC *idesc = &m32r2f_insn_data[itype];
2221 CGEN_INSN_WORD insn = entire_insn;
2222 #define FLD(f) abuf->fields.sfmt_st_plus.f
2223 UINT f_r1;
2224 UINT f_r2;
2225
2226 f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4);
2227 f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4);
2228
2229 /* Record the fields for the semantic handler. */
2230 FLD (f_r1) = f_r1;
2231 FLD (f_r2) = f_r2;
2232 FLD (i_src1) = & CPU (h_gr)[f_r1];
2233 FLD (i_src2) = & CPU (h_gr)[f_r2];
2234 CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_stb", "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0));
2235
2236 #if WITH_PROFILE_MODEL_P
2237 /* Record the fields for profiling. */
2238 if (PROFILE_MODEL_P (current_cpu))
2239 {
2240 FLD (in_src1) = f_r1;
2241 FLD (in_src2) = f_r2;
2242 }
2243 #endif
2244 #undef FLD
2245 return idesc;
2246 }
2247
2248 extract_sfmt_stb_d:
2249 {
2250 const IDESC *idesc = &m32r2f_insn_data[itype];
2251 CGEN_INSN_WORD insn = entire_insn;
2252 #define FLD(f) abuf->fields.sfmt_st_d.f
2253 UINT f_r1;
2254 UINT f_r2;
2255 INT f_simm16;
2256
2257 f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4);
2258 f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4);
2259 f_simm16 = EXTRACT_MSB0_SINT (insn, 32, 16, 16);
2260
2261 /* Record the fields for the semantic handler. */
2262 FLD (f_simm16) = f_simm16;
2263 FLD (f_r1) = f_r1;
2264 FLD (f_r2) = f_r2;
2265 FLD (i_src1) = & CPU (h_gr)[f_r1];
2266 FLD (i_src2) = & CPU (h_gr)[f_r2];
2267 CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_stb_d", "f_simm16 0x%x", 'x', f_simm16, "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0));
2268
2269 #if WITH_PROFILE_MODEL_P
2270 /* Record the fields for profiling. */
2271 if (PROFILE_MODEL_P (current_cpu))
2272 {
2273 FLD (in_src1) = f_r1;
2274 FLD (in_src2) = f_r2;
2275 }
2276 #endif
2277 #undef FLD
2278 return idesc;
2279 }
2280
2281 extract_sfmt_sth:
2282 {
2283 const IDESC *idesc = &m32r2f_insn_data[itype];
2284 CGEN_INSN_WORD insn = entire_insn;
2285 #define FLD(f) abuf->fields.sfmt_st_plus.f
2286 UINT f_r1;
2287 UINT f_r2;
2288
2289 f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4);
2290 f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4);
2291
2292 /* Record the fields for the semantic handler. */
2293 FLD (f_r1) = f_r1;
2294 FLD (f_r2) = f_r2;
2295 FLD (i_src1) = & CPU (h_gr)[f_r1];
2296 FLD (i_src2) = & CPU (h_gr)[f_r2];
2297 CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_sth", "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0));
2298
2299 #if WITH_PROFILE_MODEL_P
2300 /* Record the fields for profiling. */
2301 if (PROFILE_MODEL_P (current_cpu))
2302 {
2303 FLD (in_src1) = f_r1;
2304 FLD (in_src2) = f_r2;
2305 }
2306 #endif
2307 #undef FLD
2308 return idesc;
2309 }
2310
2311 extract_sfmt_sth_d:
2312 {
2313 const IDESC *idesc = &m32r2f_insn_data[itype];
2314 CGEN_INSN_WORD insn = entire_insn;
2315 #define FLD(f) abuf->fields.sfmt_st_d.f
2316 UINT f_r1;
2317 UINT f_r2;
2318 INT f_simm16;
2319
2320 f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4);
2321 f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4);
2322 f_simm16 = EXTRACT_MSB0_SINT (insn, 32, 16, 16);
2323
2324 /* Record the fields for the semantic handler. */
2325 FLD (f_simm16) = f_simm16;
2326 FLD (f_r1) = f_r1;
2327 FLD (f_r2) = f_r2;
2328 FLD (i_src1) = & CPU (h_gr)[f_r1];
2329 FLD (i_src2) = & CPU (h_gr)[f_r2];
2330 CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_sth_d", "f_simm16 0x%x", 'x', f_simm16, "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0));
2331
2332 #if WITH_PROFILE_MODEL_P
2333 /* Record the fields for profiling. */
2334 if (PROFILE_MODEL_P (current_cpu))
2335 {
2336 FLD (in_src1) = f_r1;
2337 FLD (in_src2) = f_r2;
2338 }
2339 #endif
2340 #undef FLD
2341 return idesc;
2342 }
2343
2344 extract_sfmt_st_plus:
2345 {
2346 const IDESC *idesc = &m32r2f_insn_data[itype];
2347 CGEN_INSN_WORD insn = entire_insn;
2348 #define FLD(f) abuf->fields.sfmt_st_plus.f
2349 UINT f_r1;
2350 UINT f_r2;
2351
2352 f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4);
2353 f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4);
2354
2355 /* Record the fields for the semantic handler. */
2356 FLD (f_r1) = f_r1;
2357 FLD (f_r2) = f_r2;
2358 FLD (i_src1) = & CPU (h_gr)[f_r1];
2359 FLD (i_src2) = & CPU (h_gr)[f_r2];
2360 CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_st_plus", "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0));
2361
2362 #if WITH_PROFILE_MODEL_P
2363 /* Record the fields for profiling. */
2364 if (PROFILE_MODEL_P (current_cpu))
2365 {
2366 FLD (in_src1) = f_r1;
2367 FLD (in_src2) = f_r2;
2368 FLD (out_src2) = f_r2;
2369 }
2370 #endif
2371 #undef FLD
2372 return idesc;
2373 }
2374
2375 extract_sfmt_sth_plus:
2376 {
2377 const IDESC *idesc = &m32r2f_insn_data[itype];
2378 CGEN_INSN_WORD insn = entire_insn;
2379 #define FLD(f) abuf->fields.sfmt_st_plus.f
2380 UINT f_r1;
2381 UINT f_r2;
2382
2383 f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4);
2384 f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4);
2385
2386 /* Record the fields for the semantic handler. */
2387 FLD (f_r1) = f_r1;
2388 FLD (f_r2) = f_r2;
2389 FLD (i_src1) = & CPU (h_gr)[f_r1];
2390 FLD (i_src2) = & CPU (h_gr)[f_r2];
2391 CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_sth_plus", "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0));
2392
2393 #if WITH_PROFILE_MODEL_P
2394 /* Record the fields for profiling. */
2395 if (PROFILE_MODEL_P (current_cpu))
2396 {
2397 FLD (in_src1) = f_r1;
2398 FLD (in_src2) = f_r2;
2399 FLD (out_src2) = f_r2;
2400 }
2401 #endif
2402 #undef FLD
2403 return idesc;
2404 }
2405
2406 extract_sfmt_stb_plus:
2407 {
2408 const IDESC *idesc = &m32r2f_insn_data[itype];
2409 CGEN_INSN_WORD insn = entire_insn;
2410 #define FLD(f) abuf->fields.sfmt_st_plus.f
2411 UINT f_r1;
2412 UINT f_r2;
2413
2414 f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4);
2415 f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4);
2416
2417 /* Record the fields for the semantic handler. */
2418 FLD (f_r1) = f_r1;
2419 FLD (f_r2) = f_r2;
2420 FLD (i_src1) = & CPU (h_gr)[f_r1];
2421 FLD (i_src2) = & CPU (h_gr)[f_r2];
2422 CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_stb_plus", "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0));
2423
2424 #if WITH_PROFILE_MODEL_P
2425 /* Record the fields for profiling. */
2426 if (PROFILE_MODEL_P (current_cpu))
2427 {
2428 FLD (in_src1) = f_r1;
2429 FLD (in_src2) = f_r2;
2430 FLD (out_src2) = f_r2;
2431 }
2432 #endif
2433 #undef FLD
2434 return idesc;
2435 }
2436
2437 extract_sfmt_trap:
2438 {
2439 const IDESC *idesc = &m32r2f_insn_data[itype];
2440 CGEN_INSN_WORD insn = entire_insn;
2441 #define FLD(f) abuf->fields.sfmt_trap.f
2442 UINT f_uimm4;
2443
2444 f_uimm4 = EXTRACT_MSB0_UINT (insn, 16, 12, 4);
2445
2446 /* Record the fields for the semantic handler. */
2447 FLD (f_uimm4) = f_uimm4;
2448 CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_trap", "f_uimm4 0x%x", 'x', f_uimm4, (char *) 0));
2449
2450 #if WITH_PROFILE_MODEL_P
2451 /* Record the fields for profiling. */
2452 if (PROFILE_MODEL_P (current_cpu))
2453 {
2454 }
2455 #endif
2456 #undef FLD
2457 return idesc;
2458 }
2459
2460 extract_sfmt_unlock:
2461 {
2462 const IDESC *idesc = &m32r2f_insn_data[itype];
2463 CGEN_INSN_WORD insn = entire_insn;
2464 #define FLD(f) abuf->fields.sfmt_st_plus.f
2465 UINT f_r1;
2466 UINT f_r2;
2467
2468 f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4);
2469 f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4);
2470
2471 /* Record the fields for the semantic handler. */
2472 FLD (f_r1) = f_r1;
2473 FLD (f_r2) = f_r2;
2474 FLD (i_src1) = & CPU (h_gr)[f_r1];
2475 FLD (i_src2) = & CPU (h_gr)[f_r2];
2476 CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_unlock", "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0));
2477
2478 #if WITH_PROFILE_MODEL_P
2479 /* Record the fields for profiling. */
2480 if (PROFILE_MODEL_P (current_cpu))
2481 {
2482 FLD (in_src1) = f_r1;
2483 FLD (in_src2) = f_r2;
2484 }
2485 #endif
2486 #undef FLD
2487 return idesc;
2488 }
2489
2490 extract_sfmt_satb:
2491 {
2492 const IDESC *idesc = &m32r2f_insn_data[itype];
2493 CGEN_INSN_WORD insn = entire_insn;
2494 #define FLD(f) abuf->fields.sfmt_ld_plus.f
2495 UINT f_r1;
2496 UINT f_r2;
2497
2498 f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4);
2499 f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4);
2500
2501 /* Record the fields for the semantic handler. */
2502 FLD (f_r2) = f_r2;
2503 FLD (f_r1) = f_r1;
2504 FLD (i_sr) = & CPU (h_gr)[f_r2];
2505 FLD (i_dr) = & CPU (h_gr)[f_r1];
2506 CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_satb", "f_r2 0x%x", 'x', f_r2, "f_r1 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0));
2507
2508 #if WITH_PROFILE_MODEL_P
2509 /* Record the fields for profiling. */
2510 if (PROFILE_MODEL_P (current_cpu))
2511 {
2512 FLD (in_sr) = f_r2;
2513 FLD (out_dr) = f_r1;
2514 }
2515 #endif
2516 #undef FLD
2517 return idesc;
2518 }
2519
2520 extract_sfmt_sat:
2521 {
2522 const IDESC *idesc = &m32r2f_insn_data[itype];
2523 CGEN_INSN_WORD insn = entire_insn;
2524 #define FLD(f) abuf->fields.sfmt_ld_plus.f
2525 UINT f_r1;
2526 UINT f_r2;
2527
2528 f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4);
2529 f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4);
2530
2531 /* Record the fields for the semantic handler. */
2532 FLD (f_r2) = f_r2;
2533 FLD (f_r1) = f_r1;
2534 FLD (i_sr) = & CPU (h_gr)[f_r2];
2535 FLD (i_dr) = & CPU (h_gr)[f_r1];
2536 CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_sat", "f_r2 0x%x", 'x', f_r2, "f_r1 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0));
2537
2538 #if WITH_PROFILE_MODEL_P
2539 /* Record the fields for profiling. */
2540 if (PROFILE_MODEL_P (current_cpu))
2541 {
2542 FLD (in_sr) = f_r2;
2543 FLD (out_dr) = f_r1;
2544 }
2545 #endif
2546 #undef FLD
2547 return idesc;
2548 }
2549
2550 extract_sfmt_sadd:
2551 {
2552 const IDESC *idesc = &m32r2f_insn_data[itype];
2553 #define FLD(f) abuf->fields.sfmt_empty.f
2554
2555
2556 /* Record the fields for the semantic handler. */
2557 CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_sadd", (char *) 0));
2558
2559 #undef FLD
2560 return idesc;
2561 }
2562
2563 extract_sfmt_macwu1:
2564 {
2565 const IDESC *idesc = &m32r2f_insn_data[itype];
2566 CGEN_INSN_WORD insn = entire_insn;
2567 #define FLD(f) abuf->fields.sfmt_st_plus.f
2568 UINT f_r1;
2569 UINT f_r2;
2570
2571 f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4);
2572 f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4);
2573
2574 /* Record the fields for the semantic handler. */
2575 FLD (f_r1) = f_r1;
2576 FLD (f_r2) = f_r2;
2577 FLD (i_src1) = & CPU (h_gr)[f_r1];
2578 FLD (i_src2) = & CPU (h_gr)[f_r2];
2579 CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_macwu1", "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0));
2580
2581 #if WITH_PROFILE_MODEL_P
2582 /* Record the fields for profiling. */
2583 if (PROFILE_MODEL_P (current_cpu))
2584 {
2585 FLD (in_src1) = f_r1;
2586 FLD (in_src2) = f_r2;
2587 }
2588 #endif
2589 #undef FLD
2590 return idesc;
2591 }
2592
2593 extract_sfmt_msblo:
2594 {
2595 const IDESC *idesc = &m32r2f_insn_data[itype];
2596 CGEN_INSN_WORD insn = entire_insn;
2597 #define FLD(f) abuf->fields.sfmt_st_plus.f
2598 UINT f_r1;
2599 UINT f_r2;
2600
2601 f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4);
2602 f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4);
2603
2604 /* Record the fields for the semantic handler. */
2605 FLD (f_r1) = f_r1;
2606 FLD (f_r2) = f_r2;
2607 FLD (i_src1) = & CPU (h_gr)[f_r1];
2608 FLD (i_src2) = & CPU (h_gr)[f_r2];
2609 CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_msblo", "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0));
2610
2611 #if WITH_PROFILE_MODEL_P
2612 /* Record the fields for profiling. */
2613 if (PROFILE_MODEL_P (current_cpu))
2614 {
2615 FLD (in_src1) = f_r1;
2616 FLD (in_src2) = f_r2;
2617 }
2618 #endif
2619 #undef FLD
2620 return idesc;
2621 }
2622
2623 extract_sfmt_mulwu1:
2624 {
2625 const IDESC *idesc = &m32r2f_insn_data[itype];
2626 CGEN_INSN_WORD insn = entire_insn;
2627 #define FLD(f) abuf->fields.sfmt_st_plus.f
2628 UINT f_r1;
2629 UINT f_r2;
2630
2631 f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4);
2632 f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4);
2633
2634 /* Record the fields for the semantic handler. */
2635 FLD (f_r1) = f_r1;
2636 FLD (f_r2) = f_r2;
2637 FLD (i_src1) = & CPU (h_gr)[f_r1];
2638 FLD (i_src2) = & CPU (h_gr)[f_r2];
2639 CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_mulwu1", "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0));
2640
2641 #if WITH_PROFILE_MODEL_P
2642 /* Record the fields for profiling. */
2643 if (PROFILE_MODEL_P (current_cpu))
2644 {
2645 FLD (in_src1) = f_r1;
2646 FLD (in_src2) = f_r2;
2647 }
2648 #endif
2649 #undef FLD
2650 return idesc;
2651 }
2652
2653 extract_sfmt_sc:
2654 {
2655 const IDESC *idesc = &m32r2f_insn_data[itype];
2656 #define FLD(f) abuf->fields.sfmt_empty.f
2657
2658
2659 /* Record the fields for the semantic handler. */
2660 CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_sc", (char *) 0));
2661
2662 #undef FLD
2663 return idesc;
2664 }
2665
2666 extract_sfmt_clrpsw:
2667 {
2668 const IDESC *idesc = &m32r2f_insn_data[itype];
2669 CGEN_INSN_WORD insn = entire_insn;
2670 #define FLD(f) abuf->fields.sfmt_clrpsw.f
2671 UINT f_uimm8;
2672
2673 f_uimm8 = EXTRACT_MSB0_UINT (insn, 16, 8, 8);
2674
2675 /* Record the fields for the semantic handler. */
2676 FLD (f_uimm8) = f_uimm8;
2677 CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_clrpsw", "f_uimm8 0x%x", 'x', f_uimm8, (char *) 0));
2678
2679 #undef FLD
2680 return idesc;
2681 }
2682
2683 extract_sfmt_setpsw:
2684 {
2685 const IDESC *idesc = &m32r2f_insn_data[itype];
2686 CGEN_INSN_WORD insn = entire_insn;
2687 #define FLD(f) abuf->fields.sfmt_clrpsw.f
2688 UINT f_uimm8;
2689
2690 f_uimm8 = EXTRACT_MSB0_UINT (insn, 16, 8, 8);
2691
2692 /* Record the fields for the semantic handler. */
2693 FLD (f_uimm8) = f_uimm8;
2694 CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_setpsw", "f_uimm8 0x%x", 'x', f_uimm8, (char *) 0));
2695
2696 #undef FLD
2697 return idesc;
2698 }
2699
2700 extract_sfmt_bset:
2701 {
2702 const IDESC *idesc = &m32r2f_insn_data[itype];
2703 CGEN_INSN_WORD insn = entire_insn;
2704 #define FLD(f) abuf->fields.sfmt_bset.f
2705 UINT f_uimm3;
2706 UINT f_r2;
2707 INT f_simm16;
2708
2709 f_uimm3 = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
2710 f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4);
2711 f_simm16 = EXTRACT_MSB0_SINT (insn, 32, 16, 16);
2712
2713 /* Record the fields for the semantic handler. */
2714 FLD (f_simm16) = f_simm16;
2715 FLD (f_r2) = f_r2;
2716 FLD (f_uimm3) = f_uimm3;
2717 FLD (i_sr) = & CPU (h_gr)[f_r2];
2718 CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_bset", "f_simm16 0x%x", 'x', f_simm16, "f_r2 0x%x", 'x', f_r2, "f_uimm3 0x%x", 'x', f_uimm3, "sr 0x%x", 'x', f_r2, (char *) 0));
2719
2720 #if WITH_PROFILE_MODEL_P
2721 /* Record the fields for profiling. */
2722 if (PROFILE_MODEL_P (current_cpu))
2723 {
2724 FLD (in_sr) = f_r2;
2725 }
2726 #endif
2727 #undef FLD
2728 return idesc;
2729 }
2730
2731 extract_sfmt_btst:
2732 {
2733 const IDESC *idesc = &m32r2f_insn_data[itype];
2734 CGEN_INSN_WORD insn = entire_insn;
2735 #define FLD(f) abuf->fields.sfmt_bset.f
2736 UINT f_uimm3;
2737 UINT f_r2;
2738
2739 f_uimm3 = EXTRACT_MSB0_UINT (insn, 16, 5, 3);
2740 f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4);
2741
2742 /* Record the fields for the semantic handler. */
2743 FLD (f_r2) = f_r2;
2744 FLD (f_uimm3) = f_uimm3;
2745 FLD (i_sr) = & CPU (h_gr)[f_r2];
2746 CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_btst", "f_r2 0x%x", 'x', f_r2, "f_uimm3 0x%x", 'x', f_uimm3, "sr 0x%x", 'x', f_r2, (char *) 0));
2747
2748 #if WITH_PROFILE_MODEL_P
2749 /* Record the fields for profiling. */
2750 if (PROFILE_MODEL_P (current_cpu))
2751 {
2752 FLD (in_sr) = f_r2;
2753 }
2754 #endif
2755 #undef FLD
2756 return idesc;
2757 }
2758
2759 }
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