]> git.ipfire.org Git - thirdparty/binutils-gdb.git/blob - sim/m32r/decodex.c
projects / thirdparty / binutils-gdb.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
blame | history | raw | HEAD
sim: use ARRAY_SIZE instead of ad-hoc sizeof calculations
[thirdparty/binutils-gdb.git] / sim / m32r / decodex.c
1 /* Simulator instruction decoder for m32rxf.
2
3 THIS FILE IS MACHINE GENERATED WITH CGEN.
4
5 Copyright 1996-2017 Free Software Foundation, Inc.
6
7 This file is part of the GNU simulators.
8
9 This file is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 3, or (at your option)
12 any later version.
13
14 It is distributed in the hope that it will be useful, but WITHOUT
15 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
16 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
17 License for more details.
18
19 You should have received a copy of the GNU General Public License along
20 with this program; if not, see <http://www.gnu.org/licenses/>.
21
22 */
23
24 #define WANT_CPU m32rxf
25 #define WANT_CPU_M32RXF
26
27 #include "sim-main.h"
28 #include "sim-assert.h"
29
30 /* Insn can't be executed in parallel.
31 Or is that "do NOt Pass to Air defense Radar"? :-) */
32 #define NOPAR (-1)
33
34 /* The instruction descriptor array.
35 This is computed at runtime. Space for it is not malloc'd to save a
36 teensy bit of cpu in the decoder. Moving it to malloc space is trivial
37 but won't be done until necessary (we don't currently support the runtime
38 addition of instructions nor an SMP machine with different cpus). */
39 static IDESC m32rxf_insn_data[M32RXF_INSN__MAX];
40
41 /* Commas between elements are contained in the macros.
42 Some of these are conditionally compiled out. */
43
44 static const struct insn_sem m32rxf_insn_sem[] =
45 {
46 { VIRTUAL_INSN_X_INVALID, M32RXF_INSN_X_INVALID, M32RXF_SFMT_EMPTY, NOPAR, NOPAR },
47 { VIRTUAL_INSN_X_AFTER, M32RXF_INSN_X_AFTER, M32RXF_SFMT_EMPTY, NOPAR, NOPAR },
48 { VIRTUAL_INSN_X_BEFORE, M32RXF_INSN_X_BEFORE, M32RXF_SFMT_EMPTY, NOPAR, NOPAR },
49 { VIRTUAL_INSN_X_CTI_CHAIN, M32RXF_INSN_X_CTI_CHAIN, M32RXF_SFMT_EMPTY, NOPAR, NOPAR },
50 { VIRTUAL_INSN_X_CHAIN, M32RXF_INSN_X_CHAIN, M32RXF_SFMT_EMPTY, NOPAR, NOPAR },
51 { VIRTUAL_INSN_X_BEGIN, M32RXF_INSN_X_BEGIN, M32RXF_SFMT_EMPTY, NOPAR, NOPAR },
52 { M32R_INSN_ADD, M32RXF_INSN_ADD, M32RXF_SFMT_ADD, M32RXF_INSN_PAR_ADD, M32RXF_INSN_WRITE_ADD },
53 { M32R_INSN_ADD3, M32RXF_INSN_ADD3, M32RXF_SFMT_ADD3, NOPAR, NOPAR },
54 { M32R_INSN_AND, M32RXF_INSN_AND, M32RXF_SFMT_ADD, M32RXF_INSN_PAR_AND, M32RXF_INSN_WRITE_AND },
55 { M32R_INSN_AND3, M32RXF_INSN_AND3, M32RXF_SFMT_AND3, NOPAR, NOPAR },
56 { M32R_INSN_OR, M32RXF_INSN_OR, M32RXF_SFMT_ADD, M32RXF_INSN_PAR_OR, M32RXF_INSN_WRITE_OR },
57 { M32R_INSN_OR3, M32RXF_INSN_OR3, M32RXF_SFMT_OR3, NOPAR, NOPAR },
58 { M32R_INSN_XOR, M32RXF_INSN_XOR, M32RXF_SFMT_ADD, M32RXF_INSN_PAR_XOR, M32RXF_INSN_WRITE_XOR },
59 { M32R_INSN_XOR3, M32RXF_INSN_XOR3, M32RXF_SFMT_AND3, NOPAR, NOPAR },
60 { M32R_INSN_ADDI, M32RXF_INSN_ADDI, M32RXF_SFMT_ADDI, M32RXF_INSN_PAR_ADDI, M32RXF_INSN_WRITE_ADDI },
61 { M32R_INSN_ADDV, M32RXF_INSN_ADDV, M32RXF_SFMT_ADDV, M32RXF_INSN_PAR_ADDV, M32RXF_INSN_WRITE_ADDV },
62 { M32R_INSN_ADDV3, M32RXF_INSN_ADDV3, M32RXF_SFMT_ADDV3, NOPAR, NOPAR },
63 { M32R_INSN_ADDX, M32RXF_INSN_ADDX, M32RXF_SFMT_ADDX, M32RXF_INSN_PAR_ADDX, M32RXF_INSN_WRITE_ADDX },
64 { M32R_INSN_BC8, M32RXF_INSN_BC8, M32RXF_SFMT_BC8, M32RXF_INSN_PAR_BC8, M32RXF_INSN_WRITE_BC8 },
65 { M32R_INSN_BC24, M32RXF_INSN_BC24, M32RXF_SFMT_BC24, NOPAR, NOPAR },
66 { M32R_INSN_BEQ, M32RXF_INSN_BEQ, M32RXF_SFMT_BEQ, NOPAR, NOPAR },
67 { M32R_INSN_BEQZ, M32RXF_INSN_BEQZ, M32RXF_SFMT_BEQZ, NOPAR, NOPAR },
68 { M32R_INSN_BGEZ, M32RXF_INSN_BGEZ, M32RXF_SFMT_BEQZ, NOPAR, NOPAR },
69 { M32R_INSN_BGTZ, M32RXF_INSN_BGTZ, M32RXF_SFMT_BEQZ, NOPAR, NOPAR },
70 { M32R_INSN_BLEZ, M32RXF_INSN_BLEZ, M32RXF_SFMT_BEQZ, NOPAR, NOPAR },
71 { M32R_INSN_BLTZ, M32RXF_INSN_BLTZ, M32RXF_SFMT_BEQZ, NOPAR, NOPAR },
72 { M32R_INSN_BNEZ, M32RXF_INSN_BNEZ, M32RXF_SFMT_BEQZ, NOPAR, NOPAR },
73 { M32R_INSN_BL8, M32RXF_INSN_BL8, M32RXF_SFMT_BL8, M32RXF_INSN_PAR_BL8, M32RXF_INSN_WRITE_BL8 },
74 { M32R_INSN_BL24, M32RXF_INSN_BL24, M32RXF_SFMT_BL24, NOPAR, NOPAR },
75 { M32R_INSN_BCL8, M32RXF_INSN_BCL8, M32RXF_SFMT_BCL8, M32RXF_INSN_PAR_BCL8, M32RXF_INSN_WRITE_BCL8 },
76 { M32R_INSN_BCL24, M32RXF_INSN_BCL24, M32RXF_SFMT_BCL24, NOPAR, NOPAR },
77 { M32R_INSN_BNC8, M32RXF_INSN_BNC8, M32RXF_SFMT_BC8, M32RXF_INSN_PAR_BNC8, M32RXF_INSN_WRITE_BNC8 },
78 { M32R_INSN_BNC24, M32RXF_INSN_BNC24, M32RXF_SFMT_BC24, NOPAR, NOPAR },
79 { M32R_INSN_BNE, M32RXF_INSN_BNE, M32RXF_SFMT_BEQ, NOPAR, NOPAR },
80 { M32R_INSN_BRA8, M32RXF_INSN_BRA8, M32RXF_SFMT_BRA8, M32RXF_INSN_PAR_BRA8, M32RXF_INSN_WRITE_BRA8 },
81 { M32R_INSN_BRA24, M32RXF_INSN_BRA24, M32RXF_SFMT_BRA24, NOPAR, NOPAR },
82 { M32R_INSN_BNCL8, M32RXF_INSN_BNCL8, M32RXF_SFMT_BCL8, M32RXF_INSN_PAR_BNCL8, M32RXF_INSN_WRITE_BNCL8 },
83 { M32R_INSN_BNCL24, M32RXF_INSN_BNCL24, M32RXF_SFMT_BCL24, NOPAR, NOPAR },
84 { M32R_INSN_CMP, M32RXF_INSN_CMP, M32RXF_SFMT_CMP, M32RXF_INSN_PAR_CMP, M32RXF_INSN_WRITE_CMP },
85 { M32R_INSN_CMPI, M32RXF_INSN_CMPI, M32RXF_SFMT_CMPI, NOPAR, NOPAR },
86 { M32R_INSN_CMPU, M32RXF_INSN_CMPU, M32RXF_SFMT_CMP, M32RXF_INSN_PAR_CMPU, M32RXF_INSN_WRITE_CMPU },
87 { M32R_INSN_CMPUI, M32RXF_INSN_CMPUI, M32RXF_SFMT_CMPI, NOPAR, NOPAR },
88 { M32R_INSN_CMPEQ, M32RXF_INSN_CMPEQ, M32RXF_SFMT_CMP, M32RXF_INSN_PAR_CMPEQ, M32RXF_INSN_WRITE_CMPEQ },
89 { M32R_INSN_CMPZ, M32RXF_INSN_CMPZ, M32RXF_SFMT_CMPZ, M32RXF_INSN_PAR_CMPZ, M32RXF_INSN_WRITE_CMPZ },
90 { M32R_INSN_DIV, M32RXF_INSN_DIV, M32RXF_SFMT_DIV, NOPAR, NOPAR },
91 { M32R_INSN_DIVU, M32RXF_INSN_DIVU, M32RXF_SFMT_DIV, NOPAR, NOPAR },
92 { M32R_INSN_REM, M32RXF_INSN_REM, M32RXF_SFMT_DIV, NOPAR, NOPAR },
93 { M32R_INSN_REMU, M32RXF_INSN_REMU, M32RXF_SFMT_DIV, NOPAR, NOPAR },
94 { M32R_INSN_DIVH, M32RXF_INSN_DIVH, M32RXF_SFMT_DIV, NOPAR, NOPAR },
95 { M32R_INSN_JC, M32RXF_INSN_JC, M32RXF_SFMT_JC, M32RXF_INSN_PAR_JC, M32RXF_INSN_WRITE_JC },
96 { M32R_INSN_JNC, M32RXF_INSN_JNC, M32RXF_SFMT_JC, M32RXF_INSN_PAR_JNC, M32RXF_INSN_WRITE_JNC },
97 { M32R_INSN_JL, M32RXF_INSN_JL, M32RXF_SFMT_JL, M32RXF_INSN_PAR_JL, M32RXF_INSN_WRITE_JL },
98 { M32R_INSN_JMP, M32RXF_INSN_JMP, M32RXF_SFMT_JMP, M32RXF_INSN_PAR_JMP, M32RXF_INSN_WRITE_JMP },
99 { M32R_INSN_LD, M32RXF_INSN_LD, M32RXF_SFMT_LD, M32RXF_INSN_PAR_LD, M32RXF_INSN_WRITE_LD },
100 { M32R_INSN_LD_D, M32RXF_INSN_LD_D, M32RXF_SFMT_LD_D, NOPAR, NOPAR },
101 { M32R_INSN_LDB, M32RXF_INSN_LDB, M32RXF_SFMT_LDB, M32RXF_INSN_PAR_LDB, M32RXF_INSN_WRITE_LDB },
102 { M32R_INSN_LDB_D, M32RXF_INSN_LDB_D, M32RXF_SFMT_LDB_D, NOPAR, NOPAR },
103 { M32R_INSN_LDH, M32RXF_INSN_LDH, M32RXF_SFMT_LDH, M32RXF_INSN_PAR_LDH, M32RXF_INSN_WRITE_LDH },
104 { M32R_INSN_LDH_D, M32RXF_INSN_LDH_D, M32RXF_SFMT_LDH_D, NOPAR, NOPAR },
105 { M32R_INSN_LDUB, M32RXF_INSN_LDUB, M32RXF_SFMT_LDB, M32RXF_INSN_PAR_LDUB, M32RXF_INSN_WRITE_LDUB },
106 { M32R_INSN_LDUB_D, M32RXF_INSN_LDUB_D, M32RXF_SFMT_LDB_D, NOPAR, NOPAR },
107 { M32R_INSN_LDUH, M32RXF_INSN_LDUH, M32RXF_SFMT_LDH, M32RXF_INSN_PAR_LDUH, M32RXF_INSN_WRITE_LDUH },
108 { M32R_INSN_LDUH_D, M32RXF_INSN_LDUH_D, M32RXF_SFMT_LDH_D, NOPAR, NOPAR },
109 { M32R_INSN_LD_PLUS, M32RXF_INSN_LD_PLUS, M32RXF_SFMT_LD_PLUS, M32RXF_INSN_PAR_LD_PLUS, M32RXF_INSN_WRITE_LD_PLUS },
110 { M32R_INSN_LD24, M32RXF_INSN_LD24, M32RXF_SFMT_LD24, NOPAR, NOPAR },
111 { M32R_INSN_LDI8, M32RXF_INSN_LDI8, M32RXF_SFMT_LDI8, M32RXF_INSN_PAR_LDI8, M32RXF_INSN_WRITE_LDI8 },
112 { M32R_INSN_LDI16, M32RXF_INSN_LDI16, M32RXF_SFMT_LDI16, NOPAR, NOPAR },
113 { M32R_INSN_LOCK, M32RXF_INSN_LOCK, M32RXF_SFMT_LOCK, M32RXF_INSN_PAR_LOCK, M32RXF_INSN_WRITE_LOCK },
114 { M32R_INSN_MACHI_A, M32RXF_INSN_MACHI_A, M32RXF_SFMT_MACHI_A, M32RXF_INSN_PAR_MACHI_A, M32RXF_INSN_WRITE_MACHI_A },
115 { M32R_INSN_MACLO_A, M32RXF_INSN_MACLO_A, M32RXF_SFMT_MACHI_A, M32RXF_INSN_PAR_MACLO_A, M32RXF_INSN_WRITE_MACLO_A },
116 { M32R_INSN_MACWHI_A, M32RXF_INSN_MACWHI_A, M32RXF_SFMT_MACHI_A, M32RXF_INSN_PAR_MACWHI_A, M32RXF_INSN_WRITE_MACWHI_A },
117 { M32R_INSN_MACWLO_A, M32RXF_INSN_MACWLO_A, M32RXF_SFMT_MACHI_A, M32RXF_INSN_PAR_MACWLO_A, M32RXF_INSN_WRITE_MACWLO_A },
118 { M32R_INSN_MUL, M32RXF_INSN_MUL, M32RXF_SFMT_ADD, M32RXF_INSN_PAR_MUL, M32RXF_INSN_WRITE_MUL },
119 { M32R_INSN_MULHI_A, M32RXF_INSN_MULHI_A, M32RXF_SFMT_MULHI_A, M32RXF_INSN_PAR_MULHI_A, M32RXF_INSN_WRITE_MULHI_A },
120 { M32R_INSN_MULLO_A, M32RXF_INSN_MULLO_A, M32RXF_SFMT_MULHI_A, M32RXF_INSN_PAR_MULLO_A, M32RXF_INSN_WRITE_MULLO_A },
121 { M32R_INSN_MULWHI_A, M32RXF_INSN_MULWHI_A, M32RXF_SFMT_MULHI_A, M32RXF_INSN_PAR_MULWHI_A, M32RXF_INSN_WRITE_MULWHI_A },
122 { M32R_INSN_MULWLO_A, M32RXF_INSN_MULWLO_A, M32RXF_SFMT_MULHI_A, M32RXF_INSN_PAR_MULWLO_A, M32RXF_INSN_WRITE_MULWLO_A },
123 { M32R_INSN_MV, M32RXF_INSN_MV, M32RXF_SFMT_MV, M32RXF_INSN_PAR_MV, M32RXF_INSN_WRITE_MV },
124 { M32R_INSN_MVFACHI_A, M32RXF_INSN_MVFACHI_A, M32RXF_SFMT_MVFACHI_A, M32RXF_INSN_PAR_MVFACHI_A, M32RXF_INSN_WRITE_MVFACHI_A },
125 { M32R_INSN_MVFACLO_A, M32RXF_INSN_MVFACLO_A, M32RXF_SFMT_MVFACHI_A, M32RXF_INSN_PAR_MVFACLO_A, M32RXF_INSN_WRITE_MVFACLO_A },
126 { M32R_INSN_MVFACMI_A, M32RXF_INSN_MVFACMI_A, M32RXF_SFMT_MVFACHI_A, M32RXF_INSN_PAR_MVFACMI_A, M32RXF_INSN_WRITE_MVFACMI_A },
127 { M32R_INSN_MVFC, M32RXF_INSN_MVFC, M32RXF_SFMT_MVFC, M32RXF_INSN_PAR_MVFC, M32RXF_INSN_WRITE_MVFC },
128 { M32R_INSN_MVTACHI_A, M32RXF_INSN_MVTACHI_A, M32RXF_SFMT_MVTACHI_A, M32RXF_INSN_PAR_MVTACHI_A, M32RXF_INSN_WRITE_MVTACHI_A },
129 { M32R_INSN_MVTACLO_A, M32RXF_INSN_MVTACLO_A, M32RXF_SFMT_MVTACHI_A, M32RXF_INSN_PAR_MVTACLO_A, M32RXF_INSN_WRITE_MVTACLO_A },
130 { M32R_INSN_MVTC, M32RXF_INSN_MVTC, M32RXF_SFMT_MVTC, M32RXF_INSN_PAR_MVTC, M32RXF_INSN_WRITE_MVTC },
131 { M32R_INSN_NEG, M32RXF_INSN_NEG, M32RXF_SFMT_MV, M32RXF_INSN_PAR_NEG, M32RXF_INSN_WRITE_NEG },
132 { M32R_INSN_NOP, M32RXF_INSN_NOP, M32RXF_SFMT_NOP, M32RXF_INSN_PAR_NOP, M32RXF_INSN_WRITE_NOP },
133 { M32R_INSN_NOT, M32RXF_INSN_NOT, M32RXF_SFMT_MV, M32RXF_INSN_PAR_NOT, M32RXF_INSN_WRITE_NOT },
134 { M32R_INSN_RAC_DSI, M32RXF_INSN_RAC_DSI, M32RXF_SFMT_RAC_DSI, M32RXF_INSN_PAR_RAC_DSI, M32RXF_INSN_WRITE_RAC_DSI },
135 { M32R_INSN_RACH_DSI, M32RXF_INSN_RACH_DSI, M32RXF_SFMT_RAC_DSI, M32RXF_INSN_PAR_RACH_DSI, M32RXF_INSN_WRITE_RACH_DSI },
136 { M32R_INSN_RTE, M32RXF_INSN_RTE, M32RXF_SFMT_RTE, M32RXF_INSN_PAR_RTE, M32RXF_INSN_WRITE_RTE },
137 { M32R_INSN_SETH, M32RXF_INSN_SETH, M32RXF_SFMT_SETH, NOPAR, NOPAR },
138 { M32R_INSN_SLL, M32RXF_INSN_SLL, M32RXF_SFMT_ADD, M32RXF_INSN_PAR_SLL, M32RXF_INSN_WRITE_SLL },
139 { M32R_INSN_SLL3, M32RXF_INSN_SLL3, M32RXF_SFMT_SLL3, NOPAR, NOPAR },
140 { M32R_INSN_SLLI, M32RXF_INSN_SLLI, M32RXF_SFMT_SLLI, M32RXF_INSN_PAR_SLLI, M32RXF_INSN_WRITE_SLLI },
141 { M32R_INSN_SRA, M32RXF_INSN_SRA, M32RXF_SFMT_ADD, M32RXF_INSN_PAR_SRA, M32RXF_INSN_WRITE_SRA },
142 { M32R_INSN_SRA3, M32RXF_INSN_SRA3, M32RXF_SFMT_SLL3, NOPAR, NOPAR },
143 { M32R_INSN_SRAI, M32RXF_INSN_SRAI, M32RXF_SFMT_SLLI, M32RXF_INSN_PAR_SRAI, M32RXF_INSN_WRITE_SRAI },
144 { M32R_INSN_SRL, M32RXF_INSN_SRL, M32RXF_SFMT_ADD, M32RXF_INSN_PAR_SRL, M32RXF_INSN_WRITE_SRL },
145 { M32R_INSN_SRL3, M32RXF_INSN_SRL3, M32RXF_SFMT_SLL3, NOPAR, NOPAR },
146 { M32R_INSN_SRLI, M32RXF_INSN_SRLI, M32RXF_SFMT_SLLI, M32RXF_INSN_PAR_SRLI, M32RXF_INSN_WRITE_SRLI },
147 { M32R_INSN_ST, M32RXF_INSN_ST, M32RXF_SFMT_ST, M32RXF_INSN_PAR_ST, M32RXF_INSN_WRITE_ST },
148 { M32R_INSN_ST_D, M32RXF_INSN_ST_D, M32RXF_SFMT_ST_D, NOPAR, NOPAR },
149 { M32R_INSN_STB, M32RXF_INSN_STB, M32RXF_SFMT_STB, M32RXF_INSN_PAR_STB, M32RXF_INSN_WRITE_STB },
150 { M32R_INSN_STB_D, M32RXF_INSN_STB_D, M32RXF_SFMT_STB_D, NOPAR, NOPAR },
151 { M32R_INSN_STH, M32RXF_INSN_STH, M32RXF_SFMT_STH, M32RXF_INSN_PAR_STH, M32RXF_INSN_WRITE_STH },
152 { M32R_INSN_STH_D, M32RXF_INSN_STH_D, M32RXF_SFMT_STH_D, NOPAR, NOPAR },
153 { M32R_INSN_ST_PLUS, M32RXF_INSN_ST_PLUS, M32RXF_SFMT_ST_PLUS, M32RXF_INSN_PAR_ST_PLUS, M32RXF_INSN_WRITE_ST_PLUS },
154 { M32R_INSN_STH_PLUS, M32RXF_INSN_STH_PLUS, M32RXF_SFMT_STH_PLUS, M32RXF_INSN_PAR_STH_PLUS, M32RXF_INSN_WRITE_STH_PLUS },
155 { M32R_INSN_STB_PLUS, M32RXF_INSN_STB_PLUS, M32RXF_SFMT_STB_PLUS, M32RXF_INSN_PAR_STB_PLUS, M32RXF_INSN_WRITE_STB_PLUS },
156 { M32R_INSN_ST_MINUS, M32RXF_INSN_ST_MINUS, M32RXF_SFMT_ST_PLUS, M32RXF_INSN_PAR_ST_MINUS, M32RXF_INSN_WRITE_ST_MINUS },
157 { M32R_INSN_SUB, M32RXF_INSN_SUB, M32RXF_SFMT_ADD, M32RXF_INSN_PAR_SUB, M32RXF_INSN_WRITE_SUB },
158 { M32R_INSN_SUBV, M32RXF_INSN_SUBV, M32RXF_SFMT_ADDV, M32RXF_INSN_PAR_SUBV, M32RXF_INSN_WRITE_SUBV },
159 { M32R_INSN_SUBX, M32RXF_INSN_SUBX, M32RXF_SFMT_ADDX, M32RXF_INSN_PAR_SUBX, M32RXF_INSN_WRITE_SUBX },
160 { M32R_INSN_TRAP, M32RXF_INSN_TRAP, M32RXF_SFMT_TRAP, M32RXF_INSN_PAR_TRAP, M32RXF_INSN_WRITE_TRAP },
161 { M32R_INSN_UNLOCK, M32RXF_INSN_UNLOCK, M32RXF_SFMT_UNLOCK, M32RXF_INSN_PAR_UNLOCK, M32RXF_INSN_WRITE_UNLOCK },
162 { M32R_INSN_SATB, M32RXF_INSN_SATB, M32RXF_SFMT_SATB, NOPAR, NOPAR },
163 { M32R_INSN_SATH, M32RXF_INSN_SATH, M32RXF_SFMT_SATB, NOPAR, NOPAR },
164 { M32R_INSN_SAT, M32RXF_INSN_SAT, M32RXF_SFMT_SAT, NOPAR, NOPAR },
165 { M32R_INSN_PCMPBZ, M32RXF_INSN_PCMPBZ, M32RXF_SFMT_CMPZ, M32RXF_INSN_PAR_PCMPBZ, M32RXF_INSN_WRITE_PCMPBZ },
166 { M32R_INSN_SADD, M32RXF_INSN_SADD, M32RXF_SFMT_SADD, M32RXF_INSN_PAR_SADD, M32RXF_INSN_WRITE_SADD },
167 { M32R_INSN_MACWU1, M32RXF_INSN_MACWU1, M32RXF_SFMT_MACWU1, M32RXF_INSN_PAR_MACWU1, M32RXF_INSN_WRITE_MACWU1 },
168 { M32R_INSN_MSBLO, M32RXF_INSN_MSBLO, M32RXF_SFMT_MSBLO, M32RXF_INSN_PAR_MSBLO, M32RXF_INSN_WRITE_MSBLO },
169 { M32R_INSN_MULWU1, M32RXF_INSN_MULWU1, M32RXF_SFMT_MULWU1, M32RXF_INSN_PAR_MULWU1, M32RXF_INSN_WRITE_MULWU1 },
170 { M32R_INSN_MACLH1, M32RXF_INSN_MACLH1, M32RXF_SFMT_MACWU1, M32RXF_INSN_PAR_MACLH1, M32RXF_INSN_WRITE_MACLH1 },
171 { M32R_INSN_SC, M32RXF_INSN_SC, M32RXF_SFMT_SC, M32RXF_INSN_PAR_SC, M32RXF_INSN_WRITE_SC },
172 { M32R_INSN_SNC, M32RXF_INSN_SNC, M32RXF_SFMT_SC, M32RXF_INSN_PAR_SNC, M32RXF_INSN_WRITE_SNC },
173 { M32R_INSN_CLRPSW, M32RXF_INSN_CLRPSW, M32RXF_SFMT_CLRPSW, M32RXF_INSN_PAR_CLRPSW, M32RXF_INSN_WRITE_CLRPSW },
174 { M32R_INSN_SETPSW, M32RXF_INSN_SETPSW, M32RXF_SFMT_SETPSW, M32RXF_INSN_PAR_SETPSW, M32RXF_INSN_WRITE_SETPSW },
175 { M32R_INSN_BSET, M32RXF_INSN_BSET, M32RXF_SFMT_BSET, NOPAR, NOPAR },
176 { M32R_INSN_BCLR, M32RXF_INSN_BCLR, M32RXF_SFMT_BSET, NOPAR, NOPAR },
177 { M32R_INSN_BTST, M32RXF_INSN_BTST, M32RXF_SFMT_BTST, M32RXF_INSN_PAR_BTST, M32RXF_INSN_WRITE_BTST },
178 };
179
180 static const struct insn_sem m32rxf_insn_sem_invalid =
181 {
182 VIRTUAL_INSN_X_INVALID, M32RXF_INSN_X_INVALID, M32RXF_SFMT_EMPTY, NOPAR, NOPAR
183 };
184
185 /* Initialize an IDESC from the compile-time computable parts. */
186
187 static INLINE void
188 init_idesc (SIM_CPU *cpu, IDESC *id, const struct insn_sem *t)
189 {
190 const CGEN_INSN *insn_table = CGEN_CPU_INSN_TABLE (CPU_CPU_DESC (cpu))->init_entries;
191
192 id->num = t->index;
193 id->sfmt = t->sfmt;
194 if ((int) t->type <= 0)
195 id->idata = & cgen_virtual_insn_table[- (int) t->type];
196 else
197 id->idata = & insn_table[t->type];
198 id->attrs = CGEN_INSN_ATTRS (id->idata);
199 /* Oh my god, a magic number. */
200 id->length = CGEN_INSN_BITSIZE (id->idata) / 8;
201
202 #if WITH_PROFILE_MODEL_P
203 id->timing = & MODEL_TIMING (CPU_MODEL (cpu)) [t->index];
204 {
205 SIM_DESC sd = CPU_STATE (cpu);
206 SIM_ASSERT (t->index == id->timing->num);
207 }
208 #endif
209
210 /* Semantic pointers are initialized elsewhere. */
211 }
212
213 /* Initialize the instruction descriptor table. */
214
215 void
216 m32rxf_init_idesc_table (SIM_CPU *cpu)
217 {
218 IDESC *id,*tabend;
219 const struct insn_sem *t,*tend;
220 int tabsize = M32RXF_INSN__MAX;
221 IDESC *table = m32rxf_insn_data;
222
223 memset (table, 0, tabsize * sizeof (IDESC));
224
225 /* First set all entries to the `invalid insn'. */
226 t = & m32rxf_insn_sem_invalid;
227 for (id = table, tabend = table + tabsize; id < tabend; ++id)
228 init_idesc (cpu, id, t);
229
230 /* Now fill in the values for the chosen cpu. */
231 for (t = m32rxf_insn_sem, tend = t + ARRAY_SIZE (m32rxf_insn_sem);
232 t != tend; ++t)
233 {
234 init_idesc (cpu, & table[t->index], t);
235 if (t->par_index != NOPAR)
236 {
237 init_idesc (cpu, &table[t->par_index], t);
238 table[t->index].par_idesc = &table[t->par_index];
239 }
240 if (t->par_index != NOPAR)
241 {
242 init_idesc (cpu, &table[t->write_index], t);
243 table[t->par_index].par_idesc = &table[t->write_index];
244 }
245 }
246
247 /* Link the IDESC table into the cpu. */
248 CPU_IDESC (cpu) = table;
249 }
250
251 /* Given an instruction, return a pointer to its IDESC entry. */
252
253 const IDESC *
254 m32rxf_decode (SIM_CPU *current_cpu, IADDR pc,
255 CGEN_INSN_WORD base_insn, CGEN_INSN_WORD entire_insn,
256 ARGBUF *abuf)
257 {
258 /* Result of decoder. */
259 M32RXF_INSN_TYPE itype;
260
261 {
262 CGEN_INSN_WORD insn = base_insn;
263
264 {
265 unsigned int val = (((insn >> 8) & (15 << 4)) | ((insn >> 4) & (15 << 0)));
266 switch (val)
267 {
268 case 0 : itype = M32RXF_INSN_SUBV; goto extract_sfmt_addv;
269 case 1 : itype = M32RXF_INSN_SUBX; goto extract_sfmt_addx;
270 case 2 : itype = M32RXF_INSN_SUB; goto extract_sfmt_add;
271 case 3 : itype = M32RXF_INSN_NEG; goto extract_sfmt_mv;
272 case 4 : itype = M32RXF_INSN_CMP; goto extract_sfmt_cmp;
273 case 5 : itype = M32RXF_INSN_CMPU; goto extract_sfmt_cmp;
274 case 6 : itype = M32RXF_INSN_CMPEQ; goto extract_sfmt_cmp;
275 case 7 :
276 {
277 unsigned int val = (((insn >> 8) & (3 << 0)));
278 switch (val)
279 {
280 case 0 :
281 if ((entire_insn & 0xfff0) == 0x70)
282 { itype = M32RXF_INSN_CMPZ; goto extract_sfmt_cmpz; }
283 itype = M32RXF_INSN_X_INVALID; goto extract_sfmt_empty;
284 case 3 :
285 if ((entire_insn & 0xfff0) == 0x370)
286 { itype = M32RXF_INSN_PCMPBZ; goto extract_sfmt_cmpz; }
287 itype = M32RXF_INSN_X_INVALID; goto extract_sfmt_empty;
288 default : itype = M32RXF_INSN_X_INVALID; goto extract_sfmt_empty;
289 }
290 }
291 case 8 : itype = M32RXF_INSN_ADDV; goto extract_sfmt_addv;
292 case 9 : itype = M32RXF_INSN_ADDX; goto extract_sfmt_addx;
293 case 10 : itype = M32RXF_INSN_ADD; goto extract_sfmt_add;
294 case 11 : itype = M32RXF_INSN_NOT; goto extract_sfmt_mv;
295 case 12 : itype = M32RXF_INSN_AND; goto extract_sfmt_add;
296 case 13 : itype = M32RXF_INSN_XOR; goto extract_sfmt_add;
297 case 14 : itype = M32RXF_INSN_OR; goto extract_sfmt_add;
298 case 15 :
299 if ((entire_insn & 0xf8f0) == 0xf0)
300 { itype = M32RXF_INSN_BTST; goto extract_sfmt_btst; }
301 itype = M32RXF_INSN_X_INVALID; goto extract_sfmt_empty;
302 case 16 : itype = M32RXF_INSN_SRL; goto extract_sfmt_add;
303 case 18 : itype = M32RXF_INSN_SRA; goto extract_sfmt_add;
304 case 20 : itype = M32RXF_INSN_SLL; goto extract_sfmt_add;
305 case 22 : itype = M32RXF_INSN_MUL; goto extract_sfmt_add;
306 case 24 : itype = M32RXF_INSN_MV; goto extract_sfmt_mv;
307 case 25 : itype = M32RXF_INSN_MVFC; goto extract_sfmt_mvfc;
308 case 26 : itype = M32RXF_INSN_MVTC; goto extract_sfmt_mvtc;
309 case 28 :
310 {
311 unsigned int val = (((insn >> 8) & (3 << 0)));
312 switch (val)
313 {
314 case 0 :
315 if ((entire_insn & 0xfff0) == 0x1cc0)
316 { itype = M32RXF_INSN_JC; goto extract_sfmt_jc; }
317 itype = M32RXF_INSN_X_INVALID; goto extract_sfmt_empty;
318 case 1 :
319 if ((entire_insn & 0xfff0) == 0x1dc0)
320 { itype = M32RXF_INSN_JNC; goto extract_sfmt_jc; }
321 itype = M32RXF_INSN_X_INVALID; goto extract_sfmt_empty;
322 case 2 :
323 if ((entire_insn & 0xfff0) == 0x1ec0)
324 { itype = M32RXF_INSN_JL; goto extract_sfmt_jl; }
325 itype = M32RXF_INSN_X_INVALID; goto extract_sfmt_empty;
326 case 3 :
327 if ((entire_insn & 0xfff0) == 0x1fc0)
328 { itype = M32RXF_INSN_JMP; goto extract_sfmt_jmp; }
329 itype = M32RXF_INSN_X_INVALID; goto extract_sfmt_empty;
330 default : itype = M32RXF_INSN_X_INVALID; goto extract_sfmt_empty;
331 }
332 }
333 case 29 :
334 if ((entire_insn & 0xffff) == 0x10d6)
335 { itype = M32RXF_INSN_RTE; goto extract_sfmt_rte; }
336 itype = M32RXF_INSN_X_INVALID; goto extract_sfmt_empty;
337 case 31 :
338 if ((entire_insn & 0xfff0) == 0x10f0)
339 { itype = M32RXF_INSN_TRAP; goto extract_sfmt_trap; }
340 itype = M32RXF_INSN_X_INVALID; goto extract_sfmt_empty;
341 case 32 : itype = M32RXF_INSN_STB; goto extract_sfmt_stb;
342 case 33 : itype = M32RXF_INSN_STB_PLUS; goto extract_sfmt_stb_plus;
343 case 34 : itype = M32RXF_INSN_STH; goto extract_sfmt_sth;
344 case 35 : itype = M32RXF_INSN_STH_PLUS; goto extract_sfmt_sth_plus;
345 case 36 : itype = M32RXF_INSN_ST; goto extract_sfmt_st;
346 case 37 : itype = M32RXF_INSN_UNLOCK; goto extract_sfmt_unlock;
347 case 38 : itype = M32RXF_INSN_ST_PLUS; goto extract_sfmt_st_plus;
348 case 39 : itype = M32RXF_INSN_ST_MINUS; goto extract_sfmt_st_plus;
349 case 40 : itype = M32RXF_INSN_LDB; goto extract_sfmt_ldb;
350 case 41 : itype = M32RXF_INSN_LDUB; goto extract_sfmt_ldb;
351 case 42 : itype = M32RXF_INSN_LDH; goto extract_sfmt_ldh;
352 case 43 : itype = M32RXF_INSN_LDUH; goto extract_sfmt_ldh;
353 case 44 : itype = M32RXF_INSN_LD; goto extract_sfmt_ld;
354 case 45 : itype = M32RXF_INSN_LOCK; goto extract_sfmt_lock;
355 case 46 : itype = M32RXF_INSN_LD_PLUS; goto extract_sfmt_ld_plus;
356 case 48 : /* fall through */
357 case 56 : itype = M32RXF_INSN_MULHI_A; goto extract_sfmt_mulhi_a;
358 case 49 : /* fall through */
359 case 57 : itype = M32RXF_INSN_MULLO_A; goto extract_sfmt_mulhi_a;
360 case 50 : /* fall through */
361 case 58 : itype = M32RXF_INSN_MULWHI_A; goto extract_sfmt_mulhi_a;
362 case 51 : /* fall through */
363 case 59 : itype = M32RXF_INSN_MULWLO_A; goto extract_sfmt_mulhi_a;
364 case 52 : /* fall through */
365 case 60 : itype = M32RXF_INSN_MACHI_A; goto extract_sfmt_machi_a;
366 case 53 : /* fall through */
367 case 61 : itype = M32RXF_INSN_MACLO_A; goto extract_sfmt_machi_a;
368 case 54 : /* fall through */
369 case 62 : itype = M32RXF_INSN_MACWHI_A; goto extract_sfmt_machi_a;
370 case 55 : /* fall through */
371 case 63 : itype = M32RXF_INSN_MACWLO_A; goto extract_sfmt_machi_a;
372 case 64 : /* fall through */
373 case 65 : /* fall through */
374 case 66 : /* fall through */
375 case 67 : /* fall through */
376 case 68 : /* fall through */
377 case 69 : /* fall through */
378 case 70 : /* fall through */
379 case 71 : /* fall through */
380 case 72 : /* fall through */
381 case 73 : /* fall through */
382 case 74 : /* fall through */
383 case 75 : /* fall through */
384 case 76 : /* fall through */
385 case 77 : /* fall through */
386 case 78 : /* fall through */
387 case 79 : itype = M32RXF_INSN_ADDI; goto extract_sfmt_addi;
388 case 80 : /* fall through */
389 case 81 : itype = M32RXF_INSN_SRLI; goto extract_sfmt_slli;
390 case 82 : /* fall through */
391 case 83 : itype = M32RXF_INSN_SRAI; goto extract_sfmt_slli;
392 case 84 : /* fall through */
393 case 85 : itype = M32RXF_INSN_SLLI; goto extract_sfmt_slli;
394 case 87 :
395 {
396 unsigned int val = (((insn >> 0) & (1 << 0)));
397 switch (val)
398 {
399 case 0 :
400 if ((entire_insn & 0xf0f3) == 0x5070)
401 { itype = M32RXF_INSN_MVTACHI_A; goto extract_sfmt_mvtachi_a; }
402 itype = M32RXF_INSN_X_INVALID; goto extract_sfmt_empty;
403 case 1 :
404 if ((entire_insn & 0xf0f3) == 0x5071)
405 { itype = M32RXF_INSN_MVTACLO_A; goto extract_sfmt_mvtachi_a; }
406 itype = M32RXF_INSN_X_INVALID; goto extract_sfmt_empty;
407 default : itype = M32RXF_INSN_X_INVALID; goto extract_sfmt_empty;
408 }
409 }
410 case 88 :
411 if ((entire_insn & 0xf3f2) == 0x5080)
412 { itype = M32RXF_INSN_RACH_DSI; goto extract_sfmt_rac_dsi; }
413 itype = M32RXF_INSN_X_INVALID; goto extract_sfmt_empty;
414 case 89 :
415 if ((entire_insn & 0xf3f2) == 0x5090)
416 { itype = M32RXF_INSN_RAC_DSI; goto extract_sfmt_rac_dsi; }
417 itype = M32RXF_INSN_X_INVALID; goto extract_sfmt_empty;
418 case 90 : itype = M32RXF_INSN_MULWU1; goto extract_sfmt_mulwu1;
419 case 91 : itype = M32RXF_INSN_MACWU1; goto extract_sfmt_macwu1;
420 case 92 : itype = M32RXF_INSN_MACLH1; goto extract_sfmt_macwu1;
421 case 93 : itype = M32RXF_INSN_MSBLO; goto extract_sfmt_msblo;
422 case 94 :
423 if ((entire_insn & 0xffff) == 0x50e4)
424 { itype = M32RXF_INSN_SADD; goto extract_sfmt_sadd; }
425 itype = M32RXF_INSN_X_INVALID; goto extract_sfmt_empty;
426 case 95 :
427 {
428 unsigned int val = (((insn >> 0) & (3 << 0)));
429 switch (val)
430 {
431 case 0 : itype = M32RXF_INSN_MVFACHI_A; goto extract_sfmt_mvfachi_a;
432 case 1 : itype = M32RXF_INSN_MVFACLO_A; goto extract_sfmt_mvfachi_a;
433 case 2 : itype = M32RXF_INSN_MVFACMI_A; goto extract_sfmt_mvfachi_a;
434 default : itype = M32RXF_INSN_X_INVALID; goto extract_sfmt_empty;
435 }
436 }
437 case 96 : /* fall through */
438 case 97 : /* fall through */
439 case 98 : /* fall through */
440 case 99 : /* fall through */
441 case 100 : /* fall through */
442 case 101 : /* fall through */
443 case 102 : /* fall through */
444 case 103 : /* fall through */
445 case 104 : /* fall through */
446 case 105 : /* fall through */
447 case 106 : /* fall through */
448 case 107 : /* fall through */
449 case 108 : /* fall through */
450 case 109 : /* fall through */
451 case 110 : /* fall through */
452 case 111 : itype = M32RXF_INSN_LDI8; goto extract_sfmt_ldi8;
453 case 112 :
454 {
455 unsigned int val = (((insn >> 7) & (15 << 1)) | ((insn >> 0) & (1 << 0)));
456 switch (val)
457 {
458 case 0 :
459 if ((entire_insn & 0xffff) == 0x7000)
460 { itype = M32RXF_INSN_NOP; goto extract_sfmt_nop; }
461 itype = M32RXF_INSN_X_INVALID; goto extract_sfmt_empty;
462 case 2 : /* fall through */
463 case 3 : itype = M32RXF_INSN_SETPSW; goto extract_sfmt_setpsw;
464 case 4 : /* fall through */
465 case 5 : itype = M32RXF_INSN_CLRPSW; goto extract_sfmt_clrpsw;
466 case 9 :
467 if ((entire_insn & 0xffff) == 0x7401)
468 { itype = M32RXF_INSN_SC; goto extract_sfmt_sc; }
469 itype = M32RXF_INSN_X_INVALID; goto extract_sfmt_empty;
470 case 11 :
471 if ((entire_insn & 0xffff) == 0x7501)
472 { itype = M32RXF_INSN_SNC; goto extract_sfmt_sc; }
473 itype = M32RXF_INSN_X_INVALID; goto extract_sfmt_empty;
474 case 16 : /* fall through */
475 case 17 : itype = M32RXF_INSN_BCL8; goto extract_sfmt_bcl8;
476 case 18 : /* fall through */
477 case 19 : itype = M32RXF_INSN_BNCL8; goto extract_sfmt_bcl8;
478 case 24 : /* fall through */
479 case 25 : itype = M32RXF_INSN_BC8; goto extract_sfmt_bc8;
480 case 26 : /* fall through */
481 case 27 : itype = M32RXF_INSN_BNC8; goto extract_sfmt_bc8;
482 case 28 : /* fall through */
483 case 29 : itype = M32RXF_INSN_BL8; goto extract_sfmt_bl8;
484 case 30 : /* fall through */
485 case 31 : itype = M32RXF_INSN_BRA8; goto extract_sfmt_bra8;
486 default : itype = M32RXF_INSN_X_INVALID; goto extract_sfmt_empty;
487 }
488 }
489 case 113 : /* fall through */
490 case 114 : /* fall through */
491 case 115 : /* fall through */
492 case 116 : /* fall through */
493 case 117 : /* fall through */
494 case 118 : /* fall through */
495 case 119 : /* fall through */
496 case 120 : /* fall through */
497 case 121 : /* fall through */
498 case 122 : /* fall through */
499 case 123 : /* fall through */
500 case 124 : /* fall through */
501 case 125 : /* fall through */
502 case 126 : /* fall through */
503 case 127 :
504 {
505 unsigned int val = (((insn >> 8) & (15 << 0)));
506 switch (val)
507 {
508 case 1 : itype = M32RXF_INSN_SETPSW; goto extract_sfmt_setpsw;
509 case 2 : itype = M32RXF_INSN_CLRPSW; goto extract_sfmt_clrpsw;
510 case 8 : itype = M32RXF_INSN_BCL8; goto extract_sfmt_bcl8;
511 case 9 : itype = M32RXF_INSN_BNCL8; goto extract_sfmt_bcl8;
512 case 12 : itype = M32RXF_INSN_BC8; goto extract_sfmt_bc8;
513 case 13 : itype = M32RXF_INSN_BNC8; goto extract_sfmt_bc8;
514 case 14 : itype = M32RXF_INSN_BL8; goto extract_sfmt_bl8;
515 case 15 : itype = M32RXF_INSN_BRA8; goto extract_sfmt_bra8;
516 default : itype = M32RXF_INSN_X_INVALID; goto extract_sfmt_empty;
517 }
518 }
519 case 132 :
520 if ((entire_insn & 0xfff00000) == 0x80400000)
521 { itype = M32RXF_INSN_CMPI; goto extract_sfmt_cmpi; }
522 itype = M32RXF_INSN_X_INVALID; goto extract_sfmt_empty;
523 case 133 :
524 if ((entire_insn & 0xfff00000) == 0x80500000)
525 { itype = M32RXF_INSN_CMPUI; goto extract_sfmt_cmpi; }
526 itype = M32RXF_INSN_X_INVALID; goto extract_sfmt_empty;
527 case 134 :
528 {
529 unsigned int val = (((entire_insn >> 8) & (3 << 0)));
530 switch (val)
531 {
532 case 0 :
533 if ((entire_insn & 0xf0f0ffff) == 0x80600000)
534 { itype = M32RXF_INSN_SAT; goto extract_sfmt_sat; }
535 itype = M32RXF_INSN_X_INVALID; goto extract_sfmt_empty;
536 case 2 :
537 if ((entire_insn & 0xf0f0ffff) == 0x80600200)
538 { itype = M32RXF_INSN_SATH; goto extract_sfmt_satb; }
539 itype = M32RXF_INSN_X_INVALID; goto extract_sfmt_empty;
540 case 3 :
541 if ((entire_insn & 0xf0f0ffff) == 0x80600300)
542 { itype = M32RXF_INSN_SATB; goto extract_sfmt_satb; }
543 itype = M32RXF_INSN_X_INVALID; goto extract_sfmt_empty;
544 default : itype = M32RXF_INSN_X_INVALID; goto extract_sfmt_empty;
545 }
546 }
547 case 136 : itype = M32RXF_INSN_ADDV3; goto extract_sfmt_addv3;
548 case 138 : itype = M32RXF_INSN_ADD3; goto extract_sfmt_add3;
549 case 140 : itype = M32RXF_INSN_AND3; goto extract_sfmt_and3;
550 case 141 : itype = M32RXF_INSN_XOR3; goto extract_sfmt_and3;
551 case 142 : itype = M32RXF_INSN_OR3; goto extract_sfmt_or3;
552 case 144 :
553 {
554 unsigned int val = (((entire_insn >> 4) & (1 << 0)));
555 switch (val)
556 {
557 case 0 :
558 if ((entire_insn & 0xf0f0ffff) == 0x90000000)
559 { itype = M32RXF_INSN_DIV; goto extract_sfmt_div; }
560 itype = M32RXF_INSN_X_INVALID; goto extract_sfmt_empty;
561 case 1 :
562 if ((entire_insn & 0xf0f0ffff) == 0x90000010)
563 { itype = M32RXF_INSN_DIVH; goto extract_sfmt_div; }
564 itype = M32RXF_INSN_X_INVALID; goto extract_sfmt_empty;
565 default : itype = M32RXF_INSN_X_INVALID; goto extract_sfmt_empty;
566 }
567 }
568 case 145 :
569 if ((entire_insn & 0xf0f0ffff) == 0x90100000)
570 { itype = M32RXF_INSN_DIVU; goto extract_sfmt_div; }
571 itype = M32RXF_INSN_X_INVALID; goto extract_sfmt_empty;
572 case 146 :
573 if ((entire_insn & 0xf0f0ffff) == 0x90200000)
574 { itype = M32RXF_INSN_REM; goto extract_sfmt_div; }
575 itype = M32RXF_INSN_X_INVALID; goto extract_sfmt_empty;
576 case 147 :
577 if ((entire_insn & 0xf0f0ffff) == 0x90300000)
578 { itype = M32RXF_INSN_REMU; goto extract_sfmt_div; }
579 itype = M32RXF_INSN_X_INVALID; goto extract_sfmt_empty;
580 case 152 : itype = M32RXF_INSN_SRL3; goto extract_sfmt_sll3;
581 case 154 : itype = M32RXF_INSN_SRA3; goto extract_sfmt_sll3;
582 case 156 : itype = M32RXF_INSN_SLL3; goto extract_sfmt_sll3;
583 case 159 :
584 if ((entire_insn & 0xf0ff0000) == 0x90f00000)
585 { itype = M32RXF_INSN_LDI16; goto extract_sfmt_ldi16; }
586 itype = M32RXF_INSN_X_INVALID; goto extract_sfmt_empty;
587 case 160 : itype = M32RXF_INSN_STB_D; goto extract_sfmt_stb_d;
588 case 162 : itype = M32RXF_INSN_STH_D; goto extract_sfmt_sth_d;
589 case 164 : itype = M32RXF_INSN_ST_D; goto extract_sfmt_st_d;
590 case 166 :
591 if ((entire_insn & 0xf8f00000) == 0xa0600000)
592 { itype = M32RXF_INSN_BSET; goto extract_sfmt_bset; }
593 itype = M32RXF_INSN_X_INVALID; goto extract_sfmt_empty;
594 case 167 :
595 if ((entire_insn & 0xf8f00000) == 0xa0700000)
596 { itype = M32RXF_INSN_BCLR; goto extract_sfmt_bset; }
597 itype = M32RXF_INSN_X_INVALID; goto extract_sfmt_empty;
598 case 168 : itype = M32RXF_INSN_LDB_D; goto extract_sfmt_ldb_d;
599 case 169 : itype = M32RXF_INSN_LDUB_D; goto extract_sfmt_ldb_d;
600 case 170 : itype = M32RXF_INSN_LDH_D; goto extract_sfmt_ldh_d;
601 case 171 : itype = M32RXF_INSN_LDUH_D; goto extract_sfmt_ldh_d;
602 case 172 : itype = M32RXF_INSN_LD_D; goto extract_sfmt_ld_d;
603 case 176 : itype = M32RXF_INSN_BEQ; goto extract_sfmt_beq;
604 case 177 : itype = M32RXF_INSN_BNE; goto extract_sfmt_beq;
605 case 184 :
606 if ((entire_insn & 0xfff00000) == 0xb0800000)
607 { itype = M32RXF_INSN_BEQZ; goto extract_sfmt_beqz; }
608 itype = M32RXF_INSN_X_INVALID; goto extract_sfmt_empty;
609 case 185 :
610 if ((entire_insn & 0xfff00000) == 0xb0900000)
611 { itype = M32RXF_INSN_BNEZ; goto extract_sfmt_beqz; }
612 itype = M32RXF_INSN_X_INVALID; goto extract_sfmt_empty;
613 case 186 :
614 if ((entire_insn & 0xfff00000) == 0xb0a00000)
615 { itype = M32RXF_INSN_BLTZ; goto extract_sfmt_beqz; }
616 itype = M32RXF_INSN_X_INVALID; goto extract_sfmt_empty;
617 case 187 :
618 if ((entire_insn & 0xfff00000) == 0xb0b00000)
619 { itype = M32RXF_INSN_BGEZ; goto extract_sfmt_beqz; }
620 itype = M32RXF_INSN_X_INVALID; goto extract_sfmt_empty;
621 case 188 :
622 if ((entire_insn & 0xfff00000) == 0xb0c00000)
623 { itype = M32RXF_INSN_BLEZ; goto extract_sfmt_beqz; }
624 itype = M32RXF_INSN_X_INVALID; goto extract_sfmt_empty;
625 case 189 :
626 if ((entire_insn & 0xfff00000) == 0xb0d00000)
627 { itype = M32RXF_INSN_BGTZ; goto extract_sfmt_beqz; }
628 itype = M32RXF_INSN_X_INVALID; goto extract_sfmt_empty;
629 case 220 :
630 if ((entire_insn & 0xf0ff0000) == 0xd0c00000)
631 { itype = M32RXF_INSN_SETH; goto extract_sfmt_seth; }
632 itype = M32RXF_INSN_X_INVALID; goto extract_sfmt_empty;
633 case 224 : /* fall through */
634 case 225 : /* fall through */
635 case 226 : /* fall through */
636 case 227 : /* fall through */
637 case 228 : /* fall through */
638 case 229 : /* fall through */
639 case 230 : /* fall through */
640 case 231 : /* fall through */
641 case 232 : /* fall through */
642 case 233 : /* fall through */
643 case 234 : /* fall through */
644 case 235 : /* fall through */
645 case 236 : /* fall through */
646 case 237 : /* fall through */
647 case 238 : /* fall through */
648 case 239 : itype = M32RXF_INSN_LD24; goto extract_sfmt_ld24;
649 case 240 : /* fall through */
650 case 241 : /* fall through */
651 case 242 : /* fall through */
652 case 243 : /* fall through */
653 case 244 : /* fall through */
654 case 245 : /* fall through */
655 case 246 : /* fall through */
656 case 247 : /* fall through */
657 case 248 : /* fall through */
658 case 249 : /* fall through */
659 case 250 : /* fall through */
660 case 251 : /* fall through */
661 case 252 : /* fall through */
662 case 253 : /* fall through */
663 case 254 : /* fall through */
664 case 255 :
665 {
666 unsigned int val = (((insn >> 8) & (7 << 0)));
667 switch (val)
668 {
669 case 0 :
670 if ((entire_insn & 0xff000000) == 0xf8000000)
671 { itype = M32RXF_INSN_BCL24; goto extract_sfmt_bcl24; }
672 itype = M32RXF_INSN_X_INVALID; goto extract_sfmt_empty;
673 case 1 :
674 if ((entire_insn & 0xff000000) == 0xf9000000)
675 { itype = M32RXF_INSN_BNCL24; goto extract_sfmt_bcl24; }
676 itype = M32RXF_INSN_X_INVALID; goto extract_sfmt_empty;
677 case 4 :
678 if ((entire_insn & 0xff000000) == 0xfc000000)
679 { itype = M32RXF_INSN_BC24; goto extract_sfmt_bc24; }
680 itype = M32RXF_INSN_X_INVALID; goto extract_sfmt_empty;
681 case 5 :
682 if ((entire_insn & 0xff000000) == 0xfd000000)
683 { itype = M32RXF_INSN_BNC24; goto extract_sfmt_bc24; }
684 itype = M32RXF_INSN_X_INVALID; goto extract_sfmt_empty;
685 case 6 :
686 if ((entire_insn & 0xff000000) == 0xfe000000)
687 { itype = M32RXF_INSN_BL24; goto extract_sfmt_bl24; }
688 itype = M32RXF_INSN_X_INVALID; goto extract_sfmt_empty;
689 case 7 :
690 if ((entire_insn & 0xff000000) == 0xff000000)
691 { itype = M32RXF_INSN_BRA24; goto extract_sfmt_bra24; }
692 itype = M32RXF_INSN_X_INVALID; goto extract_sfmt_empty;
693 default : itype = M32RXF_INSN_X_INVALID; goto extract_sfmt_empty;
694 }
695 }
696 default : itype = M32RXF_INSN_X_INVALID; goto extract_sfmt_empty;
697 }
698 }
699 }
700
701 /* The instruction has been decoded, now extract the fields. */
702
703 extract_sfmt_empty:
704 {
705 const IDESC *idesc = &m32rxf_insn_data[itype];
706 #define FLD(f) abuf->fields.sfmt_empty.f
707
708
709 /* Record the fields for the semantic handler. */
710 CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_empty", (char *) 0));
711
712 #undef FLD
713 return idesc;
714 }
715
716 extract_sfmt_add:
717 {
718 const IDESC *idesc = &m32rxf_insn_data[itype];
719 CGEN_INSN_WORD insn = entire_insn;
720 #define FLD(f) abuf->fields.sfmt_add.f
721 UINT f_r1;
722 UINT f_r2;
723
724 f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4);
725 f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4);
726
727 /* Record the fields for the semantic handler. */
728 FLD (f_r1) = f_r1;
729 FLD (f_r2) = f_r2;
730 FLD (i_dr) = & CPU (h_gr)[f_r1];
731 FLD (i_sr) = & CPU (h_gr)[f_r2];
732 CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_add", "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, (char *) 0));
733
734 #if WITH_PROFILE_MODEL_P
735 /* Record the fields for profiling. */
736 if (PROFILE_MODEL_P (current_cpu))
737 {
738 FLD (in_dr) = f_r1;
739 FLD (in_sr) = f_r2;
740 FLD (out_dr) = f_r1;
741 }
742 #endif
743 #undef FLD
744 return idesc;
745 }
746
747 extract_sfmt_add3:
748 {
749 const IDESC *idesc = &m32rxf_insn_data[itype];
750 CGEN_INSN_WORD insn = entire_insn;
751 #define FLD(f) abuf->fields.sfmt_add3.f
752 UINT f_r1;
753 UINT f_r2;
754 INT f_simm16;
755
756 f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4);
757 f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4);
758 f_simm16 = EXTRACT_MSB0_SINT (insn, 32, 16, 16);
759
760 /* Record the fields for the semantic handler. */
761 FLD (f_simm16) = f_simm16;
762 FLD (f_r2) = f_r2;
763 FLD (f_r1) = f_r1;
764 FLD (i_sr) = & CPU (h_gr)[f_r2];
765 FLD (i_dr) = & CPU (h_gr)[f_r1];
766 CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_add3", "f_simm16 0x%x", 'x', f_simm16, "f_r2 0x%x", 'x', f_r2, "f_r1 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0));
767
768 #if WITH_PROFILE_MODEL_P
769 /* Record the fields for profiling. */
770 if (PROFILE_MODEL_P (current_cpu))
771 {
772 FLD (in_sr) = f_r2;
773 FLD (out_dr) = f_r1;
774 }
775 #endif
776 #undef FLD
777 return idesc;
778 }
779
780 extract_sfmt_and3:
781 {
782 const IDESC *idesc = &m32rxf_insn_data[itype];
783 CGEN_INSN_WORD insn = entire_insn;
784 #define FLD(f) abuf->fields.sfmt_and3.f
785 UINT f_r1;
786 UINT f_r2;
787 UINT f_uimm16;
788
789 f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4);
790 f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4);
791 f_uimm16 = EXTRACT_MSB0_UINT (insn, 32, 16, 16);
792
793 /* Record the fields for the semantic handler. */
794 FLD (f_r2) = f_r2;
795 FLD (f_uimm16) = f_uimm16;
796 FLD (f_r1) = f_r1;
797 FLD (i_sr) = & CPU (h_gr)[f_r2];
798 FLD (i_dr) = & CPU (h_gr)[f_r1];
799 CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_and3", "f_r2 0x%x", 'x', f_r2, "f_uimm16 0x%x", 'x', f_uimm16, "f_r1 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0));
800
801 #if WITH_PROFILE_MODEL_P
802 /* Record the fields for profiling. */
803 if (PROFILE_MODEL_P (current_cpu))
804 {
805 FLD (in_sr) = f_r2;
806 FLD (out_dr) = f_r1;
807 }
808 #endif
809 #undef FLD
810 return idesc;
811 }
812
813 extract_sfmt_or3:
814 {
815 const IDESC *idesc = &m32rxf_insn_data[itype];
816 CGEN_INSN_WORD insn = entire_insn;
817 #define FLD(f) abuf->fields.sfmt_and3.f
818 UINT f_r1;
819 UINT f_r2;
820 UINT f_uimm16;
821
822 f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4);
823 f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4);
824 f_uimm16 = EXTRACT_MSB0_UINT (insn, 32, 16, 16);
825
826 /* Record the fields for the semantic handler. */
827 FLD (f_r2) = f_r2;
828 FLD (f_uimm16) = f_uimm16;
829 FLD (f_r1) = f_r1;
830 FLD (i_sr) = & CPU (h_gr)[f_r2];
831 FLD (i_dr) = & CPU (h_gr)[f_r1];
832 CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_or3", "f_r2 0x%x", 'x', f_r2, "f_uimm16 0x%x", 'x', f_uimm16, "f_r1 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0));
833
834 #if WITH_PROFILE_MODEL_P
835 /* Record the fields for profiling. */
836 if (PROFILE_MODEL_P (current_cpu))
837 {
838 FLD (in_sr) = f_r2;
839 FLD (out_dr) = f_r1;
840 }
841 #endif
842 #undef FLD
843 return idesc;
844 }
845
846 extract_sfmt_addi:
847 {
848 const IDESC *idesc = &m32rxf_insn_data[itype];
849 CGEN_INSN_WORD insn = entire_insn;
850 #define FLD(f) abuf->fields.sfmt_addi.f
851 UINT f_r1;
852 INT f_simm8;
853
854 f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4);
855 f_simm8 = EXTRACT_MSB0_SINT (insn, 16, 8, 8);
856
857 /* Record the fields for the semantic handler. */
858 FLD (f_r1) = f_r1;
859 FLD (f_simm8) = f_simm8;
860 FLD (i_dr) = & CPU (h_gr)[f_r1];
861 CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_addi", "f_r1 0x%x", 'x', f_r1, "f_simm8 0x%x", 'x', f_simm8, "dr 0x%x", 'x', f_r1, (char *) 0));
862
863 #if WITH_PROFILE_MODEL_P
864 /* Record the fields for profiling. */
865 if (PROFILE_MODEL_P (current_cpu))
866 {
867 FLD (in_dr) = f_r1;
868 FLD (out_dr) = f_r1;
869 }
870 #endif
871 #undef FLD
872 return idesc;
873 }
874
875 extract_sfmt_addv:
876 {
877 const IDESC *idesc = &m32rxf_insn_data[itype];
878 CGEN_INSN_WORD insn = entire_insn;
879 #define FLD(f) abuf->fields.sfmt_add.f
880 UINT f_r1;
881 UINT f_r2;
882
883 f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4);
884 f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4);
885
886 /* Record the fields for the semantic handler. */
887 FLD (f_r1) = f_r1;
888 FLD (f_r2) = f_r2;
889 FLD (i_dr) = & CPU (h_gr)[f_r1];
890 FLD (i_sr) = & CPU (h_gr)[f_r2];
891 CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_addv", "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, (char *) 0));
892
893 #if WITH_PROFILE_MODEL_P
894 /* Record the fields for profiling. */
895 if (PROFILE_MODEL_P (current_cpu))
896 {
897 FLD (in_dr) = f_r1;
898 FLD (in_sr) = f_r2;
899 FLD (out_dr) = f_r1;
900 }
901 #endif
902 #undef FLD
903 return idesc;
904 }
905
906 extract_sfmt_addv3:
907 {
908 const IDESC *idesc = &m32rxf_insn_data[itype];
909 CGEN_INSN_WORD insn = entire_insn;
910 #define FLD(f) abuf->fields.sfmt_add3.f
911 UINT f_r1;
912 UINT f_r2;
913 INT f_simm16;
914
915 f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4);
916 f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4);
917 f_simm16 = EXTRACT_MSB0_SINT (insn, 32, 16, 16);
918
919 /* Record the fields for the semantic handler. */
920 FLD (f_simm16) = f_simm16;
921 FLD (f_r2) = f_r2;
922 FLD (f_r1) = f_r1;
923 FLD (i_sr) = & CPU (h_gr)[f_r2];
924 FLD (i_dr) = & CPU (h_gr)[f_r1];
925 CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_addv3", "f_simm16 0x%x", 'x', f_simm16, "f_r2 0x%x", 'x', f_r2, "f_r1 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0));
926
927 #if WITH_PROFILE_MODEL_P
928 /* Record the fields for profiling. */
929 if (PROFILE_MODEL_P (current_cpu))
930 {
931 FLD (in_sr) = f_r2;
932 FLD (out_dr) = f_r1;
933 }
934 #endif
935 #undef FLD
936 return idesc;
937 }
938
939 extract_sfmt_addx:
940 {
941 const IDESC *idesc = &m32rxf_insn_data[itype];
942 CGEN_INSN_WORD insn = entire_insn;
943 #define FLD(f) abuf->fields.sfmt_add.f
944 UINT f_r1;
945 UINT f_r2;
946
947 f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4);
948 f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4);
949
950 /* Record the fields for the semantic handler. */
951 FLD (f_r1) = f_r1;
952 FLD (f_r2) = f_r2;
953 FLD (i_dr) = & CPU (h_gr)[f_r1];
954 FLD (i_sr) = & CPU (h_gr)[f_r2];
955 CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_addx", "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, (char *) 0));
956
957 #if WITH_PROFILE_MODEL_P
958 /* Record the fields for profiling. */
959 if (PROFILE_MODEL_P (current_cpu))
960 {
961 FLD (in_dr) = f_r1;
962 FLD (in_sr) = f_r2;
963 FLD (out_dr) = f_r1;
964 }
965 #endif
966 #undef FLD
967 return idesc;
968 }
969
970 extract_sfmt_bc8:
971 {
972 const IDESC *idesc = &m32rxf_insn_data[itype];
973 CGEN_INSN_WORD insn = entire_insn;
974 #define FLD(f) abuf->fields.sfmt_bl8.f
975 SI f_disp8;
976
977 f_disp8 = ((((EXTRACT_MSB0_SINT (insn, 16, 8, 8)) << (2))) + (((pc) & (-4))));
978
979 /* Record the fields for the semantic handler. */
980 FLD (i_disp8) = f_disp8;
981 CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_bc8", "disp8 0x%x", 'x', f_disp8, (char *) 0));
982
983 #if WITH_PROFILE_MODEL_P
984 /* Record the fields for profiling. */
985 if (PROFILE_MODEL_P (current_cpu))
986 {
987 }
988 #endif
989 #undef FLD
990 return idesc;
991 }
992
993 extract_sfmt_bc24:
994 {
995 const IDESC *idesc = &m32rxf_insn_data[itype];
996 CGEN_INSN_WORD insn = entire_insn;
997 #define FLD(f) abuf->fields.sfmt_bl24.f
998 SI f_disp24;
999
1000 f_disp24 = ((((EXTRACT_MSB0_SINT (insn, 32, 8, 24)) << (2))) + (pc));
1001
1002 /* Record the fields for the semantic handler. */
1003 FLD (i_disp24) = f_disp24;
1004 CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_bc24", "disp24 0x%x", 'x', f_disp24, (char *) 0));
1005
1006 #if WITH_PROFILE_MODEL_P
1007 /* Record the fields for profiling. */
1008 if (PROFILE_MODEL_P (current_cpu))
1009 {
1010 }
1011 #endif
1012 #undef FLD
1013 return idesc;
1014 }
1015
1016 extract_sfmt_beq:
1017 {
1018 const IDESC *idesc = &m32rxf_insn_data[itype];
1019 CGEN_INSN_WORD insn = entire_insn;
1020 #define FLD(f) abuf->fields.sfmt_beq.f
1021 UINT f_r1;
1022 UINT f_r2;
1023 SI f_disp16;
1024
1025 f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4);
1026 f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4);
1027 f_disp16 = ((((EXTRACT_MSB0_SINT (insn, 32, 16, 16)) << (2))) + (pc));
1028
1029 /* Record the fields for the semantic handler. */
1030 FLD (f_r1) = f_r1;
1031 FLD (f_r2) = f_r2;
1032 FLD (i_disp16) = f_disp16;
1033 FLD (i_src1) = & CPU (h_gr)[f_r1];
1034 FLD (i_src2) = & CPU (h_gr)[f_r2];
1035 CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_beq", "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "disp16 0x%x", 'x', f_disp16, "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0));
1036
1037 #if WITH_PROFILE_MODEL_P
1038 /* Record the fields for profiling. */
1039 if (PROFILE_MODEL_P (current_cpu))
1040 {
1041 FLD (in_src1) = f_r1;
1042 FLD (in_src2) = f_r2;
1043 }
1044 #endif
1045 #undef FLD
1046 return idesc;
1047 }
1048
1049 extract_sfmt_beqz:
1050 {
1051 const IDESC *idesc = &m32rxf_insn_data[itype];
1052 CGEN_INSN_WORD insn = entire_insn;
1053 #define FLD(f) abuf->fields.sfmt_beq.f
1054 UINT f_r2;
1055 SI f_disp16;
1056
1057 f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4);
1058 f_disp16 = ((((EXTRACT_MSB0_SINT (insn, 32, 16, 16)) << (2))) + (pc));
1059
1060 /* Record the fields for the semantic handler. */
1061 FLD (f_r2) = f_r2;
1062 FLD (i_disp16) = f_disp16;
1063 FLD (i_src2) = & CPU (h_gr)[f_r2];
1064 CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_beqz", "f_r2 0x%x", 'x', f_r2, "disp16 0x%x", 'x', f_disp16, "src2 0x%x", 'x', f_r2, (char *) 0));
1065
1066 #if WITH_PROFILE_MODEL_P
1067 /* Record the fields for profiling. */
1068 if (PROFILE_MODEL_P (current_cpu))
1069 {
1070 FLD (in_src2) = f_r2;
1071 }
1072 #endif
1073 #undef FLD
1074 return idesc;
1075 }
1076
1077 extract_sfmt_bl8:
1078 {
1079 const IDESC *idesc = &m32rxf_insn_data[itype];
1080 CGEN_INSN_WORD insn = entire_insn;
1081 #define FLD(f) abuf->fields.sfmt_bl8.f
1082 SI f_disp8;
1083
1084 f_disp8 = ((((EXTRACT_MSB0_SINT (insn, 16, 8, 8)) << (2))) + (((pc) & (-4))));
1085
1086 /* Record the fields for the semantic handler. */
1087 FLD (i_disp8) = f_disp8;
1088 CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_bl8", "disp8 0x%x", 'x', f_disp8, (char *) 0));
1089
1090 #if WITH_PROFILE_MODEL_P
1091 /* Record the fields for profiling. */
1092 if (PROFILE_MODEL_P (current_cpu))
1093 {
1094 FLD (out_h_gr_SI_14) = 14;
1095 }
1096 #endif
1097 #undef FLD
1098 return idesc;
1099 }
1100
1101 extract_sfmt_bl24:
1102 {
1103 const IDESC *idesc = &m32rxf_insn_data[itype];
1104 CGEN_INSN_WORD insn = entire_insn;
1105 #define FLD(f) abuf->fields.sfmt_bl24.f
1106 SI f_disp24;
1107
1108 f_disp24 = ((((EXTRACT_MSB0_SINT (insn, 32, 8, 24)) << (2))) + (pc));
1109
1110 /* Record the fields for the semantic handler. */
1111 FLD (i_disp24) = f_disp24;
1112 CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_bl24", "disp24 0x%x", 'x', f_disp24, (char *) 0));
1113
1114 #if WITH_PROFILE_MODEL_P
1115 /* Record the fields for profiling. */
1116 if (PROFILE_MODEL_P (current_cpu))
1117 {
1118 FLD (out_h_gr_SI_14) = 14;
1119 }
1120 #endif
1121 #undef FLD
1122 return idesc;
1123 }
1124
1125 extract_sfmt_bcl8:
1126 {
1127 const IDESC *idesc = &m32rxf_insn_data[itype];
1128 CGEN_INSN_WORD insn = entire_insn;
1129 #define FLD(f) abuf->fields.sfmt_bl8.f
1130 SI f_disp8;
1131
1132 f_disp8 = ((((EXTRACT_MSB0_SINT (insn, 16, 8, 8)) << (2))) + (((pc) & (-4))));
1133
1134 /* Record the fields for the semantic handler. */
1135 FLD (i_disp8) = f_disp8;
1136 CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_bcl8", "disp8 0x%x", 'x', f_disp8, (char *) 0));
1137
1138 #if WITH_PROFILE_MODEL_P
1139 /* Record the fields for profiling. */
1140 if (PROFILE_MODEL_P (current_cpu))
1141 {
1142 FLD (out_h_gr_SI_14) = 14;
1143 }
1144 #endif
1145 #undef FLD
1146 return idesc;
1147 }
1148
1149 extract_sfmt_bcl24:
1150 {
1151 const IDESC *idesc = &m32rxf_insn_data[itype];
1152 CGEN_INSN_WORD insn = entire_insn;
1153 #define FLD(f) abuf->fields.sfmt_bl24.f
1154 SI f_disp24;
1155
1156 f_disp24 = ((((EXTRACT_MSB0_SINT (insn, 32, 8, 24)) << (2))) + (pc));
1157
1158 /* Record the fields for the semantic handler. */
1159 FLD (i_disp24) = f_disp24;
1160 CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_bcl24", "disp24 0x%x", 'x', f_disp24, (char *) 0));
1161
1162 #if WITH_PROFILE_MODEL_P
1163 /* Record the fields for profiling. */
1164 if (PROFILE_MODEL_P (current_cpu))
1165 {
1166 FLD (out_h_gr_SI_14) = 14;
1167 }
1168 #endif
1169 #undef FLD
1170 return idesc;
1171 }
1172
1173 extract_sfmt_bra8:
1174 {
1175 const IDESC *idesc = &m32rxf_insn_data[itype];
1176 CGEN_INSN_WORD insn = entire_insn;
1177 #define FLD(f) abuf->fields.sfmt_bl8.f
1178 SI f_disp8;
1179
1180 f_disp8 = ((((EXTRACT_MSB0_SINT (insn, 16, 8, 8)) << (2))) + (((pc) & (-4))));
1181
1182 /* Record the fields for the semantic handler. */
1183 FLD (i_disp8) = f_disp8;
1184 CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_bra8", "disp8 0x%x", 'x', f_disp8, (char *) 0));
1185
1186 #if WITH_PROFILE_MODEL_P
1187 /* Record the fields for profiling. */
1188 if (PROFILE_MODEL_P (current_cpu))
1189 {
1190 }
1191 #endif
1192 #undef FLD
1193 return idesc;
1194 }
1195
1196 extract_sfmt_bra24:
1197 {
1198 const IDESC *idesc = &m32rxf_insn_data[itype];
1199 CGEN_INSN_WORD insn = entire_insn;
1200 #define FLD(f) abuf->fields.sfmt_bl24.f
1201 SI f_disp24;
1202
1203 f_disp24 = ((((EXTRACT_MSB0_SINT (insn, 32, 8, 24)) << (2))) + (pc));
1204
1205 /* Record the fields for the semantic handler. */
1206 FLD (i_disp24) = f_disp24;
1207 CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_bra24", "disp24 0x%x", 'x', f_disp24, (char *) 0));
1208
1209 #if WITH_PROFILE_MODEL_P
1210 /* Record the fields for profiling. */
1211 if (PROFILE_MODEL_P (current_cpu))
1212 {
1213 }
1214 #endif
1215 #undef FLD
1216 return idesc;
1217 }
1218
1219 extract_sfmt_cmp:
1220 {
1221 const IDESC *idesc = &m32rxf_insn_data[itype];
1222 CGEN_INSN_WORD insn = entire_insn;
1223 #define FLD(f) abuf->fields.sfmt_st_plus.f
1224 UINT f_r1;
1225 UINT f_r2;
1226
1227 f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4);
1228 f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4);
1229
1230 /* Record the fields for the semantic handler. */
1231 FLD (f_r1) = f_r1;
1232 FLD (f_r2) = f_r2;
1233 FLD (i_src1) = & CPU (h_gr)[f_r1];
1234 FLD (i_src2) = & CPU (h_gr)[f_r2];
1235 CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_cmp", "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0));
1236
1237 #if WITH_PROFILE_MODEL_P
1238 /* Record the fields for profiling. */
1239 if (PROFILE_MODEL_P (current_cpu))
1240 {
1241 FLD (in_src1) = f_r1;
1242 FLD (in_src2) = f_r2;
1243 }
1244 #endif
1245 #undef FLD
1246 return idesc;
1247 }
1248
1249 extract_sfmt_cmpi:
1250 {
1251 const IDESC *idesc = &m32rxf_insn_data[itype];
1252 CGEN_INSN_WORD insn = entire_insn;
1253 #define FLD(f) abuf->fields.sfmt_st_d.f
1254 UINT f_r2;
1255 INT f_simm16;
1256
1257 f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4);
1258 f_simm16 = EXTRACT_MSB0_SINT (insn, 32, 16, 16);
1259
1260 /* Record the fields for the semantic handler. */
1261 FLD (f_simm16) = f_simm16;
1262 FLD (f_r2) = f_r2;
1263 FLD (i_src2) = & CPU (h_gr)[f_r2];
1264 CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_cmpi", "f_simm16 0x%x", 'x', f_simm16, "f_r2 0x%x", 'x', f_r2, "src2 0x%x", 'x', f_r2, (char *) 0));
1265
1266 #if WITH_PROFILE_MODEL_P
1267 /* Record the fields for profiling. */
1268 if (PROFILE_MODEL_P (current_cpu))
1269 {
1270 FLD (in_src2) = f_r2;
1271 }
1272 #endif
1273 #undef FLD
1274 return idesc;
1275 }
1276
1277 extract_sfmt_cmpz:
1278 {
1279 const IDESC *idesc = &m32rxf_insn_data[itype];
1280 CGEN_INSN_WORD insn = entire_insn;
1281 #define FLD(f) abuf->fields.sfmt_st_plus.f
1282 UINT f_r2;
1283
1284 f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4);
1285
1286 /* Record the fields for the semantic handler. */
1287 FLD (f_r2) = f_r2;
1288 FLD (i_src2) = & CPU (h_gr)[f_r2];
1289 CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_cmpz", "f_r2 0x%x", 'x', f_r2, "src2 0x%x", 'x', f_r2, (char *) 0));
1290
1291 #if WITH_PROFILE_MODEL_P
1292 /* Record the fields for profiling. */
1293 if (PROFILE_MODEL_P (current_cpu))
1294 {
1295 FLD (in_src2) = f_r2;
1296 }
1297 #endif
1298 #undef FLD
1299 return idesc;
1300 }
1301
1302 extract_sfmt_div:
1303 {
1304 const IDESC *idesc = &m32rxf_insn_data[itype];
1305 CGEN_INSN_WORD insn = entire_insn;
1306 #define FLD(f) abuf->fields.sfmt_add.f
1307 UINT f_r1;
1308 UINT f_r2;
1309
1310 f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4);
1311 f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4);
1312
1313 /* Record the fields for the semantic handler. */
1314 FLD (f_r1) = f_r1;
1315 FLD (f_r2) = f_r2;
1316 FLD (i_dr) = & CPU (h_gr)[f_r1];
1317 FLD (i_sr) = & CPU (h_gr)[f_r2];
1318 CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_div", "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, (char *) 0));
1319
1320 #if WITH_PROFILE_MODEL_P
1321 /* Record the fields for profiling. */
1322 if (PROFILE_MODEL_P (current_cpu))
1323 {
1324 FLD (in_dr) = f_r1;
1325 FLD (in_sr) = f_r2;
1326 FLD (out_dr) = f_r1;
1327 }
1328 #endif
1329 #undef FLD
1330 return idesc;
1331 }
1332
1333 extract_sfmt_jc:
1334 {
1335 const IDESC *idesc = &m32rxf_insn_data[itype];
1336 CGEN_INSN_WORD insn = entire_insn;
1337 #define FLD(f) abuf->fields.sfmt_jl.f
1338 UINT f_r2;
1339
1340 f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4);
1341
1342 /* Record the fields for the semantic handler. */
1343 FLD (f_r2) = f_r2;
1344 FLD (i_sr) = & CPU (h_gr)[f_r2];
1345 CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_jc", "f_r2 0x%x", 'x', f_r2, "sr 0x%x", 'x', f_r2, (char *) 0));
1346
1347 #if WITH_PROFILE_MODEL_P
1348 /* Record the fields for profiling. */
1349 if (PROFILE_MODEL_P (current_cpu))
1350 {
1351 FLD (in_sr) = f_r2;
1352 }
1353 #endif
1354 #undef FLD
1355 return idesc;
1356 }
1357
1358 extract_sfmt_jl:
1359 {
1360 const IDESC *idesc = &m32rxf_insn_data[itype];
1361 CGEN_INSN_WORD insn = entire_insn;
1362 #define FLD(f) abuf->fields.sfmt_jl.f
1363 UINT f_r2;
1364
1365 f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4);
1366
1367 /* Record the fields for the semantic handler. */
1368 FLD (f_r2) = f_r2;
1369 FLD (i_sr) = & CPU (h_gr)[f_r2];
1370 CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_jl", "f_r2 0x%x", 'x', f_r2, "sr 0x%x", 'x', f_r2, (char *) 0));
1371
1372 #if WITH_PROFILE_MODEL_P
1373 /* Record the fields for profiling. */
1374 if (PROFILE_MODEL_P (current_cpu))
1375 {
1376 FLD (in_sr) = f_r2;
1377 FLD (out_h_gr_SI_14) = 14;
1378 }
1379 #endif
1380 #undef FLD
1381 return idesc;
1382 }
1383
1384 extract_sfmt_jmp:
1385 {
1386 const IDESC *idesc = &m32rxf_insn_data[itype];
1387 CGEN_INSN_WORD insn = entire_insn;
1388 #define FLD(f) abuf->fields.sfmt_jl.f
1389 UINT f_r2;
1390
1391 f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4);
1392
1393 /* Record the fields for the semantic handler. */
1394 FLD (f_r2) = f_r2;
1395 FLD (i_sr) = & CPU (h_gr)[f_r2];
1396 CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_jmp", "f_r2 0x%x", 'x', f_r2, "sr 0x%x", 'x', f_r2, (char *) 0));
1397
1398 #if WITH_PROFILE_MODEL_P
1399 /* Record the fields for profiling. */
1400 if (PROFILE_MODEL_P (current_cpu))
1401 {
1402 FLD (in_sr) = f_r2;
1403 }
1404 #endif
1405 #undef FLD
1406 return idesc;
1407 }
1408
1409 extract_sfmt_ld:
1410 {
1411 const IDESC *idesc = &m32rxf_insn_data[itype];
1412 CGEN_INSN_WORD insn = entire_insn;
1413 #define FLD(f) abuf->fields.sfmt_ld_plus.f
1414 UINT f_r1;
1415 UINT f_r2;
1416
1417 f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4);
1418 f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4);
1419
1420 /* Record the fields for the semantic handler. */
1421 FLD (f_r2) = f_r2;
1422 FLD (f_r1) = f_r1;
1423 FLD (i_sr) = & CPU (h_gr)[f_r2];
1424 FLD (i_dr) = & CPU (h_gr)[f_r1];
1425 CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ld", "f_r2 0x%x", 'x', f_r2, "f_r1 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0));
1426
1427 #if WITH_PROFILE_MODEL_P
1428 /* Record the fields for profiling. */
1429 if (PROFILE_MODEL_P (current_cpu))
1430 {
1431 FLD (in_sr) = f_r2;
1432 FLD (out_dr) = f_r1;
1433 }
1434 #endif
1435 #undef FLD
1436 return idesc;
1437 }
1438
1439 extract_sfmt_ld_d:
1440 {
1441 const IDESC *idesc = &m32rxf_insn_data[itype];
1442 CGEN_INSN_WORD insn = entire_insn;
1443 #define FLD(f) abuf->fields.sfmt_add3.f
1444 UINT f_r1;
1445 UINT f_r2;
1446 INT f_simm16;
1447
1448 f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4);
1449 f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4);
1450 f_simm16 = EXTRACT_MSB0_SINT (insn, 32, 16, 16);
1451
1452 /* Record the fields for the semantic handler. */
1453 FLD (f_simm16) = f_simm16;
1454 FLD (f_r2) = f_r2;
1455 FLD (f_r1) = f_r1;
1456 FLD (i_sr) = & CPU (h_gr)[f_r2];
1457 FLD (i_dr) = & CPU (h_gr)[f_r1];
1458 CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ld_d", "f_simm16 0x%x", 'x', f_simm16, "f_r2 0x%x", 'x', f_r2, "f_r1 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0));
1459
1460 #if WITH_PROFILE_MODEL_P
1461 /* Record the fields for profiling. */
1462 if (PROFILE_MODEL_P (current_cpu))
1463 {
1464 FLD (in_sr) = f_r2;
1465 FLD (out_dr) = f_r1;
1466 }
1467 #endif
1468 #undef FLD
1469 return idesc;
1470 }
1471
1472 extract_sfmt_ldb:
1473 {
1474 const IDESC *idesc = &m32rxf_insn_data[itype];
1475 CGEN_INSN_WORD insn = entire_insn;
1476 #define FLD(f) abuf->fields.sfmt_ld_plus.f
1477 UINT f_r1;
1478 UINT f_r2;
1479
1480 f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4);
1481 f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4);
1482
1483 /* Record the fields for the semantic handler. */
1484 FLD (f_r2) = f_r2;
1485 FLD (f_r1) = f_r1;
1486 FLD (i_sr) = & CPU (h_gr)[f_r2];
1487 FLD (i_dr) = & CPU (h_gr)[f_r1];
1488 CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ldb", "f_r2 0x%x", 'x', f_r2, "f_r1 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0));
1489
1490 #if WITH_PROFILE_MODEL_P
1491 /* Record the fields for profiling. */
1492 if (PROFILE_MODEL_P (current_cpu))
1493 {
1494 FLD (in_sr) = f_r2;
1495 FLD (out_dr) = f_r1;
1496 }
1497 #endif
1498 #undef FLD
1499 return idesc;
1500 }
1501
1502 extract_sfmt_ldb_d:
1503 {
1504 const IDESC *idesc = &m32rxf_insn_data[itype];
1505 CGEN_INSN_WORD insn = entire_insn;
1506 #define FLD(f) abuf->fields.sfmt_add3.f
1507 UINT f_r1;
1508 UINT f_r2;
1509 INT f_simm16;
1510
1511 f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4);
1512 f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4);
1513 f_simm16 = EXTRACT_MSB0_SINT (insn, 32, 16, 16);
1514
1515 /* Record the fields for the semantic handler. */
1516 FLD (f_simm16) = f_simm16;
1517 FLD (f_r2) = f_r2;
1518 FLD (f_r1) = f_r1;
1519 FLD (i_sr) = & CPU (h_gr)[f_r2];
1520 FLD (i_dr) = & CPU (h_gr)[f_r1];
1521 CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ldb_d", "f_simm16 0x%x", 'x', f_simm16, "f_r2 0x%x", 'x', f_r2, "f_r1 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0));
1522
1523 #if WITH_PROFILE_MODEL_P
1524 /* Record the fields for profiling. */
1525 if (PROFILE_MODEL_P (current_cpu))
1526 {
1527 FLD (in_sr) = f_r2;
1528 FLD (out_dr) = f_r1;
1529 }
1530 #endif
1531 #undef FLD
1532 return idesc;
1533 }
1534
1535 extract_sfmt_ldh:
1536 {
1537 const IDESC *idesc = &m32rxf_insn_data[itype];
1538 CGEN_INSN_WORD insn = entire_insn;
1539 #define FLD(f) abuf->fields.sfmt_ld_plus.f
1540 UINT f_r1;
1541 UINT f_r2;
1542
1543 f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4);
1544 f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4);
1545
1546 /* Record the fields for the semantic handler. */
1547 FLD (f_r2) = f_r2;
1548 FLD (f_r1) = f_r1;
1549 FLD (i_sr) = & CPU (h_gr)[f_r2];
1550 FLD (i_dr) = & CPU (h_gr)[f_r1];
1551 CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ldh", "f_r2 0x%x", 'x', f_r2, "f_r1 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0));
1552
1553 #if WITH_PROFILE_MODEL_P
1554 /* Record the fields for profiling. */
1555 if (PROFILE_MODEL_P (current_cpu))
1556 {
1557 FLD (in_sr) = f_r2;
1558 FLD (out_dr) = f_r1;
1559 }
1560 #endif
1561 #undef FLD
1562 return idesc;
1563 }
1564
1565 extract_sfmt_ldh_d:
1566 {
1567 const IDESC *idesc = &m32rxf_insn_data[itype];
1568 CGEN_INSN_WORD insn = entire_insn;
1569 #define FLD(f) abuf->fields.sfmt_add3.f
1570 UINT f_r1;
1571 UINT f_r2;
1572 INT f_simm16;
1573
1574 f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4);
1575 f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4);
1576 f_simm16 = EXTRACT_MSB0_SINT (insn, 32, 16, 16);
1577
1578 /* Record the fields for the semantic handler. */
1579 FLD (f_simm16) = f_simm16;
1580 FLD (f_r2) = f_r2;
1581 FLD (f_r1) = f_r1;
1582 FLD (i_sr) = & CPU (h_gr)[f_r2];
1583 FLD (i_dr) = & CPU (h_gr)[f_r1];
1584 CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ldh_d", "f_simm16 0x%x", 'x', f_simm16, "f_r2 0x%x", 'x', f_r2, "f_r1 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0));
1585
1586 #if WITH_PROFILE_MODEL_P
1587 /* Record the fields for profiling. */
1588 if (PROFILE_MODEL_P (current_cpu))
1589 {
1590 FLD (in_sr) = f_r2;
1591 FLD (out_dr) = f_r1;
1592 }
1593 #endif
1594 #undef FLD
1595 return idesc;
1596 }
1597
1598 extract_sfmt_ld_plus:
1599 {
1600 const IDESC *idesc = &m32rxf_insn_data[itype];
1601 CGEN_INSN_WORD insn = entire_insn;
1602 #define FLD(f) abuf->fields.sfmt_ld_plus.f
1603 UINT f_r1;
1604 UINT f_r2;
1605
1606 f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4);
1607 f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4);
1608
1609 /* Record the fields for the semantic handler. */
1610 FLD (f_r2) = f_r2;
1611 FLD (f_r1) = f_r1;
1612 FLD (i_sr) = & CPU (h_gr)[f_r2];
1613 FLD (i_dr) = & CPU (h_gr)[f_r1];
1614 CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ld_plus", "f_r2 0x%x", 'x', f_r2, "f_r1 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0));
1615
1616 #if WITH_PROFILE_MODEL_P
1617 /* Record the fields for profiling. */
1618 if (PROFILE_MODEL_P (current_cpu))
1619 {
1620 FLD (in_sr) = f_r2;
1621 FLD (out_dr) = f_r1;
1622 FLD (out_sr) = f_r2;
1623 }
1624 #endif
1625 #undef FLD
1626 return idesc;
1627 }
1628
1629 extract_sfmt_ld24:
1630 {
1631 const IDESC *idesc = &m32rxf_insn_data[itype];
1632 CGEN_INSN_WORD insn = entire_insn;
1633 #define FLD(f) abuf->fields.sfmt_ld24.f
1634 UINT f_r1;
1635 UINT f_uimm24;
1636
1637 f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4);
1638 f_uimm24 = EXTRACT_MSB0_UINT (insn, 32, 8, 24);
1639
1640 /* Record the fields for the semantic handler. */
1641 FLD (f_r1) = f_r1;
1642 FLD (i_uimm24) = f_uimm24;
1643 FLD (i_dr) = & CPU (h_gr)[f_r1];
1644 CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ld24", "f_r1 0x%x", 'x', f_r1, "uimm24 0x%x", 'x', f_uimm24, "dr 0x%x", 'x', f_r1, (char *) 0));
1645
1646 #if WITH_PROFILE_MODEL_P
1647 /* Record the fields for profiling. */
1648 if (PROFILE_MODEL_P (current_cpu))
1649 {
1650 FLD (out_dr) = f_r1;
1651 }
1652 #endif
1653 #undef FLD
1654 return idesc;
1655 }
1656
1657 extract_sfmt_ldi8:
1658 {
1659 const IDESC *idesc = &m32rxf_insn_data[itype];
1660 CGEN_INSN_WORD insn = entire_insn;
1661 #define FLD(f) abuf->fields.sfmt_addi.f
1662 UINT f_r1;
1663 INT f_simm8;
1664
1665 f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4);
1666 f_simm8 = EXTRACT_MSB0_SINT (insn, 16, 8, 8);
1667
1668 /* Record the fields for the semantic handler. */
1669 FLD (f_simm8) = f_simm8;
1670 FLD (f_r1) = f_r1;
1671 FLD (i_dr) = & CPU (h_gr)[f_r1];
1672 CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ldi8", "f_simm8 0x%x", 'x', f_simm8, "f_r1 0x%x", 'x', f_r1, "dr 0x%x", 'x', f_r1, (char *) 0));
1673
1674 #if WITH_PROFILE_MODEL_P
1675 /* Record the fields for profiling. */
1676 if (PROFILE_MODEL_P (current_cpu))
1677 {
1678 FLD (out_dr) = f_r1;
1679 }
1680 #endif
1681 #undef FLD
1682 return idesc;
1683 }
1684
1685 extract_sfmt_ldi16:
1686 {
1687 const IDESC *idesc = &m32rxf_insn_data[itype];
1688 CGEN_INSN_WORD insn = entire_insn;
1689 #define FLD(f) abuf->fields.sfmt_add3.f
1690 UINT f_r1;
1691 INT f_simm16;
1692
1693 f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4);
1694 f_simm16 = EXTRACT_MSB0_SINT (insn, 32, 16, 16);
1695
1696 /* Record the fields for the semantic handler. */
1697 FLD (f_simm16) = f_simm16;
1698 FLD (f_r1) = f_r1;
1699 FLD (i_dr) = & CPU (h_gr)[f_r1];
1700 CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ldi16", "f_simm16 0x%x", 'x', f_simm16, "f_r1 0x%x", 'x', f_r1, "dr 0x%x", 'x', f_r1, (char *) 0));
1701
1702 #if WITH_PROFILE_MODEL_P
1703 /* Record the fields for profiling. */
1704 if (PROFILE_MODEL_P (current_cpu))
1705 {
1706 FLD (out_dr) = f_r1;
1707 }
1708 #endif
1709 #undef FLD
1710 return idesc;
1711 }
1712
1713 extract_sfmt_lock:
1714 {
1715 const IDESC *idesc = &m32rxf_insn_data[itype];
1716 CGEN_INSN_WORD insn = entire_insn;
1717 #define FLD(f) abuf->fields.sfmt_ld_plus.f
1718 UINT f_r1;
1719 UINT f_r2;
1720
1721 f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4);
1722 f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4);
1723
1724 /* Record the fields for the semantic handler. */
1725 FLD (f_r2) = f_r2;
1726 FLD (f_r1) = f_r1;
1727 FLD (i_sr) = & CPU (h_gr)[f_r2];
1728 FLD (i_dr) = & CPU (h_gr)[f_r1];
1729 CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_lock", "f_r2 0x%x", 'x', f_r2, "f_r1 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0));
1730
1731 #if WITH_PROFILE_MODEL_P
1732 /* Record the fields for profiling. */
1733 if (PROFILE_MODEL_P (current_cpu))
1734 {
1735 FLD (in_sr) = f_r2;
1736 FLD (out_dr) = f_r1;
1737 }
1738 #endif
1739 #undef FLD
1740 return idesc;
1741 }
1742
1743 extract_sfmt_machi_a:
1744 {
1745 const IDESC *idesc = &m32rxf_insn_data[itype];
1746 CGEN_INSN_WORD insn = entire_insn;
1747 #define FLD(f) abuf->fields.sfmt_machi_a.f
1748 UINT f_r1;
1749 UINT f_acc;
1750 UINT f_r2;
1751
1752 f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4);
1753 f_acc = EXTRACT_MSB0_UINT (insn, 16, 8, 1);
1754 f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4);
1755
1756 /* Record the fields for the semantic handler. */
1757 FLD (f_acc) = f_acc;
1758 FLD (f_r1) = f_r1;
1759 FLD (f_r2) = f_r2;
1760 FLD (i_src1) = & CPU (h_gr)[f_r1];
1761 FLD (i_src2) = & CPU (h_gr)[f_r2];
1762 CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_machi_a", "f_acc 0x%x", 'x', f_acc, "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0));
1763
1764 #if WITH_PROFILE_MODEL_P
1765 /* Record the fields for profiling. */
1766 if (PROFILE_MODEL_P (current_cpu))
1767 {
1768 FLD (in_src1) = f_r1;
1769 FLD (in_src2) = f_r2;
1770 }
1771 #endif
1772 #undef FLD
1773 return idesc;
1774 }
1775
1776 extract_sfmt_mulhi_a:
1777 {
1778 const IDESC *idesc = &m32rxf_insn_data[itype];
1779 CGEN_INSN_WORD insn = entire_insn;
1780 #define FLD(f) abuf->fields.sfmt_machi_a.f
1781 UINT f_r1;
1782 UINT f_acc;
1783 UINT f_r2;
1784
1785 f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4);
1786 f_acc = EXTRACT_MSB0_UINT (insn, 16, 8, 1);
1787 f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4);
1788
1789 /* Record the fields for the semantic handler. */
1790 FLD (f_r1) = f_r1;
1791 FLD (f_r2) = f_r2;
1792 FLD (f_acc) = f_acc;
1793 FLD (i_src1) = & CPU (h_gr)[f_r1];
1794 FLD (i_src2) = & CPU (h_gr)[f_r2];
1795 CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_mulhi_a", "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "f_acc 0x%x", 'x', f_acc, "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0));
1796
1797 #if WITH_PROFILE_MODEL_P
1798 /* Record the fields for profiling. */
1799 if (PROFILE_MODEL_P (current_cpu))
1800 {
1801 FLD (in_src1) = f_r1;
1802 FLD (in_src2) = f_r2;
1803 }
1804 #endif
1805 #undef FLD
1806 return idesc;
1807 }
1808
1809 extract_sfmt_mv:
1810 {
1811 const IDESC *idesc = &m32rxf_insn_data[itype];
1812 CGEN_INSN_WORD insn = entire_insn;
1813 #define FLD(f) abuf->fields.sfmt_ld_plus.f
1814 UINT f_r1;
1815 UINT f_r2;
1816
1817 f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4);
1818 f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4);
1819
1820 /* Record the fields for the semantic handler. */
1821 FLD (f_r2) = f_r2;
1822 FLD (f_r1) = f_r1;
1823 FLD (i_sr) = & CPU (h_gr)[f_r2];
1824 FLD (i_dr) = & CPU (h_gr)[f_r1];
1825 CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_mv", "f_r2 0x%x", 'x', f_r2, "f_r1 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0));
1826
1827 #if WITH_PROFILE_MODEL_P
1828 /* Record the fields for profiling. */
1829 if (PROFILE_MODEL_P (current_cpu))
1830 {
1831 FLD (in_sr) = f_r2;
1832 FLD (out_dr) = f_r1;
1833 }
1834 #endif
1835 #undef FLD
1836 return idesc;
1837 }
1838
1839 extract_sfmt_mvfachi_a:
1840 {
1841 const IDESC *idesc = &m32rxf_insn_data[itype];
1842 CGEN_INSN_WORD insn = entire_insn;
1843 #define FLD(f) abuf->fields.sfmt_mvfachi_a.f
1844 UINT f_r1;
1845 UINT f_accs;
1846
1847 f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4);
1848 f_accs = EXTRACT_MSB0_UINT (insn, 16, 12, 2);
1849
1850 /* Record the fields for the semantic handler. */
1851 FLD (f_accs) = f_accs;
1852 FLD (f_r1) = f_r1;
1853 FLD (i_dr) = & CPU (h_gr)[f_r1];
1854 CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_mvfachi_a", "f_accs 0x%x", 'x', f_accs, "f_r1 0x%x", 'x', f_r1, "dr 0x%x", 'x', f_r1, (char *) 0));
1855
1856 #if WITH_PROFILE_MODEL_P
1857 /* Record the fields for profiling. */
1858 if (PROFILE_MODEL_P (current_cpu))
1859 {
1860 FLD (out_dr) = f_r1;
1861 }
1862 #endif
1863 #undef FLD
1864 return idesc;
1865 }
1866
1867 extract_sfmt_mvfc:
1868 {
1869 const IDESC *idesc = &m32rxf_insn_data[itype];
1870 CGEN_INSN_WORD insn = entire_insn;
1871 #define FLD(f) abuf->fields.sfmt_ld_plus.f
1872 UINT f_r1;
1873 UINT f_r2;
1874
1875 f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4);
1876 f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4);
1877
1878 /* Record the fields for the semantic handler. */
1879 FLD (f_r2) = f_r2;
1880 FLD (f_r1) = f_r1;
1881 FLD (i_dr) = & CPU (h_gr)[f_r1];
1882 CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_mvfc", "f_r2 0x%x", 'x', f_r2, "f_r1 0x%x", 'x', f_r1, "dr 0x%x", 'x', f_r1, (char *) 0));
1883
1884 #if WITH_PROFILE_MODEL_P
1885 /* Record the fields for profiling. */
1886 if (PROFILE_MODEL_P (current_cpu))
1887 {
1888 FLD (out_dr) = f_r1;
1889 }
1890 #endif
1891 #undef FLD
1892 return idesc;
1893 }
1894
1895 extract_sfmt_mvtachi_a:
1896 {
1897 const IDESC *idesc = &m32rxf_insn_data[itype];
1898 CGEN_INSN_WORD insn = entire_insn;
1899 #define FLD(f) abuf->fields.sfmt_mvtachi_a.f
1900 UINT f_r1;
1901 UINT f_accs;
1902
1903 f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4);
1904 f_accs = EXTRACT_MSB0_UINT (insn, 16, 12, 2);
1905
1906 /* Record the fields for the semantic handler. */
1907 FLD (f_accs) = f_accs;
1908 FLD (f_r1) = f_r1;
1909 FLD (i_src1) = & CPU (h_gr)[f_r1];
1910 CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_mvtachi_a", "f_accs 0x%x", 'x', f_accs, "f_r1 0x%x", 'x', f_r1, "src1 0x%x", 'x', f_r1, (char *) 0));
1911
1912 #if WITH_PROFILE_MODEL_P
1913 /* Record the fields for profiling. */
1914 if (PROFILE_MODEL_P (current_cpu))
1915 {
1916 FLD (in_src1) = f_r1;
1917 }
1918 #endif
1919 #undef FLD
1920 return idesc;
1921 }
1922
1923 extract_sfmt_mvtc:
1924 {
1925 const IDESC *idesc = &m32rxf_insn_data[itype];
1926 CGEN_INSN_WORD insn = entire_insn;
1927 #define FLD(f) abuf->fields.sfmt_ld_plus.f
1928 UINT f_r1;
1929 UINT f_r2;
1930
1931 f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4);
1932 f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4);
1933
1934 /* Record the fields for the semantic handler. */
1935 FLD (f_r2) = f_r2;
1936 FLD (f_r1) = f_r1;
1937 FLD (i_sr) = & CPU (h_gr)[f_r2];
1938 CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_mvtc", "f_r2 0x%x", 'x', f_r2, "f_r1 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, (char *) 0));
1939
1940 #if WITH_PROFILE_MODEL_P
1941 /* Record the fields for profiling. */
1942 if (PROFILE_MODEL_P (current_cpu))
1943 {
1944 FLD (in_sr) = f_r2;
1945 }
1946 #endif
1947 #undef FLD
1948 return idesc;
1949 }
1950
1951 extract_sfmt_nop:
1952 {
1953 const IDESC *idesc = &m32rxf_insn_data[itype];
1954 #define FLD(f) abuf->fields.sfmt_empty.f
1955
1956
1957 /* Record the fields for the semantic handler. */
1958 CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_nop", (char *) 0));
1959
1960 #undef FLD
1961 return idesc;
1962 }
1963
1964 extract_sfmt_rac_dsi:
1965 {
1966 const IDESC *idesc = &m32rxf_insn_data[itype];
1967 CGEN_INSN_WORD insn = entire_insn;
1968 #define FLD(f) abuf->fields.sfmt_rac_dsi.f
1969 UINT f_accd;
1970 UINT f_accs;
1971 SI f_imm1;
1972
1973 f_accd = EXTRACT_MSB0_UINT (insn, 16, 4, 2);
1974 f_accs = EXTRACT_MSB0_UINT (insn, 16, 12, 2);
1975 f_imm1 = ((EXTRACT_MSB0_UINT (insn, 16, 15, 1)) + (1));
1976
1977 /* Record the fields for the semantic handler. */
1978 FLD (f_accs) = f_accs;
1979 FLD (f_imm1) = f_imm1;
1980 FLD (f_accd) = f_accd;
1981 CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_rac_dsi", "f_accs 0x%x", 'x', f_accs, "f_imm1 0x%x", 'x', f_imm1, "f_accd 0x%x", 'x', f_accd, (char *) 0));
1982
1983 #undef FLD
1984 return idesc;
1985 }
1986
1987 extract_sfmt_rte:
1988 {
1989 const IDESC *idesc = &m32rxf_insn_data[itype];
1990 #define FLD(f) abuf->fields.sfmt_empty.f
1991
1992
1993 /* Record the fields for the semantic handler. */
1994 CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_rte", (char *) 0));
1995
1996 #if WITH_PROFILE_MODEL_P
1997 /* Record the fields for profiling. */
1998 if (PROFILE_MODEL_P (current_cpu))
1999 {
2000 }
2001 #endif
2002 #undef FLD
2003 return idesc;
2004 }
2005
2006 extract_sfmt_seth:
2007 {
2008 const IDESC *idesc = &m32rxf_insn_data[itype];
2009 CGEN_INSN_WORD insn = entire_insn;
2010 #define FLD(f) abuf->fields.sfmt_seth.f
2011 UINT f_r1;
2012 UINT f_hi16;
2013
2014 f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4);
2015 f_hi16 = EXTRACT_MSB0_UINT (insn, 32, 16, 16);
2016
2017 /* Record the fields for the semantic handler. */
2018 FLD (f_hi16) = f_hi16;
2019 FLD (f_r1) = f_r1;
2020 FLD (i_dr) = & CPU (h_gr)[f_r1];
2021 CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_seth", "f_hi16 0x%x", 'x', f_hi16, "f_r1 0x%x", 'x', f_r1, "dr 0x%x", 'x', f_r1, (char *) 0));
2022
2023 #if WITH_PROFILE_MODEL_P
2024 /* Record the fields for profiling. */
2025 if (PROFILE_MODEL_P (current_cpu))
2026 {
2027 FLD (out_dr) = f_r1;
2028 }
2029 #endif
2030 #undef FLD
2031 return idesc;
2032 }
2033
2034 extract_sfmt_sll3:
2035 {
2036 const IDESC *idesc = &m32rxf_insn_data[itype];
2037 CGEN_INSN_WORD insn = entire_insn;
2038 #define FLD(f) abuf->fields.sfmt_add3.f
2039 UINT f_r1;
2040 UINT f_r2;
2041 INT f_simm16;
2042
2043 f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4);
2044 f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4);
2045 f_simm16 = EXTRACT_MSB0_SINT (insn, 32, 16, 16);
2046
2047 /* Record the fields for the semantic handler. */
2048 FLD (f_simm16) = f_simm16;
2049 FLD (f_r2) = f_r2;
2050 FLD (f_r1) = f_r1;
2051 FLD (i_sr) = & CPU (h_gr)[f_r2];
2052 FLD (i_dr) = & CPU (h_gr)[f_r1];
2053 CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_sll3", "f_simm16 0x%x", 'x', f_simm16, "f_r2 0x%x", 'x', f_r2, "f_r1 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0));
2054
2055 #if WITH_PROFILE_MODEL_P
2056 /* Record the fields for profiling. */
2057 if (PROFILE_MODEL_P (current_cpu))
2058 {
2059 FLD (in_sr) = f_r2;
2060 FLD (out_dr) = f_r1;
2061 }
2062 #endif
2063 #undef FLD
2064 return idesc;
2065 }
2066
2067 extract_sfmt_slli:
2068 {
2069 const IDESC *idesc = &m32rxf_insn_data[itype];
2070 CGEN_INSN_WORD insn = entire_insn;
2071 #define FLD(f) abuf->fields.sfmt_slli.f
2072 UINT f_r1;
2073 UINT f_uimm5;
2074
2075 f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4);
2076 f_uimm5 = EXTRACT_MSB0_UINT (insn, 16, 11, 5);
2077
2078 /* Record the fields for the semantic handler. */
2079 FLD (f_r1) = f_r1;
2080 FLD (f_uimm5) = f_uimm5;
2081 FLD (i_dr) = & CPU (h_gr)[f_r1];
2082 CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_slli", "f_r1 0x%x", 'x', f_r1, "f_uimm5 0x%x", 'x', f_uimm5, "dr 0x%x", 'x', f_r1, (char *) 0));
2083
2084 #if WITH_PROFILE_MODEL_P
2085 /* Record the fields for profiling. */
2086 if (PROFILE_MODEL_P (current_cpu))
2087 {
2088 FLD (in_dr) = f_r1;
2089 FLD (out_dr) = f_r1;
2090 }
2091 #endif
2092 #undef FLD
2093 return idesc;
2094 }
2095
2096 extract_sfmt_st:
2097 {
2098 const IDESC *idesc = &m32rxf_insn_data[itype];
2099 CGEN_INSN_WORD insn = entire_insn;
2100 #define FLD(f) abuf->fields.sfmt_st_plus.f
2101 UINT f_r1;
2102 UINT f_r2;
2103
2104 f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4);
2105 f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4);
2106
2107 /* Record the fields for the semantic handler. */
2108 FLD (f_r1) = f_r1;
2109 FLD (f_r2) = f_r2;
2110 FLD (i_src1) = & CPU (h_gr)[f_r1];
2111 FLD (i_src2) = & CPU (h_gr)[f_r2];
2112 CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_st", "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0));
2113
2114 #if WITH_PROFILE_MODEL_P
2115 /* Record the fields for profiling. */
2116 if (PROFILE_MODEL_P (current_cpu))
2117 {
2118 FLD (in_src1) = f_r1;
2119 FLD (in_src2) = f_r2;
2120 }
2121 #endif
2122 #undef FLD
2123 return idesc;
2124 }
2125
2126 extract_sfmt_st_d:
2127 {
2128 const IDESC *idesc = &m32rxf_insn_data[itype];
2129 CGEN_INSN_WORD insn = entire_insn;
2130 #define FLD(f) abuf->fields.sfmt_st_d.f
2131 UINT f_r1;
2132 UINT f_r2;
2133 INT f_simm16;
2134
2135 f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4);
2136 f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4);
2137 f_simm16 = EXTRACT_MSB0_SINT (insn, 32, 16, 16);
2138
2139 /* Record the fields for the semantic handler. */
2140 FLD (f_simm16) = f_simm16;
2141 FLD (f_r1) = f_r1;
2142 FLD (f_r2) = f_r2;
2143 FLD (i_src1) = & CPU (h_gr)[f_r1];
2144 FLD (i_src2) = & CPU (h_gr)[f_r2];
2145 CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_st_d", "f_simm16 0x%x", 'x', f_simm16, "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0));
2146
2147 #if WITH_PROFILE_MODEL_P
2148 /* Record the fields for profiling. */
2149 if (PROFILE_MODEL_P (current_cpu))
2150 {
2151 FLD (in_src1) = f_r1;
2152 FLD (in_src2) = f_r2;
2153 }
2154 #endif
2155 #undef FLD
2156 return idesc;
2157 }
2158
2159 extract_sfmt_stb:
2160 {
2161 const IDESC *idesc = &m32rxf_insn_data[itype];
2162 CGEN_INSN_WORD insn = entire_insn;
2163 #define FLD(f) abuf->fields.sfmt_st_plus.f
2164 UINT f_r1;
2165 UINT f_r2;
2166
2167 f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4);
2168 f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4);
2169
2170 /* Record the fields for the semantic handler. */
2171 FLD (f_r1) = f_r1;
2172 FLD (f_r2) = f_r2;
2173 FLD (i_src1) = & CPU (h_gr)[f_r1];
2174 FLD (i_src2) = & CPU (h_gr)[f_r2];
2175 CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_stb", "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0));
2176
2177 #if WITH_PROFILE_MODEL_P
2178 /* Record the fields for profiling. */
2179 if (PROFILE_MODEL_P (current_cpu))
2180 {
2181 FLD (in_src1) = f_r1;
2182 FLD (in_src2) = f_r2;
2183 }
2184 #endif
2185 #undef FLD
2186 return idesc;
2187 }
2188
2189 extract_sfmt_stb_d:
2190 {
2191 const IDESC *idesc = &m32rxf_insn_data[itype];
2192 CGEN_INSN_WORD insn = entire_insn;
2193 #define FLD(f) abuf->fields.sfmt_st_d.f
2194 UINT f_r1;
2195 UINT f_r2;
2196 INT f_simm16;
2197
2198 f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4);
2199 f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4);
2200 f_simm16 = EXTRACT_MSB0_SINT (insn, 32, 16, 16);
2201
2202 /* Record the fields for the semantic handler. */
2203 FLD (f_simm16) = f_simm16;
2204 FLD (f_r1) = f_r1;
2205 FLD (f_r2) = f_r2;
2206 FLD (i_src1) = & CPU (h_gr)[f_r1];
2207 FLD (i_src2) = & CPU (h_gr)[f_r2];
2208 CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_stb_d", "f_simm16 0x%x", 'x', f_simm16, "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0));
2209
2210 #if WITH_PROFILE_MODEL_P
2211 /* Record the fields for profiling. */
2212 if (PROFILE_MODEL_P (current_cpu))
2213 {
2214 FLD (in_src1) = f_r1;
2215 FLD (in_src2) = f_r2;
2216 }
2217 #endif
2218 #undef FLD
2219 return idesc;
2220 }
2221
2222 extract_sfmt_sth:
2223 {
2224 const IDESC *idesc = &m32rxf_insn_data[itype];
2225 CGEN_INSN_WORD insn = entire_insn;
2226 #define FLD(f) abuf->fields.sfmt_st_plus.f
2227 UINT f_r1;
2228 UINT f_r2;
2229
2230 f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4);
2231 f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4);
2232
2233 /* Record the fields for the semantic handler. */
2234 FLD (f_r1) = f_r1;
2235 FLD (f_r2) = f_r2;
2236 FLD (i_src1) = & CPU (h_gr)[f_r1];
2237 FLD (i_src2) = & CPU (h_gr)[f_r2];
2238 CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_sth", "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0));
2239
2240 #if WITH_PROFILE_MODEL_P
2241 /* Record the fields for profiling. */
2242 if (PROFILE_MODEL_P (current_cpu))
2243 {
2244 FLD (in_src1) = f_r1;
2245 FLD (in_src2) = f_r2;
2246 }
2247 #endif
2248 #undef FLD
2249 return idesc;
2250 }
2251
2252 extract_sfmt_sth_d:
2253 {
2254 const IDESC *idesc = &m32rxf_insn_data[itype];
2255 CGEN_INSN_WORD insn = entire_insn;
2256 #define FLD(f) abuf->fields.sfmt_st_d.f
2257 UINT f_r1;
2258 UINT f_r2;
2259 INT f_simm16;
2260
2261 f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4);
2262 f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4);
2263 f_simm16 = EXTRACT_MSB0_SINT (insn, 32, 16, 16);
2264
2265 /* Record the fields for the semantic handler. */
2266 FLD (f_simm16) = f_simm16;
2267 FLD (f_r1) = f_r1;
2268 FLD (f_r2) = f_r2;
2269 FLD (i_src1) = & CPU (h_gr)[f_r1];
2270 FLD (i_src2) = & CPU (h_gr)[f_r2];
2271 CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_sth_d", "f_simm16 0x%x", 'x', f_simm16, "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0));
2272
2273 #if WITH_PROFILE_MODEL_P
2274 /* Record the fields for profiling. */
2275 if (PROFILE_MODEL_P (current_cpu))
2276 {
2277 FLD (in_src1) = f_r1;
2278 FLD (in_src2) = f_r2;
2279 }
2280 #endif
2281 #undef FLD
2282 return idesc;
2283 }
2284
2285 extract_sfmt_st_plus:
2286 {
2287 const IDESC *idesc = &m32rxf_insn_data[itype];
2288 CGEN_INSN_WORD insn = entire_insn;
2289 #define FLD(f) abuf->fields.sfmt_st_plus.f
2290 UINT f_r1;
2291 UINT f_r2;
2292
2293 f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4);
2294 f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4);
2295
2296 /* Record the fields for the semantic handler. */
2297 FLD (f_r1) = f_r1;
2298 FLD (f_r2) = f_r2;
2299 FLD (i_src1) = & CPU (h_gr)[f_r1];
2300 FLD (i_src2) = & CPU (h_gr)[f_r2];
2301 CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_st_plus", "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0));
2302
2303 #if WITH_PROFILE_MODEL_P
2304 /* Record the fields for profiling. */
2305 if (PROFILE_MODEL_P (current_cpu))
2306 {
2307 FLD (in_src1) = f_r1;
2308 FLD (in_src2) = f_r2;
2309 FLD (out_src2) = f_r2;
2310 }
2311 #endif
2312 #undef FLD
2313 return idesc;
2314 }
2315
2316 extract_sfmt_sth_plus:
2317 {
2318 const IDESC *idesc = &m32rxf_insn_data[itype];
2319 CGEN_INSN_WORD insn = entire_insn;
2320 #define FLD(f) abuf->fields.sfmt_st_plus.f
2321 UINT f_r1;
2322 UINT f_r2;
2323
2324 f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4);
2325 f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4);
2326
2327 /* Record the fields for the semantic handler. */
2328 FLD (f_r1) = f_r1;
2329 FLD (f_r2) = f_r2;
2330 FLD (i_src1) = & CPU (h_gr)[f_r1];
2331 FLD (i_src2) = & CPU (h_gr)[f_r2];
2332 CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_sth_plus", "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0));
2333
2334 #if WITH_PROFILE_MODEL_P
2335 /* Record the fields for profiling. */
2336 if (PROFILE_MODEL_P (current_cpu))
2337 {
2338 FLD (in_src1) = f_r1;
2339 FLD (in_src2) = f_r2;
2340 FLD (out_src2) = f_r2;
2341 }
2342 #endif
2343 #undef FLD
2344 return idesc;
2345 }
2346
2347 extract_sfmt_stb_plus:
2348 {
2349 const IDESC *idesc = &m32rxf_insn_data[itype];
2350 CGEN_INSN_WORD insn = entire_insn;
2351 #define FLD(f) abuf->fields.sfmt_st_plus.f
2352 UINT f_r1;
2353 UINT f_r2;
2354
2355 f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4);
2356 f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4);
2357
2358 /* Record the fields for the semantic handler. */
2359 FLD (f_r1) = f_r1;
2360 FLD (f_r2) = f_r2;
2361 FLD (i_src1) = & CPU (h_gr)[f_r1];
2362 FLD (i_src2) = & CPU (h_gr)[f_r2];
2363 CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_stb_plus", "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0));
2364
2365 #if WITH_PROFILE_MODEL_P
2366 /* Record the fields for profiling. */
2367 if (PROFILE_MODEL_P (current_cpu))
2368 {
2369 FLD (in_src1) = f_r1;
2370 FLD (in_src2) = f_r2;
2371 FLD (out_src2) = f_r2;
2372 }
2373 #endif
2374 #undef FLD
2375 return idesc;
2376 }
2377
2378 extract_sfmt_trap:
2379 {
2380 const IDESC *idesc = &m32rxf_insn_data[itype];
2381 CGEN_INSN_WORD insn = entire_insn;
2382 #define FLD(f) abuf->fields.sfmt_trap.f
2383 UINT f_uimm4;
2384
2385 f_uimm4 = EXTRACT_MSB0_UINT (insn, 16, 12, 4);
2386
2387 /* Record the fields for the semantic handler. */
2388 FLD (f_uimm4) = f_uimm4;
2389 CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_trap", "f_uimm4 0x%x", 'x', f_uimm4, (char *) 0));
2390
2391 #if WITH_PROFILE_MODEL_P
2392 /* Record the fields for profiling. */
2393 if (PROFILE_MODEL_P (current_cpu))
2394 {
2395 }
2396 #endif
2397 #undef FLD
2398 return idesc;
2399 }
2400
2401 extract_sfmt_unlock:
2402 {
2403 const IDESC *idesc = &m32rxf_insn_data[itype];
2404 CGEN_INSN_WORD insn = entire_insn;
2405 #define FLD(f) abuf->fields.sfmt_st_plus.f
2406 UINT f_r1;
2407 UINT f_r2;
2408
2409 f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4);
2410 f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4);
2411
2412 /* Record the fields for the semantic handler. */
2413 FLD (f_r1) = f_r1;
2414 FLD (f_r2) = f_r2;
2415 FLD (i_src1) = & CPU (h_gr)[f_r1];
2416 FLD (i_src2) = & CPU (h_gr)[f_r2];
2417 CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_unlock", "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0));
2418
2419 #if WITH_PROFILE_MODEL_P
2420 /* Record the fields for profiling. */
2421 if (PROFILE_MODEL_P (current_cpu))
2422 {
2423 FLD (in_src1) = f_r1;
2424 FLD (in_src2) = f_r2;
2425 }
2426 #endif
2427 #undef FLD
2428 return idesc;
2429 }
2430
2431 extract_sfmt_satb:
2432 {
2433 const IDESC *idesc = &m32rxf_insn_data[itype];
2434 CGEN_INSN_WORD insn = entire_insn;
2435 #define FLD(f) abuf->fields.sfmt_ld_plus.f
2436 UINT f_r1;
2437 UINT f_r2;
2438
2439 f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4);
2440 f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4);
2441
2442 /* Record the fields for the semantic handler. */
2443 FLD (f_r2) = f_r2;
2444 FLD (f_r1) = f_r1;
2445 FLD (i_sr) = & CPU (h_gr)[f_r2];
2446 FLD (i_dr) = & CPU (h_gr)[f_r1];
2447 CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_satb", "f_r2 0x%x", 'x', f_r2, "f_r1 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0));
2448
2449 #if WITH_PROFILE_MODEL_P
2450 /* Record the fields for profiling. */
2451 if (PROFILE_MODEL_P (current_cpu))
2452 {
2453 FLD (in_sr) = f_r2;
2454 FLD (out_dr) = f_r1;
2455 }
2456 #endif
2457 #undef FLD
2458 return idesc;
2459 }
2460
2461 extract_sfmt_sat:
2462 {
2463 const IDESC *idesc = &m32rxf_insn_data[itype];
2464 CGEN_INSN_WORD insn = entire_insn;
2465 #define FLD(f) abuf->fields.sfmt_ld_plus.f
2466 UINT f_r1;
2467 UINT f_r2;
2468
2469 f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4);
2470 f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4);
2471
2472 /* Record the fields for the semantic handler. */
2473 FLD (f_r2) = f_r2;
2474 FLD (f_r1) = f_r1;
2475 FLD (i_sr) = & CPU (h_gr)[f_r2];
2476 FLD (i_dr) = & CPU (h_gr)[f_r1];
2477 CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_sat", "f_r2 0x%x", 'x', f_r2, "f_r1 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0));
2478
2479 #if WITH_PROFILE_MODEL_P
2480 /* Record the fields for profiling. */
2481 if (PROFILE_MODEL_P (current_cpu))
2482 {
2483 FLD (in_sr) = f_r2;
2484 FLD (out_dr) = f_r1;
2485 }
2486 #endif
2487 #undef FLD
2488 return idesc;
2489 }
2490
2491 extract_sfmt_sadd:
2492 {
2493 const IDESC *idesc = &m32rxf_insn_data[itype];
2494 #define FLD(f) abuf->fields.sfmt_empty.f
2495
2496
2497 /* Record the fields for the semantic handler. */
2498 CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_sadd", (char *) 0));
2499
2500 #undef FLD
2501 return idesc;
2502 }
2503
2504 extract_sfmt_macwu1:
2505 {
2506 const IDESC *idesc = &m32rxf_insn_data[itype];
2507 CGEN_INSN_WORD insn = entire_insn;
2508 #define FLD(f) abuf->fields.sfmt_st_plus.f
2509 UINT f_r1;
2510 UINT f_r2;
2511
2512 f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4);
2513 f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4);
2514
2515 /* Record the fields for the semantic handler. */
2516 FLD (f_r1) = f_r1;
2517 FLD (f_r2) = f_r2;
2518 FLD (i_src1) = & CPU (h_gr)[f_r1];
2519 FLD (i_src2) = & CPU (h_gr)[f_r2];
2520 CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_macwu1", "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0));
2521
2522 #if WITH_PROFILE_MODEL_P
2523 /* Record the fields for profiling. */
2524 if (PROFILE_MODEL_P (current_cpu))
2525 {
2526 FLD (in_src1) = f_r1;
2527 FLD (in_src2) = f_r2;
2528 }
2529 #endif
2530 #undef FLD
2531 return idesc;
2532 }
2533
2534 extract_sfmt_msblo:
2535 {
2536 const IDESC *idesc = &m32rxf_insn_data[itype];
2537 CGEN_INSN_WORD insn = entire_insn;
2538 #define FLD(f) abuf->fields.sfmt_st_plus.f
2539 UINT f_r1;
2540 UINT f_r2;
2541
2542 f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4);
2543 f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4);
2544
2545 /* Record the fields for the semantic handler. */
2546 FLD (f_r1) = f_r1;
2547 FLD (f_r2) = f_r2;
2548 FLD (i_src1) = & CPU (h_gr)[f_r1];
2549 FLD (i_src2) = & CPU (h_gr)[f_r2];
2550 CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_msblo", "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0));
2551
2552 #if WITH_PROFILE_MODEL_P
2553 /* Record the fields for profiling. */
2554 if (PROFILE_MODEL_P (current_cpu))
2555 {
2556 FLD (in_src1) = f_r1;
2557 FLD (in_src2) = f_r2;
2558 }
2559 #endif
2560 #undef FLD
2561 return idesc;
2562 }
2563
2564 extract_sfmt_mulwu1:
2565 {
2566 const IDESC *idesc = &m32rxf_insn_data[itype];
2567 CGEN_INSN_WORD insn = entire_insn;
2568 #define FLD(f) abuf->fields.sfmt_st_plus.f
2569 UINT f_r1;
2570 UINT f_r2;
2571
2572 f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4);
2573 f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4);
2574
2575 /* Record the fields for the semantic handler. */
2576 FLD (f_r1) = f_r1;
2577 FLD (f_r2) = f_r2;
2578 FLD (i_src1) = & CPU (h_gr)[f_r1];
2579 FLD (i_src2) = & CPU (h_gr)[f_r2];
2580 CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_mulwu1", "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0));
2581
2582 #if WITH_PROFILE_MODEL_P
2583 /* Record the fields for profiling. */
2584 if (PROFILE_MODEL_P (current_cpu))
2585 {
2586 FLD (in_src1) = f_r1;
2587 FLD (in_src2) = f_r2;
2588 }
2589 #endif
2590 #undef FLD
2591 return idesc;
2592 }
2593
2594 extract_sfmt_sc:
2595 {
2596 const IDESC *idesc = &m32rxf_insn_data[itype];
2597 #define FLD(f) abuf->fields.sfmt_empty.f
2598
2599
2600 /* Record the fields for the semantic handler. */
2601 CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_sc", (char *) 0));
2602
2603 #undef FLD
2604 return idesc;
2605 }
2606
2607 extract_sfmt_clrpsw:
2608 {
2609 const IDESC *idesc = &m32rxf_insn_data[itype];
2610 CGEN_INSN_WORD insn = entire_insn;
2611 #define FLD(f) abuf->fields.sfmt_clrpsw.f
2612 UINT f_uimm8;
2613
2614 f_uimm8 = EXTRACT_MSB0_UINT (insn, 16, 8, 8);
2615
2616 /* Record the fields for the semantic handler. */
2617 FLD (f_uimm8) = f_uimm8;
2618 CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_clrpsw", "f_uimm8 0x%x", 'x', f_uimm8, (char *) 0));
2619
2620 #undef FLD
2621 return idesc;
2622 }
2623
2624 extract_sfmt_setpsw:
2625 {
2626 const IDESC *idesc = &m32rxf_insn_data[itype];
2627 CGEN_INSN_WORD insn = entire_insn;
2628 #define FLD(f) abuf->fields.sfmt_clrpsw.f
2629 UINT f_uimm8;
2630
2631 f_uimm8 = EXTRACT_MSB0_UINT (insn, 16, 8, 8);
2632
2633 /* Record the fields for the semantic handler. */
2634 FLD (f_uimm8) = f_uimm8;
2635 CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_setpsw", "f_uimm8 0x%x", 'x', f_uimm8, (char *) 0));
2636
2637 #undef FLD
2638 return idesc;
2639 }
2640
2641 extract_sfmt_bset:
2642 {
2643 const IDESC *idesc = &m32rxf_insn_data[itype];
2644 CGEN_INSN_WORD insn = entire_insn;
2645 #define FLD(f) abuf->fields.sfmt_bset.f
2646 UINT f_uimm3;
2647 UINT f_r2;
2648 INT f_simm16;
2649
2650 f_uimm3 = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
2651 f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4);
2652 f_simm16 = EXTRACT_MSB0_SINT (insn, 32, 16, 16);
2653
2654 /* Record the fields for the semantic handler. */
2655 FLD (f_simm16) = f_simm16;
2656 FLD (f_r2) = f_r2;
2657 FLD (f_uimm3) = f_uimm3;
2658 FLD (i_sr) = & CPU (h_gr)[f_r2];
2659 CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_bset", "f_simm16 0x%x", 'x', f_simm16, "f_r2 0x%x", 'x', f_r2, "f_uimm3 0x%x", 'x', f_uimm3, "sr 0x%x", 'x', f_r2, (char *) 0));
2660
2661 #if WITH_PROFILE_MODEL_P
2662 /* Record the fields for profiling. */
2663 if (PROFILE_MODEL_P (current_cpu))
2664 {
2665 FLD (in_sr) = f_r2;
2666 }
2667 #endif
2668 #undef FLD
2669 return idesc;
2670 }
2671
2672 extract_sfmt_btst:
2673 {
2674 const IDESC *idesc = &m32rxf_insn_data[itype];
2675 CGEN_INSN_WORD insn = entire_insn;
2676 #define FLD(f) abuf->fields.sfmt_bset.f
2677 UINT f_uimm3;
2678 UINT f_r2;
2679
2680 f_uimm3 = EXTRACT_MSB0_UINT (insn, 16, 5, 3);
2681 f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4);
2682
2683 /* Record the fields for the semantic handler. */
2684 FLD (f_r2) = f_r2;
2685 FLD (f_uimm3) = f_uimm3;
2686 FLD (i_sr) = & CPU (h_gr)[f_r2];
2687 CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_btst", "f_r2 0x%x", 'x', f_r2, "f_uimm3 0x%x", 'x', f_uimm3, "sr 0x%x", 'x', f_r2, (char *) 0));
2688
2689 #if WITH_PROFILE_MODEL_P
2690 /* Record the fields for profiling. */
2691 if (PROFILE_MODEL_P (current_cpu))
2692 {
2693 FLD (in_sr) = f_r2;
2694 }
2695 #endif
2696 #undef FLD
2697 return idesc;
2698 }
2699
2700 }
A mirror of the official binutils-gdb repository