sim/m32r/m32r-sim.h

   1 /* collection of junk waiting time to sort out
   2    Copyright (C) 1996, 1997, 1998 Free Software Foundation, Inc.
   3    Contributed by Cygnus Support.
   4
   5 This file is part of the GNU Simulators.
   6
   7 This program is free software; you can redistribute it and/or modify
   8 it under the terms of the GNU General Public License as published by
   9 the Free Software Foundation; either version 2, or (at your option)
  10 any later version.
  11
  12 This program is distributed in the hope that it will be useful,
  13 but WITHOUT ANY WARRANTY; without even the implied warranty of
  14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15 GNU General Public License for more details.
  16
  17 You should have received a copy of the GNU General Public License along
  18 with this program; if not, write to the Free Software Foundation, Inc.,
  19 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
  20
  21 #ifndef M32R_SIM_H
  22 #define M32R_SIM_H
  23
  24 /* gdb register numbers */
  25 #define PSW_REGNUM      16
  26 #define CBR_REGNUM      17
  27 #define SPI_REGNUM      18
  28 #define SPU_REGNUM      19
  29 #define BPC_REGNUM      20
  30 #define PC_REGNUM       21
  31 #define ACCL_REGNUM     22
  32 #define ACCH_REGNUM     23
  33 #define ACC1L_REGNUM    24
  34 #define ACC1H_REGNUM    25
  35 #define BBPSW_REGNUM    26
  36 #define BBPC_REGNUM     27
  37
  38 extern int m32r_decode_gdb_ctrl_regnum (int);
  39
  40 /* Cover macros for hardware accesses.
  41    FIXME: Eventually move to cgen.  */
  42 #define GET_H_SM() ((CPU (h_psw) & 0x80) != 0)
  43
  44 extern USI m32rbf_h_cr_get_handler (SIM_CPU *, UINT);
  45 extern void m32rbf_h_cr_set_handler (SIM_CPU *, UINT, USI);
  46 #define GET_H_CR(regno) \
  47   XCONCAT2 (WANT_CPU,_h_cr_get_handler) (current_cpu, (regno))
  48 #define SET_H_CR(regno, val) \
  49   XCONCAT2 (WANT_CPU,_h_cr_set_handler) (current_cpu, (regno), (val))
  50
  51 extern UQI m32rbf_h_psw_get_handler (SIM_CPU *);
  52 extern void m32rbf_h_psw_set_handler (SIM_CPU *, UQI);
  53 #define GET_H_PSW() \
  54   XCONCAT2 (WANT_CPU,_h_psw_get_handler) (current_cpu)
  55 #define SET_H_PSW(val) \
  56   XCONCAT2 (WANT_CPU,_h_psw_set_handler) (current_cpu, (val))
  57
  58 extern DI m32rbf_h_accum_get_handler (SIM_CPU *);
  59 extern void m32rbf_h_accum_set_handler (SIM_CPU *, DI);
  60 #define GET_H_ACCUM() \
  61   XCONCAT2 (WANT_CPU,_h_accum_get_handler) (current_cpu)
  62 #define SET_H_ACCUM(val) \
  63   XCONCAT2 (WANT_CPU,_h_accum_set_handler) (current_cpu, (val))
  64
  65 \f
  66 /* Misc. profile data.  */
  67
  68 typedef struct {
  69   /* nop insn slot filler count */
  70   unsigned int fillnop_count;
  71   /* number of parallel insns */
  72   unsigned int parallel_count;
  73
  74   /* FIXME: generalize this to handle all insn lengths, move to common.  */
  75   /* number of short insns, not including parallel ones */
  76   unsigned int short_count;
  77   /* number of long insns */
  78   unsigned int long_count;
  79
  80   /* Working area for computing cycle counts.  */
  81   unsigned long insn_cycles; /* FIXME: delete */
  82   unsigned long cti_stall;
  83   unsigned long load_stall;
  84   unsigned long biggest_cycles;
  85
  86   /* Bitmask of registers loaded by previous insn.  */
  87   unsigned int load_regs;
  88   /* Bitmask of registers loaded by current insn.  */
  89   unsigned int load_regs_pending;
  90 } M32R_MISC_PROFILE;
  91
  92 /* Initialize the working area.  */
  93 void m32r_init_insn_cycles (SIM_CPU *, int);
  94 /* Update the totals for the insn.  */
  95 void m32r_record_insn_cycles (SIM_CPU *, int);
  96
  97 /* This is invoked by the nop pattern in the .cpu file.  */
  98 #define PROFILE_COUNT_FILLNOPS(cpu, addr) \
  99 do { \
 100   if (PROFILE_INSN_P (cpu) \
 101       && (addr & 3) != 0) \
 102     ++ CPU_M32R_MISC_PROFILE (cpu)->fillnop_count; \
 103 } while (0)
 104
 105 /* This is invoked by the execute section of mloop{,x}.in.  */
 106 #define PROFILE_COUNT_PARINSNS(cpu) \
 107 do { \
 108   if (PROFILE_INSN_P (cpu)) \
 109     ++ CPU_M32R_MISC_PROFILE (cpu)->parallel_count; \
 110 } while (0)
 111
 112 /* This is invoked by the execute section of mloop{,x}.in.  */
 113 #define PROFILE_COUNT_SHORTINSNS(cpu) \
 114 do { \
 115   if (PROFILE_INSN_P (cpu)) \
 116     ++ CPU_M32R_MISC_PROFILE (cpu)->short_count; \
 117 } while (0)
 118
 119 /* This is invoked by the execute section of mloop{,x}.in.  */
 120 #define PROFILE_COUNT_LONGINSNS(cpu) \
 121 do { \
 122   if (PROFILE_INSN_P (cpu)) \
 123     ++ CPU_M32R_MISC_PROFILE (cpu)->long_count; \
 124 } while (0)
 125 \f
 126 #define GETTWI GETTSI
 127 #define SETTWI SETTSI
 128 \f
 129 /* Additional execution support.  */
 130
 131 \f
 132 /* Hardware/device support.
 133    ??? Will eventually want to move device stuff to config files.  */
 134
 135 /* Exception, Interrupt, and Trap addresses */
 136 #define EIT_SYSBREAK_ADDR       0x10
 137 #define EIT_RSVD_INSN_ADDR      0x20
 138 #define EIT_ADDR_EXCP_ADDR      0x30
 139 #define EIT_TRAP_BASE_ADDR      0x40
 140 #define EIT_EXTERN_ADDR         0x80
 141 #define EIT_RESET_ADDR          0x7ffffff0
 142 #define EIT_WAKEUP_ADDR         0x7ffffff0
 143
 144 /* Special purpose traps.  */
 145 #define TRAP_SYSCALL    0
 146 #define TRAP_BREAKPOINT 1
 147
 148 /* Support for the MSPR register (Cache Purge Control Register)
 149    and the MCCR register (Cache Control Register) are needed in order for
 150    overlays to work correctly with the scache.
 151    MSPR no longer exists but is supported for upward compatibility with
 152    early overlay support.  */
 153
 154 /* Cache Purge Control (only exists on early versions of chips) */
 155 #define MSPR_ADDR 0xfffffff7
 156 #define MSPR_PURGE 1
 157
 158 /* Lock Control Register (not supported) */
 159 #define MLCR_ADDR 0xfffffff7
 160 #define MLCR_LM 1
 161
 162 /* Power Management Control Register (not supported) */
 163 #define MPMR_ADDR 0xfffffffb
 164
 165 /* Cache Control Register */
 166 #define MCCR_ADDR 0xffffffff
 167 #define MCCR_CP 0x80
 168 /* not supported */
 169 #define MCCR_CM0 2
 170 #define MCCR_CM1 1
 171
 172 /* Serial device addresses.  */
 173 #ifdef M32R_EVA /* orig eva board, no longer supported */
 174 #define UART_INCHAR_ADDR        0xff102013
 175 #define UART_OUTCHAR_ADDR       0xff10200f
 176 #define UART_STATUS_ADDR        0xff102006
 177 /* Indicate ready bit is inverted.  */
 178 #define UART_INPUT_READY0
 179 #else
 180 /* These are the values for the MSA2000 board.
 181    ??? Will eventually need to move this to a config file.  */
 182 #define UART_INCHAR_ADDR        0xff004009
 183 #define UART_OUTCHAR_ADDR       0xff004007
 184 #define UART_STATUS_ADDR        0xff004002
 185 #endif
 186
 187 #define UART_INPUT_READY        0x4
 188 #define UART_OUTPUT_READY       0x1
 189
 190 /* Start address and length of all device support.  */
 191 #define M32R_DEVICE_ADDR        0xff000000
 192 #define M32R_DEVICE_LEN         0x00ffffff
 193
 194 /* sim_core_attach device argument.  */
 195 extern device m32r_devices;
 196
 197 /* FIXME: Temporary, until device support ready.  */
 198 struct _device { int foo; };
 199
 200 /* Handle the trap insn.  */
 201 USI m32r_trap (SIM_CPU *, PCADDR, int);
 202
 203 #endif /* M32R_SIM_H */