sim/m32r/m32r-sim.h

   1 /* collection of junk waiting time to sort out
   2    Copyright (C) 1996, 1997, 1998, 2003, 2007, 2008
   3    Free Software Foundation, Inc.
   4    Contributed by Cygnus Support.
   5
   6    This file is part of GDB, the GNU debugger.
   7
   8    This program is free software; you can redistribute it and/or modify
   9    it under the terms of the GNU General Public License as published by
  10    the Free Software Foundation; either version 3 of the License, or
  11    (at your option) any later version.
  12
  13    This program is distributed in the hope that it will be useful,
  14    but WITHOUT ANY WARRANTY; without even the implied warranty of
  15    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16    GNU General Public License for more details.
  17
  18    You should have received a copy of the GNU General Public License
  19    along with this program.  If not, see <http://www.gnu.org/licenses/>.  */
  20
  21 #ifndef M32R_SIM_H
  22 #define M32R_SIM_H
  23
  24 /* GDB register numbers.  */
  25 #define PSW_REGNUM      16
  26 #define CBR_REGNUM      17
  27 #define SPI_REGNUM      18
  28 #define SPU_REGNUM      19
  29 #define BPC_REGNUM      20
  30 #define PC_REGNUM       21
  31 #define ACCL_REGNUM     22
  32 #define ACCH_REGNUM     23
  33 #define ACC1L_REGNUM    24
  34 #define ACC1H_REGNUM    25
  35 #define BBPSW_REGNUM    26
  36 #define BBPC_REGNUM     27
  37 #define EVB_REGNUM      28
  38
  39 extern int m32r_decode_gdb_ctrl_regnum (int);
  40
  41 /* Cover macros for hardware accesses.
  42    FIXME: Eventually move to cgen.  */
  43 #define GET_H_SM() ((CPU (h_psw) & 0x80) != 0)
  44
  45 #ifndef GET_H_CR
  46 extern USI  m32rbf_h_cr_get_handler (SIM_CPU *, UINT);
  47 extern void m32rbf_h_cr_set_handler (SIM_CPU *, UINT, USI);
  48
  49 #define GET_H_CR(regno) \
  50   XCONCAT2 (WANT_CPU,_h_cr_get_handler) (current_cpu, (regno))
  51 #define SET_H_CR(regno, val) \
  52   XCONCAT2 (WANT_CPU,_h_cr_set_handler) (current_cpu, (regno), (val))
  53 #endif
  54
  55 #ifndef  GET_H_PSW
  56 extern UQI  m32rbf_h_psw_get_handler (SIM_CPU *);
  57 extern void m32rbf_h_psw_set_handler (SIM_CPU *, UQI);
  58
  59 #define GET_H_PSW() \
  60   XCONCAT2 (WANT_CPU,_h_psw_get_handler) (current_cpu)
  61 #define SET_H_PSW(val) \
  62   XCONCAT2 (WANT_CPU,_h_psw_set_handler) (current_cpu, (val))
  63 #endif
  64
  65 #ifndef  GET_H_ACCUM
  66 extern DI   m32rbf_h_accum_get_handler (SIM_CPU *);
  67 extern void m32rbf_h_accum_set_handler (SIM_CPU *, DI);
  68
  69 #define GET_H_ACCUM() \
  70   XCONCAT2 (WANT_CPU,_h_accum_get_handler) (current_cpu)
  71 #define SET_H_ACCUM(val) \
  72   XCONCAT2 (WANT_CPU,_h_accum_set_handler) (current_cpu, (val))
  73 #endif
  74 \f
  75 /* Misc. profile data.  */
  76
  77 typedef struct {
  78   /* nop insn slot filler count */
  79   unsigned int fillnop_count;
  80   /* number of parallel insns */
  81   unsigned int parallel_count;
  82
  83   /* FIXME: generalize this to handle all insn lengths, move to common.  */
  84   /* number of short insns, not including parallel ones */
  85   unsigned int short_count;
  86   /* number of long insns */
  87   unsigned int long_count;
  88
  89   /* Working area for computing cycle counts.  */
  90   unsigned long insn_cycles; /* FIXME: delete */
  91   unsigned long cti_stall;
  92   unsigned long load_stall;
  93   unsigned long biggest_cycles;
  94
  95   /* Bitmask of registers loaded by previous insn.  */
  96   unsigned int load_regs;
  97   /* Bitmask of registers loaded by current insn.  */
  98   unsigned int load_regs_pending;
  99 } M32R_MISC_PROFILE;
 100
 101 /* Initialize the working area.  */
 102 void m32r_init_insn_cycles (SIM_CPU *, int);
 103 /* Update the totals for the insn.  */
 104 void m32r_record_insn_cycles (SIM_CPU *, int);
 105
 106 /* This is invoked by the nop pattern in the .cpu file.  */
 107 #define PROFILE_COUNT_FILLNOPS(cpu, addr) \
 108 do { \
 109   if (PROFILE_INSN_P (cpu) \
 110       && (addr & 3) != 0) \
 111     ++ CPU_M32R_MISC_PROFILE (cpu)->fillnop_count; \
 112 } while (0)
 113
 114 /* This is invoked by the execute section of mloop{,x}.in.  */
 115 #define PROFILE_COUNT_PARINSNS(cpu) \
 116 do { \
 117   if (PROFILE_INSN_P (cpu)) \
 118     ++ CPU_M32R_MISC_PROFILE (cpu)->parallel_count; \
 119 } while (0)
 120
 121 /* This is invoked by the execute section of mloop{,x}.in.  */
 122 #define PROFILE_COUNT_SHORTINSNS(cpu) \
 123 do { \
 124   if (PROFILE_INSN_P (cpu)) \
 125     ++ CPU_M32R_MISC_PROFILE (cpu)->short_count; \
 126 } while (0)
 127
 128 /* This is invoked by the execute section of mloop{,x}.in.  */
 129 #define PROFILE_COUNT_LONGINSNS(cpu) \
 130 do { \
 131   if (PROFILE_INSN_P (cpu)) \
 132     ++ CPU_M32R_MISC_PROFILE (cpu)->long_count; \
 133 } while (0)
 134 \f
 135 #define GETTWI GETTSI
 136 #define SETTWI SETTSI
 137 \f
 138 /* Additional execution support.  */
 139
 140 \f
 141 /* Hardware/device support.
 142    ??? Will eventually want to move device stuff to config files.  */
 143
 144 /* Exception, Interrupt, and Trap addresses */
 145 #define EIT_SYSBREAK_ADDR       0x10
 146 #define EIT_RSVD_INSN_ADDR      0x20
 147 #define EIT_ADDR_EXCP_ADDR      0x30
 148 #define EIT_TRAP_BASE_ADDR      0x40
 149 #define EIT_EXTERN_ADDR         0x80
 150 #define EIT_RESET_ADDR          0x7ffffff0
 151 #define EIT_WAKEUP_ADDR         0x7ffffff0
 152
 153 /* Special purpose traps.  */
 154 #define TRAP_SYSCALL    0
 155 #define TRAP_BREAKPOINT 1
 156
 157 /* Support for the MSPR register (Cache Purge Control Register)
 158    and the MCCR register (Cache Control Register) are needed in order for
 159    overlays to work correctly with the scache.
 160    MSPR no longer exists but is supported for upward compatibility with
 161    early overlay support.  */
 162
 163 /* Cache Purge Control (only exists on early versions of chips) */
 164 #define MSPR_ADDR 0xfffffff7
 165 #define MSPR_PURGE 1
 166
 167 /* Lock Control Register (not supported) */
 168 #define MLCR_ADDR 0xfffffff7
 169 #define MLCR_LM 1
 170
 171 /* Power Management Control Register (not supported) */
 172 #define MPMR_ADDR 0xfffffffb
 173
 174 /* Cache Control Register */
 175 #define MCCR_ADDR 0xffffffff
 176 #define MCCR_CP 0x80
 177 /* not supported */
 178 #define MCCR_CM0 2
 179 #define MCCR_CM1 1
 180
 181 /* Serial device addresses.  */
 182 #ifdef M32R_EVA /* orig eva board, no longer supported */
 183 #define UART_INCHAR_ADDR        0xff102013
 184 #define UART_OUTCHAR_ADDR       0xff10200f
 185 #define UART_STATUS_ADDR        0xff102006
 186 /* Indicate ready bit is inverted.  */
 187 #define UART_INPUT_READY0
 188 #else
 189 /* These are the values for the MSA2000 board.
 190    ??? Will eventually need to move this to a config file.  */
 191 #define UART_INCHAR_ADDR        0xff004009
 192 #define UART_OUTCHAR_ADDR       0xff004007
 193 #define UART_STATUS_ADDR        0xff004002
 194 #endif
 195
 196 #define UART_INPUT_READY        0x4
 197 #define UART_OUTPUT_READY       0x1
 198
 199 /* Start address and length of all device support.  */
 200 #define M32R_DEVICE_ADDR        0xff000000
 201 #define M32R_DEVICE_LEN         0x00ffffff
 202
 203 /* sim_core_attach device argument.  */
 204 extern device m32r_devices;
 205
 206 /* FIXME: Temporary, until device support ready.  */
 207 struct _device { int foo; };
 208
 209 /* Handle the trap insn.  */
 210 USI m32r_trap (SIM_CPU *, PCADDR, int);
 211
 212 #endif /* M32R_SIM_H */