sim/m32r/sem-switch.c

   1 /* Simulator instruction semantics for m32rbf.
   2
   3 THIS FILE IS MACHINE GENERATED WITH CGEN.
   4
   5 Copyright 1996-2013 Free Software Foundation, Inc.
   6
   7 This file is part of the GNU simulators.
   8
   9    This file is free software; you can redistribute it and/or modify
  10    it under the terms of the GNU General Public License as published by
  11    the Free Software Foundation; either version 3, or (at your option)
  12    any later version.
  13
  14    It is distributed in the hope that it will be useful, but WITHOUT
  15    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  16    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  17    License for more details.
  18
  19    You should have received a copy of the GNU General Public License along
  20    with this program; if not, see <http://www.gnu.org/licenses/>.
  21
  22 */
  23
  24 #ifdef DEFINE_LABELS
  25
  26   /* The labels have the case they have because the enum of insn types
  27      is all uppercase and in the non-stdc case the insn symbol is built
  28      into the enum name.  */
  29
  30   static struct {
  31     int index;
  32     void *label;
  33   } labels[] = {
  34     { M32RBF_INSN_X_INVALID, && case_sem_INSN_X_INVALID },
  35     { M32RBF_INSN_X_AFTER, && case_sem_INSN_X_AFTER },
  36     { M32RBF_INSN_X_BEFORE, && case_sem_INSN_X_BEFORE },
  37     { M32RBF_INSN_X_CTI_CHAIN, && case_sem_INSN_X_CTI_CHAIN },
  38     { M32RBF_INSN_X_CHAIN, && case_sem_INSN_X_CHAIN },
  39     { M32RBF_INSN_X_BEGIN, && case_sem_INSN_X_BEGIN },
  40     { M32RBF_INSN_ADD, && case_sem_INSN_ADD },
  41     { M32RBF_INSN_ADD3, && case_sem_INSN_ADD3 },
  42     { M32RBF_INSN_AND, && case_sem_INSN_AND },
  43     { M32RBF_INSN_AND3, && case_sem_INSN_AND3 },
  44     { M32RBF_INSN_OR, && case_sem_INSN_OR },
  45     { M32RBF_INSN_OR3, && case_sem_INSN_OR3 },
  46     { M32RBF_INSN_XOR, && case_sem_INSN_XOR },
  47     { M32RBF_INSN_XOR3, && case_sem_INSN_XOR3 },
  48     { M32RBF_INSN_ADDI, && case_sem_INSN_ADDI },
  49     { M32RBF_INSN_ADDV, && case_sem_INSN_ADDV },
  50     { M32RBF_INSN_ADDV3, && case_sem_INSN_ADDV3 },
  51     { M32RBF_INSN_ADDX, && case_sem_INSN_ADDX },
  52     { M32RBF_INSN_BC8, && case_sem_INSN_BC8 },
  53     { M32RBF_INSN_BC24, && case_sem_INSN_BC24 },
  54     { M32RBF_INSN_BEQ, && case_sem_INSN_BEQ },
  55     { M32RBF_INSN_BEQZ, && case_sem_INSN_BEQZ },
  56     { M32RBF_INSN_BGEZ, && case_sem_INSN_BGEZ },
  57     { M32RBF_INSN_BGTZ, && case_sem_INSN_BGTZ },
  58     { M32RBF_INSN_BLEZ, && case_sem_INSN_BLEZ },
  59     { M32RBF_INSN_BLTZ, && case_sem_INSN_BLTZ },
  60     { M32RBF_INSN_BNEZ, && case_sem_INSN_BNEZ },
  61     { M32RBF_INSN_BL8, && case_sem_INSN_BL8 },
  62     { M32RBF_INSN_BL24, && case_sem_INSN_BL24 },
  63     { M32RBF_INSN_BNC8, && case_sem_INSN_BNC8 },
  64     { M32RBF_INSN_BNC24, && case_sem_INSN_BNC24 },
  65     { M32RBF_INSN_BNE, && case_sem_INSN_BNE },
  66     { M32RBF_INSN_BRA8, && case_sem_INSN_BRA8 },
  67     { M32RBF_INSN_BRA24, && case_sem_INSN_BRA24 },
  68     { M32RBF_INSN_CMP, && case_sem_INSN_CMP },
  69     { M32RBF_INSN_CMPI, && case_sem_INSN_CMPI },
  70     { M32RBF_INSN_CMPU, && case_sem_INSN_CMPU },
  71     { M32RBF_INSN_CMPUI, && case_sem_INSN_CMPUI },
  72     { M32RBF_INSN_DIV, && case_sem_INSN_DIV },
  73     { M32RBF_INSN_DIVU, && case_sem_INSN_DIVU },
  74     { M32RBF_INSN_REM, && case_sem_INSN_REM },
  75     { M32RBF_INSN_REMU, && case_sem_INSN_REMU },
  76     { M32RBF_INSN_JL, && case_sem_INSN_JL },
  77     { M32RBF_INSN_JMP, && case_sem_INSN_JMP },
  78     { M32RBF_INSN_LD, && case_sem_INSN_LD },
  79     { M32RBF_INSN_LD_D, && case_sem_INSN_LD_D },
  80     { M32RBF_INSN_LDB, && case_sem_INSN_LDB },
  81     { M32RBF_INSN_LDB_D, && case_sem_INSN_LDB_D },
  82     { M32RBF_INSN_LDH, && case_sem_INSN_LDH },
  83     { M32RBF_INSN_LDH_D, && case_sem_INSN_LDH_D },
  84     { M32RBF_INSN_LDUB, && case_sem_INSN_LDUB },
  85     { M32RBF_INSN_LDUB_D, && case_sem_INSN_LDUB_D },
  86     { M32RBF_INSN_LDUH, && case_sem_INSN_LDUH },
  87     { M32RBF_INSN_LDUH_D, && case_sem_INSN_LDUH_D },
  88     { M32RBF_INSN_LD_PLUS, && case_sem_INSN_LD_PLUS },
  89     { M32RBF_INSN_LD24, && case_sem_INSN_LD24 },
  90     { M32RBF_INSN_LDI8, && case_sem_INSN_LDI8 },
  91     { M32RBF_INSN_LDI16, && case_sem_INSN_LDI16 },
  92     { M32RBF_INSN_LOCK, && case_sem_INSN_LOCK },
  93     { M32RBF_INSN_MACHI, && case_sem_INSN_MACHI },
  94     { M32RBF_INSN_MACLO, && case_sem_INSN_MACLO },
  95     { M32RBF_INSN_MACWHI, && case_sem_INSN_MACWHI },
  96     { M32RBF_INSN_MACWLO, && case_sem_INSN_MACWLO },
  97     { M32RBF_INSN_MUL, && case_sem_INSN_MUL },
  98     { M32RBF_INSN_MULHI, && case_sem_INSN_MULHI },
  99     { M32RBF_INSN_MULLO, && case_sem_INSN_MULLO },
 100     { M32RBF_INSN_MULWHI, && case_sem_INSN_MULWHI },
 101     { M32RBF_INSN_MULWLO, && case_sem_INSN_MULWLO },
 102     { M32RBF_INSN_MV, && case_sem_INSN_MV },
 103     { M32RBF_INSN_MVFACHI, && case_sem_INSN_MVFACHI },
 104     { M32RBF_INSN_MVFACLO, && case_sem_INSN_MVFACLO },
 105     { M32RBF_INSN_MVFACMI, && case_sem_INSN_MVFACMI },
 106     { M32RBF_INSN_MVFC, && case_sem_INSN_MVFC },
 107     { M32RBF_INSN_MVTACHI, && case_sem_INSN_MVTACHI },
 108     { M32RBF_INSN_MVTACLO, && case_sem_INSN_MVTACLO },
 109     { M32RBF_INSN_MVTC, && case_sem_INSN_MVTC },
 110     { M32RBF_INSN_NEG, && case_sem_INSN_NEG },
 111     { M32RBF_INSN_NOP, && case_sem_INSN_NOP },
 112     { M32RBF_INSN_NOT, && case_sem_INSN_NOT },
 113     { M32RBF_INSN_RAC, && case_sem_INSN_RAC },
 114     { M32RBF_INSN_RACH, && case_sem_INSN_RACH },
 115     { M32RBF_INSN_RTE, && case_sem_INSN_RTE },
 116     { M32RBF_INSN_SETH, && case_sem_INSN_SETH },
 117     { M32RBF_INSN_SLL, && case_sem_INSN_SLL },
 118     { M32RBF_INSN_SLL3, && case_sem_INSN_SLL3 },
 119     { M32RBF_INSN_SLLI, && case_sem_INSN_SLLI },
 120     { M32RBF_INSN_SRA, && case_sem_INSN_SRA },
 121     { M32RBF_INSN_SRA3, && case_sem_INSN_SRA3 },
 122     { M32RBF_INSN_SRAI, && case_sem_INSN_SRAI },
 123     { M32RBF_INSN_SRL, && case_sem_INSN_SRL },
 124     { M32RBF_INSN_SRL3, && case_sem_INSN_SRL3 },
 125     { M32RBF_INSN_SRLI, && case_sem_INSN_SRLI },
 126     { M32RBF_INSN_ST, && case_sem_INSN_ST },
 127     { M32RBF_INSN_ST_D, && case_sem_INSN_ST_D },
 128     { M32RBF_INSN_STB, && case_sem_INSN_STB },
 129     { M32RBF_INSN_STB_D, && case_sem_INSN_STB_D },
 130     { M32RBF_INSN_STH, && case_sem_INSN_STH },
 131     { M32RBF_INSN_STH_D, && case_sem_INSN_STH_D },
 132     { M32RBF_INSN_ST_PLUS, && case_sem_INSN_ST_PLUS },
 133     { M32RBF_INSN_ST_MINUS, && case_sem_INSN_ST_MINUS },
 134     { M32RBF_INSN_SUB, && case_sem_INSN_SUB },
 135     { M32RBF_INSN_SUBV, && case_sem_INSN_SUBV },
 136     { M32RBF_INSN_SUBX, && case_sem_INSN_SUBX },
 137     { M32RBF_INSN_TRAP, && case_sem_INSN_TRAP },
 138     { M32RBF_INSN_UNLOCK, && case_sem_INSN_UNLOCK },
 139     { M32RBF_INSN_CLRPSW, && case_sem_INSN_CLRPSW },
 140     { M32RBF_INSN_SETPSW, && case_sem_INSN_SETPSW },
 141     { M32RBF_INSN_BSET, && case_sem_INSN_BSET },
 142     { M32RBF_INSN_BCLR, && case_sem_INSN_BCLR },
 143     { M32RBF_INSN_BTST, && case_sem_INSN_BTST },
 144     { 0, 0 }
 145   };
 146   int i;
 147
 148   for (i = 0; labels[i].label != 0; ++i)
 149     {
 150 #if FAST_P
 151       CPU_IDESC (current_cpu) [labels[i].index].sem_fast_lab = labels[i].label;
 152 #else
 153       CPU_IDESC (current_cpu) [labels[i].index].sem_full_lab = labels[i].label;
 154 #endif
 155     }
 156
 157 #undef DEFINE_LABELS
 158 #endif /* DEFINE_LABELS */
 159
 160 #ifdef DEFINE_SWITCH
 161
 162 /* If hyper-fast [well not unnecessarily slow] execution is selected, turn
 163    off frills like tracing and profiling.  */
 164 /* FIXME: A better way would be to have TRACE_RESULT check for something
 165    that can cause it to be optimized out.  Another way would be to emit
 166    special handlers into the instruction "stream".  */
 167
 168 #if FAST_P
 169 #undef TRACE_RESULT
 170 #define TRACE_RESULT(cpu, abuf, name, type, val)
 171 #endif
 172
 173 #undef GET_ATTR
 174 #define GET_ATTR(cpu, num, attr) CGEN_ATTR_VALUE (NULL, abuf->idesc->attrs, CGEN_INSN_##attr)
 175
 176 {
 177
 178 #if WITH_SCACHE_PBB
 179
 180 /* Branch to next handler without going around main loop.  */
 181 #define NEXT(vpc) goto * SEM_ARGBUF (vpc) -> semantic.sem_case
 182 SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case)
 183
 184 #else /* ! WITH_SCACHE_PBB */
 185
 186 #define NEXT(vpc) BREAK (sem)
 187 #ifdef __GNUC__
 188 #if FAST_P
 189   SWITCH (sem, SEM_ARGBUF (sc) -> idesc->sem_fast_lab)
 190 #else
 191   SWITCH (sem, SEM_ARGBUF (sc) -> idesc->sem_full_lab)
 192 #endif
 193 #else
 194   SWITCH (sem, SEM_ARGBUF (sc) -> idesc->num)
 195 #endif
 196
 197 #endif /* ! WITH_SCACHE_PBB */
 198
 199     {
 200
 201   CASE (sem, INSN_X_INVALID) : /* --invalid-- */
 202 {
 203   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
 204   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
 205 #define FLD(f) abuf->fields.sfmt_empty.f
 206   int UNUSED written = 0;
 207   IADDR UNUSED pc = abuf->addr;
 208   vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
 209
 210   {
 211     /* Update the recorded pc in the cpu state struct.
 212        Only necessary for WITH_SCACHE case, but to avoid the
 213        conditional compilation ....  */
 214     SET_H_PC (pc);
 215     /* Virtual insns have zero size.  Overwrite vpc with address of next insn
 216        using the default-insn-bitsize spec.  When executing insns in parallel
 217        we may want to queue the fault and continue execution.  */
 218     vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
 219     vpc = sim_engine_invalid_insn (current_cpu, pc, vpc);
 220   }
 221
 222 #undef FLD
 223 }
 224   NEXT (vpc);
 225
 226   CASE (sem, INSN_X_AFTER) : /* --after-- */
 227 {
 228   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
 229   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
 230 #define FLD(f) abuf->fields.sfmt_empty.f
 231   int UNUSED written = 0;
 232   IADDR UNUSED pc = abuf->addr;
 233   vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
 234
 235   {
 236 #if WITH_SCACHE_PBB_M32RBF
 237     m32rbf_pbb_after (current_cpu, sem_arg);
 238 #endif
 239   }
 240
 241 #undef FLD
 242 }
 243   NEXT (vpc);
 244
 245   CASE (sem, INSN_X_BEFORE) : /* --before-- */
 246 {
 247   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
 248   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
 249 #define FLD(f) abuf->fields.sfmt_empty.f
 250   int UNUSED written = 0;
 251   IADDR UNUSED pc = abuf->addr;
 252   vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
 253
 254   {
 255 #if WITH_SCACHE_PBB_M32RBF
 256     m32rbf_pbb_before (current_cpu, sem_arg);
 257 #endif
 258   }
 259
 260 #undef FLD
 261 }
 262   NEXT (vpc);
 263
 264   CASE (sem, INSN_X_CTI_CHAIN) : /* --cti-chain-- */
 265 {
 266   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
 267   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
 268 #define FLD(f) abuf->fields.sfmt_empty.f
 269   int UNUSED written = 0;
 270   IADDR UNUSED pc = abuf->addr;
 271   vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
 272
 273   {
 274 #if WITH_SCACHE_PBB_M32RBF
 275 #ifdef DEFINE_SWITCH
 276     vpc = m32rbf_pbb_cti_chain (current_cpu, sem_arg,
 277                                pbb_br_type, pbb_br_npc);
 278     BREAK (sem);
 279 #else
 280     /* FIXME: Allow provision of explicit ifmt spec in insn spec.  */
 281     vpc = m32rbf_pbb_cti_chain (current_cpu, sem_arg,
 282                                CPU_PBB_BR_TYPE (current_cpu),
 283                                CPU_PBB_BR_NPC (current_cpu));
 284 #endif
 285 #endif
 286   }
 287
 288 #undef FLD
 289 }
 290   NEXT (vpc);
 291
 292   CASE (sem, INSN_X_CHAIN) : /* --chain-- */
 293 {
 294   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
 295   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
 296 #define FLD(f) abuf->fields.sfmt_empty.f
 297   int UNUSED written = 0;
 298   IADDR UNUSED pc = abuf->addr;
 299   vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
 300
 301   {
 302 #if WITH_SCACHE_PBB_M32RBF
 303     vpc = m32rbf_pbb_chain (current_cpu, sem_arg);
 304 #ifdef DEFINE_SWITCH
 305     BREAK (sem);
 306 #endif
 307 #endif
 308   }
 309
 310 #undef FLD
 311 }
 312   NEXT (vpc);
 313
 314   CASE (sem, INSN_X_BEGIN) : /* --begin-- */
 315 {
 316   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
 317   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
 318 #define FLD(f) abuf->fields.sfmt_empty.f
 319   int UNUSED written = 0;
 320   IADDR UNUSED pc = abuf->addr;
 321   vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
 322
 323   {
 324 #if WITH_SCACHE_PBB_M32RBF
 325 #if defined DEFINE_SWITCH || defined FAST_P
 326     /* In the switch case FAST_P is a constant, allowing several optimizations
 327        in any called inline functions.  */
 328     vpc = m32rbf_pbb_begin (current_cpu, FAST_P);
 329 #else
 330 #if 0 /* cgen engine can't handle dynamic fast/full switching yet.  */
 331     vpc = m32rbf_pbb_begin (current_cpu, STATE_RUN_FAST_P (CPU_STATE (current_cpu)));
 332 #else
 333     vpc = m32rbf_pbb_begin (current_cpu, 0);
 334 #endif
 335 #endif
 336 #endif
 337   }
 338
 339 #undef FLD
 340 }
 341   NEXT (vpc);
 342
 343   CASE (sem, INSN_ADD) : /* add $dr,$sr */
 344 {
 345   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
 346   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
 347 #define FLD(f) abuf->fields.sfmt_add.f
 348   int UNUSED written = 0;
 349   IADDR UNUSED pc = abuf->addr;
 350   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
 351
 352   {
 353     SI opval = ADDSI (* FLD (i_dr), * FLD (i_sr));
 354     * FLD (i_dr) = opval;
 355     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
 356   }
 357
 358 #undef FLD
 359 }
 360   NEXT (vpc);
 361
 362   CASE (sem, INSN_ADD3) : /* add3 $dr,$sr,$hash$slo16 */
 363 {
 364   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
 365   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
 366 #define FLD(f) abuf->fields.sfmt_add3.f
 367   int UNUSED written = 0;
 368   IADDR UNUSED pc = abuf->addr;
 369   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
 370
 371   {
 372     SI opval = ADDSI (* FLD (i_sr), FLD (f_simm16));
 373     * FLD (i_dr) = opval;
 374     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
 375   }
 376
 377 #undef FLD
 378 }
 379   NEXT (vpc);
 380
 381   CASE (sem, INSN_AND) : /* and $dr,$sr */
 382 {
 383   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
 384   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
 385 #define FLD(f) abuf->fields.sfmt_add.f
 386   int UNUSED written = 0;
 387   IADDR UNUSED pc = abuf->addr;
 388   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
 389
 390   {
 391     SI opval = ANDSI (* FLD (i_dr), * FLD (i_sr));
 392     * FLD (i_dr) = opval;
 393     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
 394   }
 395
 396 #undef FLD
 397 }
 398   NEXT (vpc);
 399
 400   CASE (sem, INSN_AND3) : /* and3 $dr,$sr,$uimm16 */
 401 {
 402   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
 403   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
 404 #define FLD(f) abuf->fields.sfmt_and3.f
 405   int UNUSED written = 0;
 406   IADDR UNUSED pc = abuf->addr;
 407   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
 408
 409   {
 410     SI opval = ANDSI (* FLD (i_sr), FLD (f_uimm16));
 411     * FLD (i_dr) = opval;
 412     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
 413   }
 414
 415 #undef FLD
 416 }
 417   NEXT (vpc);
 418
 419   CASE (sem, INSN_OR) : /* or $dr,$sr */
 420 {
 421   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
 422   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
 423 #define FLD(f) abuf->fields.sfmt_add.f
 424   int UNUSED written = 0;
 425   IADDR UNUSED pc = abuf->addr;
 426   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
 427
 428   {
 429     SI opval = ORSI (* FLD (i_dr), * FLD (i_sr));
 430     * FLD (i_dr) = opval;
 431     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
 432   }
 433
 434 #undef FLD
 435 }
 436   NEXT (vpc);
 437
 438   CASE (sem, INSN_OR3) : /* or3 $dr,$sr,$hash$ulo16 */
 439 {
 440   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
 441   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
 442 #define FLD(f) abuf->fields.sfmt_and3.f
 443   int UNUSED written = 0;
 444   IADDR UNUSED pc = abuf->addr;
 445   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
 446
 447   {
 448     SI opval = ORSI (* FLD (i_sr), FLD (f_uimm16));
 449     * FLD (i_dr) = opval;
 450     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
 451   }
 452
 453 #undef FLD
 454 }
 455   NEXT (vpc);
 456
 457   CASE (sem, INSN_XOR) : /* xor $dr,$sr */
 458 {
 459   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
 460   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
 461 #define FLD(f) abuf->fields.sfmt_add.f
 462   int UNUSED written = 0;
 463   IADDR UNUSED pc = abuf->addr;
 464   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
 465
 466   {
 467     SI opval = XORSI (* FLD (i_dr), * FLD (i_sr));
 468     * FLD (i_dr) = opval;
 469     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
 470   }
 471
 472 #undef FLD
 473 }
 474   NEXT (vpc);
 475
 476   CASE (sem, INSN_XOR3) : /* xor3 $dr,$sr,$uimm16 */
 477 {
 478   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
 479   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
 480 #define FLD(f) abuf->fields.sfmt_and3.f
 481   int UNUSED written = 0;
 482   IADDR UNUSED pc = abuf->addr;
 483   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
 484
 485   {
 486     SI opval = XORSI (* FLD (i_sr), FLD (f_uimm16));
 487     * FLD (i_dr) = opval;
 488     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
 489   }
 490
 491 #undef FLD
 492 }
 493   NEXT (vpc);
 494
 495   CASE (sem, INSN_ADDI) : /* addi $dr,$simm8 */
 496 {
 497   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
 498   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
 499 #define FLD(f) abuf->fields.sfmt_addi.f
 500   int UNUSED written = 0;
 501   IADDR UNUSED pc = abuf->addr;
 502   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
 503
 504   {
 505     SI opval = ADDSI (* FLD (i_dr), FLD (f_simm8));
 506     * FLD (i_dr) = opval;
 507     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
 508   }
 509
 510 #undef FLD
 511 }
 512   NEXT (vpc);
 513
 514   CASE (sem, INSN_ADDV) : /* addv $dr,$sr */
 515 {
 516   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
 517   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
 518 #define FLD(f) abuf->fields.sfmt_add.f
 519   int UNUSED written = 0;
 520   IADDR UNUSED pc = abuf->addr;
 521   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
 522
 523 {
 524   SI temp0;BI temp1;
 525   temp0 = ADDSI (* FLD (i_dr), * FLD (i_sr));
 526   temp1 = ADDOFSI (* FLD (i_dr), * FLD (i_sr), 0);
 527   {
 528     SI opval = temp0;
 529     * FLD (i_dr) = opval;
 530     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
 531   }
 532   {
 533     BI opval = temp1;
 534     CPU (h_cond) = opval;
 535     TRACE_RESULT (current_cpu, abuf, "cond", 'x', opval);
 536   }
 537 }
 538
 539 #undef FLD
 540 }
 541   NEXT (vpc);
 542
 543   CASE (sem, INSN_ADDV3) : /* addv3 $dr,$sr,$simm16 */
 544 {
 545   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
 546   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
 547 #define FLD(f) abuf->fields.sfmt_add3.f
 548   int UNUSED written = 0;
 549   IADDR UNUSED pc = abuf->addr;
 550   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
 551
 552 {
 553   SI temp0;BI temp1;
 554   temp0 = ADDSI (* FLD (i_sr), FLD (f_simm16));
 555   temp1 = ADDOFSI (* FLD (i_sr), FLD (f_simm16), 0);
 556   {
 557     SI opval = temp0;
 558     * FLD (i_dr) = opval;
 559     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
 560   }
 561   {
 562     BI opval = temp1;
 563     CPU (h_cond) = opval;
 564     TRACE_RESULT (current_cpu, abuf, "cond", 'x', opval);
 565   }
 566 }
 567
 568 #undef FLD
 569 }
 570   NEXT (vpc);
 571
 572   CASE (sem, INSN_ADDX) : /* addx $dr,$sr */
 573 {
 574   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
 575   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
 576 #define FLD(f) abuf->fields.sfmt_add.f
 577   int UNUSED written = 0;
 578   IADDR UNUSED pc = abuf->addr;
 579   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
 580
 581 {
 582   SI temp0;BI temp1;
 583   temp0 = ADDCSI (* FLD (i_dr), * FLD (i_sr), CPU (h_cond));
 584   temp1 = ADDCFSI (* FLD (i_dr), * FLD (i_sr), CPU (h_cond));
 585   {
 586     SI opval = temp0;
 587     * FLD (i_dr) = opval;
 588     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
 589   }
 590   {
 591     BI opval = temp1;
 592     CPU (h_cond) = opval;
 593     TRACE_RESULT (current_cpu, abuf, "cond", 'x', opval);
 594   }
 595 }
 596
 597 #undef FLD
 598 }
 599   NEXT (vpc);
 600
 601   CASE (sem, INSN_BC8) : /* bc.s $disp8 */
 602 {
 603   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
 604   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
 605 #define FLD(f) abuf->fields.sfmt_bl8.f
 606   int UNUSED written = 0;
 607   IADDR UNUSED pc = abuf->addr;
 608   SEM_BRANCH_INIT
 609   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
 610
 611 if (CPU (h_cond)) {
 612   {
 613     USI opval = FLD (i_disp8);
 614     SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
 615     written |= (1 << 2);
 616     TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
 617   }
 618 }
 619
 620   abuf->written = written;
 621   SEM_BRANCH_FINI (vpc);
 622 #undef FLD
 623 }
 624   NEXT (vpc);
 625
 626   CASE (sem, INSN_BC24) : /* bc.l $disp24 */
 627 {
 628   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
 629   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
 630 #define FLD(f) abuf->fields.sfmt_bl24.f
 631   int UNUSED written = 0;
 632   IADDR UNUSED pc = abuf->addr;
 633   SEM_BRANCH_INIT
 634   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
 635
 636 if (CPU (h_cond)) {
 637   {
 638     USI opval = FLD (i_disp24);
 639     SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
 640     written |= (1 << 2);
 641     TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
 642   }
 643 }
 644
 645   abuf->written = written;
 646   SEM_BRANCH_FINI (vpc);
 647 #undef FLD
 648 }
 649   NEXT (vpc);
 650
 651   CASE (sem, INSN_BEQ) : /* beq $src1,$src2,$disp16 */
 652 {
 653   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
 654   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
 655 #define FLD(f) abuf->fields.sfmt_beq.f
 656   int UNUSED written = 0;
 657   IADDR UNUSED pc = abuf->addr;
 658   SEM_BRANCH_INIT
 659   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
 660
 661 if (EQSI (* FLD (i_src1), * FLD (i_src2))) {
 662   {
 663     USI opval = FLD (i_disp16);
 664     SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
 665     written |= (1 << 3);
 666     TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
 667   }
 668 }
 669
 670   abuf->written = written;
 671   SEM_BRANCH_FINI (vpc);
 672 #undef FLD
 673 }
 674   NEXT (vpc);
 675
 676   CASE (sem, INSN_BEQZ) : /* beqz $src2,$disp16 */
 677 {
 678   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
 679   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
 680 #define FLD(f) abuf->fields.sfmt_beq.f
 681   int UNUSED written = 0;
 682   IADDR UNUSED pc = abuf->addr;
 683   SEM_BRANCH_INIT
 684   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
 685
 686 if (EQSI (* FLD (i_src2), 0)) {
 687   {
 688     USI opval = FLD (i_disp16);
 689     SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
 690     written |= (1 << 2);
 691     TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
 692   }
 693 }
 694
 695   abuf->written = written;
 696   SEM_BRANCH_FINI (vpc);
 697 #undef FLD
 698 }
 699   NEXT (vpc);
 700
 701   CASE (sem, INSN_BGEZ) : /* bgez $src2,$disp16 */
 702 {
 703   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
 704   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
 705 #define FLD(f) abuf->fields.sfmt_beq.f
 706   int UNUSED written = 0;
 707   IADDR UNUSED pc = abuf->addr;
 708   SEM_BRANCH_INIT
 709   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
 710
 711 if (GESI (* FLD (i_src2), 0)) {
 712   {
 713     USI opval = FLD (i_disp16);
 714     SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
 715     written |= (1 << 2);
 716     TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
 717   }
 718 }
 719
 720   abuf->written = written;
 721   SEM_BRANCH_FINI (vpc);
 722 #undef FLD
 723 }
 724   NEXT (vpc);
 725
 726   CASE (sem, INSN_BGTZ) : /* bgtz $src2,$disp16 */
 727 {
 728   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
 729   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
 730 #define FLD(f) abuf->fields.sfmt_beq.f
 731   int UNUSED written = 0;
 732   IADDR UNUSED pc = abuf->addr;
 733   SEM_BRANCH_INIT
 734   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
 735
 736 if (GTSI (* FLD (i_src2), 0)) {
 737   {
 738     USI opval = FLD (i_disp16);
 739     SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
 740     written |= (1 << 2);
 741     TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
 742   }
 743 }
 744
 745   abuf->written = written;
 746   SEM_BRANCH_FINI (vpc);
 747 #undef FLD
 748 }
 749   NEXT (vpc);
 750
 751   CASE (sem, INSN_BLEZ) : /* blez $src2,$disp16 */
 752 {
 753   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
 754   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
 755 #define FLD(f) abuf->fields.sfmt_beq.f
 756   int UNUSED written = 0;
 757   IADDR UNUSED pc = abuf->addr;
 758   SEM_BRANCH_INIT
 759   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
 760
 761 if (LESI (* FLD (i_src2), 0)) {
 762   {
 763     USI opval = FLD (i_disp16);
 764     SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
 765     written |= (1 << 2);
 766     TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
 767   }
 768 }
 769
 770   abuf->written = written;
 771   SEM_BRANCH_FINI (vpc);
 772 #undef FLD
 773 }
 774   NEXT (vpc);
 775
 776   CASE (sem, INSN_BLTZ) : /* bltz $src2,$disp16 */
 777 {
 778   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
 779   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
 780 #define FLD(f) abuf->fields.sfmt_beq.f
 781   int UNUSED written = 0;
 782   IADDR UNUSED pc = abuf->addr;
 783   SEM_BRANCH_INIT
 784   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
 785
 786 if (LTSI (* FLD (i_src2), 0)) {
 787   {
 788     USI opval = FLD (i_disp16);
 789     SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
 790     written |= (1 << 2);
 791     TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
 792   }
 793 }
 794
 795   abuf->written = written;
 796   SEM_BRANCH_FINI (vpc);
 797 #undef FLD
 798 }
 799   NEXT (vpc);
 800
 801   CASE (sem, INSN_BNEZ) : /* bnez $src2,$disp16 */
 802 {
 803   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
 804   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
 805 #define FLD(f) abuf->fields.sfmt_beq.f
 806   int UNUSED written = 0;
 807   IADDR UNUSED pc = abuf->addr;
 808   SEM_BRANCH_INIT
 809   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
 810
 811 if (NESI (* FLD (i_src2), 0)) {
 812   {
 813     USI opval = FLD (i_disp16);
 814     SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
 815     written |= (1 << 2);
 816     TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
 817   }
 818 }
 819
 820   abuf->written = written;
 821   SEM_BRANCH_FINI (vpc);
 822 #undef FLD
 823 }
 824   NEXT (vpc);
 825
 826   CASE (sem, INSN_BL8) : /* bl.s $disp8 */
 827 {
 828   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
 829   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
 830 #define FLD(f) abuf->fields.sfmt_bl8.f
 831   int UNUSED written = 0;
 832   IADDR UNUSED pc = abuf->addr;
 833   SEM_BRANCH_INIT
 834   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
 835
 836 {
 837   {
 838     SI opval = ADDSI (ANDSI (pc, -4), 4);
 839     CPU (h_gr[((UINT) 14)]) = opval;
 840     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
 841   }
 842   {
 843     USI opval = FLD (i_disp8);
 844     SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
 845     TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
 846   }
 847 }
 848
 849   SEM_BRANCH_FINI (vpc);
 850 #undef FLD
 851 }
 852   NEXT (vpc);
 853
 854   CASE (sem, INSN_BL24) : /* bl.l $disp24 */
 855 {
 856   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
 857   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
 858 #define FLD(f) abuf->fields.sfmt_bl24.f
 859   int UNUSED written = 0;
 860   IADDR UNUSED pc = abuf->addr;
 861   SEM_BRANCH_INIT
 862   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
 863
 864 {
 865   {
 866     SI opval = ADDSI (pc, 4);
 867     CPU (h_gr[((UINT) 14)]) = opval;
 868     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
 869   }
 870   {
 871     USI opval = FLD (i_disp24);
 872     SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
 873     TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
 874   }
 875 }
 876
 877   SEM_BRANCH_FINI (vpc);
 878 #undef FLD
 879 }
 880   NEXT (vpc);
 881
 882   CASE (sem, INSN_BNC8) : /* bnc.s $disp8 */
 883 {
 884   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
 885   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
 886 #define FLD(f) abuf->fields.sfmt_bl8.f
 887   int UNUSED written = 0;
 888   IADDR UNUSED pc = abuf->addr;
 889   SEM_BRANCH_INIT
 890   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
 891
 892 if (NOTBI (CPU (h_cond))) {
 893   {
 894     USI opval = FLD (i_disp8);
 895     SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
 896     written |= (1 << 2);
 897     TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
 898   }
 899 }
 900
 901   abuf->written = written;
 902   SEM_BRANCH_FINI (vpc);
 903 #undef FLD
 904 }
 905   NEXT (vpc);
 906
 907   CASE (sem, INSN_BNC24) : /* bnc.l $disp24 */
 908 {
 909   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
 910   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
 911 #define FLD(f) abuf->fields.sfmt_bl24.f
 912   int UNUSED written = 0;
 913   IADDR UNUSED pc = abuf->addr;
 914   SEM_BRANCH_INIT
 915   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
 916
 917 if (NOTBI (CPU (h_cond))) {
 918   {
 919     USI opval = FLD (i_disp24);
 920     SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
 921     written |= (1 << 2);
 922     TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
 923   }
 924 }
 925
 926   abuf->written = written;
 927   SEM_BRANCH_FINI (vpc);
 928 #undef FLD
 929 }
 930   NEXT (vpc);
 931
 932   CASE (sem, INSN_BNE) : /* bne $src1,$src2,$disp16 */
 933 {
 934   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
 935   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
 936 #define FLD(f) abuf->fields.sfmt_beq.f
 937   int UNUSED written = 0;
 938   IADDR UNUSED pc = abuf->addr;
 939   SEM_BRANCH_INIT
 940   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
 941
 942 if (NESI (* FLD (i_src1), * FLD (i_src2))) {
 943   {
 944     USI opval = FLD (i_disp16);
 945     SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
 946     written |= (1 << 3);
 947     TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
 948   }
 949 }
 950
 951   abuf->written = written;
 952   SEM_BRANCH_FINI (vpc);
 953 #undef FLD
 954 }
 955   NEXT (vpc);
 956
 957   CASE (sem, INSN_BRA8) : /* bra.s $disp8 */
 958 {
 959   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
 960   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
 961 #define FLD(f) abuf->fields.sfmt_bl8.f
 962   int UNUSED written = 0;
 963   IADDR UNUSED pc = abuf->addr;
 964   SEM_BRANCH_INIT
 965   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
 966
 967   {
 968     USI opval = FLD (i_disp8);
 969     SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
 970     TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
 971   }
 972
 973   SEM_BRANCH_FINI (vpc);
 974 #undef FLD
 975 }
 976   NEXT (vpc);
 977
 978   CASE (sem, INSN_BRA24) : /* bra.l $disp24 */
 979 {
 980   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
 981   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
 982 #define FLD(f) abuf->fields.sfmt_bl24.f
 983   int UNUSED written = 0;
 984   IADDR UNUSED pc = abuf->addr;
 985   SEM_BRANCH_INIT
 986   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
 987
 988   {
 989     USI opval = FLD (i_disp24);
 990     SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
 991     TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
 992   }
 993
 994   SEM_BRANCH_FINI (vpc);
 995 #undef FLD
 996 }
 997   NEXT (vpc);
 998
 999   CASE (sem, INSN_CMP) : /* cmp $src1,$src2 */
1000 {
1001   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1002   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1003 #define FLD(f) abuf->fields.sfmt_st_plus.f
1004   int UNUSED written = 0;
1005   IADDR UNUSED pc = abuf->addr;
1006   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
1007
1008   {
1009     BI opval = LTSI (* FLD (i_src1), * FLD (i_src2));
1010     CPU (h_cond) = opval;
1011     TRACE_RESULT (current_cpu, abuf, "cond", 'x', opval);
1012   }
1013
1014 #undef FLD
1015 }
1016   NEXT (vpc);
1017
1018   CASE (sem, INSN_CMPI) : /* cmpi $src2,$simm16 */
1019 {
1020   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1021   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1022 #define FLD(f) abuf->fields.sfmt_st_d.f
1023   int UNUSED written = 0;
1024   IADDR UNUSED pc = abuf->addr;
1025   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
1026
1027   {
1028     BI opval = LTSI (* FLD (i_src2), FLD (f_simm16));
1029     CPU (h_cond) = opval;
1030     TRACE_RESULT (current_cpu, abuf, "cond", 'x', opval);
1031   }
1032
1033 #undef FLD
1034 }
1035   NEXT (vpc);
1036
1037   CASE (sem, INSN_CMPU) : /* cmpu $src1,$src2 */
1038 {
1039   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1040   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1041 #define FLD(f) abuf->fields.sfmt_st_plus.f
1042   int UNUSED written = 0;
1043   IADDR UNUSED pc = abuf->addr;
1044   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
1045
1046   {
1047     BI opval = LTUSI (* FLD (i_src1), * FLD (i_src2));
1048     CPU (h_cond) = opval;
1049     TRACE_RESULT (current_cpu, abuf, "cond", 'x', opval);
1050   }
1051
1052 #undef FLD
1053 }
1054   NEXT (vpc);
1055
1056   CASE (sem, INSN_CMPUI) : /* cmpui $src2,$simm16 */
1057 {
1058   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1059   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1060 #define FLD(f) abuf->fields.sfmt_st_d.f
1061   int UNUSED written = 0;
1062   IADDR UNUSED pc = abuf->addr;
1063   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
1064
1065   {
1066     BI opval = LTUSI (* FLD (i_src2), FLD (f_simm16));
1067     CPU (h_cond) = opval;
1068     TRACE_RESULT (current_cpu, abuf, "cond", 'x', opval);
1069   }
1070
1071 #undef FLD
1072 }
1073   NEXT (vpc);
1074
1075   CASE (sem, INSN_DIV) : /* div $dr,$sr */
1076 {
1077   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1078   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1079 #define FLD(f) abuf->fields.sfmt_add.f
1080   int UNUSED written = 0;
1081   IADDR UNUSED pc = abuf->addr;
1082   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
1083
1084 if (NESI (* FLD (i_sr), 0)) {
1085   {
1086     SI opval = DIVSI (* FLD (i_dr), * FLD (i_sr));
1087     * FLD (i_dr) = opval;
1088     written |= (1 << 2);
1089     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
1090   }
1091 }
1092
1093   abuf->written = written;
1094 #undef FLD
1095 }
1096   NEXT (vpc);
1097
1098   CASE (sem, INSN_DIVU) : /* divu $dr,$sr */
1099 {
1100   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1101   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1102 #define FLD(f) abuf->fields.sfmt_add.f
1103   int UNUSED written = 0;
1104   IADDR UNUSED pc = abuf->addr;
1105   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
1106
1107 if (NESI (* FLD (i_sr), 0)) {
1108   {
1109     SI opval = UDIVSI (* FLD (i_dr), * FLD (i_sr));
1110     * FLD (i_dr) = opval;
1111     written |= (1 << 2);
1112     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
1113   }
1114 }
1115
1116   abuf->written = written;
1117 #undef FLD
1118 }
1119   NEXT (vpc);
1120
1121   CASE (sem, INSN_REM) : /* rem $dr,$sr */
1122 {
1123   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1124   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1125 #define FLD(f) abuf->fields.sfmt_add.f
1126   int UNUSED written = 0;
1127   IADDR UNUSED pc = abuf->addr;
1128   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
1129
1130 if (NESI (* FLD (i_sr), 0)) {
1131   {
1132     SI opval = MODSI (* FLD (i_dr), * FLD (i_sr));
1133     * FLD (i_dr) = opval;
1134     written |= (1 << 2);
1135     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
1136   }
1137 }
1138
1139   abuf->written = written;
1140 #undef FLD
1141 }
1142   NEXT (vpc);
1143
1144   CASE (sem, INSN_REMU) : /* remu $dr,$sr */
1145 {
1146   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1147   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1148 #define FLD(f) abuf->fields.sfmt_add.f
1149   int UNUSED written = 0;
1150   IADDR UNUSED pc = abuf->addr;
1151   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
1152
1153 if (NESI (* FLD (i_sr), 0)) {
1154   {
1155     SI opval = UMODSI (* FLD (i_dr), * FLD (i_sr));
1156     * FLD (i_dr) = opval;
1157     written |= (1 << 2);
1158     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
1159   }
1160 }
1161
1162   abuf->written = written;
1163 #undef FLD
1164 }
1165   NEXT (vpc);
1166
1167   CASE (sem, INSN_JL) : /* jl $sr */
1168 {
1169   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1170   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1171 #define FLD(f) abuf->fields.sfmt_jl.f
1172   int UNUSED written = 0;
1173   IADDR UNUSED pc = abuf->addr;
1174   SEM_BRANCH_INIT
1175   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
1176
1177 {
1178   SI temp0;USI temp1;
1179   temp0 = ADDSI (ANDSI (pc, -4), 4);
1180   temp1 = ANDSI (* FLD (i_sr), -4);
1181   {
1182     SI opval = temp0;
1183     CPU (h_gr[((UINT) 14)]) = opval;
1184     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
1185   }
1186   {
1187     USI opval = temp1;
1188     SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
1189     TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
1190   }
1191 }
1192
1193   SEM_BRANCH_FINI (vpc);
1194 #undef FLD
1195 }
1196   NEXT (vpc);
1197
1198   CASE (sem, INSN_JMP) : /* jmp $sr */
1199 {
1200   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1201   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1202 #define FLD(f) abuf->fields.sfmt_jl.f
1203   int UNUSED written = 0;
1204   IADDR UNUSED pc = abuf->addr;
1205   SEM_BRANCH_INIT
1206   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
1207
1208   {
1209     USI opval = ANDSI (* FLD (i_sr), -4);
1210     SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
1211     TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
1212   }
1213
1214   SEM_BRANCH_FINI (vpc);
1215 #undef FLD
1216 }
1217   NEXT (vpc);
1218
1219   CASE (sem, INSN_LD) : /* ld $dr,@$sr */
1220 {
1221   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1222   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1223 #define FLD(f) abuf->fields.sfmt_ld_plus.f
1224   int UNUSED written = 0;
1225   IADDR UNUSED pc = abuf->addr;
1226   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
1227
1228   {
1229     SI opval = GETMEMSI (current_cpu, pc, * FLD (i_sr));
1230     * FLD (i_dr) = opval;
1231     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
1232   }
1233
1234 #undef FLD
1235 }
1236   NEXT (vpc);
1237
1238   CASE (sem, INSN_LD_D) : /* ld $dr,@($slo16,$sr) */
1239 {
1240   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1241   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1242 #define FLD(f) abuf->fields.sfmt_add3.f
1243   int UNUSED written = 0;
1244   IADDR UNUSED pc = abuf->addr;
1245   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
1246
1247   {
1248     SI opval = GETMEMSI (current_cpu, pc, ADDSI (* FLD (i_sr), FLD (f_simm16)));
1249     * FLD (i_dr) = opval;
1250     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
1251   }
1252
1253 #undef FLD
1254 }
1255   NEXT (vpc);
1256
1257   CASE (sem, INSN_LDB) : /* ldb $dr,@$sr */
1258 {
1259   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1260   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1261 #define FLD(f) abuf->fields.sfmt_ld_plus.f
1262   int UNUSED written = 0;
1263   IADDR UNUSED pc = abuf->addr;
1264   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
1265
1266   {
1267     SI opval = EXTQISI (GETMEMQI (current_cpu, pc, * FLD (i_sr)));
1268     * FLD (i_dr) = opval;
1269     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
1270   }
1271
1272 #undef FLD
1273 }
1274   NEXT (vpc);
1275
1276   CASE (sem, INSN_LDB_D) : /* ldb $dr,@($slo16,$sr) */
1277 {
1278   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1279   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1280 #define FLD(f) abuf->fields.sfmt_add3.f
1281   int UNUSED written = 0;
1282   IADDR UNUSED pc = abuf->addr;
1283   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
1284
1285   {
1286     SI opval = EXTQISI (GETMEMQI (current_cpu, pc, ADDSI (* FLD (i_sr), FLD (f_simm16))));
1287     * FLD (i_dr) = opval;
1288     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
1289   }
1290
1291 #undef FLD
1292 }
1293   NEXT (vpc);
1294
1295   CASE (sem, INSN_LDH) : /* ldh $dr,@$sr */
1296 {
1297   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1298   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1299 #define FLD(f) abuf->fields.sfmt_ld_plus.f
1300   int UNUSED written = 0;
1301   IADDR UNUSED pc = abuf->addr;
1302   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
1303
1304   {
1305     SI opval = EXTHISI (GETMEMHI (current_cpu, pc, * FLD (i_sr)));
1306     * FLD (i_dr) = opval;
1307     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
1308   }
1309
1310 #undef FLD
1311 }
1312   NEXT (vpc);
1313
1314   CASE (sem, INSN_LDH_D) : /* ldh $dr,@($slo16,$sr) */
1315 {
1316   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1317   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1318 #define FLD(f) abuf->fields.sfmt_add3.f
1319   int UNUSED written = 0;
1320   IADDR UNUSED pc = abuf->addr;
1321   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
1322
1323   {
1324     SI opval = EXTHISI (GETMEMHI (current_cpu, pc, ADDSI (* FLD (i_sr), FLD (f_simm16))));
1325     * FLD (i_dr) = opval;
1326     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
1327   }
1328
1329 #undef FLD
1330 }
1331   NEXT (vpc);
1332
1333   CASE (sem, INSN_LDUB) : /* ldub $dr,@$sr */
1334 {
1335   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1336   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1337 #define FLD(f) abuf->fields.sfmt_ld_plus.f
1338   int UNUSED written = 0;
1339   IADDR UNUSED pc = abuf->addr;
1340   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
1341
1342   {
1343     SI opval = ZEXTQISI (GETMEMQI (current_cpu, pc, * FLD (i_sr)));
1344     * FLD (i_dr) = opval;
1345     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
1346   }
1347
1348 #undef FLD
1349 }
1350   NEXT (vpc);
1351
1352   CASE (sem, INSN_LDUB_D) : /* ldub $dr,@($slo16,$sr) */
1353 {
1354   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1355   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1356 #define FLD(f) abuf->fields.sfmt_add3.f
1357   int UNUSED written = 0;
1358   IADDR UNUSED pc = abuf->addr;
1359   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
1360
1361   {
1362     SI opval = ZEXTQISI (GETMEMQI (current_cpu, pc, ADDSI (* FLD (i_sr), FLD (f_simm16))));
1363     * FLD (i_dr) = opval;
1364     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
1365   }
1366
1367 #undef FLD
1368 }
1369   NEXT (vpc);
1370
1371   CASE (sem, INSN_LDUH) : /* lduh $dr,@$sr */
1372 {
1373   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1374   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1375 #define FLD(f) abuf->fields.sfmt_ld_plus.f
1376   int UNUSED written = 0;
1377   IADDR UNUSED pc = abuf->addr;
1378   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
1379
1380   {
1381     SI opval = ZEXTHISI (GETMEMHI (current_cpu, pc, * FLD (i_sr)));
1382     * FLD (i_dr) = opval;
1383     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
1384   }
1385
1386 #undef FLD
1387 }
1388   NEXT (vpc);
1389
1390   CASE (sem, INSN_LDUH_D) : /* lduh $dr,@($slo16,$sr) */
1391 {
1392   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1393   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1394 #define FLD(f) abuf->fields.sfmt_add3.f
1395   int UNUSED written = 0;
1396   IADDR UNUSED pc = abuf->addr;
1397   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
1398
1399   {
1400     SI opval = ZEXTHISI (GETMEMHI (current_cpu, pc, ADDSI (* FLD (i_sr), FLD (f_simm16))));
1401     * FLD (i_dr) = opval;
1402     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
1403   }
1404
1405 #undef FLD
1406 }
1407   NEXT (vpc);
1408
1409   CASE (sem, INSN_LD_PLUS) : /* ld $dr,@$sr+ */
1410 {
1411   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1412   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1413 #define FLD(f) abuf->fields.sfmt_ld_plus.f
1414   int UNUSED written = 0;
1415   IADDR UNUSED pc = abuf->addr;
1416   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
1417
1418 {
1419   SI temp0;SI temp1;
1420   temp0 = GETMEMSI (current_cpu, pc, * FLD (i_sr));
1421   temp1 = ADDSI (* FLD (i_sr), 4);
1422   {
1423     SI opval = temp0;
1424     * FLD (i_dr) = opval;
1425     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
1426   }
1427   {
1428     SI opval = temp1;
1429     * FLD (i_sr) = opval;
1430     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
1431   }
1432 }
1433
1434 #undef FLD
1435 }
1436   NEXT (vpc);
1437
1438   CASE (sem, INSN_LD24) : /* ld24 $dr,$uimm24 */
1439 {
1440   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1441   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1442 #define FLD(f) abuf->fields.sfmt_ld24.f
1443   int UNUSED written = 0;
1444   IADDR UNUSED pc = abuf->addr;
1445   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
1446
1447   {
1448     SI opval = FLD (i_uimm24);
1449     * FLD (i_dr) = opval;
1450     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
1451   }
1452
1453 #undef FLD
1454 }
1455   NEXT (vpc);
1456
1457   CASE (sem, INSN_LDI8) : /* ldi8 $dr,$simm8 */
1458 {
1459   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1460   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1461 #define FLD(f) abuf->fields.sfmt_addi.f
1462   int UNUSED written = 0;
1463   IADDR UNUSED pc = abuf->addr;
1464   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
1465
1466   {
1467     SI opval = FLD (f_simm8);
1468     * FLD (i_dr) = opval;
1469     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
1470   }
1471
1472 #undef FLD
1473 }
1474   NEXT (vpc);
1475
1476   CASE (sem, INSN_LDI16) : /* ldi16 $dr,$hash$slo16 */
1477 {
1478   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1479   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1480 #define FLD(f) abuf->fields.sfmt_add3.f
1481   int UNUSED written = 0;
1482   IADDR UNUSED pc = abuf->addr;
1483   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
1484
1485   {
1486     SI opval = FLD (f_simm16);
1487     * FLD (i_dr) = opval;
1488     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
1489   }
1490
1491 #undef FLD
1492 }
1493   NEXT (vpc);
1494
1495   CASE (sem, INSN_LOCK) : /* lock $dr,@$sr */
1496 {
1497   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1498   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1499 #define FLD(f) abuf->fields.sfmt_ld_plus.f
1500   int UNUSED written = 0;
1501   IADDR UNUSED pc = abuf->addr;
1502   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
1503
1504 {
1505   {
1506     BI opval = 1;
1507     CPU (h_lock) = opval;
1508     TRACE_RESULT (current_cpu, abuf, "lock", 'x', opval);
1509   }
1510   {
1511     SI opval = GETMEMSI (current_cpu, pc, * FLD (i_sr));
1512     * FLD (i_dr) = opval;
1513     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
1514   }
1515 }
1516
1517 #undef FLD
1518 }
1519   NEXT (vpc);
1520
1521   CASE (sem, INSN_MACHI) : /* machi $src1,$src2 */
1522 {
1523   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1524   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1525 #define FLD(f) abuf->fields.sfmt_st_plus.f
1526   int UNUSED written = 0;
1527   IADDR UNUSED pc = abuf->addr;
1528   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
1529
1530   {
1531     DI opval = SRADI (SLLDI (ADDDI (GET_H_ACCUM (), MULDI (EXTSIDI (ANDSI (* FLD (i_src1), 0xffff0000)), EXTHIDI (TRUNCSIHI (SRASI (* FLD (i_src2), 16))))), 8), 8);
1532     SET_H_ACCUM (opval);
1533     TRACE_RESULT (current_cpu, abuf, "accum", 'D', opval);
1534   }
1535
1536 #undef FLD
1537 }
1538   NEXT (vpc);
1539
1540   CASE (sem, INSN_MACLO) : /* maclo $src1,$src2 */
1541 {
1542   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1543   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1544 #define FLD(f) abuf->fields.sfmt_st_plus.f
1545   int UNUSED written = 0;
1546   IADDR UNUSED pc = abuf->addr;
1547   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
1548
1549   {
1550     DI opval = SRADI (SLLDI (ADDDI (GET_H_ACCUM (), MULDI (EXTSIDI (SLLSI (* FLD (i_src1), 16)), EXTHIDI (TRUNCSIHI (* FLD (i_src2))))), 8), 8);
1551     SET_H_ACCUM (opval);
1552     TRACE_RESULT (current_cpu, abuf, "accum", 'D', opval);
1553   }
1554
1555 #undef FLD
1556 }
1557   NEXT (vpc);
1558
1559   CASE (sem, INSN_MACWHI) : /* macwhi $src1,$src2 */
1560 {
1561   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1562   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1563 #define FLD(f) abuf->fields.sfmt_st_plus.f
1564   int UNUSED written = 0;
1565   IADDR UNUSED pc = abuf->addr;
1566   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
1567
1568   {
1569     DI opval = SRADI (SLLDI (ADDDI (GET_H_ACCUM (), MULDI (EXTSIDI (* FLD (i_src1)), EXTHIDI (TRUNCSIHI (SRASI (* FLD (i_src2), 16))))), 8), 8);
1570     SET_H_ACCUM (opval);
1571     TRACE_RESULT (current_cpu, abuf, "accum", 'D', opval);
1572   }
1573
1574 #undef FLD
1575 }
1576   NEXT (vpc);
1577
1578   CASE (sem, INSN_MACWLO) : /* macwlo $src1,$src2 */
1579 {
1580   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1581   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1582 #define FLD(f) abuf->fields.sfmt_st_plus.f
1583   int UNUSED written = 0;
1584   IADDR UNUSED pc = abuf->addr;
1585   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
1586
1587   {
1588     DI opval = SRADI (SLLDI (ADDDI (GET_H_ACCUM (), MULDI (EXTSIDI (* FLD (i_src1)), EXTHIDI (TRUNCSIHI (* FLD (i_src2))))), 8), 8);
1589     SET_H_ACCUM (opval);
1590     TRACE_RESULT (current_cpu, abuf, "accum", 'D', opval);
1591   }
1592
1593 #undef FLD
1594 }
1595   NEXT (vpc);
1596
1597   CASE (sem, INSN_MUL) : /* mul $dr,$sr */
1598 {
1599   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1600   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1601 #define FLD(f) abuf->fields.sfmt_add.f
1602   int UNUSED written = 0;
1603   IADDR UNUSED pc = abuf->addr;
1604   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
1605
1606   {
1607     SI opval = MULSI (* FLD (i_dr), * FLD (i_sr));
1608     * FLD (i_dr) = opval;
1609     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
1610   }
1611
1612 #undef FLD
1613 }
1614   NEXT (vpc);
1615
1616   CASE (sem, INSN_MULHI) : /* mulhi $src1,$src2 */
1617 {
1618   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1619   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1620 #define FLD(f) abuf->fields.sfmt_st_plus.f
1621   int UNUSED written = 0;
1622   IADDR UNUSED pc = abuf->addr;
1623   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
1624
1625   {
1626     DI opval = SRADI (SLLDI (MULDI (EXTSIDI (ANDSI (* FLD (i_src1), 0xffff0000)), EXTHIDI (TRUNCSIHI (SRASI (* FLD (i_src2), 16)))), 16), 16);
1627     SET_H_ACCUM (opval);
1628     TRACE_RESULT (current_cpu, abuf, "accum", 'D', opval);
1629   }
1630
1631 #undef FLD
1632 }
1633   NEXT (vpc);
1634
1635   CASE (sem, INSN_MULLO) : /* mullo $src1,$src2 */
1636 {
1637   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1638   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1639 #define FLD(f) abuf->fields.sfmt_st_plus.f
1640   int UNUSED written = 0;
1641   IADDR UNUSED pc = abuf->addr;
1642   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
1643
1644   {
1645     DI opval = SRADI (SLLDI (MULDI (EXTSIDI (SLLSI (* FLD (i_src1), 16)), EXTHIDI (TRUNCSIHI (* FLD (i_src2)))), 16), 16);
1646     SET_H_ACCUM (opval);
1647     TRACE_RESULT (current_cpu, abuf, "accum", 'D', opval);
1648   }
1649
1650 #undef FLD
1651 }
1652   NEXT (vpc);
1653
1654   CASE (sem, INSN_MULWHI) : /* mulwhi $src1,$src2 */
1655 {
1656   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1657   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1658 #define FLD(f) abuf->fields.sfmt_st_plus.f
1659   int UNUSED written = 0;
1660   IADDR UNUSED pc = abuf->addr;
1661   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
1662
1663   {
1664     DI opval = SRADI (SLLDI (MULDI (EXTSIDI (* FLD (i_src1)), EXTHIDI (TRUNCSIHI (SRASI (* FLD (i_src2), 16)))), 8), 8);
1665     SET_H_ACCUM (opval);
1666     TRACE_RESULT (current_cpu, abuf, "accum", 'D', opval);
1667   }
1668
1669 #undef FLD
1670 }
1671   NEXT (vpc);
1672
1673   CASE (sem, INSN_MULWLO) : /* mulwlo $src1,$src2 */
1674 {
1675   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1676   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1677 #define FLD(f) abuf->fields.sfmt_st_plus.f
1678   int UNUSED written = 0;
1679   IADDR UNUSED pc = abuf->addr;
1680   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
1681
1682   {
1683     DI opval = SRADI (SLLDI (MULDI (EXTSIDI (* FLD (i_src1)), EXTHIDI (TRUNCSIHI (* FLD (i_src2)))), 8), 8);
1684     SET_H_ACCUM (opval);
1685     TRACE_RESULT (current_cpu, abuf, "accum", 'D', opval);
1686   }
1687
1688 #undef FLD
1689 }
1690   NEXT (vpc);
1691
1692   CASE (sem, INSN_MV) : /* mv $dr,$sr */
1693 {
1694   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1695   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1696 #define FLD(f) abuf->fields.sfmt_ld_plus.f
1697   int UNUSED written = 0;
1698   IADDR UNUSED pc = abuf->addr;
1699   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
1700
1701   {
1702     SI opval = * FLD (i_sr);
1703     * FLD (i_dr) = opval;
1704     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
1705   }
1706
1707 #undef FLD
1708 }
1709   NEXT (vpc);
1710
1711   CASE (sem, INSN_MVFACHI) : /* mvfachi $dr */
1712 {
1713   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1714   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1715 #define FLD(f) abuf->fields.sfmt_seth.f
1716   int UNUSED written = 0;
1717   IADDR UNUSED pc = abuf->addr;
1718   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
1719
1720   {
1721     SI opval = TRUNCDISI (SRADI (GET_H_ACCUM (), 32));
1722     * FLD (i_dr) = opval;
1723     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
1724   }
1725
1726 #undef FLD
1727 }
1728   NEXT (vpc);
1729
1730   CASE (sem, INSN_MVFACLO) : /* mvfaclo $dr */
1731 {
1732   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1733   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1734 #define FLD(f) abuf->fields.sfmt_seth.f
1735   int UNUSED written = 0;
1736   IADDR UNUSED pc = abuf->addr;
1737   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
1738
1739   {
1740     SI opval = TRUNCDISI (GET_H_ACCUM ());
1741     * FLD (i_dr) = opval;
1742     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
1743   }
1744
1745 #undef FLD
1746 }
1747   NEXT (vpc);
1748
1749   CASE (sem, INSN_MVFACMI) : /* mvfacmi $dr */
1750 {
1751   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1752   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1753 #define FLD(f) abuf->fields.sfmt_seth.f
1754   int UNUSED written = 0;
1755   IADDR UNUSED pc = abuf->addr;
1756   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
1757
1758   {
1759     SI opval = TRUNCDISI (SRADI (GET_H_ACCUM (), 16));
1760     * FLD (i_dr) = opval;
1761     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
1762   }
1763
1764 #undef FLD
1765 }
1766   NEXT (vpc);
1767
1768   CASE (sem, INSN_MVFC) : /* mvfc $dr,$scr */
1769 {
1770   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1771   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1772 #define FLD(f) abuf->fields.sfmt_ld_plus.f
1773   int UNUSED written = 0;
1774   IADDR UNUSED pc = abuf->addr;
1775   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
1776
1777   {
1778     SI opval = GET_H_CR (FLD (f_r2));
1779     * FLD (i_dr) = opval;
1780     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
1781   }
1782
1783 #undef FLD
1784 }
1785   NEXT (vpc);
1786
1787   CASE (sem, INSN_MVTACHI) : /* mvtachi $src1 */
1788 {
1789   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1790   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1791 #define FLD(f) abuf->fields.sfmt_st_plus.f
1792   int UNUSED written = 0;
1793   IADDR UNUSED pc = abuf->addr;
1794   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
1795
1796   {
1797     DI opval = ORDI (ANDDI (GET_H_ACCUM (), MAKEDI (0, 0xffffffff)), SLLDI (EXTSIDI (* FLD (i_src1)), 32));
1798     SET_H_ACCUM (opval);
1799     TRACE_RESULT (current_cpu, abuf, "accum", 'D', opval);
1800   }
1801
1802 #undef FLD
1803 }
1804   NEXT (vpc);
1805
1806   CASE (sem, INSN_MVTACLO) : /* mvtaclo $src1 */
1807 {
1808   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1809   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1810 #define FLD(f) abuf->fields.sfmt_st_plus.f
1811   int UNUSED written = 0;
1812   IADDR UNUSED pc = abuf->addr;
1813   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
1814
1815   {
1816     DI opval = ORDI (ANDDI (GET_H_ACCUM (), MAKEDI (0xffffffff, 0)), ZEXTSIDI (* FLD (i_src1)));
1817     SET_H_ACCUM (opval);
1818     TRACE_RESULT (current_cpu, abuf, "accum", 'D', opval);
1819   }
1820
1821 #undef FLD
1822 }
1823   NEXT (vpc);
1824
1825   CASE (sem, INSN_MVTC) : /* mvtc $sr,$dcr */
1826 {
1827   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1828   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1829 #define FLD(f) abuf->fields.sfmt_ld_plus.f
1830   int UNUSED written = 0;
1831   IADDR UNUSED pc = abuf->addr;
1832   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
1833
1834   {
1835     USI opval = * FLD (i_sr);
1836     SET_H_CR (FLD (f_r1), opval);
1837     TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
1838   }
1839
1840 #undef FLD
1841 }
1842   NEXT (vpc);
1843
1844   CASE (sem, INSN_NEG) : /* neg $dr,$sr */
1845 {
1846   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1847   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1848 #define FLD(f) abuf->fields.sfmt_ld_plus.f
1849   int UNUSED written = 0;
1850   IADDR UNUSED pc = abuf->addr;
1851   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
1852
1853   {
1854     SI opval = NEGSI (* FLD (i_sr));
1855     * FLD (i_dr) = opval;
1856     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
1857   }
1858
1859 #undef FLD
1860 }
1861   NEXT (vpc);
1862
1863   CASE (sem, INSN_NOP) : /* nop */
1864 {
1865   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1866   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1867 #define FLD(f) abuf->fields.sfmt_empty.f
1868   int UNUSED written = 0;
1869   IADDR UNUSED pc = abuf->addr;
1870   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
1871
1872 PROFILE_COUNT_FILLNOPS (current_cpu, abuf->addr);
1873
1874 #undef FLD
1875 }
1876   NEXT (vpc);
1877
1878   CASE (sem, INSN_NOT) : /* not $dr,$sr */
1879 {
1880   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1881   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1882 #define FLD(f) abuf->fields.sfmt_ld_plus.f
1883   int UNUSED written = 0;
1884   IADDR UNUSED pc = abuf->addr;
1885   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
1886
1887   {
1888     SI opval = INVSI (* FLD (i_sr));
1889     * FLD (i_dr) = opval;
1890     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
1891   }
1892
1893 #undef FLD
1894 }
1895   NEXT (vpc);
1896
1897   CASE (sem, INSN_RAC) : /* rac */
1898 {
1899   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1900   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1901 #define FLD(f) abuf->fields.sfmt_empty.f
1902   int UNUSED written = 0;
1903   IADDR UNUSED pc = abuf->addr;
1904   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
1905
1906 {
1907   DI tmp_tmp1;
1908   tmp_tmp1 = SLLDI (GET_H_ACCUM (), 1);
1909   tmp_tmp1 = ADDDI (tmp_tmp1, MAKEDI (0, 32768));
1910   {
1911     DI opval = (GTDI (tmp_tmp1, MAKEDI (32767, 0xffff0000))) ? (MAKEDI (32767, 0xffff0000)) : (LTDI (tmp_tmp1, MAKEDI (0xffff8000, 0))) ? (MAKEDI (0xffff8000, 0)) : (ANDDI (tmp_tmp1, MAKEDI (0xffffffff, 0xffff0000)));
1912     SET_H_ACCUM (opval);
1913     TRACE_RESULT (current_cpu, abuf, "accum", 'D', opval);
1914   }
1915 }
1916
1917 #undef FLD
1918 }
1919   NEXT (vpc);
1920
1921   CASE (sem, INSN_RACH) : /* rach */
1922 {
1923   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1924   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1925 #define FLD(f) abuf->fields.sfmt_empty.f
1926   int UNUSED written = 0;
1927   IADDR UNUSED pc = abuf->addr;
1928   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
1929
1930 {
1931   DI tmp_tmp1;
1932   tmp_tmp1 = ANDDI (GET_H_ACCUM (), MAKEDI (16777215, 0xffffffff));
1933 if (ANDIF (GEDI (tmp_tmp1, MAKEDI (16383, 0x80000000)), LEDI (tmp_tmp1, MAKEDI (8388607, 0xffffffff)))) {
1934   tmp_tmp1 = MAKEDI (16383, 0x80000000);
1935 } else {
1936 if (ANDIF (GEDI (tmp_tmp1, MAKEDI (8388608, 0)), LEDI (tmp_tmp1, MAKEDI (16760832, 0)))) {
1937   tmp_tmp1 = MAKEDI (16760832, 0);
1938 } else {
1939   tmp_tmp1 = ANDDI (ADDDI (GET_H_ACCUM (), MAKEDI (0, 1073741824)), MAKEDI (0xffffffff, 0x80000000));
1940 }
1941 }
1942   tmp_tmp1 = SLLDI (tmp_tmp1, 1);
1943   {
1944     DI opval = SRADI (SLLDI (tmp_tmp1, 7), 7);
1945     SET_H_ACCUM (opval);
1946     TRACE_RESULT (current_cpu, abuf, "accum", 'D', opval);
1947   }
1948 }
1949
1950 #undef FLD
1951 }
1952   NEXT (vpc);
1953
1954   CASE (sem, INSN_RTE) : /* rte */
1955 {
1956   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1957   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1958 #define FLD(f) abuf->fields.sfmt_empty.f
1959   int UNUSED written = 0;
1960   IADDR UNUSED pc = abuf->addr;
1961   SEM_BRANCH_INIT
1962   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
1963
1964 {
1965   {
1966     USI opval = ANDSI (GET_H_CR (((UINT) 6)), -4);
1967     SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
1968     TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
1969   }
1970   {
1971     USI opval = GET_H_CR (((UINT) 14));
1972     SET_H_CR (((UINT) 6), opval);
1973     TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
1974   }
1975   {
1976     UQI opval = CPU (h_bpsw);
1977     SET_H_PSW (opval);
1978     TRACE_RESULT (current_cpu, abuf, "psw", 'x', opval);
1979   }
1980   {
1981     UQI opval = CPU (h_bbpsw);
1982     CPU (h_bpsw) = opval;
1983     TRACE_RESULT (current_cpu, abuf, "bpsw", 'x', opval);
1984   }
1985 }
1986
1987   SEM_BRANCH_FINI (vpc);
1988 #undef FLD
1989 }
1990   NEXT (vpc);
1991
1992   CASE (sem, INSN_SETH) : /* seth $dr,$hash$hi16 */
1993 {
1994   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1995   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1996 #define FLD(f) abuf->fields.sfmt_seth.f
1997   int UNUSED written = 0;
1998   IADDR UNUSED pc = abuf->addr;
1999   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
2000
2001   {
2002     SI opval = SLLSI (FLD (f_hi16), 16);
2003     * FLD (i_dr) = opval;
2004     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
2005   }
2006
2007 #undef FLD
2008 }
2009   NEXT (vpc);
2010
2011   CASE (sem, INSN_SLL) : /* sll $dr,$sr */
2012 {
2013   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2014   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2015 #define FLD(f) abuf->fields.sfmt_add.f
2016   int UNUSED written = 0;
2017   IADDR UNUSED pc = abuf->addr;
2018   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
2019
2020   {
2021     SI opval = SLLSI (* FLD (i_dr), ANDSI (* FLD (i_sr), 31));
2022     * FLD (i_dr) = opval;
2023     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
2024   }
2025
2026 #undef FLD
2027 }
2028   NEXT (vpc);
2029
2030   CASE (sem, INSN_SLL3) : /* sll3 $dr,$sr,$simm16 */
2031 {
2032   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2033   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2034 #define FLD(f) abuf->fields.sfmt_add3.f
2035   int UNUSED written = 0;
2036   IADDR UNUSED pc = abuf->addr;
2037   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
2038
2039   {
2040     SI opval = SLLSI (* FLD (i_sr), ANDSI (FLD (f_simm16), 31));
2041     * FLD (i_dr) = opval;
2042     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
2043   }
2044
2045 #undef FLD
2046 }
2047   NEXT (vpc);
2048
2049   CASE (sem, INSN_SLLI) : /* slli $dr,$uimm5 */
2050 {
2051   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2052   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2053 #define FLD(f) abuf->fields.sfmt_slli.f
2054   int UNUSED written = 0;
2055   IADDR UNUSED pc = abuf->addr;
2056   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
2057
2058   {
2059     SI opval = SLLSI (* FLD (i_dr), FLD (f_uimm5));
2060     * FLD (i_dr) = opval;
2061     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
2062   }
2063
2064 #undef FLD
2065 }
2066   NEXT (vpc);
2067
2068   CASE (sem, INSN_SRA) : /* sra $dr,$sr */
2069 {
2070   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2071   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2072 #define FLD(f) abuf->fields.sfmt_add.f
2073   int UNUSED written = 0;
2074   IADDR UNUSED pc = abuf->addr;
2075   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
2076
2077   {
2078     SI opval = SRASI (* FLD (i_dr), ANDSI (* FLD (i_sr), 31));
2079     * FLD (i_dr) = opval;
2080     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
2081   }
2082
2083 #undef FLD
2084 }
2085   NEXT (vpc);
2086
2087   CASE (sem, INSN_SRA3) : /* sra3 $dr,$sr,$simm16 */
2088 {
2089   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2090   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2091 #define FLD(f) abuf->fields.sfmt_add3.f
2092   int UNUSED written = 0;
2093   IADDR UNUSED pc = abuf->addr;
2094   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
2095
2096   {
2097     SI opval = SRASI (* FLD (i_sr), ANDSI (FLD (f_simm16), 31));
2098     * FLD (i_dr) = opval;
2099     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
2100   }
2101
2102 #undef FLD
2103 }
2104   NEXT (vpc);
2105
2106   CASE (sem, INSN_SRAI) : /* srai $dr,$uimm5 */
2107 {
2108   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2109   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2110 #define FLD(f) abuf->fields.sfmt_slli.f
2111   int UNUSED written = 0;
2112   IADDR UNUSED pc = abuf->addr;
2113   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
2114
2115   {
2116     SI opval = SRASI (* FLD (i_dr), FLD (f_uimm5));
2117     * FLD (i_dr) = opval;
2118     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
2119   }
2120
2121 #undef FLD
2122 }
2123   NEXT (vpc);
2124
2125   CASE (sem, INSN_SRL) : /* srl $dr,$sr */
2126 {
2127   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2128   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2129 #define FLD(f) abuf->fields.sfmt_add.f
2130   int UNUSED written = 0;
2131   IADDR UNUSED pc = abuf->addr;
2132   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
2133
2134   {
2135     SI opval = SRLSI (* FLD (i_dr), ANDSI (* FLD (i_sr), 31));
2136     * FLD (i_dr) = opval;
2137     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
2138   }
2139
2140 #undef FLD
2141 }
2142   NEXT (vpc);
2143
2144   CASE (sem, INSN_SRL3) : /* srl3 $dr,$sr,$simm16 */
2145 {
2146   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2147   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2148 #define FLD(f) abuf->fields.sfmt_add3.f
2149   int UNUSED written = 0;
2150   IADDR UNUSED pc = abuf->addr;
2151   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
2152
2153   {
2154     SI opval = SRLSI (* FLD (i_sr), ANDSI (FLD (f_simm16), 31));
2155     * FLD (i_dr) = opval;
2156     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
2157   }
2158
2159 #undef FLD
2160 }
2161   NEXT (vpc);
2162
2163   CASE (sem, INSN_SRLI) : /* srli $dr,$uimm5 */
2164 {
2165   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2166   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2167 #define FLD(f) abuf->fields.sfmt_slli.f
2168   int UNUSED written = 0;
2169   IADDR UNUSED pc = abuf->addr;
2170   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
2171
2172   {
2173     SI opval = SRLSI (* FLD (i_dr), FLD (f_uimm5));
2174     * FLD (i_dr) = opval;
2175     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
2176   }
2177
2178 #undef FLD
2179 }
2180   NEXT (vpc);
2181
2182   CASE (sem, INSN_ST) : /* st $src1,@$src2 */
2183 {
2184   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2185   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2186 #define FLD(f) abuf->fields.sfmt_st_plus.f
2187   int UNUSED written = 0;
2188   IADDR UNUSED pc = abuf->addr;
2189   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
2190
2191   {
2192     SI opval = * FLD (i_src1);
2193     SETMEMSI (current_cpu, pc, * FLD (i_src2), opval);
2194     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
2195   }
2196
2197 #undef FLD
2198 }
2199   NEXT (vpc);
2200
2201   CASE (sem, INSN_ST_D) : /* st $src1,@($slo16,$src2) */
2202 {
2203   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2204   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2205 #define FLD(f) abuf->fields.sfmt_st_d.f
2206   int UNUSED written = 0;
2207   IADDR UNUSED pc = abuf->addr;
2208   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
2209
2210   {
2211     SI opval = * FLD (i_src1);
2212     SETMEMSI (current_cpu, pc, ADDSI (* FLD (i_src2), FLD (f_simm16)), opval);
2213     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
2214   }
2215
2216 #undef FLD
2217 }
2218   NEXT (vpc);
2219
2220   CASE (sem, INSN_STB) : /* stb $src1,@$src2 */
2221 {
2222   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2223   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2224 #define FLD(f) abuf->fields.sfmt_st_plus.f
2225   int UNUSED written = 0;
2226   IADDR UNUSED pc = abuf->addr;
2227   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
2228
2229   {
2230     QI opval = * FLD (i_src1);
2231     SETMEMQI (current_cpu, pc, * FLD (i_src2), opval);
2232     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
2233   }
2234
2235 #undef FLD
2236 }
2237   NEXT (vpc);
2238
2239   CASE (sem, INSN_STB_D) : /* stb $src1,@($slo16,$src2) */
2240 {
2241   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2242   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2243 #define FLD(f) abuf->fields.sfmt_st_d.f
2244   int UNUSED written = 0;
2245   IADDR UNUSED pc = abuf->addr;
2246   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
2247
2248   {
2249     QI opval = * FLD (i_src1);
2250     SETMEMQI (current_cpu, pc, ADDSI (* FLD (i_src2), FLD (f_simm16)), opval);
2251     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
2252   }
2253
2254 #undef FLD
2255 }
2256   NEXT (vpc);
2257
2258   CASE (sem, INSN_STH) : /* sth $src1,@$src2 */
2259 {
2260   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2261   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2262 #define FLD(f) abuf->fields.sfmt_st_plus.f
2263   int UNUSED written = 0;
2264   IADDR UNUSED pc = abuf->addr;
2265   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
2266
2267   {
2268     HI opval = * FLD (i_src1);
2269     SETMEMHI (current_cpu, pc, * FLD (i_src2), opval);
2270     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
2271   }
2272
2273 #undef FLD
2274 }
2275   NEXT (vpc);
2276
2277   CASE (sem, INSN_STH_D) : /* sth $src1,@($slo16,$src2) */
2278 {
2279   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2280   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2281 #define FLD(f) abuf->fields.sfmt_st_d.f
2282   int UNUSED written = 0;
2283   IADDR UNUSED pc = abuf->addr;
2284   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
2285
2286   {
2287     HI opval = * FLD (i_src1);
2288     SETMEMHI (current_cpu, pc, ADDSI (* FLD (i_src2), FLD (f_simm16)), opval);
2289     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
2290   }
2291
2292 #undef FLD
2293 }
2294   NEXT (vpc);
2295
2296   CASE (sem, INSN_ST_PLUS) : /* st $src1,@+$src2 */
2297 {
2298   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2299   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2300 #define FLD(f) abuf->fields.sfmt_st_plus.f
2301   int UNUSED written = 0;
2302   IADDR UNUSED pc = abuf->addr;
2303   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
2304
2305 {
2306   SI tmp_new_src2;
2307   tmp_new_src2 = ADDSI (* FLD (i_src2), 4);
2308   {
2309     SI opval = * FLD (i_src1);
2310     SETMEMSI (current_cpu, pc, tmp_new_src2, opval);
2311     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
2312   }
2313   {
2314     SI opval = tmp_new_src2;
2315     * FLD (i_src2) = opval;
2316     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
2317   }
2318 }
2319
2320 #undef FLD
2321 }
2322   NEXT (vpc);
2323
2324   CASE (sem, INSN_ST_MINUS) : /* st $src1,@-$src2 */
2325 {
2326   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2327   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2328 #define FLD(f) abuf->fields.sfmt_st_plus.f
2329   int UNUSED written = 0;
2330   IADDR UNUSED pc = abuf->addr;
2331   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
2332
2333 {
2334   SI tmp_new_src2;
2335   tmp_new_src2 = SUBSI (* FLD (i_src2), 4);
2336   {
2337     SI opval = * FLD (i_src1);
2338     SETMEMSI (current_cpu, pc, tmp_new_src2, opval);
2339     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
2340   }
2341   {
2342     SI opval = tmp_new_src2;
2343     * FLD (i_src2) = opval;
2344     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
2345   }
2346 }
2347
2348 #undef FLD
2349 }
2350   NEXT (vpc);
2351
2352   CASE (sem, INSN_SUB) : /* sub $dr,$sr */
2353 {
2354   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2355   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2356 #define FLD(f) abuf->fields.sfmt_add.f
2357   int UNUSED written = 0;
2358   IADDR UNUSED pc = abuf->addr;
2359   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
2360
2361   {
2362     SI opval = SUBSI (* FLD (i_dr), * FLD (i_sr));
2363     * FLD (i_dr) = opval;
2364     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
2365   }
2366
2367 #undef FLD
2368 }
2369   NEXT (vpc);
2370
2371   CASE (sem, INSN_SUBV) : /* subv $dr,$sr */
2372 {
2373   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2374   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2375 #define FLD(f) abuf->fields.sfmt_add.f
2376   int UNUSED written = 0;
2377   IADDR UNUSED pc = abuf->addr;
2378   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
2379
2380 {
2381   SI temp0;BI temp1;
2382   temp0 = SUBSI (* FLD (i_dr), * FLD (i_sr));
2383   temp1 = SUBOFSI (* FLD (i_dr), * FLD (i_sr), 0);
2384   {
2385     SI opval = temp0;
2386     * FLD (i_dr) = opval;
2387     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
2388   }
2389   {
2390     BI opval = temp1;
2391     CPU (h_cond) = opval;
2392     TRACE_RESULT (current_cpu, abuf, "cond", 'x', opval);
2393   }
2394 }
2395
2396 #undef FLD
2397 }
2398   NEXT (vpc);
2399
2400   CASE (sem, INSN_SUBX) : /* subx $dr,$sr */
2401 {
2402   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2403   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2404 #define FLD(f) abuf->fields.sfmt_add.f
2405   int UNUSED written = 0;
2406   IADDR UNUSED pc = abuf->addr;
2407   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
2408
2409 {
2410   SI temp0;BI temp1;
2411   temp0 = SUBCSI (* FLD (i_dr), * FLD (i_sr), CPU (h_cond));
2412   temp1 = SUBCFSI (* FLD (i_dr), * FLD (i_sr), CPU (h_cond));
2413   {
2414     SI opval = temp0;
2415     * FLD (i_dr) = opval;
2416     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
2417   }
2418   {
2419     BI opval = temp1;
2420     CPU (h_cond) = opval;
2421     TRACE_RESULT (current_cpu, abuf, "cond", 'x', opval);
2422   }
2423 }
2424
2425 #undef FLD
2426 }
2427   NEXT (vpc);
2428
2429   CASE (sem, INSN_TRAP) : /* trap $uimm4 */
2430 {
2431   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2432   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2433 #define FLD(f) abuf->fields.sfmt_trap.f
2434   int UNUSED written = 0;
2435   IADDR UNUSED pc = abuf->addr;
2436   SEM_BRANCH_INIT
2437   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
2438
2439 {
2440   {
2441     USI opval = GET_H_CR (((UINT) 6));
2442     SET_H_CR (((UINT) 14), opval);
2443     TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
2444   }
2445   {
2446     USI opval = ADDSI (pc, 4);
2447     SET_H_CR (((UINT) 6), opval);
2448     TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
2449   }
2450   {
2451     UQI opval = CPU (h_bpsw);
2452     CPU (h_bbpsw) = opval;
2453     TRACE_RESULT (current_cpu, abuf, "bbpsw", 'x', opval);
2454   }
2455   {
2456     UQI opval = GET_H_PSW ();
2457     CPU (h_bpsw) = opval;
2458     TRACE_RESULT (current_cpu, abuf, "bpsw", 'x', opval);
2459   }
2460   {
2461     UQI opval = ANDQI (GET_H_PSW (), 128);
2462     SET_H_PSW (opval);
2463     TRACE_RESULT (current_cpu, abuf, "psw", 'x', opval);
2464   }
2465   {
2466     SI opval = m32r_trap (current_cpu, pc, FLD (f_uimm4));
2467     SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
2468     TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
2469   }
2470 }
2471
2472   SEM_BRANCH_FINI (vpc);
2473 #undef FLD
2474 }
2475   NEXT (vpc);
2476
2477   CASE (sem, INSN_UNLOCK) : /* unlock $src1,@$src2 */
2478 {
2479   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2480   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2481 #define FLD(f) abuf->fields.sfmt_st_plus.f
2482   int UNUSED written = 0;
2483   IADDR UNUSED pc = abuf->addr;
2484   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
2485
2486 {
2487 if (CPU (h_lock)) {
2488   {
2489     SI opval = * FLD (i_src1);
2490     SETMEMSI (current_cpu, pc, * FLD (i_src2), opval);
2491     written |= (1 << 4);
2492     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
2493   }
2494 }
2495   {
2496     BI opval = 0;
2497     CPU (h_lock) = opval;
2498     TRACE_RESULT (current_cpu, abuf, "lock", 'x', opval);
2499   }
2500 }
2501
2502   abuf->written = written;
2503 #undef FLD
2504 }
2505   NEXT (vpc);
2506
2507   CASE (sem, INSN_CLRPSW) : /* clrpsw $uimm8 */
2508 {
2509   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2510   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2511 #define FLD(f) abuf->fields.sfmt_clrpsw.f
2512   int UNUSED written = 0;
2513   IADDR UNUSED pc = abuf->addr;
2514   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
2515
2516   {
2517     USI opval = ANDSI (GET_H_CR (((UINT) 0)), ORSI (ZEXTQISI (INVQI (FLD (f_uimm8))), 65280));
2518     SET_H_CR (((UINT) 0), opval);
2519     TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
2520   }
2521
2522 #undef FLD
2523 }
2524   NEXT (vpc);
2525
2526   CASE (sem, INSN_SETPSW) : /* setpsw $uimm8 */
2527 {
2528   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2529   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2530 #define FLD(f) abuf->fields.sfmt_clrpsw.f
2531   int UNUSED written = 0;
2532   IADDR UNUSED pc = abuf->addr;
2533   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
2534
2535   {
2536     USI opval = FLD (f_uimm8);
2537     SET_H_CR (((UINT) 0), opval);
2538     TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
2539   }
2540
2541 #undef FLD
2542 }
2543   NEXT (vpc);
2544
2545   CASE (sem, INSN_BSET) : /* bset $uimm3,@($slo16,$sr) */
2546 {
2547   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2548   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2549 #define FLD(f) abuf->fields.sfmt_bset.f
2550   int UNUSED written = 0;
2551   IADDR UNUSED pc = abuf->addr;
2552   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
2553
2554   {
2555     QI opval = ORQI (GETMEMQI (current_cpu, pc, ADDSI (* FLD (i_sr), FLD (f_simm16))), SLLQI (1, SUBSI (7, FLD (f_uimm3))));
2556     SETMEMQI (current_cpu, pc, ADDSI (* FLD (i_sr), FLD (f_simm16)), opval);
2557     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
2558   }
2559
2560 #undef FLD
2561 }
2562   NEXT (vpc);
2563
2564   CASE (sem, INSN_BCLR) : /* bclr $uimm3,@($slo16,$sr) */
2565 {
2566   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2567   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2568 #define FLD(f) abuf->fields.sfmt_bset.f
2569   int UNUSED written = 0;
2570   IADDR UNUSED pc = abuf->addr;
2571   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
2572
2573   {
2574     QI opval = ANDQI (GETMEMQI (current_cpu, pc, ADDSI (* FLD (i_sr), FLD (f_simm16))), INVQI (SLLQI (1, SUBSI (7, FLD (f_uimm3)))));
2575     SETMEMQI (current_cpu, pc, ADDSI (* FLD (i_sr), FLD (f_simm16)), opval);
2576     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
2577   }
2578
2579 #undef FLD
2580 }
2581   NEXT (vpc);
2582
2583   CASE (sem, INSN_BTST) : /* btst $uimm3,$sr */
2584 {
2585   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2586   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2587 #define FLD(f) abuf->fields.sfmt_bset.f
2588   int UNUSED written = 0;
2589   IADDR UNUSED pc = abuf->addr;
2590   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
2591
2592   {
2593     BI opval = ANDQI (SRLQI (* FLD (i_sr), SUBSI (7, FLD (f_uimm3))), 1);
2594     CPU (h_cond) = opval;
2595     TRACE_RESULT (current_cpu, abuf, "cond", 'x', opval);
2596   }
2597
2598 #undef FLD
2599 }
2600   NEXT (vpc);
2601
2602
2603     }
2604   ENDSWITCH (sem) /* End of semantic switch.  */
2605
2606   /* At this point `vpc' contains the next insn to execute.  */
2607 }
2608
2609 #undef DEFINE_SWITCH
2610 #endif /* DEFINE_SWITCH */