sim/m32r/sem-switch.c

   1 /* Simulator instruction semantics for m32rbf.
   2
   3 THIS FILE IS MACHINE GENERATED WITH CGEN.
   4
   5 Copyright (C) 1996, 1997, 1998, 1999 Free Software Foundation, Inc.
   6
   7 This file is part of the GNU Simulators.
   8
   9 This program is free software; you can redistribute it and/or modify
  10 it under the terms of the GNU General Public License as published by
  11 the Free Software Foundation; either version 2, or (at your option)
  12 any later version.
  13
  14 This program is distributed in the hope that it will be useful,
  15 but WITHOUT ANY WARRANTY; without even the implied warranty of
  16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17 GNU General Public License for more details.
  18
  19 You should have received a copy of the GNU General Public License along
  20 with this program; if not, write to the Free Software Foundation, Inc.,
  21 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  22
  23 */
  24
  25 #ifdef DEFINE_LABELS
  26
  27   /* The labels have the case they have because the enum of insn types
  28      is all uppercase and in the non-stdc case the insn symbol is built
  29      into the enum name.  */
  30
  31   static struct {
  32     int index;
  33     void *label;
  34   } labels[] = {
  35     { M32RBF_INSN_X_INVALID, && case_sem_INSN_X_INVALID },
  36     { M32RBF_INSN_X_AFTER, && case_sem_INSN_X_AFTER },
  37     { M32RBF_INSN_X_BEFORE, && case_sem_INSN_X_BEFORE },
  38     { M32RBF_INSN_X_CTI_CHAIN, && case_sem_INSN_X_CTI_CHAIN },
  39     { M32RBF_INSN_X_CHAIN, && case_sem_INSN_X_CHAIN },
  40     { M32RBF_INSN_X_BEGIN, && case_sem_INSN_X_BEGIN },
  41     { M32RBF_INSN_ADD, && case_sem_INSN_ADD },
  42     { M32RBF_INSN_ADD3, && case_sem_INSN_ADD3 },
  43     { M32RBF_INSN_AND, && case_sem_INSN_AND },
  44     { M32RBF_INSN_AND3, && case_sem_INSN_AND3 },
  45     { M32RBF_INSN_OR, && case_sem_INSN_OR },
  46     { M32RBF_INSN_OR3, && case_sem_INSN_OR3 },
  47     { M32RBF_INSN_XOR, && case_sem_INSN_XOR },
  48     { M32RBF_INSN_XOR3, && case_sem_INSN_XOR3 },
  49     { M32RBF_INSN_ADDI, && case_sem_INSN_ADDI },
  50     { M32RBF_INSN_ADDV, && case_sem_INSN_ADDV },
  51     { M32RBF_INSN_ADDV3, && case_sem_INSN_ADDV3 },
  52     { M32RBF_INSN_ADDX, && case_sem_INSN_ADDX },
  53     { M32RBF_INSN_BC8, && case_sem_INSN_BC8 },
  54     { M32RBF_INSN_BC24, && case_sem_INSN_BC24 },
  55     { M32RBF_INSN_BEQ, && case_sem_INSN_BEQ },
  56     { M32RBF_INSN_BEQZ, && case_sem_INSN_BEQZ },
  57     { M32RBF_INSN_BGEZ, && case_sem_INSN_BGEZ },
  58     { M32RBF_INSN_BGTZ, && case_sem_INSN_BGTZ },
  59     { M32RBF_INSN_BLEZ, && case_sem_INSN_BLEZ },
  60     { M32RBF_INSN_BLTZ, && case_sem_INSN_BLTZ },
  61     { M32RBF_INSN_BNEZ, && case_sem_INSN_BNEZ },
  62     { M32RBF_INSN_BL8, && case_sem_INSN_BL8 },
  63     { M32RBF_INSN_BL24, && case_sem_INSN_BL24 },
  64     { M32RBF_INSN_BNC8, && case_sem_INSN_BNC8 },
  65     { M32RBF_INSN_BNC24, && case_sem_INSN_BNC24 },
  66     { M32RBF_INSN_BNE, && case_sem_INSN_BNE },
  67     { M32RBF_INSN_BRA8, && case_sem_INSN_BRA8 },
  68     { M32RBF_INSN_BRA24, && case_sem_INSN_BRA24 },
  69     { M32RBF_INSN_CMP, && case_sem_INSN_CMP },
  70     { M32RBF_INSN_CMPI, && case_sem_INSN_CMPI },
  71     { M32RBF_INSN_CMPU, && case_sem_INSN_CMPU },
  72     { M32RBF_INSN_CMPUI, && case_sem_INSN_CMPUI },
  73     { M32RBF_INSN_DIV, && case_sem_INSN_DIV },
  74     { M32RBF_INSN_DIVU, && case_sem_INSN_DIVU },
  75     { M32RBF_INSN_REM, && case_sem_INSN_REM },
  76     { M32RBF_INSN_REMU, && case_sem_INSN_REMU },
  77     { M32RBF_INSN_JL, && case_sem_INSN_JL },
  78     { M32RBF_INSN_JMP, && case_sem_INSN_JMP },
  79     { M32RBF_INSN_LD, && case_sem_INSN_LD },
  80     { M32RBF_INSN_LD_D, && case_sem_INSN_LD_D },
  81     { M32RBF_INSN_LDB, && case_sem_INSN_LDB },
  82     { M32RBF_INSN_LDB_D, && case_sem_INSN_LDB_D },
  83     { M32RBF_INSN_LDH, && case_sem_INSN_LDH },
  84     { M32RBF_INSN_LDH_D, && case_sem_INSN_LDH_D },
  85     { M32RBF_INSN_LDUB, && case_sem_INSN_LDUB },
  86     { M32RBF_INSN_LDUB_D, && case_sem_INSN_LDUB_D },
  87     { M32RBF_INSN_LDUH, && case_sem_INSN_LDUH },
  88     { M32RBF_INSN_LDUH_D, && case_sem_INSN_LDUH_D },
  89     { M32RBF_INSN_LD_PLUS, && case_sem_INSN_LD_PLUS },
  90     { M32RBF_INSN_LD24, && case_sem_INSN_LD24 },
  91     { M32RBF_INSN_LDI8, && case_sem_INSN_LDI8 },
  92     { M32RBF_INSN_LDI16, && case_sem_INSN_LDI16 },
  93     { M32RBF_INSN_LOCK, && case_sem_INSN_LOCK },
  94     { M32RBF_INSN_MACHI, && case_sem_INSN_MACHI },
  95     { M32RBF_INSN_MACLO, && case_sem_INSN_MACLO },
  96     { M32RBF_INSN_MACWHI, && case_sem_INSN_MACWHI },
  97     { M32RBF_INSN_MACWLO, && case_sem_INSN_MACWLO },
  98     { M32RBF_INSN_MUL, && case_sem_INSN_MUL },
  99     { M32RBF_INSN_MULHI, && case_sem_INSN_MULHI },
 100     { M32RBF_INSN_MULLO, && case_sem_INSN_MULLO },
 101     { M32RBF_INSN_MULWHI, && case_sem_INSN_MULWHI },
 102     { M32RBF_INSN_MULWLO, && case_sem_INSN_MULWLO },
 103     { M32RBF_INSN_MV, && case_sem_INSN_MV },
 104     { M32RBF_INSN_MVFACHI, && case_sem_INSN_MVFACHI },
 105     { M32RBF_INSN_MVFACLO, && case_sem_INSN_MVFACLO },
 106     { M32RBF_INSN_MVFACMI, && case_sem_INSN_MVFACMI },
 107     { M32RBF_INSN_MVFC, && case_sem_INSN_MVFC },
 108     { M32RBF_INSN_MVTACHI, && case_sem_INSN_MVTACHI },
 109     { M32RBF_INSN_MVTACLO, && case_sem_INSN_MVTACLO },
 110     { M32RBF_INSN_MVTC, && case_sem_INSN_MVTC },
 111     { M32RBF_INSN_NEG, && case_sem_INSN_NEG },
 112     { M32RBF_INSN_NOP, && case_sem_INSN_NOP },
 113     { M32RBF_INSN_NOT, && case_sem_INSN_NOT },
 114     { M32RBF_INSN_RAC, && case_sem_INSN_RAC },
 115     { M32RBF_INSN_RACH, && case_sem_INSN_RACH },
 116     { M32RBF_INSN_RTE, && case_sem_INSN_RTE },
 117     { M32RBF_INSN_SETH, && case_sem_INSN_SETH },
 118     { M32RBF_INSN_SLL, && case_sem_INSN_SLL },
 119     { M32RBF_INSN_SLL3, && case_sem_INSN_SLL3 },
 120     { M32RBF_INSN_SLLI, && case_sem_INSN_SLLI },
 121     { M32RBF_INSN_SRA, && case_sem_INSN_SRA },
 122     { M32RBF_INSN_SRA3, && case_sem_INSN_SRA3 },
 123     { M32RBF_INSN_SRAI, && case_sem_INSN_SRAI },
 124     { M32RBF_INSN_SRL, && case_sem_INSN_SRL },
 125     { M32RBF_INSN_SRL3, && case_sem_INSN_SRL3 },
 126     { M32RBF_INSN_SRLI, && case_sem_INSN_SRLI },
 127     { M32RBF_INSN_ST, && case_sem_INSN_ST },
 128     { M32RBF_INSN_ST_D, && case_sem_INSN_ST_D },
 129     { M32RBF_INSN_STB, && case_sem_INSN_STB },
 130     { M32RBF_INSN_STB_D, && case_sem_INSN_STB_D },
 131     { M32RBF_INSN_STH, && case_sem_INSN_STH },
 132     { M32RBF_INSN_STH_D, && case_sem_INSN_STH_D },
 133     { M32RBF_INSN_ST_PLUS, && case_sem_INSN_ST_PLUS },
 134     { M32RBF_INSN_ST_MINUS, && case_sem_INSN_ST_MINUS },
 135     { M32RBF_INSN_SUB, && case_sem_INSN_SUB },
 136     { M32RBF_INSN_SUBV, && case_sem_INSN_SUBV },
 137     { M32RBF_INSN_SUBX, && case_sem_INSN_SUBX },
 138     { M32RBF_INSN_TRAP, && case_sem_INSN_TRAP },
 139     { M32RBF_INSN_UNLOCK, && case_sem_INSN_UNLOCK },
 140     { 0, 0 }
 141   };
 142   int i;
 143
 144   for (i = 0; labels[i].label != 0; ++i)
 145 #if FAST_P
 146     CPU_IDESC (current_cpu) [labels[i].index].sem_fast_lab = labels[i].label;
 147 #else
 148     CPU_IDESC (current_cpu) [labels[i].index].sem_full_lab = labels[i].label;
 149 #endif
 150
 151 #undef DEFINE_LABELS
 152 #endif /* DEFINE_LABELS */
 153
 154 #ifdef DEFINE_SWITCH
 155
 156 /* If hyper-fast [well not unnecessarily slow] execution is selected, turn
 157    off frills like tracing and profiling.  */
 158 /* FIXME: A better way would be to have TRACE_RESULT check for something
 159    that can cause it to be optimized out.  Another way would be to emit
 160    special handlers into the instruction "stream".  */
 161
 162 #if FAST_P
 163 #undef TRACE_RESULT
 164 #define TRACE_RESULT(cpu, abuf, name, type, val)
 165 #endif
 166
 167 #undef GET_ATTR
 168 #define GET_ATTR(cpu, num, attr) CGEN_ATTR_VALUE (NULL, abuf->idesc->attrs, CGEN_INSN_##attr)
 169
 170 {
 171
 172 #if WITH_SCACHE_PBB
 173
 174 /* Branch to next handler without going around main loop.  */
 175 #define NEXT(vpc) goto * SEM_ARGBUF (vpc) -> semantic.sem_case
 176 SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case)
 177
 178 #else /* ! WITH_SCACHE_PBB */
 179
 180 #define NEXT(vpc) BREAK (sem)
 181 #ifdef __GNUC__
 182 #if FAST_P
 183   SWITCH (sem, SEM_ARGBUF (sc) -> idesc->sem_fast_lab)
 184 #else
 185   SWITCH (sem, SEM_ARGBUF (sc) -> idesc->sem_full_lab)
 186 #endif
 187 #else
 188   SWITCH (sem, SEM_ARGBUF (sc) -> idesc->num)
 189 #endif
 190
 191 #endif /* ! WITH_SCACHE_PBB */
 192
 193     {
 194
 195   CASE (sem, INSN_X_INVALID) : /* --invalid-- */
 196 {
 197   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
 198   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
 199 #define FLD(f) abuf->fields.fmt_empty.f
 200   int UNUSED written = 0;
 201   IADDR UNUSED pc = abuf->addr;
 202   vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
 203
 204   {
 205 #if WITH_SCACHE
 206     /* Update the recorded pc in the cpu state struct.  */
 207     SET_H_PC (pc);
 208 #endif
 209     sim_engine_invalid_insn (current_cpu, pc);
 210     sim_io_error (CPU_STATE (current_cpu), "invalid insn not handled\n");
 211     /* NOTREACHED */
 212   }
 213
 214 #undef FLD
 215 }
 216   NEXT (vpc);
 217
 218   CASE (sem, INSN_X_AFTER) : /* --after-- */
 219 {
 220   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
 221   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
 222 #define FLD(f) abuf->fields.fmt_empty.f
 223   int UNUSED written = 0;
 224   IADDR UNUSED pc = abuf->addr;
 225   vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
 226
 227   {
 228 #if WITH_SCACHE_PBB_M32RBF
 229     m32rbf_pbb_after (current_cpu, sem_arg);
 230 #endif
 231   }
 232
 233 #undef FLD
 234 }
 235   NEXT (vpc);
 236
 237   CASE (sem, INSN_X_BEFORE) : /* --before-- */
 238 {
 239   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
 240   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
 241 #define FLD(f) abuf->fields.fmt_empty.f
 242   int UNUSED written = 0;
 243   IADDR UNUSED pc = abuf->addr;
 244   vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
 245
 246   {
 247 #if WITH_SCACHE_PBB_M32RBF
 248     m32rbf_pbb_before (current_cpu, sem_arg);
 249 #endif
 250   }
 251
 252 #undef FLD
 253 }
 254   NEXT (vpc);
 255
 256   CASE (sem, INSN_X_CTI_CHAIN) : /* --cti-chain-- */
 257 {
 258   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
 259   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
 260 #define FLD(f) abuf->fields.fmt_empty.f
 261   int UNUSED written = 0;
 262   IADDR UNUSED pc = abuf->addr;
 263   vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
 264
 265   {
 266 #if WITH_SCACHE_PBB_M32RBF
 267 #ifdef DEFINE_SWITCH
 268     vpc = m32rbf_pbb_cti_chain (current_cpu, sem_arg,
 269                                pbb_br_npc_ptr, pbb_br_npc);
 270     BREAK (sem);
 271 #else
 272     /* FIXME: Allow provision of explicit ifmt spec in insn spec.  */
 273     vpc = m32rbf_pbb_cti_chain (current_cpu, sem_arg,
 274                                CPU_PBB_BR_NPC_PTR (current_cpu),
 275                                CPU_PBB_BR_NPC (current_cpu));
 276 #endif
 277 #endif
 278   }
 279
 280 #undef FLD
 281 }
 282   NEXT (vpc);
 283
 284   CASE (sem, INSN_X_CHAIN) : /* --chain-- */
 285 {
 286   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
 287   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
 288 #define FLD(f) abuf->fields.fmt_empty.f
 289   int UNUSED written = 0;
 290   IADDR UNUSED pc = abuf->addr;
 291   vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
 292
 293   {
 294 #if WITH_SCACHE_PBB_M32RBF
 295     vpc = m32rbf_pbb_chain (current_cpu, sem_arg);
 296 #ifdef DEFINE_SWITCH
 297     BREAK (sem);
 298 #endif
 299 #endif
 300   }
 301
 302 #undef FLD
 303 }
 304   NEXT (vpc);
 305
 306   CASE (sem, INSN_X_BEGIN) : /* --begin-- */
 307 {
 308   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
 309   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
 310 #define FLD(f) abuf->fields.fmt_empty.f
 311   int UNUSED written = 0;
 312   IADDR UNUSED pc = abuf->addr;
 313   vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
 314
 315   {
 316 #if WITH_SCACHE_PBB_M32RBF
 317 #ifdef DEFINE_SWITCH
 318     /* In the switch case FAST_P is a constant, allowing several optimizations
 319        in any called inline functions.  */
 320     vpc = m32rbf_pbb_begin (current_cpu, FAST_P);
 321 #else
 322     vpc = m32rbf_pbb_begin (current_cpu, STATE_RUN_FAST_P (CPU_STATE (current_cpu)));
 323 #endif
 324 #endif
 325   }
 326
 327 #undef FLD
 328 }
 329   NEXT (vpc);
 330
 331   CASE (sem, INSN_ADD) : /* add $dr,$sr */
 332 {
 333   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
 334   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
 335 #define FLD(f) abuf->fields.fmt_add.f
 336   int UNUSED written = 0;
 337   IADDR UNUSED pc = abuf->addr;
 338   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
 339
 340   {
 341     SI opval = ADDSI (* FLD (i_dr), * FLD (i_sr));
 342     * FLD (i_dr) = opval;
 343     TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
 344   }
 345
 346 #undef FLD
 347 }
 348   NEXT (vpc);
 349
 350   CASE (sem, INSN_ADD3) : /* add3 $dr,$sr,$hash$slo16 */
 351 {
 352   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
 353   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
 354 #define FLD(f) abuf->fields.fmt_add3.f
 355   int UNUSED written = 0;
 356   IADDR UNUSED pc = abuf->addr;
 357   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
 358
 359   {
 360     SI opval = ADDSI (* FLD (i_sr), FLD (f_simm16));
 361     * FLD (i_dr) = opval;
 362     TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
 363   }
 364
 365 #undef FLD
 366 }
 367   NEXT (vpc);
 368
 369   CASE (sem, INSN_AND) : /* and $dr,$sr */
 370 {
 371   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
 372   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
 373 #define FLD(f) abuf->fields.fmt_add.f
 374   int UNUSED written = 0;
 375   IADDR UNUSED pc = abuf->addr;
 376   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
 377
 378   {
 379     SI opval = ANDSI (* FLD (i_dr), * FLD (i_sr));
 380     * FLD (i_dr) = opval;
 381     TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
 382   }
 383
 384 #undef FLD
 385 }
 386   NEXT (vpc);
 387
 388   CASE (sem, INSN_AND3) : /* and3 $dr,$sr,$uimm16 */
 389 {
 390   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
 391   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
 392 #define FLD(f) abuf->fields.fmt_and3.f
 393   int UNUSED written = 0;
 394   IADDR UNUSED pc = abuf->addr;
 395   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
 396
 397   {
 398     SI opval = ANDSI (* FLD (i_sr), FLD (f_uimm16));
 399     * FLD (i_dr) = opval;
 400     TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
 401   }
 402
 403 #undef FLD
 404 }
 405   NEXT (vpc);
 406
 407   CASE (sem, INSN_OR) : /* or $dr,$sr */
 408 {
 409   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
 410   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
 411 #define FLD(f) abuf->fields.fmt_add.f
 412   int UNUSED written = 0;
 413   IADDR UNUSED pc = abuf->addr;
 414   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
 415
 416   {
 417     SI opval = ORSI (* FLD (i_dr), * FLD (i_sr));
 418     * FLD (i_dr) = opval;
 419     TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
 420   }
 421
 422 #undef FLD
 423 }
 424   NEXT (vpc);
 425
 426   CASE (sem, INSN_OR3) : /* or3 $dr,$sr,$hash$ulo16 */
 427 {
 428   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
 429   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
 430 #define FLD(f) abuf->fields.fmt_or3.f
 431   int UNUSED written = 0;
 432   IADDR UNUSED pc = abuf->addr;
 433   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
 434
 435   {
 436     SI opval = ORSI (* FLD (i_sr), FLD (f_uimm16));
 437     * FLD (i_dr) = opval;
 438     TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
 439   }
 440
 441 #undef FLD
 442 }
 443   NEXT (vpc);
 444
 445   CASE (sem, INSN_XOR) : /* xor $dr,$sr */
 446 {
 447   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
 448   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
 449 #define FLD(f) abuf->fields.fmt_add.f
 450   int UNUSED written = 0;
 451   IADDR UNUSED pc = abuf->addr;
 452   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
 453
 454   {
 455     SI opval = XORSI (* FLD (i_dr), * FLD (i_sr));
 456     * FLD (i_dr) = opval;
 457     TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
 458   }
 459
 460 #undef FLD
 461 }
 462   NEXT (vpc);
 463
 464   CASE (sem, INSN_XOR3) : /* xor3 $dr,$sr,$uimm16 */
 465 {
 466   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
 467   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
 468 #define FLD(f) abuf->fields.fmt_and3.f
 469   int UNUSED written = 0;
 470   IADDR UNUSED pc = abuf->addr;
 471   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
 472
 473   {
 474     SI opval = XORSI (* FLD (i_sr), FLD (f_uimm16));
 475     * FLD (i_dr) = opval;
 476     TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
 477   }
 478
 479 #undef FLD
 480 }
 481   NEXT (vpc);
 482
 483   CASE (sem, INSN_ADDI) : /* addi $dr,$simm8 */
 484 {
 485   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
 486   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
 487 #define FLD(f) abuf->fields.fmt_addi.f
 488   int UNUSED written = 0;
 489   IADDR UNUSED pc = abuf->addr;
 490   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
 491
 492   {
 493     SI opval = ADDSI (* FLD (i_dr), FLD (f_simm8));
 494     * FLD (i_dr) = opval;
 495     TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
 496   }
 497
 498 #undef FLD
 499 }
 500   NEXT (vpc);
 501
 502   CASE (sem, INSN_ADDV) : /* addv $dr,$sr */
 503 {
 504   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
 505   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
 506 #define FLD(f) abuf->fields.fmt_addv.f
 507   int UNUSED written = 0;
 508   IADDR UNUSED pc = abuf->addr;
 509   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
 510
 511 do {
 512   BI temp1;SI temp0;
 513   temp0 = ADDSI (* FLD (i_dr), * FLD (i_sr));
 514   temp1 = ADDOFSI (* FLD (i_dr), * FLD (i_sr), 0);
 515   {
 516     SI opval = temp0;
 517     * FLD (i_dr) = opval;
 518     TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
 519   }
 520   {
 521     BI opval = temp1;
 522     CPU (h_cond) = opval;
 523     TRACE_RESULT (current_cpu, abuf, "condbit", 'x', opval);
 524   }
 525 } while (0);
 526
 527 #undef FLD
 528 }
 529   NEXT (vpc);
 530
 531   CASE (sem, INSN_ADDV3) : /* addv3 $dr,$sr,$simm16 */
 532 {
 533   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
 534   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
 535 #define FLD(f) abuf->fields.fmt_addv3.f
 536   int UNUSED written = 0;
 537   IADDR UNUSED pc = abuf->addr;
 538   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
 539
 540 do {
 541   BI temp1;SI temp0;
 542   temp0 = ADDSI (* FLD (i_sr), FLD (f_simm16));
 543   temp1 = ADDOFSI (* FLD (i_sr), FLD (f_simm16), 0);
 544   {
 545     SI opval = temp0;
 546     * FLD (i_dr) = opval;
 547     TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
 548   }
 549   {
 550     BI opval = temp1;
 551     CPU (h_cond) = opval;
 552     TRACE_RESULT (current_cpu, abuf, "condbit", 'x', opval);
 553   }
 554 } while (0);
 555
 556 #undef FLD
 557 }
 558   NEXT (vpc);
 559
 560   CASE (sem, INSN_ADDX) : /* addx $dr,$sr */
 561 {
 562   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
 563   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
 564 #define FLD(f) abuf->fields.fmt_addx.f
 565   int UNUSED written = 0;
 566   IADDR UNUSED pc = abuf->addr;
 567   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
 568
 569 do {
 570   BI temp1;SI temp0;
 571   temp0 = ADDCSI (* FLD (i_dr), * FLD (i_sr), CPU (h_cond));
 572   temp1 = ADDCFSI (* FLD (i_dr), * FLD (i_sr), CPU (h_cond));
 573   {
 574     SI opval = temp0;
 575     * FLD (i_dr) = opval;
 576     TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
 577   }
 578   {
 579     BI opval = temp1;
 580     CPU (h_cond) = opval;
 581     TRACE_RESULT (current_cpu, abuf, "condbit", 'x', opval);
 582   }
 583 } while (0);
 584
 585 #undef FLD
 586 }
 587   NEXT (vpc);
 588
 589   CASE (sem, INSN_BC8) : /* bc.s $disp8 */
 590 {
 591   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
 592   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
 593 #define FLD(f) abuf->fields.cti.fields.fmt_bc8.f
 594   int UNUSED written = 0;
 595   IADDR UNUSED pc = abuf->addr;
 596   SEM_BRANCH_INIT
 597   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
 598
 599 if (CPU (h_cond)) {
 600   {
 601     USI opval = FLD (i_disp8);
 602     SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg));
 603     written |= (1 << 2);
 604     TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
 605   }
 606 }
 607
 608   abuf->written = written;
 609   SEM_BRANCH_FINI (vpc);
 610 #undef FLD
 611 }
 612   NEXT (vpc);
 613
 614   CASE (sem, INSN_BC24) : /* bc.l $disp24 */
 615 {
 616   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
 617   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
 618 #define FLD(f) abuf->fields.cti.fields.fmt_bc24.f
 619   int UNUSED written = 0;
 620   IADDR UNUSED pc = abuf->addr;
 621   SEM_BRANCH_INIT
 622   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
 623
 624 if (CPU (h_cond)) {
 625   {
 626     USI opval = FLD (i_disp24);
 627     SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg));
 628     written |= (1 << 2);
 629     TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
 630   }
 631 }
 632
 633   abuf->written = written;
 634   SEM_BRANCH_FINI (vpc);
 635 #undef FLD
 636 }
 637   NEXT (vpc);
 638
 639   CASE (sem, INSN_BEQ) : /* beq $src1,$src2,$disp16 */
 640 {
 641   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
 642   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
 643 #define FLD(f) abuf->fields.cti.fields.fmt_beq.f
 644   int UNUSED written = 0;
 645   IADDR UNUSED pc = abuf->addr;
 646   SEM_BRANCH_INIT
 647   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
 648
 649 if (EQSI (* FLD (i_src1), * FLD (i_src2))) {
 650   {
 651     USI opval = FLD (i_disp16);
 652     SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg));
 653     written |= (1 << 3);
 654     TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
 655   }
 656 }
 657
 658   abuf->written = written;
 659   SEM_BRANCH_FINI (vpc);
 660 #undef FLD
 661 }
 662   NEXT (vpc);
 663
 664   CASE (sem, INSN_BEQZ) : /* beqz $src2,$disp16 */
 665 {
 666   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
 667   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
 668 #define FLD(f) abuf->fields.cti.fields.fmt_beqz.f
 669   int UNUSED written = 0;
 670   IADDR UNUSED pc = abuf->addr;
 671   SEM_BRANCH_INIT
 672   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
 673
 674 if (EQSI (* FLD (i_src2), 0)) {
 675   {
 676     USI opval = FLD (i_disp16);
 677     SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg));
 678     written |= (1 << 2);
 679     TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
 680   }
 681 }
 682
 683   abuf->written = written;
 684   SEM_BRANCH_FINI (vpc);
 685 #undef FLD
 686 }
 687   NEXT (vpc);
 688
 689   CASE (sem, INSN_BGEZ) : /* bgez $src2,$disp16 */
 690 {
 691   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
 692   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
 693 #define FLD(f) abuf->fields.cti.fields.fmt_beqz.f
 694   int UNUSED written = 0;
 695   IADDR UNUSED pc = abuf->addr;
 696   SEM_BRANCH_INIT
 697   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
 698
 699 if (GESI (* FLD (i_src2), 0)) {
 700   {
 701     USI opval = FLD (i_disp16);
 702     SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg));
 703     written |= (1 << 2);
 704     TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
 705   }
 706 }
 707
 708   abuf->written = written;
 709   SEM_BRANCH_FINI (vpc);
 710 #undef FLD
 711 }
 712   NEXT (vpc);
 713
 714   CASE (sem, INSN_BGTZ) : /* bgtz $src2,$disp16 */
 715 {
 716   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
 717   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
 718 #define FLD(f) abuf->fields.cti.fields.fmt_beqz.f
 719   int UNUSED written = 0;
 720   IADDR UNUSED pc = abuf->addr;
 721   SEM_BRANCH_INIT
 722   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
 723
 724 if (GTSI (* FLD (i_src2), 0)) {
 725   {
 726     USI opval = FLD (i_disp16);
 727     SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg));
 728     written |= (1 << 2);
 729     TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
 730   }
 731 }
 732
 733   abuf->written = written;
 734   SEM_BRANCH_FINI (vpc);
 735 #undef FLD
 736 }
 737   NEXT (vpc);
 738
 739   CASE (sem, INSN_BLEZ) : /* blez $src2,$disp16 */
 740 {
 741   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
 742   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
 743 #define FLD(f) abuf->fields.cti.fields.fmt_beqz.f
 744   int UNUSED written = 0;
 745   IADDR UNUSED pc = abuf->addr;
 746   SEM_BRANCH_INIT
 747   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
 748
 749 if (LESI (* FLD (i_src2), 0)) {
 750   {
 751     USI opval = FLD (i_disp16);
 752     SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg));
 753     written |= (1 << 2);
 754     TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
 755   }
 756 }
 757
 758   abuf->written = written;
 759   SEM_BRANCH_FINI (vpc);
 760 #undef FLD
 761 }
 762   NEXT (vpc);
 763
 764   CASE (sem, INSN_BLTZ) : /* bltz $src2,$disp16 */
 765 {
 766   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
 767   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
 768 #define FLD(f) abuf->fields.cti.fields.fmt_beqz.f
 769   int UNUSED written = 0;
 770   IADDR UNUSED pc = abuf->addr;
 771   SEM_BRANCH_INIT
 772   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
 773
 774 if (LTSI (* FLD (i_src2), 0)) {
 775   {
 776     USI opval = FLD (i_disp16);
 777     SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg));
 778     written |= (1 << 2);
 779     TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
 780   }
 781 }
 782
 783   abuf->written = written;
 784   SEM_BRANCH_FINI (vpc);
 785 #undef FLD
 786 }
 787   NEXT (vpc);
 788
 789   CASE (sem, INSN_BNEZ) : /* bnez $src2,$disp16 */
 790 {
 791   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
 792   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
 793 #define FLD(f) abuf->fields.cti.fields.fmt_beqz.f
 794   int UNUSED written = 0;
 795   IADDR UNUSED pc = abuf->addr;
 796   SEM_BRANCH_INIT
 797   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
 798
 799 if (NESI (* FLD (i_src2), 0)) {
 800   {
 801     USI opval = FLD (i_disp16);
 802     SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg));
 803     written |= (1 << 2);
 804     TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
 805   }
 806 }
 807
 808   abuf->written = written;
 809   SEM_BRANCH_FINI (vpc);
 810 #undef FLD
 811 }
 812   NEXT (vpc);
 813
 814   CASE (sem, INSN_BL8) : /* bl.s $disp8 */
 815 {
 816   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
 817   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
 818 #define FLD(f) abuf->fields.cti.fields.fmt_bl8.f
 819   int UNUSED written = 0;
 820   IADDR UNUSED pc = abuf->addr;
 821   SEM_BRANCH_INIT
 822   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
 823
 824 do {
 825   {
 826     SI opval = ADDSI (ANDSI (pc, -4), 4);
 827     CPU (h_gr[((UINT) 14)]) = opval;
 828     TRACE_RESULT (current_cpu, abuf, "gr-14", 'x', opval);
 829   }
 830   {
 831     USI opval = FLD (i_disp8);
 832     SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg));
 833     TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
 834   }
 835 } while (0);
 836
 837   SEM_BRANCH_FINI (vpc);
 838 #undef FLD
 839 }
 840   NEXT (vpc);
 841
 842   CASE (sem, INSN_BL24) : /* bl.l $disp24 */
 843 {
 844   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
 845   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
 846 #define FLD(f) abuf->fields.cti.fields.fmt_bl24.f
 847   int UNUSED written = 0;
 848   IADDR UNUSED pc = abuf->addr;
 849   SEM_BRANCH_INIT
 850   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
 851
 852 do {
 853   {
 854     SI opval = ADDSI (pc, 4);
 855     CPU (h_gr[((UINT) 14)]) = opval;
 856     TRACE_RESULT (current_cpu, abuf, "gr-14", 'x', opval);
 857   }
 858   {
 859     USI opval = FLD (i_disp24);
 860     SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg));
 861     TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
 862   }
 863 } while (0);
 864
 865   SEM_BRANCH_FINI (vpc);
 866 #undef FLD
 867 }
 868   NEXT (vpc);
 869
 870   CASE (sem, INSN_BNC8) : /* bnc.s $disp8 */
 871 {
 872   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
 873   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
 874 #define FLD(f) abuf->fields.cti.fields.fmt_bc8.f
 875   int UNUSED written = 0;
 876   IADDR UNUSED pc = abuf->addr;
 877   SEM_BRANCH_INIT
 878   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
 879
 880 if (NOTBI (CPU (h_cond))) {
 881   {
 882     USI opval = FLD (i_disp8);
 883     SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg));
 884     written |= (1 << 2);
 885     TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
 886   }
 887 }
 888
 889   abuf->written = written;
 890   SEM_BRANCH_FINI (vpc);
 891 #undef FLD
 892 }
 893   NEXT (vpc);
 894
 895   CASE (sem, INSN_BNC24) : /* bnc.l $disp24 */
 896 {
 897   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
 898   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
 899 #define FLD(f) abuf->fields.cti.fields.fmt_bc24.f
 900   int UNUSED written = 0;
 901   IADDR UNUSED pc = abuf->addr;
 902   SEM_BRANCH_INIT
 903   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
 904
 905 if (NOTBI (CPU (h_cond))) {
 906   {
 907     USI opval = FLD (i_disp24);
 908     SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg));
 909     written |= (1 << 2);
 910     TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
 911   }
 912 }
 913
 914   abuf->written = written;
 915   SEM_BRANCH_FINI (vpc);
 916 #undef FLD
 917 }
 918   NEXT (vpc);
 919
 920   CASE (sem, INSN_BNE) : /* bne $src1,$src2,$disp16 */
 921 {
 922   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
 923   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
 924 #define FLD(f) abuf->fields.cti.fields.fmt_beq.f
 925   int UNUSED written = 0;
 926   IADDR UNUSED pc = abuf->addr;
 927   SEM_BRANCH_INIT
 928   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
 929
 930 if (NESI (* FLD (i_src1), * FLD (i_src2))) {
 931   {
 932     USI opval = FLD (i_disp16);
 933     SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg));
 934     written |= (1 << 3);
 935     TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
 936   }
 937 }
 938
 939   abuf->written = written;
 940   SEM_BRANCH_FINI (vpc);
 941 #undef FLD
 942 }
 943   NEXT (vpc);
 944
 945   CASE (sem, INSN_BRA8) : /* bra.s $disp8 */
 946 {
 947   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
 948   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
 949 #define FLD(f) abuf->fields.cti.fields.fmt_bra8.f
 950   int UNUSED written = 0;
 951   IADDR UNUSED pc = abuf->addr;
 952   SEM_BRANCH_INIT
 953   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
 954
 955   {
 956     USI opval = FLD (i_disp8);
 957     SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg));
 958     TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
 959   }
 960
 961   SEM_BRANCH_FINI (vpc);
 962 #undef FLD
 963 }
 964   NEXT (vpc);
 965
 966   CASE (sem, INSN_BRA24) : /* bra.l $disp24 */
 967 {
 968   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
 969   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
 970 #define FLD(f) abuf->fields.cti.fields.fmt_bra24.f
 971   int UNUSED written = 0;
 972   IADDR UNUSED pc = abuf->addr;
 973   SEM_BRANCH_INIT
 974   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
 975
 976   {
 977     USI opval = FLD (i_disp24);
 978     SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg));
 979     TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
 980   }
 981
 982   SEM_BRANCH_FINI (vpc);
 983 #undef FLD
 984 }
 985   NEXT (vpc);
 986
 987   CASE (sem, INSN_CMP) : /* cmp $src1,$src2 */
 988 {
 989   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
 990   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
 991 #define FLD(f) abuf->fields.fmt_cmp.f
 992   int UNUSED written = 0;
 993   IADDR UNUSED pc = abuf->addr;
 994   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
 995
 996   {
 997     BI opval = LTSI (* FLD (i_src1), * FLD (i_src2));
 998     CPU (h_cond) = opval;
 999     TRACE_RESULT (current_cpu, abuf, "condbit", 'x', opval);
1000   }
1001
1002 #undef FLD
1003 }
1004   NEXT (vpc);
1005
1006   CASE (sem, INSN_CMPI) : /* cmpi $src2,$simm16 */
1007 {
1008   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1009   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1010 #define FLD(f) abuf->fields.fmt_cmpi.f
1011   int UNUSED written = 0;
1012   IADDR UNUSED pc = abuf->addr;
1013   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
1014
1015   {
1016     BI opval = LTSI (* FLD (i_src2), FLD (f_simm16));
1017     CPU (h_cond) = opval;
1018     TRACE_RESULT (current_cpu, abuf, "condbit", 'x', opval);
1019   }
1020
1021 #undef FLD
1022 }
1023   NEXT (vpc);
1024
1025   CASE (sem, INSN_CMPU) : /* cmpu $src1,$src2 */
1026 {
1027   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1028   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1029 #define FLD(f) abuf->fields.fmt_cmp.f
1030   int UNUSED written = 0;
1031   IADDR UNUSED pc = abuf->addr;
1032   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
1033
1034   {
1035     BI opval = LTUSI (* FLD (i_src1), * FLD (i_src2));
1036     CPU (h_cond) = opval;
1037     TRACE_RESULT (current_cpu, abuf, "condbit", 'x', opval);
1038   }
1039
1040 #undef FLD
1041 }
1042   NEXT (vpc);
1043
1044   CASE (sem, INSN_CMPUI) : /* cmpui $src2,$simm16 */
1045 {
1046   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1047   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1048 #define FLD(f) abuf->fields.fmt_cmpi.f
1049   int UNUSED written = 0;
1050   IADDR UNUSED pc = abuf->addr;
1051   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
1052
1053   {
1054     BI opval = LTUSI (* FLD (i_src2), FLD (f_simm16));
1055     CPU (h_cond) = opval;
1056     TRACE_RESULT (current_cpu, abuf, "condbit", 'x', opval);
1057   }
1058
1059 #undef FLD
1060 }
1061   NEXT (vpc);
1062
1063   CASE (sem, INSN_DIV) : /* div $dr,$sr */
1064 {
1065   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1066   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1067 #define FLD(f) abuf->fields.fmt_div.f
1068   int UNUSED written = 0;
1069   IADDR UNUSED pc = abuf->addr;
1070   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
1071
1072 if (NESI (* FLD (i_sr), 0)) {
1073   {
1074     SI opval = DIVSI (* FLD (i_dr), * FLD (i_sr));
1075     * FLD (i_dr) = opval;
1076     written |= (1 << 2);
1077     TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
1078   }
1079 }
1080
1081   abuf->written = written;
1082 #undef FLD
1083 }
1084   NEXT (vpc);
1085
1086   CASE (sem, INSN_DIVU) : /* divu $dr,$sr */
1087 {
1088   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1089   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1090 #define FLD(f) abuf->fields.fmt_div.f
1091   int UNUSED written = 0;
1092   IADDR UNUSED pc = abuf->addr;
1093   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
1094
1095 if (NESI (* FLD (i_sr), 0)) {
1096   {
1097     SI opval = UDIVSI (* FLD (i_dr), * FLD (i_sr));
1098     * FLD (i_dr) = opval;
1099     written |= (1 << 2);
1100     TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
1101   }
1102 }
1103
1104   abuf->written = written;
1105 #undef FLD
1106 }
1107   NEXT (vpc);
1108
1109   CASE (sem, INSN_REM) : /* rem $dr,$sr */
1110 {
1111   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1112   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1113 #define FLD(f) abuf->fields.fmt_div.f
1114   int UNUSED written = 0;
1115   IADDR UNUSED pc = abuf->addr;
1116   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
1117
1118 if (NESI (* FLD (i_sr), 0)) {
1119   {
1120     SI opval = MODSI (* FLD (i_dr), * FLD (i_sr));
1121     * FLD (i_dr) = opval;
1122     written |= (1 << 2);
1123     TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
1124   }
1125 }
1126
1127   abuf->written = written;
1128 #undef FLD
1129 }
1130   NEXT (vpc);
1131
1132   CASE (sem, INSN_REMU) : /* remu $dr,$sr */
1133 {
1134   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1135   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1136 #define FLD(f) abuf->fields.fmt_div.f
1137   int UNUSED written = 0;
1138   IADDR UNUSED pc = abuf->addr;
1139   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
1140
1141 if (NESI (* FLD (i_sr), 0)) {
1142   {
1143     SI opval = UMODSI (* FLD (i_dr), * FLD (i_sr));
1144     * FLD (i_dr) = opval;
1145     written |= (1 << 2);
1146     TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
1147   }
1148 }
1149
1150   abuf->written = written;
1151 #undef FLD
1152 }
1153   NEXT (vpc);
1154
1155   CASE (sem, INSN_JL) : /* jl $sr */
1156 {
1157   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1158   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1159 #define FLD(f) abuf->fields.cti.fields.fmt_jl.f
1160   int UNUSED written = 0;
1161   IADDR UNUSED pc = abuf->addr;
1162   SEM_BRANCH_INIT
1163   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
1164
1165 do {
1166   USI temp1;SI temp0;
1167   temp0 = ADDSI (ANDSI (pc, -4), 4);
1168   temp1 = ANDSI (* FLD (i_sr), -4);
1169   {
1170     SI opval = temp0;
1171     CPU (h_gr[((UINT) 14)]) = opval;
1172     TRACE_RESULT (current_cpu, abuf, "gr-14", 'x', opval);
1173   }
1174   {
1175     USI opval = temp1;
1176     SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
1177     TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
1178   }
1179 } while (0);
1180
1181   SEM_BRANCH_FINI (vpc);
1182 #undef FLD
1183 }
1184   NEXT (vpc);
1185
1186   CASE (sem, INSN_JMP) : /* jmp $sr */
1187 {
1188   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1189   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1190 #define FLD(f) abuf->fields.cti.fields.fmt_jmp.f
1191   int UNUSED written = 0;
1192   IADDR UNUSED pc = abuf->addr;
1193   SEM_BRANCH_INIT
1194   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
1195
1196   {
1197     USI opval = ANDSI (* FLD (i_sr), -4);
1198     SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
1199     TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
1200   }
1201
1202   SEM_BRANCH_FINI (vpc);
1203 #undef FLD
1204 }
1205   NEXT (vpc);
1206
1207   CASE (sem, INSN_LD) : /* ld $dr,@$sr */
1208 {
1209   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1210   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1211 #define FLD(f) abuf->fields.fmt_ld.f
1212   int UNUSED written = 0;
1213   IADDR UNUSED pc = abuf->addr;
1214   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
1215
1216   {
1217     SI opval = GETMEMSI (current_cpu, pc, * FLD (i_sr));
1218     * FLD (i_dr) = opval;
1219     TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
1220   }
1221
1222 #undef FLD
1223 }
1224   NEXT (vpc);
1225
1226   CASE (sem, INSN_LD_D) : /* ld $dr,@($slo16,$sr) */
1227 {
1228   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1229   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1230 #define FLD(f) abuf->fields.fmt_ld_d.f
1231   int UNUSED written = 0;
1232   IADDR UNUSED pc = abuf->addr;
1233   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
1234
1235   {
1236     SI opval = GETMEMSI (current_cpu, pc, ADDSI (* FLD (i_sr), FLD (f_simm16)));
1237     * FLD (i_dr) = opval;
1238     TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
1239   }
1240
1241 #undef FLD
1242 }
1243   NEXT (vpc);
1244
1245   CASE (sem, INSN_LDB) : /* ldb $dr,@$sr */
1246 {
1247   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1248   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1249 #define FLD(f) abuf->fields.fmt_ldb.f
1250   int UNUSED written = 0;
1251   IADDR UNUSED pc = abuf->addr;
1252   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
1253
1254   {
1255     SI opval = EXTQISI (GETMEMQI (current_cpu, pc, * FLD (i_sr)));
1256     * FLD (i_dr) = opval;
1257     TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
1258   }
1259
1260 #undef FLD
1261 }
1262   NEXT (vpc);
1263
1264   CASE (sem, INSN_LDB_D) : /* ldb $dr,@($slo16,$sr) */
1265 {
1266   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1267   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1268 #define FLD(f) abuf->fields.fmt_ldb_d.f
1269   int UNUSED written = 0;
1270   IADDR UNUSED pc = abuf->addr;
1271   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
1272
1273   {
1274     SI opval = EXTQISI (GETMEMQI (current_cpu, pc, ADDSI (* FLD (i_sr), FLD (f_simm16))));
1275     * FLD (i_dr) = opval;
1276     TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
1277   }
1278
1279 #undef FLD
1280 }
1281   NEXT (vpc);
1282
1283   CASE (sem, INSN_LDH) : /* ldh $dr,@$sr */
1284 {
1285   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1286   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1287 #define FLD(f) abuf->fields.fmt_ldh.f
1288   int UNUSED written = 0;
1289   IADDR UNUSED pc = abuf->addr;
1290   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
1291
1292   {
1293     SI opval = EXTHISI (GETMEMHI (current_cpu, pc, * FLD (i_sr)));
1294     * FLD (i_dr) = opval;
1295     TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
1296   }
1297
1298 #undef FLD
1299 }
1300   NEXT (vpc);
1301
1302   CASE (sem, INSN_LDH_D) : /* ldh $dr,@($slo16,$sr) */
1303 {
1304   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1305   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1306 #define FLD(f) abuf->fields.fmt_ldh_d.f
1307   int UNUSED written = 0;
1308   IADDR UNUSED pc = abuf->addr;
1309   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
1310
1311   {
1312     SI opval = EXTHISI (GETMEMHI (current_cpu, pc, ADDSI (* FLD (i_sr), FLD (f_simm16))));
1313     * FLD (i_dr) = opval;
1314     TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
1315   }
1316
1317 #undef FLD
1318 }
1319   NEXT (vpc);
1320
1321   CASE (sem, INSN_LDUB) : /* ldub $dr,@$sr */
1322 {
1323   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1324   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1325 #define FLD(f) abuf->fields.fmt_ldb.f
1326   int UNUSED written = 0;
1327   IADDR UNUSED pc = abuf->addr;
1328   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
1329
1330   {
1331     SI opval = ZEXTQISI (GETMEMQI (current_cpu, pc, * FLD (i_sr)));
1332     * FLD (i_dr) = opval;
1333     TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
1334   }
1335
1336 #undef FLD
1337 }
1338   NEXT (vpc);
1339
1340   CASE (sem, INSN_LDUB_D) : /* ldub $dr,@($slo16,$sr) */
1341 {
1342   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1343   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1344 #define FLD(f) abuf->fields.fmt_ldb_d.f
1345   int UNUSED written = 0;
1346   IADDR UNUSED pc = abuf->addr;
1347   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
1348
1349   {
1350     SI opval = ZEXTQISI (GETMEMQI (current_cpu, pc, ADDSI (* FLD (i_sr), FLD (f_simm16))));
1351     * FLD (i_dr) = opval;
1352     TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
1353   }
1354
1355 #undef FLD
1356 }
1357   NEXT (vpc);
1358
1359   CASE (sem, INSN_LDUH) : /* lduh $dr,@$sr */
1360 {
1361   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1362   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1363 #define FLD(f) abuf->fields.fmt_ldh.f
1364   int UNUSED written = 0;
1365   IADDR UNUSED pc = abuf->addr;
1366   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
1367
1368   {
1369     SI opval = ZEXTHISI (GETMEMHI (current_cpu, pc, * FLD (i_sr)));
1370     * FLD (i_dr) = opval;
1371     TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
1372   }
1373
1374 #undef FLD
1375 }
1376   NEXT (vpc);
1377
1378   CASE (sem, INSN_LDUH_D) : /* lduh $dr,@($slo16,$sr) */
1379 {
1380   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1381   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1382 #define FLD(f) abuf->fields.fmt_ldh_d.f
1383   int UNUSED written = 0;
1384   IADDR UNUSED pc = abuf->addr;
1385   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
1386
1387   {
1388     SI opval = ZEXTHISI (GETMEMHI (current_cpu, pc, ADDSI (* FLD (i_sr), FLD (f_simm16))));
1389     * FLD (i_dr) = opval;
1390     TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
1391   }
1392
1393 #undef FLD
1394 }
1395   NEXT (vpc);
1396
1397   CASE (sem, INSN_LD_PLUS) : /* ld $dr,@$sr+ */
1398 {
1399   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1400   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1401 #define FLD(f) abuf->fields.fmt_ld_plus.f
1402   int UNUSED written = 0;
1403   IADDR UNUSED pc = abuf->addr;
1404   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
1405
1406 do {
1407   SI temp1;SI temp0;
1408   temp0 = GETMEMSI (current_cpu, pc, * FLD (i_sr));
1409   temp1 = ADDSI (* FLD (i_sr), 4);
1410   {
1411     SI opval = temp0;
1412     * FLD (i_dr) = opval;
1413     TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
1414   }
1415   {
1416     SI opval = temp1;
1417     * FLD (i_sr) = opval;
1418     TRACE_RESULT (current_cpu, abuf, "sr", 'x', opval);
1419   }
1420 } while (0);
1421
1422 #undef FLD
1423 }
1424   NEXT (vpc);
1425
1426   CASE (sem, INSN_LD24) : /* ld24 $dr,$uimm24 */
1427 {
1428   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1429   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1430 #define FLD(f) abuf->fields.fmt_ld24.f
1431   int UNUSED written = 0;
1432   IADDR UNUSED pc = abuf->addr;
1433   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
1434
1435   {
1436     SI opval = FLD (i_uimm24);
1437     * FLD (i_dr) = opval;
1438     TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
1439   }
1440
1441 #undef FLD
1442 }
1443   NEXT (vpc);
1444
1445   CASE (sem, INSN_LDI8) : /* ldi8 $dr,$simm8 */
1446 {
1447   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1448   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1449 #define FLD(f) abuf->fields.fmt_ldi8.f
1450   int UNUSED written = 0;
1451   IADDR UNUSED pc = abuf->addr;
1452   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
1453
1454   {
1455     SI opval = FLD (f_simm8);
1456     * FLD (i_dr) = opval;
1457     TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
1458   }
1459
1460 #undef FLD
1461 }
1462   NEXT (vpc);
1463
1464   CASE (sem, INSN_LDI16) : /* ldi16 $dr,$hash$slo16 */
1465 {
1466   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1467   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1468 #define FLD(f) abuf->fields.fmt_ldi16.f
1469   int UNUSED written = 0;
1470   IADDR UNUSED pc = abuf->addr;
1471   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
1472
1473   {
1474     SI opval = FLD (f_simm16);
1475     * FLD (i_dr) = opval;
1476     TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
1477   }
1478
1479 #undef FLD
1480 }
1481   NEXT (vpc);
1482
1483   CASE (sem, INSN_LOCK) : /* lock $dr,@$sr */
1484 {
1485   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1486   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1487 #define FLD(f) abuf->fields.fmt_lock.f
1488   int UNUSED written = 0;
1489   IADDR UNUSED pc = abuf->addr;
1490   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
1491
1492 do {
1493   {
1494     BI opval = 1;
1495     CPU (h_lock) = opval;
1496     TRACE_RESULT (current_cpu, abuf, "lock-0", 'x', opval);
1497   }
1498   {
1499     SI opval = GETMEMSI (current_cpu, pc, * FLD (i_sr));
1500     * FLD (i_dr) = opval;
1501     TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
1502   }
1503 } while (0);
1504
1505 #undef FLD
1506 }
1507   NEXT (vpc);
1508
1509   CASE (sem, INSN_MACHI) : /* machi $src1,$src2 */
1510 {
1511   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1512   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1513 #define FLD(f) abuf->fields.fmt_machi.f
1514   int UNUSED written = 0;
1515   IADDR UNUSED pc = abuf->addr;
1516   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
1517
1518   {
1519     DI opval = SRADI (SLLDI (ADDDI (GET_H_ACCUM (), MULDI (EXTSIDI (ANDSI (* FLD (i_src1), 0xffff0000)), EXTHIDI (TRUNCSIHI (SRASI (* FLD (i_src2), 16))))), 8), 8);
1520     SET_H_ACCUM (opval);
1521     TRACE_RESULT (current_cpu, abuf, "accum", 'D', opval);
1522   }
1523
1524 #undef FLD
1525 }
1526   NEXT (vpc);
1527
1528   CASE (sem, INSN_MACLO) : /* maclo $src1,$src2 */
1529 {
1530   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1531   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1532 #define FLD(f) abuf->fields.fmt_machi.f
1533   int UNUSED written = 0;
1534   IADDR UNUSED pc = abuf->addr;
1535   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
1536
1537   {
1538     DI opval = SRADI (SLLDI (ADDDI (GET_H_ACCUM (), MULDI (EXTSIDI (SLLSI (* FLD (i_src1), 16)), EXTHIDI (TRUNCSIHI (* FLD (i_src2))))), 8), 8);
1539     SET_H_ACCUM (opval);
1540     TRACE_RESULT (current_cpu, abuf, "accum", 'D', opval);
1541   }
1542
1543 #undef FLD
1544 }
1545   NEXT (vpc);
1546
1547   CASE (sem, INSN_MACWHI) : /* macwhi $src1,$src2 */
1548 {
1549   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1550   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1551 #define FLD(f) abuf->fields.fmt_machi.f
1552   int UNUSED written = 0;
1553   IADDR UNUSED pc = abuf->addr;
1554   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
1555
1556   {
1557     DI opval = SRADI (SLLDI (ADDDI (GET_H_ACCUM (), MULDI (EXTSIDI (* FLD (i_src1)), EXTHIDI (TRUNCSIHI (SRASI (* FLD (i_src2), 16))))), 8), 8);
1558     SET_H_ACCUM (opval);
1559     TRACE_RESULT (current_cpu, abuf, "accum", 'D', opval);
1560   }
1561
1562 #undef FLD
1563 }
1564   NEXT (vpc);
1565
1566   CASE (sem, INSN_MACWLO) : /* macwlo $src1,$src2 */
1567 {
1568   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1569   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1570 #define FLD(f) abuf->fields.fmt_machi.f
1571   int UNUSED written = 0;
1572   IADDR UNUSED pc = abuf->addr;
1573   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
1574
1575   {
1576     DI opval = SRADI (SLLDI (ADDDI (GET_H_ACCUM (), MULDI (EXTSIDI (* FLD (i_src1)), EXTHIDI (TRUNCSIHI (* FLD (i_src2))))), 8), 8);
1577     SET_H_ACCUM (opval);
1578     TRACE_RESULT (current_cpu, abuf, "accum", 'D', opval);
1579   }
1580
1581 #undef FLD
1582 }
1583   NEXT (vpc);
1584
1585   CASE (sem, INSN_MUL) : /* mul $dr,$sr */
1586 {
1587   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1588   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1589 #define FLD(f) abuf->fields.fmt_add.f
1590   int UNUSED written = 0;
1591   IADDR UNUSED pc = abuf->addr;
1592   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
1593
1594   {
1595     SI opval = MULSI (* FLD (i_dr), * FLD (i_sr));
1596     * FLD (i_dr) = opval;
1597     TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
1598   }
1599
1600 #undef FLD
1601 }
1602   NEXT (vpc);
1603
1604   CASE (sem, INSN_MULHI) : /* mulhi $src1,$src2 */
1605 {
1606   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1607   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1608 #define FLD(f) abuf->fields.fmt_mulhi.f
1609   int UNUSED written = 0;
1610   IADDR UNUSED pc = abuf->addr;
1611   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
1612
1613   {
1614     DI opval = SRADI (SLLDI (MULDI (EXTSIDI (ANDSI (* FLD (i_src1), 0xffff0000)), EXTHIDI (TRUNCSIHI (SRASI (* FLD (i_src2), 16)))), 16), 16);
1615     SET_H_ACCUM (opval);
1616     TRACE_RESULT (current_cpu, abuf, "accum", 'D', opval);
1617   }
1618
1619 #undef FLD
1620 }
1621   NEXT (vpc);
1622
1623   CASE (sem, INSN_MULLO) : /* mullo $src1,$src2 */
1624 {
1625   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1626   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1627 #define FLD(f) abuf->fields.fmt_mulhi.f
1628   int UNUSED written = 0;
1629   IADDR UNUSED pc = abuf->addr;
1630   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
1631
1632   {
1633     DI opval = SRADI (SLLDI (MULDI (EXTSIDI (SLLSI (* FLD (i_src1), 16)), EXTHIDI (TRUNCSIHI (* FLD (i_src2)))), 16), 16);
1634     SET_H_ACCUM (opval);
1635     TRACE_RESULT (current_cpu, abuf, "accum", 'D', opval);
1636   }
1637
1638 #undef FLD
1639 }
1640   NEXT (vpc);
1641
1642   CASE (sem, INSN_MULWHI) : /* mulwhi $src1,$src2 */
1643 {
1644   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1645   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1646 #define FLD(f) abuf->fields.fmt_mulhi.f
1647   int UNUSED written = 0;
1648   IADDR UNUSED pc = abuf->addr;
1649   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
1650
1651   {
1652     DI opval = SRADI (SLLDI (MULDI (EXTSIDI (* FLD (i_src1)), EXTHIDI (TRUNCSIHI (SRASI (* FLD (i_src2), 16)))), 8), 8);
1653     SET_H_ACCUM (opval);
1654     TRACE_RESULT (current_cpu, abuf, "accum", 'D', opval);
1655   }
1656
1657 #undef FLD
1658 }
1659   NEXT (vpc);
1660
1661   CASE (sem, INSN_MULWLO) : /* mulwlo $src1,$src2 */
1662 {
1663   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1664   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1665 #define FLD(f) abuf->fields.fmt_mulhi.f
1666   int UNUSED written = 0;
1667   IADDR UNUSED pc = abuf->addr;
1668   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
1669
1670   {
1671     DI opval = SRADI (SLLDI (MULDI (EXTSIDI (* FLD (i_src1)), EXTHIDI (TRUNCSIHI (* FLD (i_src2)))), 8), 8);
1672     SET_H_ACCUM (opval);
1673     TRACE_RESULT (current_cpu, abuf, "accum", 'D', opval);
1674   }
1675
1676 #undef FLD
1677 }
1678   NEXT (vpc);
1679
1680   CASE (sem, INSN_MV) : /* mv $dr,$sr */
1681 {
1682   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1683   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1684 #define FLD(f) abuf->fields.fmt_mv.f
1685   int UNUSED written = 0;
1686   IADDR UNUSED pc = abuf->addr;
1687   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
1688
1689   {
1690     SI opval = * FLD (i_sr);
1691     * FLD (i_dr) = opval;
1692     TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
1693   }
1694
1695 #undef FLD
1696 }
1697   NEXT (vpc);
1698
1699   CASE (sem, INSN_MVFACHI) : /* mvfachi $dr */
1700 {
1701   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1702   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1703 #define FLD(f) abuf->fields.fmt_mvfachi.f
1704   int UNUSED written = 0;
1705   IADDR UNUSED pc = abuf->addr;
1706   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
1707
1708   {
1709     SI opval = TRUNCDISI (SRADI (GET_H_ACCUM (), 32));
1710     * FLD (i_dr) = opval;
1711     TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
1712   }
1713
1714 #undef FLD
1715 }
1716   NEXT (vpc);
1717
1718   CASE (sem, INSN_MVFACLO) : /* mvfaclo $dr */
1719 {
1720   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1721   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1722 #define FLD(f) abuf->fields.fmt_mvfachi.f
1723   int UNUSED written = 0;
1724   IADDR UNUSED pc = abuf->addr;
1725   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
1726
1727   {
1728     SI opval = TRUNCDISI (GET_H_ACCUM ());
1729     * FLD (i_dr) = opval;
1730     TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
1731   }
1732
1733 #undef FLD
1734 }
1735   NEXT (vpc);
1736
1737   CASE (sem, INSN_MVFACMI) : /* mvfacmi $dr */
1738 {
1739   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1740   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1741 #define FLD(f) abuf->fields.fmt_mvfachi.f
1742   int UNUSED written = 0;
1743   IADDR UNUSED pc = abuf->addr;
1744   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
1745
1746   {
1747     SI opval = TRUNCDISI (SRADI (GET_H_ACCUM (), 16));
1748     * FLD (i_dr) = opval;
1749     TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
1750   }
1751
1752 #undef FLD
1753 }
1754   NEXT (vpc);
1755
1756   CASE (sem, INSN_MVFC) : /* mvfc $dr,$scr */
1757 {
1758   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1759   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1760 #define FLD(f) abuf->fields.fmt_mvfc.f
1761   int UNUSED written = 0;
1762   IADDR UNUSED pc = abuf->addr;
1763   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
1764
1765   {
1766     SI opval = GET_H_CR (FLD (f_r2));
1767     * FLD (i_dr) = opval;
1768     TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
1769   }
1770
1771 #undef FLD
1772 }
1773   NEXT (vpc);
1774
1775   CASE (sem, INSN_MVTACHI) : /* mvtachi $src1 */
1776 {
1777   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1778   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1779 #define FLD(f) abuf->fields.fmt_mvtachi.f
1780   int UNUSED written = 0;
1781   IADDR UNUSED pc = abuf->addr;
1782   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
1783
1784   {
1785     DI opval = ORDI (ANDDI (GET_H_ACCUM (), MAKEDI (0, 0xffffffff)), SLLDI (EXTSIDI (* FLD (i_src1)), 32));
1786     SET_H_ACCUM (opval);
1787     TRACE_RESULT (current_cpu, abuf, "accum", 'D', opval);
1788   }
1789
1790 #undef FLD
1791 }
1792   NEXT (vpc);
1793
1794   CASE (sem, INSN_MVTACLO) : /* mvtaclo $src1 */
1795 {
1796   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1797   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1798 #define FLD(f) abuf->fields.fmt_mvtachi.f
1799   int UNUSED written = 0;
1800   IADDR UNUSED pc = abuf->addr;
1801   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
1802
1803   {
1804     DI opval = ORDI (ANDDI (GET_H_ACCUM (), MAKEDI (0xffffffff, 0)), ZEXTSIDI (* FLD (i_src1)));
1805     SET_H_ACCUM (opval);
1806     TRACE_RESULT (current_cpu, abuf, "accum", 'D', opval);
1807   }
1808
1809 #undef FLD
1810 }
1811   NEXT (vpc);
1812
1813   CASE (sem, INSN_MVTC) : /* mvtc $sr,$dcr */
1814 {
1815   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1816   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1817 #define FLD(f) abuf->fields.fmt_mvtc.f
1818   int UNUSED written = 0;
1819   IADDR UNUSED pc = abuf->addr;
1820   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
1821
1822   {
1823     USI opval = * FLD (i_sr);
1824     SET_H_CR (FLD (f_r1), opval);
1825     TRACE_RESULT (current_cpu, abuf, "dcr", 'x', opval);
1826   }
1827
1828 #undef FLD
1829 }
1830   NEXT (vpc);
1831
1832   CASE (sem, INSN_NEG) : /* neg $dr,$sr */
1833 {
1834   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1835   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1836 #define FLD(f) abuf->fields.fmt_mv.f
1837   int UNUSED written = 0;
1838   IADDR UNUSED pc = abuf->addr;
1839   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
1840
1841   {
1842     SI opval = NEGSI (* FLD (i_sr));
1843     * FLD (i_dr) = opval;
1844     TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
1845   }
1846
1847 #undef FLD
1848 }
1849   NEXT (vpc);
1850
1851   CASE (sem, INSN_NOP) : /* nop */
1852 {
1853   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1854   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1855 #define FLD(f) abuf->fields.fmt_nop.f
1856   int UNUSED written = 0;
1857   IADDR UNUSED pc = abuf->addr;
1858   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
1859
1860 PROFILE_COUNT_FILLNOPS (current_cpu, abuf->addr);
1861
1862 #undef FLD
1863 }
1864   NEXT (vpc);
1865
1866   CASE (sem, INSN_NOT) : /* not $dr,$sr */
1867 {
1868   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1869   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1870 #define FLD(f) abuf->fields.fmt_mv.f
1871   int UNUSED written = 0;
1872   IADDR UNUSED pc = abuf->addr;
1873   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
1874
1875   {
1876     SI opval = INVSI (* FLD (i_sr));
1877     * FLD (i_dr) = opval;
1878     TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
1879   }
1880
1881 #undef FLD
1882 }
1883   NEXT (vpc);
1884
1885   CASE (sem, INSN_RAC) : /* rac */
1886 {
1887   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1888   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1889 #define FLD(f) abuf->fields.fmt_rac.f
1890   int UNUSED written = 0;
1891   IADDR UNUSED pc = abuf->addr;
1892   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
1893
1894 do {
1895   DI tmp_tmp1;
1896   tmp_tmp1 = SLLDI (GET_H_ACCUM (), 1);
1897   tmp_tmp1 = ADDDI (tmp_tmp1, MAKEDI (0, 32768));
1898   {
1899     DI opval = (GTDI (tmp_tmp1, MAKEDI (32767, 0xffff0000))) ? (MAKEDI (32767, 0xffff0000)) : (LTDI (tmp_tmp1, MAKEDI (0xffff8000, 0))) ? (MAKEDI (0xffff8000, 0)) : (ANDDI (tmp_tmp1, MAKEDI (0xffffffff, 0xffff0000)));
1900     SET_H_ACCUM (opval);
1901     TRACE_RESULT (current_cpu, abuf, "accum", 'D', opval);
1902   }
1903 } while (0);
1904
1905 #undef FLD
1906 }
1907   NEXT (vpc);
1908
1909   CASE (sem, INSN_RACH) : /* rach */
1910 {
1911   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1912   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1913 #define FLD(f) abuf->fields.fmt_rac.f
1914   int UNUSED written = 0;
1915   IADDR UNUSED pc = abuf->addr;
1916   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
1917
1918 do {
1919   DI tmp_tmp1;
1920   tmp_tmp1 = ANDDI (GET_H_ACCUM (), MAKEDI (16777215, 0xffffffff));
1921 if (ANDIF (GEDI (tmp_tmp1, MAKEDI (16383, 0x80000000)), LEDI (tmp_tmp1, MAKEDI (8388607, 0xffffffff)))) {
1922   tmp_tmp1 = MAKEDI (16383, 0x80000000);
1923 } else {
1924 if (ANDIF (GEDI (tmp_tmp1, MAKEDI (8388608, 0)), LEDI (tmp_tmp1, MAKEDI (16760832, 0)))) {
1925   tmp_tmp1 = MAKEDI (16760832, 0);
1926 } else {
1927   tmp_tmp1 = ANDDI (ADDDI (GET_H_ACCUM (), MAKEDI (0, 1073741824)), MAKEDI (0xffffffff, 0x80000000));
1928 }
1929 }
1930   tmp_tmp1 = SLLDI (tmp_tmp1, 1);
1931   {
1932     DI opval = SRADI (SLLDI (tmp_tmp1, 7), 7);
1933     SET_H_ACCUM (opval);
1934     TRACE_RESULT (current_cpu, abuf, "accum", 'D', opval);
1935   }
1936 } while (0);
1937
1938 #undef FLD
1939 }
1940   NEXT (vpc);
1941
1942   CASE (sem, INSN_RTE) : /* rte */
1943 {
1944   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1945   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1946 #define FLD(f) abuf->fields.cti.fields.fmt_rte.f
1947   int UNUSED written = 0;
1948   IADDR UNUSED pc = abuf->addr;
1949   SEM_BRANCH_INIT
1950   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
1951
1952 do {
1953   {
1954     USI opval = ANDSI (GET_H_CR (((UINT) 6)), -4);
1955     SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
1956     TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
1957   }
1958   {
1959     USI opval = GET_H_CR (((UINT) 14));
1960     SET_H_CR (((UINT) 6), opval);
1961     TRACE_RESULT (current_cpu, abuf, "cr-6", 'x', opval);
1962   }
1963   {
1964     UQI opval = CPU (h_bpsw);
1965     SET_H_PSW (opval);
1966     TRACE_RESULT (current_cpu, abuf, "psw-0", 'x', opval);
1967   }
1968   {
1969     UQI opval = CPU (h_bbpsw);
1970     CPU (h_bpsw) = opval;
1971     TRACE_RESULT (current_cpu, abuf, "bpsw-0", 'x', opval);
1972   }
1973 } while (0);
1974
1975   SEM_BRANCH_FINI (vpc);
1976 #undef FLD
1977 }
1978   NEXT (vpc);
1979
1980   CASE (sem, INSN_SETH) : /* seth $dr,$hash$hi16 */
1981 {
1982   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1983   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1984 #define FLD(f) abuf->fields.fmt_seth.f
1985   int UNUSED written = 0;
1986   IADDR UNUSED pc = abuf->addr;
1987   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
1988
1989   {
1990     SI opval = SLLSI (FLD (f_hi16), 16);
1991     * FLD (i_dr) = opval;
1992     TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
1993   }
1994
1995 #undef FLD
1996 }
1997   NEXT (vpc);
1998
1999   CASE (sem, INSN_SLL) : /* sll $dr,$sr */
2000 {
2001   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2002   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2003 #define FLD(f) abuf->fields.fmt_add.f
2004   int UNUSED written = 0;
2005   IADDR UNUSED pc = abuf->addr;
2006   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
2007
2008   {
2009     SI opval = SLLSI (* FLD (i_dr), ANDSI (* FLD (i_sr), 31));
2010     * FLD (i_dr) = opval;
2011     TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
2012   }
2013
2014 #undef FLD
2015 }
2016   NEXT (vpc);
2017
2018   CASE (sem, INSN_SLL3) : /* sll3 $dr,$sr,$simm16 */
2019 {
2020   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2021   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2022 #define FLD(f) abuf->fields.fmt_sll3.f
2023   int UNUSED written = 0;
2024   IADDR UNUSED pc = abuf->addr;
2025   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
2026
2027   {
2028     SI opval = SLLSI (* FLD (i_sr), ANDSI (FLD (f_simm16), 31));
2029     * FLD (i_dr) = opval;
2030     TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
2031   }
2032
2033 #undef FLD
2034 }
2035   NEXT (vpc);
2036
2037   CASE (sem, INSN_SLLI) : /* slli $dr,$uimm5 */
2038 {
2039   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2040   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2041 #define FLD(f) abuf->fields.fmt_slli.f
2042   int UNUSED written = 0;
2043   IADDR UNUSED pc = abuf->addr;
2044   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
2045
2046   {
2047     SI opval = SLLSI (* FLD (i_dr), FLD (f_uimm5));
2048     * FLD (i_dr) = opval;
2049     TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
2050   }
2051
2052 #undef FLD
2053 }
2054   NEXT (vpc);
2055
2056   CASE (sem, INSN_SRA) : /* sra $dr,$sr */
2057 {
2058   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2059   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2060 #define FLD(f) abuf->fields.fmt_add.f
2061   int UNUSED written = 0;
2062   IADDR UNUSED pc = abuf->addr;
2063   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
2064
2065   {
2066     SI opval = SRASI (* FLD (i_dr), ANDSI (* FLD (i_sr), 31));
2067     * FLD (i_dr) = opval;
2068     TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
2069   }
2070
2071 #undef FLD
2072 }
2073   NEXT (vpc);
2074
2075   CASE (sem, INSN_SRA3) : /* sra3 $dr,$sr,$simm16 */
2076 {
2077   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2078   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2079 #define FLD(f) abuf->fields.fmt_sll3.f
2080   int UNUSED written = 0;
2081   IADDR UNUSED pc = abuf->addr;
2082   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
2083
2084   {
2085     SI opval = SRASI (* FLD (i_sr), ANDSI (FLD (f_simm16), 31));
2086     * FLD (i_dr) = opval;
2087     TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
2088   }
2089
2090 #undef FLD
2091 }
2092   NEXT (vpc);
2093
2094   CASE (sem, INSN_SRAI) : /* srai $dr,$uimm5 */
2095 {
2096   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2097   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2098 #define FLD(f) abuf->fields.fmt_slli.f
2099   int UNUSED written = 0;
2100   IADDR UNUSED pc = abuf->addr;
2101   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
2102
2103   {
2104     SI opval = SRASI (* FLD (i_dr), FLD (f_uimm5));
2105     * FLD (i_dr) = opval;
2106     TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
2107   }
2108
2109 #undef FLD
2110 }
2111   NEXT (vpc);
2112
2113   CASE (sem, INSN_SRL) : /* srl $dr,$sr */
2114 {
2115   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2116   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2117 #define FLD(f) abuf->fields.fmt_add.f
2118   int UNUSED written = 0;
2119   IADDR UNUSED pc = abuf->addr;
2120   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
2121
2122   {
2123     SI opval = SRLSI (* FLD (i_dr), ANDSI (* FLD (i_sr), 31));
2124     * FLD (i_dr) = opval;
2125     TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
2126   }
2127
2128 #undef FLD
2129 }
2130   NEXT (vpc);
2131
2132   CASE (sem, INSN_SRL3) : /* srl3 $dr,$sr,$simm16 */
2133 {
2134   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2135   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2136 #define FLD(f) abuf->fields.fmt_sll3.f
2137   int UNUSED written = 0;
2138   IADDR UNUSED pc = abuf->addr;
2139   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
2140
2141   {
2142     SI opval = SRLSI (* FLD (i_sr), ANDSI (FLD (f_simm16), 31));
2143     * FLD (i_dr) = opval;
2144     TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
2145   }
2146
2147 #undef FLD
2148 }
2149   NEXT (vpc);
2150
2151   CASE (sem, INSN_SRLI) : /* srli $dr,$uimm5 */
2152 {
2153   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2154   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2155 #define FLD(f) abuf->fields.fmt_slli.f
2156   int UNUSED written = 0;
2157   IADDR UNUSED pc = abuf->addr;
2158   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
2159
2160   {
2161     SI opval = SRLSI (* FLD (i_dr), FLD (f_uimm5));
2162     * FLD (i_dr) = opval;
2163     TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
2164   }
2165
2166 #undef FLD
2167 }
2168   NEXT (vpc);
2169
2170   CASE (sem, INSN_ST) : /* st $src1,@$src2 */
2171 {
2172   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2173   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2174 #define FLD(f) abuf->fields.fmt_st.f
2175   int UNUSED written = 0;
2176   IADDR UNUSED pc = abuf->addr;
2177   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
2178
2179   {
2180     SI opval = * FLD (i_src1);
2181     SETMEMSI (current_cpu, pc, * FLD (i_src2), opval);
2182     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
2183   }
2184
2185 #undef FLD
2186 }
2187   NEXT (vpc);
2188
2189   CASE (sem, INSN_ST_D) : /* st $src1,@($slo16,$src2) */
2190 {
2191   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2192   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2193 #define FLD(f) abuf->fields.fmt_st_d.f
2194   int UNUSED written = 0;
2195   IADDR UNUSED pc = abuf->addr;
2196   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
2197
2198   {
2199     SI opval = * FLD (i_src1);
2200     SETMEMSI (current_cpu, pc, ADDSI (* FLD (i_src2), FLD (f_simm16)), opval);
2201     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
2202   }
2203
2204 #undef FLD
2205 }
2206   NEXT (vpc);
2207
2208   CASE (sem, INSN_STB) : /* stb $src1,@$src2 */
2209 {
2210   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2211   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2212 #define FLD(f) abuf->fields.fmt_stb.f
2213   int UNUSED written = 0;
2214   IADDR UNUSED pc = abuf->addr;
2215   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
2216
2217   {
2218     QI opval = * FLD (i_src1);
2219     SETMEMQI (current_cpu, pc, * FLD (i_src2), opval);
2220     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
2221   }
2222
2223 #undef FLD
2224 }
2225   NEXT (vpc);
2226
2227   CASE (sem, INSN_STB_D) : /* stb $src1,@($slo16,$src2) */
2228 {
2229   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2230   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2231 #define FLD(f) abuf->fields.fmt_stb_d.f
2232   int UNUSED written = 0;
2233   IADDR UNUSED pc = abuf->addr;
2234   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
2235
2236   {
2237     QI opval = * FLD (i_src1);
2238     SETMEMQI (current_cpu, pc, ADDSI (* FLD (i_src2), FLD (f_simm16)), opval);
2239     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
2240   }
2241
2242 #undef FLD
2243 }
2244   NEXT (vpc);
2245
2246   CASE (sem, INSN_STH) : /* sth $src1,@$src2 */
2247 {
2248   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2249   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2250 #define FLD(f) abuf->fields.fmt_sth.f
2251   int UNUSED written = 0;
2252   IADDR UNUSED pc = abuf->addr;
2253   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
2254
2255   {
2256     HI opval = * FLD (i_src1);
2257     SETMEMHI (current_cpu, pc, * FLD (i_src2), opval);
2258     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
2259   }
2260
2261 #undef FLD
2262 }
2263   NEXT (vpc);
2264
2265   CASE (sem, INSN_STH_D) : /* sth $src1,@($slo16,$src2) */
2266 {
2267   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2268   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2269 #define FLD(f) abuf->fields.fmt_sth_d.f
2270   int UNUSED written = 0;
2271   IADDR UNUSED pc = abuf->addr;
2272   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
2273
2274   {
2275     HI opval = * FLD (i_src1);
2276     SETMEMHI (current_cpu, pc, ADDSI (* FLD (i_src2), FLD (f_simm16)), opval);
2277     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
2278   }
2279
2280 #undef FLD
2281 }
2282   NEXT (vpc);
2283
2284   CASE (sem, INSN_ST_PLUS) : /* st $src1,@+$src2 */
2285 {
2286   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2287   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2288 #define FLD(f) abuf->fields.fmt_st_plus.f
2289   int UNUSED written = 0;
2290   IADDR UNUSED pc = abuf->addr;
2291   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
2292
2293 do {
2294   SI tmp_new_src2;
2295   tmp_new_src2 = ADDSI (* FLD (i_src2), 4);
2296   {
2297     SI opval = * FLD (i_src1);
2298     SETMEMSI (current_cpu, pc, tmp_new_src2, opval);
2299     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
2300   }
2301   {
2302     SI opval = tmp_new_src2;
2303     * FLD (i_src2) = opval;
2304     TRACE_RESULT (current_cpu, abuf, "src2", 'x', opval);
2305   }
2306 } while (0);
2307
2308 #undef FLD
2309 }
2310   NEXT (vpc);
2311
2312   CASE (sem, INSN_ST_MINUS) : /* st $src1,@-$src2 */
2313 {
2314   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2315   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2316 #define FLD(f) abuf->fields.fmt_st_plus.f
2317   int UNUSED written = 0;
2318   IADDR UNUSED pc = abuf->addr;
2319   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
2320
2321 do {
2322   SI tmp_new_src2;
2323   tmp_new_src2 = SUBSI (* FLD (i_src2), 4);
2324   {
2325     SI opval = * FLD (i_src1);
2326     SETMEMSI (current_cpu, pc, tmp_new_src2, opval);
2327     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
2328   }
2329   {
2330     SI opval = tmp_new_src2;
2331     * FLD (i_src2) = opval;
2332     TRACE_RESULT (current_cpu, abuf, "src2", 'x', opval);
2333   }
2334 } while (0);
2335
2336 #undef FLD
2337 }
2338   NEXT (vpc);
2339
2340   CASE (sem, INSN_SUB) : /* sub $dr,$sr */
2341 {
2342   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2343   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2344 #define FLD(f) abuf->fields.fmt_add.f
2345   int UNUSED written = 0;
2346   IADDR UNUSED pc = abuf->addr;
2347   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
2348
2349   {
2350     SI opval = SUBSI (* FLD (i_dr), * FLD (i_sr));
2351     * FLD (i_dr) = opval;
2352     TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
2353   }
2354
2355 #undef FLD
2356 }
2357   NEXT (vpc);
2358
2359   CASE (sem, INSN_SUBV) : /* subv $dr,$sr */
2360 {
2361   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2362   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2363 #define FLD(f) abuf->fields.fmt_addv.f
2364   int UNUSED written = 0;
2365   IADDR UNUSED pc = abuf->addr;
2366   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
2367
2368 do {
2369   BI temp1;SI temp0;
2370   temp0 = SUBSI (* FLD (i_dr), * FLD (i_sr));
2371   temp1 = SUBOFSI (* FLD (i_dr), * FLD (i_sr), 0);
2372   {
2373     SI opval = temp0;
2374     * FLD (i_dr) = opval;
2375     TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
2376   }
2377   {
2378     BI opval = temp1;
2379     CPU (h_cond) = opval;
2380     TRACE_RESULT (current_cpu, abuf, "condbit", 'x', opval);
2381   }
2382 } while (0);
2383
2384 #undef FLD
2385 }
2386   NEXT (vpc);
2387
2388   CASE (sem, INSN_SUBX) : /* subx $dr,$sr */
2389 {
2390   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2391   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2392 #define FLD(f) abuf->fields.fmt_addx.f
2393   int UNUSED written = 0;
2394   IADDR UNUSED pc = abuf->addr;
2395   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
2396
2397 do {
2398   BI temp1;SI temp0;
2399   temp0 = SUBCSI (* FLD (i_dr), * FLD (i_sr), CPU (h_cond));
2400   temp1 = SUBCFSI (* FLD (i_dr), * FLD (i_sr), CPU (h_cond));
2401   {
2402     SI opval = temp0;
2403     * FLD (i_dr) = opval;
2404     TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
2405   }
2406   {
2407     BI opval = temp1;
2408     CPU (h_cond) = opval;
2409     TRACE_RESULT (current_cpu, abuf, "condbit", 'x', opval);
2410   }
2411 } while (0);
2412
2413 #undef FLD
2414 }
2415   NEXT (vpc);
2416
2417   CASE (sem, INSN_TRAP) : /* trap $uimm4 */
2418 {
2419   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2420   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2421 #define FLD(f) abuf->fields.cti.fields.fmt_trap.f
2422   int UNUSED written = 0;
2423   IADDR UNUSED pc = abuf->addr;
2424   SEM_BRANCH_INIT
2425   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
2426
2427 do {
2428   {
2429     USI opval = GET_H_CR (((UINT) 6));
2430     SET_H_CR (((UINT) 14), opval);
2431     TRACE_RESULT (current_cpu, abuf, "cr-14", 'x', opval);
2432   }
2433   {
2434     USI opval = ADDSI (pc, 4);
2435     SET_H_CR (((UINT) 6), opval);
2436     TRACE_RESULT (current_cpu, abuf, "cr-6", 'x', opval);
2437   }
2438   {
2439     UQI opval = CPU (h_bpsw);
2440     CPU (h_bbpsw) = opval;
2441     TRACE_RESULT (current_cpu, abuf, "bbpsw-0", 'x', opval);
2442   }
2443   {
2444     UQI opval = GET_H_PSW ();
2445     CPU (h_bpsw) = opval;
2446     TRACE_RESULT (current_cpu, abuf, "bpsw-0", 'x', opval);
2447   }
2448   {
2449     UQI opval = ANDQI (GET_H_PSW (), 128);
2450     SET_H_PSW (opval);
2451     TRACE_RESULT (current_cpu, abuf, "psw-0", 'x', opval);
2452   }
2453   {
2454     SI opval = m32r_trap (current_cpu, pc, FLD (f_uimm4));
2455     SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
2456     TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
2457   }
2458 } while (0);
2459
2460   SEM_BRANCH_FINI (vpc);
2461 #undef FLD
2462 }
2463   NEXT (vpc);
2464
2465   CASE (sem, INSN_UNLOCK) : /* unlock $src1,@$src2 */
2466 {
2467   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2468   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2469 #define FLD(f) abuf->fields.fmt_unlock.f
2470   int UNUSED written = 0;
2471   IADDR UNUSED pc = abuf->addr;
2472   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
2473
2474 do {
2475 if (CPU (h_lock)) {
2476   {
2477     SI opval = * FLD (i_src1);
2478     SETMEMSI (current_cpu, pc, * FLD (i_src2), opval);
2479     written |= (1 << 4);
2480     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
2481   }
2482 }
2483   {
2484     BI opval = 0;
2485     CPU (h_lock) = opval;
2486     TRACE_RESULT (current_cpu, abuf, "lock-0", 'x', opval);
2487   }
2488 } while (0);
2489
2490   abuf->written = written;
2491 #undef FLD
2492 }
2493   NEXT (vpc);
2494
2495
2496     }
2497   ENDSWITCH (sem) /* End of semantic switch.  */
2498
2499   /* At this point `vpc' contains the next insn to execute.  */
2500 }
2501
2502 #undef DEFINE_SWITCH
2503 #endif /* DEFINE_SWITCH */