sim/m32r/sim-if.c

   1 /* Main simulator entry points specific to the M32R.
   2    Copyright (C) 1996-2021 Free Software Foundation, Inc.
   3    Contributed by Cygnus Support.
   4
   5    This file is part of GDB, the GNU debugger.
   6
   7    This program is free software; you can redistribute it and/or modify
   8    it under the terms of the GNU General Public License as published by
   9    the Free Software Foundation; either version 3 of the License, or
  10    (at your option) any later version.
  11
  12    This program is distributed in the hope that it will be useful,
  13    but WITHOUT ANY WARRANTY; without even the implied warranty of
  14    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15    GNU General Public License for more details.
  16
  17    You should have received a copy of the GNU General Public License
  18    along with this program.  If not, see <http://www.gnu.org/licenses/>.  */
  19
  20 #include "sim-main.h"
  21 #include "sim-options.h"
  22 #include "libiberty.h"
  23 #include "bfd.h"
  24
  25 #include <string.h>
  26 #include <stdlib.h>
  27
  28 #include "dv-m32r_uart.h"
  29
  30 static void free_state (SIM_DESC);
  31 static void print_m32r_misc_cpu (SIM_CPU *cpu, int verbose);
  32 \f
  33 /* Cover function of sim_state_free to free the cpu buffers as well.  */
  34
  35 static void
  36 free_state (SIM_DESC sd)
  37 {
  38   if (STATE_MODULES (sd) != NULL)
  39     sim_module_uninstall (sd);
  40   sim_cpu_free_all (sd);
  41   sim_state_free (sd);
  42 }
  43
  44 /* Create an instance of the simulator.  */
  45
  46 SIM_DESC
  47 sim_open (kind, callback, abfd, argv)
  48      SIM_OPEN_KIND kind;
  49      host_callback *callback;
  50      struct bfd *abfd;
  51      char * const *argv;
  52 {
  53   SIM_DESC sd = sim_state_alloc (kind, callback);
  54   char c;
  55   int i;
  56
  57   /* The cpu data is kept in a separately allocated chunk of memory.  */
  58   if (sim_cpu_alloc_all (sd, 1, cgen_cpu_max_extra_bytes ()) != SIM_RC_OK)
  59     {
  60       free_state (sd);
  61       return 0;
  62     }
  63
  64   if (sim_pre_argv_init (sd, argv[0]) != SIM_RC_OK)
  65     {
  66       free_state (sd);
  67       return 0;
  68     }
  69
  70   /* The parser will print an error message for us, so we silently return.  */
  71   if (sim_parse_args (sd, argv) != SIM_RC_OK)
  72     {
  73       free_state (sd);
  74       return 0;
  75     }
  76
  77   /* Allocate a handler for the control registers and other devices
  78      if no memory for that range has been allocated by the user.
  79      All are allocated in one chunk to keep things from being
  80      unnecessarily complicated.
  81      TODO: Move these to the sim-model framework.  */
  82   sim_hw_parse (sd, "/core/%s/reg %#x %i", "m32r_uart", UART_BASE_ADDR, 0x100);
  83   sim_hw_parse (sd, "/core/%s/reg %#x %i", "m32r_cache", 0xfffffff0, 0x10);
  84
  85   /* Allocate core managed memory if none specified by user.
  86      Use address 4 here in case the user wanted address 0 unmapped.  */
  87   if (sim_core_read_buffer (sd, NULL, read_map, &c, 4, 1) == 0)
  88     sim_do_commandf (sd, "memory region 0,0x%x", M32R_DEFAULT_MEM_SIZE);
  89
  90   /* check for/establish the reference program image */
  91   if (sim_analyze_program (sd,
  92                            (STATE_PROG_ARGV (sd) != NULL
  93                             ? *STATE_PROG_ARGV (sd)
  94                             : NULL),
  95                            abfd) != SIM_RC_OK)
  96     {
  97       free_state (sd);
  98       return 0;
  99     }
 100
 101   /* Establish any remaining configuration options.  */
 102   if (sim_config (sd) != SIM_RC_OK)
 103     {
 104       free_state (sd);
 105       return 0;
 106     }
 107
 108   if (sim_post_argv_init (sd) != SIM_RC_OK)
 109     {
 110       free_state (sd);
 111       return 0;
 112     }
 113
 114   /* Open a copy of the cpu descriptor table.  */
 115   {
 116     CGEN_CPU_DESC cd = m32r_cgen_cpu_open_1 (STATE_ARCHITECTURE (sd)->printable_name,
 117                                              CGEN_ENDIAN_BIG);
 118     for (i = 0; i < MAX_NR_PROCESSORS; ++i)
 119       {
 120         SIM_CPU *cpu = STATE_CPU (sd, i);
 121         CPU_CPU_DESC (cpu) = cd;
 122         CPU_DISASSEMBLER (cpu) = sim_cgen_disassemble_insn;
 123       }
 124     m32r_cgen_init_dis (cd);
 125   }
 126
 127   /* Initialize various cgen things not done by common framework.
 128      Must be done after m32r_cgen_cpu_open.  */
 129   cgen_init (sd);
 130
 131   for (c = 0; c < MAX_NR_PROCESSORS; ++c)
 132     {
 133       /* Only needed for profiling, but the structure member is small.  */
 134       memset (CPU_M32R_MISC_PROFILE (STATE_CPU (sd, i)), 0,
 135               sizeof (* CPU_M32R_MISC_PROFILE (STATE_CPU (sd, i))));
 136       /* Hook in callback for reporting these stats */
 137       PROFILE_INFO_CPU_CALLBACK (CPU_PROFILE_DATA (STATE_CPU (sd, i)))
 138         = print_m32r_misc_cpu;
 139     }
 140
 141   return sd;
 142 }
 143 \f
 144 SIM_RC
 145 sim_create_inferior (sd, abfd, argv, envp)
 146      SIM_DESC sd;
 147      struct bfd *abfd;
 148      char * const *argv;
 149      char * const *envp;
 150 {
 151   SIM_CPU *current_cpu = STATE_CPU (sd, 0);
 152   SIM_ADDR addr;
 153
 154   if (abfd != NULL)
 155     addr = bfd_get_start_address (abfd);
 156   else
 157     addr = 0;
 158   sim_pc_set (current_cpu, addr);
 159
 160 #ifdef M32R_LINUX
 161   m32rbf_h_cr_set (current_cpu,
 162                     m32r_decode_gdb_ctrl_regnum(SPI_REGNUM), 0x1f00000);
 163   m32rbf_h_cr_set (current_cpu,
 164                     m32r_decode_gdb_ctrl_regnum(SPU_REGNUM), 0x1f00000);
 165 #endif
 166
 167   /* Standalone mode (i.e. `run`) will take care of the argv for us in
 168      sim_open() -> sim_parse_args().  But in debug mode (i.e. 'target sim'
 169      with `gdb`), we need to handle it because the user can change the
 170      argv on the fly via gdb's 'run'.  */
 171   if (STATE_PROG_ARGV (sd) != argv)
 172     {
 173       freeargv (STATE_PROG_ARGV (sd));
 174       STATE_PROG_ARGV (sd) = dupargv (argv);
 175     }
 176
 177   return SIM_RC_OK;
 178 }
 179
 180 /* PROFILE_CPU_CALLBACK */
 181
 182 static void
 183 print_m32r_misc_cpu (SIM_CPU *cpu, int verbose)
 184 {
 185   SIM_DESC sd = CPU_STATE (cpu);
 186   char buf[20];
 187
 188   if (CPU_PROFILE_FLAGS (cpu) [PROFILE_INSN_IDX])
 189     {
 190       sim_io_printf (sd, "Miscellaneous Statistics\n\n");
 191       sim_io_printf (sd, "  %-*s %s\n\n",
 192                      PROFILE_LABEL_WIDTH, "Fill nops:",
 193                      sim_add_commas (buf, sizeof (buf),
 194                                      CPU_M32R_MISC_PROFILE (cpu)->fillnop_count));
 195       if (STATE_ARCHITECTURE (sd)->mach == bfd_mach_m32rx)
 196         sim_io_printf (sd, "  %-*s %s\n\n",
 197                        PROFILE_LABEL_WIDTH, "Parallel insns:",
 198                        sim_add_commas (buf, sizeof (buf),
 199                                        CPU_M32R_MISC_PROFILE (cpu)->parallel_count));
 200       if (STATE_ARCHITECTURE (sd)->mach == bfd_mach_m32r2)
 201         sim_io_printf (sd, "  %-*s %s\n\n",
 202                        PROFILE_LABEL_WIDTH, "Parallel insns:",
 203                        sim_add_commas (buf, sizeof (buf),
 204                                        CPU_M32R_MISC_PROFILE (cpu)->parallel_count));
 205     }
 206 }