sim/m32r/traps.c

   1 /* m32r exception, interrupt, and trap (EIT) support
   2    Copyright (C) 1998 Free Software Foundation, Inc.
   3    Contributed by Cygnus Solutions.
   4
   5 This file is part of GDB, the GNU debugger.
   6
   7 This program is free software; you can redistribute it and/or modify
   8 it under the terms of the GNU General Public License as published by
   9 the Free Software Foundation; either version 2, or (at your option)
  10 any later version.
  11
  12 This program is distributed in the hope that it will be useful,
  13 but WITHOUT ANY WARRANTY; without even the implied warranty of
  14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15 GNU General Public License for more details.
  16
  17 You should have received a copy of the GNU General Public License along
  18 with this program; if not, write to the Free Software Foundation, Inc.,
  19 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
  20
  21 #include "sim-main.h"
  22 #include "targ-vals.h"
  23
  24 /* The semantic code invokes this for invalid (unrecognized) instructions.  */
  25
  26 void
  27 sim_engine_invalid_insn (SIM_CPU *current_cpu, IADDR cia)
  28 {
  29   SIM_DESC sd = CPU_STATE (current_cpu);
  30
  31 #if 0
  32   if (STATE_ENVIRONMENT (sd) == OPERATING_ENVIRONMENT)
  33     {
  34       h_bsm_set (current_cpu, h_sm_get (current_cpu));
  35       h_bie_set (current_cpu, h_ie_get (current_cpu));
  36       h_bcond_set (current_cpu, h_cond_get (current_cpu));
  37       /* sm not changed */
  38       h_ie_set (current_cpu, 0);
  39       h_cond_set (current_cpu, 0);
  40
  41       h_bpc_set (current_cpu, cia);
  42
  43       sim_engine_restart (CPU_STATE (current_cpu), current_cpu, NULL,
  44                           EIT_RSVD_INSN_ADDR);
  45     }
  46   else
  47 #endif
  48     sim_engine_halt (sd, current_cpu, NULL, cia, sim_stopped, SIM_SIGILL);
  49 }
  50
  51 /* Process an address exception.  */
  52
  53 void
  54 m32r_core_signal (SIM_DESC sd, SIM_CPU *current_cpu, sim_cia cia,
  55                   unsigned int map, int nr_bytes, address_word addr,
  56                   transfer_type transfer, sim_core_signals sig)
  57 {
  58   if (STATE_ENVIRONMENT (sd) == OPERATING_ENVIRONMENT)
  59     {
  60       a_m32r_h_cr_set (current_cpu, H_CR_BBPC,
  61                        a_m32r_h_cr_get (current_cpu, H_CR_BPC));
  62       a_m32r_h_bpsw_set (current_cpu, a_m32r_h_psw_get (current_cpu));
  63       /* sm not changed */
  64       a_m32r_h_psw_set (current_cpu, a_m32r_h_psw_get (current_cpu) & 0x80);
  65       a_m32r_h_cr_set (current_cpu, H_CR_BPC, cia);
  66
  67       sim_engine_restart (CPU_STATE (current_cpu), current_cpu, NULL,
  68                           EIT_ADDR_EXCP_ADDR);
  69     }
  70   else
  71     sim_core_signal (sd, current_cpu, cia, map, nr_bytes, addr,
  72                      transfer, sig);
  73 }
  74 \f
  75 /* Read/write functions for system call interface.  */
  76
  77 static int
  78 syscall_read_mem (host_callback *cb, struct cb_syscall *sc,
  79                   unsigned long taddr, char *buf, int bytes)
  80 {
  81   SIM_DESC sd = (SIM_DESC) sc->p1;
  82   SIM_CPU *cpu = (SIM_CPU *) sc->p2;
  83
  84   return sim_core_read_buffer (sd, cpu, read_map, buf, taddr, bytes);
  85 }
  86
  87 static int
  88 syscall_write_mem (host_callback *cb, struct cb_syscall *sc,
  89                    unsigned long taddr, const char *buf, int bytes)
  90 {
  91   SIM_DESC sd = (SIM_DESC) sc->p1;
  92   SIM_CPU *cpu = (SIM_CPU *) sc->p2;
  93
  94   return sim_core_write_buffer (sd, cpu, write_map, buf, taddr, bytes);
  95 }
  96
  97 /* Trap support.
  98    The result is the pc address to continue at.
  99    Preprocessing like saving the various registers has already been done.  */
 100
 101 USI
 102 m32r_trap (SIM_CPU *current_cpu, PCADDR pc, int num)
 103 {
 104   SIM_DESC sd = CPU_STATE (current_cpu);
 105   host_callback *cb = STATE_CALLBACK (sd);
 106
 107 #ifdef SIM_HAVE_BREAKPOINTS
 108   /* Check for breakpoints "owned" by the simulator first, regardless
 109      of --environment.  */
 110   if (num == TRAP_BREAKPOINT)
 111     {
 112       /* First try sim-break.c.  If it's a breakpoint the simulator "owns"
 113          it doesn't return.  Otherwise it returns and let's us try.  */
 114       sim_handle_breakpoint (sd, current_cpu, pc);
 115       /* Fall through.  */
 116     }
 117 #endif
 118
 119   if (STATE_ENVIRONMENT (sd) == OPERATING_ENVIRONMENT)
 120     {
 121       /* The new pc is the trap vector entry.
 122          We assume there's a branch there to some handler.  */
 123       USI new_pc = EIT_TRAP_BASE_ADDR + num * 4;
 124       return new_pc;
 125     }
 126
 127   switch (num)
 128     {
 129     case TRAP_SYSCALL :
 130       {
 131         CB_SYSCALL s;
 132
 133         CB_SYSCALL_INIT (&s);
 134         s.func = a_m32r_h_gr_get (current_cpu, 0);
 135         s.arg1 = a_m32r_h_gr_get (current_cpu, 1);
 136         s.arg2 = a_m32r_h_gr_get (current_cpu, 2);
 137         s.arg3 = a_m32r_h_gr_get (current_cpu, 3);
 138
 139         if (s.func == TARGET_SYS_exit)
 140           {
 141             sim_engine_halt (sd, current_cpu, NULL, pc, sim_exited, s.arg1);
 142           }
 143
 144         s.p1 = (PTR) sd;
 145         s.p2 = (PTR) current_cpu;
 146         s.read_mem = syscall_read_mem;
 147         s.write_mem = syscall_write_mem;
 148         cb_syscall (cb, &s);
 149         a_m32r_h_gr_set (current_cpu, 2, s.errcode);
 150         a_m32r_h_gr_set (current_cpu, 0, s.result);
 151         a_m32r_h_gr_set (current_cpu, 1, s.result2);
 152         break;
 153       }
 154
 155     case TRAP_BREAKPOINT:
 156       sim_engine_halt (sd, current_cpu, NULL, pc,
 157                        sim_stopped, SIM_SIGTRAP);
 158       break;
 159
 160     default :
 161       {
 162         USI new_pc = EIT_TRAP_BASE_ADDR + num * 4;
 163         return new_pc;
 164       }
 165     }
 166
 167   /* Fake an "rte" insn.  */
 168   /* FIXME: Should duplicate all of rte processing.  */
 169   return (pc & -4) + 4;
 170 }