sim/m68hc11/sim-main.h

   1 /* sim-main.h -- Simulator for Motorola 68HC11 & 68HC12
   2    Copyright (C) 1999-2013 Free Software Foundation, Inc.
   3    Written by Stephane Carrez (stcarrez@nerim.fr)
   4
   5 This file is part of GDB, the GNU debugger.
   6
   7 This program is free software; you can redistribute it and/or modify
   8 it under the terms of the GNU General Public License as published by
   9 the Free Software Foundation; either version 3 of the License, or
  10 (at your option) any later version.
  11
  12 This program is distributed in the hope that it will be useful,
  13 but WITHOUT ANY WARRANTY; without even the implied warranty of
  14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15 GNU General Public License for more details.
  16
  17 You should have received a copy of the GNU General Public License
  18 along with this program.  If not, see <http://www.gnu.org/licenses/>.  */
  19
  20 #ifndef _SIM_MAIN_H
  21 #define _SIM_MAIN_H
  22
  23 #define WITH_MODULO_MEMORY 1
  24 #define WITH_WATCHPOINTS 1
  25 #define SIM_HANDLES_LMA 1
  26
  27 #include "sim-basics.h"
  28
  29 typedef address_word sim_cia;
  30
  31 #include "sim-signal.h"
  32 #include "sim-base.h"
  33
  34 #include "bfd.h"
  35
  36 #include "opcode/m68hc11.h"
  37
  38 #include "gdb/callback.h"
  39 #include "gdb/remote-sim.h"
  40 #include "opcode/m68hc11.h"
  41 #include "sim-types.h"
  42
  43 typedef unsigned8 uint8;
  44 typedef unsigned16 uint16;
  45 typedef signed16 int16;
  46 typedef unsigned32 uint32;
  47 typedef signed32 int32;
  48 typedef unsigned64 uint64;
  49 typedef signed64 int64;
  50
  51 struct _sim_cpu;
  52
  53 #include "interrupts.h"
  54 #include <setjmp.h>
  55
  56 /* Specifies the level of mapping for the IO, EEprom, nvram and external
  57    RAM.  IO registers are mapped over everything and the external RAM
  58    is last (ie, it can be hidden by everything above it in the list).  */
  59 enum m68hc11_map_level
  60 {
  61   M6811_IO_LEVEL,
  62   M6811_EEPROM_LEVEL,
  63   M6811_NVRAM_LEVEL,
  64   M6811_RAM_LEVEL
  65 };
  66
  67 enum cpu_type
  68 {
  69   CPU_M6811,
  70   CPU_M6812
  71 };
  72
  73 #define X_REGNUM        0
  74 #define D_REGNUM        1
  75 #define Y_REGNUM        2
  76 #define SP_REGNUM       3
  77 #define PC_REGNUM       4
  78 #define A_REGNUM        5
  79 #define B_REGNUM        6
  80 #define PSW_REGNUM      7
  81 #define PAGE_REGNUM     8
  82 #define Z_REGNUM        9
  83
  84 typedef struct m6811_regs {
  85     unsigned short      d;
  86     unsigned short      ix;
  87     unsigned short      iy;
  88     unsigned short      sp;
  89     unsigned short      pc;
  90     unsigned char       ccr;
  91   unsigned short      page;
  92 } m6811_regs;
  93
  94
  95 /* Description of 68HC11 IO registers.  Such description is only provided
  96    for the info command to display the current setting of IO registers
  97    from GDB.  */
  98 struct io_reg_desc
  99 {
 100   int        mask;
 101   const char *short_name;
 102   const char *long_name;
 103 };
 104 typedef struct io_reg_desc io_reg_desc;
 105
 106 extern void print_io_reg_desc (SIM_DESC sd, io_reg_desc *desc, int val,
 107                                int mode);
 108 extern void print_io_byte (SIM_DESC sd, const char *name,
 109                            io_reg_desc *desc, uint8 val, uint16 addr);
 110 extern void print_io_word (SIM_DESC sd, const char *name,
 111                            io_reg_desc *desc, uint16 val, uint16 addr);
 112
 113
 114 /* List of special 68HC11&68HC12 instructions that are not handled by the
 115    'gencode.c' generator.  These complex instructions are implemented
 116    by 'cpu_special'.  */
 117 enum M6811_Special
 118 {
 119   /* 68HC11 instructions.  */
 120   M6811_DAA,
 121   M6811_EMUL_SYSCALL,
 122   M6811_ILLEGAL,
 123   M6811_RTI,
 124   M6811_STOP,
 125   M6811_SWI,
 126   M6811_TEST,
 127   M6811_WAI,
 128
 129   /* 68HC12 instructions.  */
 130   M6812_BGND,
 131   M6812_CALL,
 132   M6812_CALL_INDIRECT,
 133   M6812_IDIVS,
 134   M6812_EDIV,
 135   M6812_EDIVS,
 136   M6812_EMACS,
 137   M6812_EMUL,
 138   M6812_EMULS,
 139   M6812_ETBL,
 140   M6812_MEM,
 141   M6812_REV,
 142   M6812_REVW,
 143   M6812_RTC,
 144   M6812_RTI,
 145   M6812_WAV
 146 };
 147
 148 #define M6811_MAX_PORTS (0x03f+1)
 149 #define M6812_MAX_PORTS (0x3ff+1)
 150 #define MAX_PORTS       (M6812_MAX_PORTS)
 151
 152 struct _sim_cpu;
 153
 154 typedef void (* cpu_interp) (struct _sim_cpu*);
 155
 156 struct _sim_cpu {
 157   /* CPU registers.  */
 158   struct m6811_regs     cpu_regs;
 159
 160   /* CPU interrupts.  */
 161   struct interrupts     cpu_interrupts;
 162
 163   /* Pointer to the interpretor routine.  */
 164   cpu_interp            cpu_interpretor;
 165
 166   /* Pointer to the architecture currently configured in the simulator.  */
 167   const struct bfd_arch_info  *cpu_configured_arch;
 168
 169   /* CPU absolute cycle time.  The cycle time is updated after
 170      each instruction, by the number of cycles taken by the instruction.
 171      It is cleared only when reset occurs.  */
 172   signed64              cpu_absolute_cycle;
 173
 174   /* Number of cycles to increment after the current instruction.
 175      This is also the number of ticks for the generic event scheduler.  */
 176   uint8                 cpu_current_cycle;
 177   int                   cpu_emul_syscall;
 178   int                   cpu_is_initialized;
 179   int                   cpu_running;
 180   int                   cpu_check_memory;
 181   int                   cpu_stop_on_interrupt;
 182
 183   /* When this is set, start execution of program at address specified
 184      in the ELF header.  This is used for testing some programs that do not
 185      have an interrupt table linked with them.  Programs created during the
 186      GCC validation are like this. A normal 68HC11 does not behave like
 187      this (unless there is some OS or downloadable feature).  */
 188   int                   cpu_use_elf_start;
 189
 190   /* The starting address specified in ELF header.  */
 191   int                   cpu_elf_start;
 192
 193   uint16                cpu_insn_pc;
 194
 195   /* CPU frequency.  This is the quartz frequency.  It is divided by 4 to
 196      get the cycle time.  This is used for the timer rate and for the baud
 197      rate generation.  */
 198   unsigned long         cpu_frequency;
 199
 200   /* The mode in which the CPU is configured (MODA and MODB pins).  */
 201   unsigned int          cpu_mode;
 202   const char*           cpu_start_mode;
 203
 204   /* The cpu being configured.  */
 205   enum cpu_type         cpu_type;
 206
 207   /* Initial value of the CONFIG register.  */
 208   uint8                 cpu_config;
 209   uint8                 cpu_use_local_config;
 210
 211   uint8                 ios[MAX_PORTS];
 212
 213   /* Memory bank parameters which describe how the memory bank window
 214      is mapped in memory and how to convert it in virtual address.  */
 215   uint16                bank_start;
 216   uint16                bank_end;
 217   address_word          bank_virtual;
 218   unsigned              bank_shift;
 219
 220
 221   struct hw            *hw_cpu;
 222
 223   /* ... base type ... */
 224   sim_cpu_base base;
 225 };
 226
 227 /* Returns the cpu absolute cycle time (A virtual counter incremented
 228    at each 68HC11 E clock).  */
 229 #define cpu_current_cycle(PROC) ((PROC)->cpu_absolute_cycle)
 230 #define cpu_add_cycles(PROC,T)  ((PROC)->cpu_current_cycle += (signed64) (T))
 231 #define cpu_is_running(PROC)    ((PROC)->cpu_running)
 232
 233 /* Get the IO/RAM base addresses depending on the M6811_INIT register.  */
 234 #define cpu_get_io_base(PROC) \
 235         (((uint16)(((PROC)->ios[M6811_INIT]) & 0x0F))<<12)
 236 #define cpu_get_reg_base(PROC) \
 237         (((uint16)(((PROC)->ios[M6811_INIT]) & 0xF0))<<8)
 238
 239 /* Returns the different CPU registers.  */
 240 #define cpu_get_ccr(PROC)          ((PROC)->cpu_regs.ccr)
 241 #define cpu_get_pc(PROC)           ((PROC)->cpu_regs.pc)
 242 #define cpu_get_d(PROC)            ((PROC)->cpu_regs.d)
 243 #define cpu_get_x(PROC)            ((PROC)->cpu_regs.ix)
 244 #define cpu_get_y(PROC)            ((PROC)->cpu_regs.iy)
 245 #define cpu_get_sp(PROC)           ((PROC)->cpu_regs.sp)
 246 #define cpu_get_a(PROC)            ((PROC->cpu_regs.d >> 8) & 0x0FF)
 247 #define cpu_get_b(PROC)            ((PROC->cpu_regs.d) & 0x0FF)
 248 #define cpu_get_page(PROC)         ((PROC)->cpu_regs.page)
 249
 250 /* 68HC12 specific and Motorola internal registers.  */
 251 #define cpu_get_tmp3(PROC)         (0)
 252 #define cpu_get_tmp2(PROC)         (0)
 253
 254 #define cpu_set_d(PROC,VAL)        (((PROC)->cpu_regs.d) = (VAL))
 255 #define cpu_set_x(PROC,VAL)        (((PROC)->cpu_regs.ix) = (VAL))
 256 #define cpu_set_y(PROC,VAL)        (((PROC)->cpu_regs.iy) = (VAL))
 257 #define cpu_set_page(PROC,VAL)     (((PROC)->cpu_regs.page) = (VAL))
 258
 259 /* 68HC12 specific and Motorola internal registers.  */
 260 #define cpu_set_tmp3(PROC,VAL)     (0)
 261 #define cpu_set_tmp2(PROC,VAL)     (void) (0)
 262
 263 #if 0
 264 /* This is a function in m68hc11_sim.c to keep track of the frame.  */
 265 #define cpu_set_sp(PROC,VAL)       (((PROC)->cpu_regs.sp) = (VAL))
 266 #endif
 267
 268 #define cpu_set_pc(PROC,VAL)       (((PROC)->cpu_regs.pc) = (VAL))
 269
 270 #define cpu_set_a(PROC,VAL)  \
 271       cpu_set_d(PROC,((VAL) << 8) | cpu_get_b(PROC))
 272 #define cpu_set_b(PROC,VAL)  \
 273       cpu_set_d(PROC,((cpu_get_a(PROC)) << 8)|(VAL & 0x0FF))
 274
 275 #define cpu_set_ccr(PROC,VAL)      ((PROC)->cpu_regs.ccr = (VAL))
 276 #define cpu_get_ccr_H(PROC)        ((cpu_get_ccr(PROC) & M6811_H_BIT) ? 1: 0)
 277 #define cpu_get_ccr_X(PROC)        ((cpu_get_ccr(PROC) & M6811_X_BIT) ? 1: 0)
 278 #define cpu_get_ccr_S(PROC)        ((cpu_get_ccr(PROC) & M6811_S_BIT) ? 1: 0)
 279 #define cpu_get_ccr_N(PROC)        ((cpu_get_ccr(PROC) & M6811_N_BIT) ? 1: 0)
 280 #define cpu_get_ccr_V(PROC)        ((cpu_get_ccr(PROC) & M6811_V_BIT) ? 1: 0)
 281 #define cpu_get_ccr_C(PROC)        ((cpu_get_ccr(PROC) & M6811_C_BIT) ? 1: 0)
 282 #define cpu_get_ccr_Z(PROC)        ((cpu_get_ccr(PROC) & M6811_Z_BIT) ? 1: 0)
 283 #define cpu_get_ccr_I(PROC)        ((cpu_get_ccr(PROC) & M6811_I_BIT) ? 1: 0)
 284
 285 #define cpu_set_ccr_flag(S,B,V) \
 286 cpu_set_ccr(S,(cpu_get_ccr(S) & ~(B)) | ((V) ? B : 0))
 287
 288 #define cpu_set_ccr_H(PROC,VAL)    cpu_set_ccr_flag(PROC, M6811_H_BIT, VAL)
 289 #define cpu_set_ccr_X(PROC,VAL)    cpu_set_ccr_flag(PROC, M6811_X_BIT, VAL)
 290 #define cpu_set_ccr_S(PROC,VAL)    cpu_set_ccr_flag(PROC, M6811_S_BIT, VAL)
 291 #define cpu_set_ccr_N(PROC,VAL)    cpu_set_ccr_flag(PROC, M6811_N_BIT, VAL)
 292 #define cpu_set_ccr_V(PROC,VAL)    cpu_set_ccr_flag(PROC, M6811_V_BIT, VAL)
 293 #define cpu_set_ccr_C(PROC,VAL)    cpu_set_ccr_flag(PROC, M6811_C_BIT, VAL)
 294 #define cpu_set_ccr_Z(PROC,VAL)    cpu_set_ccr_flag(PROC, M6811_Z_BIT, VAL)
 295 #define cpu_set_ccr_I(PROC,VAL)    cpu_set_ccr_flag(PROC, M6811_I_BIT, VAL)
 296
 297 #undef inline
 298 #define inline static __inline__
 299
 300 extern void cpu_memory_exception (struct _sim_cpu *proc,
 301                                   SIM_SIGNAL excep,
 302                                   uint16 addr,
 303                                   const char *message);
 304
 305 inline address_word
 306 phys_to_virt (sim_cpu *cpu, address_word addr)
 307 {
 308   if (addr >= cpu->bank_start && addr < cpu->bank_end)
 309     return ((address_word) (addr - cpu->bank_start)
 310             + (((address_word) cpu->cpu_regs.page) << cpu->bank_shift)
 311             + cpu->bank_virtual);
 312   else
 313     return (address_word) (addr);
 314 }
 315
 316 inline uint8
 317 memory_read8 (sim_cpu *cpu, uint16 addr)
 318 {
 319   uint8 val;
 320
 321   if (sim_core_read_buffer (CPU_STATE (cpu), cpu, 0, &val, addr, 1) != 1)
 322     {
 323       cpu_memory_exception (cpu, SIM_SIGSEGV, addr,
 324                             "Read error");
 325     }
 326   return val;
 327 }
 328
 329 inline void
 330 memory_write8 (sim_cpu *cpu, uint16 addr, uint8 val)
 331 {
 332   if (sim_core_write_buffer (CPU_STATE (cpu), cpu, 0, &val, addr, 1) != 1)
 333     {
 334       cpu_memory_exception (cpu, SIM_SIGSEGV, addr,
 335                             "Write error");
 336     }
 337 }
 338
 339 inline uint16
 340 memory_read16 (sim_cpu *cpu, uint16 addr)
 341 {
 342   uint8 b[2];
 343
 344   if (sim_core_read_buffer (CPU_STATE (cpu), cpu, 0, b, addr, 2) != 2)
 345     {
 346       cpu_memory_exception (cpu, SIM_SIGSEGV, addr,
 347                             "Read error");
 348     }
 349   return (((uint16) (b[0])) << 8) | ((uint16) b[1]);
 350 }
 351
 352 inline void
 353 memory_write16 (sim_cpu *cpu, uint16 addr, uint16 val)
 354 {
 355   uint8 b[2];
 356
 357   b[0] = val >> 8;
 358   b[1] = val;
 359   if (sim_core_write_buffer (CPU_STATE (cpu), cpu, 0, b, addr, 2) != 2)
 360     {
 361       cpu_memory_exception (cpu, SIM_SIGSEGV, addr,
 362                             "Write error");
 363     }
 364 }
 365 extern void
 366 cpu_ccr_update_tst8 (sim_cpu *proc, uint8 val);
 367
 368      inline void
 369 cpu_ccr_update_tst16 (sim_cpu *proc, uint16 val)
 370 {
 371   cpu_set_ccr_V (proc, 0);
 372   cpu_set_ccr_N (proc, val & 0x8000 ? 1 : 0);
 373   cpu_set_ccr_Z (proc, val == 0 ? 1 : 0);
 374 }
 375
 376      inline void
 377 cpu_ccr_update_shift8 (sim_cpu *proc, uint8 val)
 378 {
 379   cpu_set_ccr_N (proc, val & 0x80 ? 1 : 0);
 380   cpu_set_ccr_Z (proc, val == 0 ? 1 : 0);
 381   cpu_set_ccr_V (proc, cpu_get_ccr_N (proc) ^ cpu_get_ccr_C (proc));
 382 }
 383
 384      inline void
 385 cpu_ccr_update_shift16 (sim_cpu *proc, uint16 val)
 386 {
 387   cpu_set_ccr_N (proc, val & 0x8000 ? 1 : 0);
 388   cpu_set_ccr_Z (proc, val == 0 ? 1 : 0);
 389   cpu_set_ccr_V (proc, cpu_get_ccr_N (proc) ^ cpu_get_ccr_C (proc));
 390 }
 391
 392 inline void
 393 cpu_ccr_update_add8 (sim_cpu *proc, uint8 r, uint8 a, uint8 b)
 394 {
 395   cpu_set_ccr_C (proc, ((a & b) | (b & ~r) | (a & ~r)) & 0x80 ? 1 : 0);
 396   cpu_set_ccr_V (proc, ((a & b & ~r) | (~a & ~b & r)) & 0x80 ? 1 : 0);
 397   cpu_set_ccr_Z (proc, r == 0);
 398   cpu_set_ccr_N (proc, r & 0x80 ? 1 : 0);
 399 }
 400
 401
 402 inline void
 403 cpu_ccr_update_sub8 (sim_cpu *proc, uint8 r, uint8 a, uint8 b)
 404 {
 405   cpu_set_ccr_C (proc, ((~a & b) | (b & r) | (~a & r)) & 0x80 ? 1 : 0);
 406   cpu_set_ccr_V (proc, ((a & ~b & ~r) | (~a & b & r)) & 0x80 ? 1 : 0);
 407   cpu_set_ccr_Z (proc, r == 0);
 408   cpu_set_ccr_N (proc, r & 0x80 ? 1 : 0);
 409 }
 410
 411 inline void
 412 cpu_ccr_update_add16 (sim_cpu *proc, uint16 r, uint16 a, uint16 b)
 413 {
 414   cpu_set_ccr_C (proc, ((a & b) | (b & ~r) | (a & ~r)) & 0x8000 ? 1 : 0);
 415   cpu_set_ccr_V (proc, ((a & b & ~r) | (~a & ~b & r)) & 0x8000 ? 1 : 0);
 416   cpu_set_ccr_Z (proc, r == 0);
 417   cpu_set_ccr_N (proc, r & 0x8000 ? 1 : 0);
 418 }
 419
 420 inline void
 421 cpu_ccr_update_sub16 (sim_cpu *proc, uint16 r, uint16 a, uint16 b)
 422 {
 423   cpu_set_ccr_C (proc, ((~a & b) | (b & r) | (~a & r)) & 0x8000 ? 1 : 0);
 424   cpu_set_ccr_V (proc, ((a & ~b & ~r) | (~a & b & r)) & 0x8000 ? 1 : 0);
 425   cpu_set_ccr_Z (proc, r == 0);
 426   cpu_set_ccr_N (proc, r & 0x8000 ? 1 : 0);
 427 }
 428
 429 /* Push and pop instructions for 68HC11 (next-available stack mode).  */
 430 inline void
 431 cpu_m68hc11_push_uint8 (sim_cpu *proc, uint8 val)
 432 {
 433   uint16 addr = proc->cpu_regs.sp;
 434
 435   memory_write8 (proc, addr, val);
 436   proc->cpu_regs.sp = addr - 1;
 437 }
 438
 439 inline void
 440 cpu_m68hc11_push_uint16 (sim_cpu *proc, uint16 val)
 441 {
 442   uint16 addr = proc->cpu_regs.sp - 1;
 443
 444   memory_write16 (proc, addr, val);
 445   proc->cpu_regs.sp = addr - 1;
 446 }
 447
 448 inline uint8
 449 cpu_m68hc11_pop_uint8 (sim_cpu *proc)
 450 {
 451   uint16 addr = proc->cpu_regs.sp;
 452   uint8 val;
 453
 454   val = memory_read8 (proc, addr + 1);
 455   proc->cpu_regs.sp = addr + 1;
 456   return val;
 457 }
 458
 459 inline uint16
 460 cpu_m68hc11_pop_uint16 (sim_cpu *proc)
 461 {
 462   uint16 addr = proc->cpu_regs.sp;
 463   uint16 val;
 464
 465   val = memory_read16 (proc, addr + 1);
 466   proc->cpu_regs.sp = addr + 2;
 467   return val;
 468 }
 469
 470 /* Push and pop instructions for 68HC12 (last-used stack mode).  */
 471 inline void
 472 cpu_m68hc12_push_uint8 (sim_cpu *proc, uint8 val)
 473 {
 474   uint16 addr = proc->cpu_regs.sp;
 475
 476   addr --;
 477   memory_write8 (proc, addr, val);
 478   proc->cpu_regs.sp = addr;
 479 }
 480
 481 inline void
 482 cpu_m68hc12_push_uint16 (sim_cpu *proc, uint16 val)
 483 {
 484   uint16 addr = proc->cpu_regs.sp;
 485
 486   addr -= 2;
 487   memory_write16 (proc, addr, val);
 488   proc->cpu_regs.sp = addr;
 489 }
 490
 491 inline uint8
 492 cpu_m68hc12_pop_uint8 (sim_cpu *proc)
 493 {
 494   uint16 addr = proc->cpu_regs.sp;
 495   uint8 val;
 496
 497   val = memory_read8 (proc, addr);
 498   proc->cpu_regs.sp = addr + 1;
 499   return val;
 500 }
 501
 502 inline uint16
 503 cpu_m68hc12_pop_uint16 (sim_cpu *proc)
 504 {
 505   uint16 addr = proc->cpu_regs.sp;
 506   uint16 val;
 507
 508   val = memory_read16 (proc, addr);
 509   proc->cpu_regs.sp = addr + 2;
 510   return val;
 511 }
 512
 513 /* Fetch a 8/16 bit value and update the PC.  */
 514 inline uint8
 515 cpu_fetch8 (sim_cpu *proc)
 516 {
 517   uint16 addr = proc->cpu_regs.pc;
 518   uint8 val;
 519
 520   val = memory_read8 (proc, addr);
 521   proc->cpu_regs.pc = addr + 1;
 522   return val;
 523 }
 524
 525 inline uint16
 526 cpu_fetch16 (sim_cpu *proc)
 527 {
 528   uint16 addr = proc->cpu_regs.pc;
 529   uint16 val;
 530
 531   val = memory_read16 (proc, addr);
 532   proc->cpu_regs.pc = addr + 2;
 533   return val;
 534 }
 535
 536 extern void cpu_call (sim_cpu* proc, uint16 addr);
 537 extern void cpu_exg (sim_cpu* proc, uint8 code);
 538 extern void cpu_dbcc (sim_cpu* proc);
 539 extern void cpu_special (sim_cpu *proc, enum M6811_Special special);
 540 extern void cpu_move8 (sim_cpu *proc, uint8 op);
 541 extern void cpu_move16 (sim_cpu *proc, uint8 op);
 542
 543 extern uint16 cpu_fetch_relbranch (sim_cpu *proc);
 544 extern uint16 cpu_fetch_relbranch16 (sim_cpu *proc);
 545 extern void cpu_push_all (sim_cpu *proc);
 546 extern void cpu_single_step (sim_cpu *proc);
 547
 548 extern void cpu_info (SIM_DESC sd, sim_cpu *proc);
 549
 550 extern int cpu_initialize (SIM_DESC sd, sim_cpu *cpu);
 551
 552 /* Returns the address of a 68HC12 indexed operand.
 553    Pre and post modifications are handled on the source register.  */
 554 extern uint16 cpu_get_indexed_operand_addr (sim_cpu* cpu, int restrict);
 555
 556 extern void cpu_return (sim_cpu *cpu);
 557 extern void cpu_set_sp (sim_cpu *cpu, uint16 val);
 558 extern int cpu_reset (sim_cpu *cpu);
 559 extern int cpu_restart (sim_cpu *cpu);
 560 extern void sim_memory_error (sim_cpu *cpu, SIM_SIGNAL excep,
 561                               uint16 addr, const char *message, ...);
 562 extern void emul_os (int op, sim_cpu *cpu);
 563 extern void cpu_interp_m6811 (sim_cpu *cpu);
 564 extern void cpu_interp_m6812 (sim_cpu *cpu);
 565
 566 extern int m68hc11cpu_set_oscillator (SIM_DESC sd, const char *port,
 567                                       double ton, double toff,
 568                                       signed64 repeat);
 569 extern int m68hc11cpu_clear_oscillator (SIM_DESC sd, const char *port);
 570 extern void m68hc11cpu_set_port (struct hw *me, sim_cpu *cpu,
 571                                  unsigned addr, uint8 val);
 572
 573 /* The current state of the processor; registers, memory, etc.  */
 574
 575 #define CIA_GET(CPU)      (cpu_get_pc (CPU))
 576 #define CIA_SET(CPU,VAL)  (cpu_set_pc ((CPU), (VAL)))
 577
 578 #if (WITH_SMP)
 579 #define STATE_CPU(sd,n) (&(sd)->cpu[n])
 580 #else
 581 #define STATE_CPU(sd,n) (&(sd)->cpu[0])
 582 #endif
 583
 584 struct sim_state {
 585   sim_cpu        cpu[MAX_NR_PROCESSORS];
 586   device         *devices;
 587   sim_state_base base;
 588 };
 589
 590 extern void sim_set_profile (int n);
 591 extern void sim_set_profile_size (int n);
 592 extern void sim_board_reset (SIM_DESC sd);
 593
 594 #define PRINT_TIME  0x01
 595 #define PRINT_CYCLE 0x02
 596 extern const char *cycle_to_string (sim_cpu *cpu, signed64 t, int flags);
 597
 598 #endif
 599
 600