sim/m68hc11/sim-main.h

   1 /* sim-main.h -- Simulator for Motorola 68HC11 & 68HC12
   2    Copyright (C) 1999-2021 Free Software Foundation, Inc.
   3    Written by Stephane Carrez (stcarrez@nerim.fr)
   4
   5 This file is part of GDB, the GNU debugger.
   6
   7 This program is free software; you can redistribute it and/or modify
   8 it under the terms of the GNU General Public License as published by
   9 the Free Software Foundation; either version 3 of the License, or
  10 (at your option) any later version.
  11
  12 This program is distributed in the hope that it will be useful,
  13 but WITHOUT ANY WARRANTY; without even the implied warranty of
  14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15 GNU General Public License for more details.
  16
  17 You should have received a copy of the GNU General Public License
  18 along with this program.  If not, see <http://www.gnu.org/licenses/>.  */
  19
  20 #ifndef _SIM_MAIN_H
  21 #define _SIM_MAIN_H
  22
  23 #include "sim-basics.h"
  24 #include "sim-base.h"
  25
  26 #include "bfd.h"
  27
  28 #include "opcode/m68hc11.h"
  29
  30 #include "sim/sim.h"
  31 #include "opcode/m68hc11.h"
  32 #include "sim-signal.h"
  33 #include "sim-types.h"
  34
  35 typedef unsigned8 uint8;
  36 typedef unsigned16 uint16;
  37 typedef signed16 int16;
  38 typedef unsigned32 uint32;
  39 typedef signed32 int32;
  40 typedef unsigned64 uint64;
  41 typedef signed64 int64;
  42
  43 struct _sim_cpu;
  44
  45 #include "interrupts.h"
  46 #include <setjmp.h>
  47
  48 /* Specifies the level of mapping for the IO, EEprom, nvram and external
  49    RAM.  IO registers are mapped over everything and the external RAM
  50    is last (ie, it can be hidden by everything above it in the list).  */
  51 enum m68hc11_map_level
  52 {
  53   M6811_IO_LEVEL,
  54   M6811_EEPROM_LEVEL,
  55   M6811_NVRAM_LEVEL,
  56   M6811_RAM_LEVEL
  57 };
  58
  59 enum cpu_type
  60 {
  61   CPU_M6811,
  62   CPU_M6812
  63 };
  64
  65 #define X_REGNUM        0
  66 #define D_REGNUM        1
  67 #define Y_REGNUM        2
  68 #define SP_REGNUM       3
  69 #define PC_REGNUM       4
  70 #define A_REGNUM        5
  71 #define B_REGNUM        6
  72 #define PSW_REGNUM      7
  73 #define PAGE_REGNUM     8
  74 #define Z_REGNUM        9
  75
  76 typedef struct m6811_regs {
  77     unsigned short      d;
  78     unsigned short      ix;
  79     unsigned short      iy;
  80     unsigned short      sp;
  81     unsigned short      pc;
  82     unsigned char       ccr;
  83   unsigned short      page;
  84 } m6811_regs;
  85
  86
  87 /* Description of 68HC11 IO registers.  Such description is only provided
  88    for the info command to display the current setting of IO registers
  89    from GDB.  */
  90 struct io_reg_desc
  91 {
  92   int        mask;
  93   const char *short_name;
  94   const char *long_name;
  95 };
  96 typedef struct io_reg_desc io_reg_desc;
  97
  98 extern void print_io_reg_desc (SIM_DESC sd, io_reg_desc *desc, int val,
  99                                int mode);
 100 extern void print_io_byte (SIM_DESC sd, const char *name,
 101                            io_reg_desc *desc, uint8 val, uint16 addr);
 102 extern void print_io_word (SIM_DESC sd, const char *name,
 103                            io_reg_desc *desc, uint16 val, uint16 addr);
 104
 105
 106 /* List of special 68HC11&68HC12 instructions that are not handled by the
 107    'gencode.c' generator.  These complex instructions are implemented
 108    by 'cpu_special'.  */
 109 enum M6811_Special
 110 {
 111   /* 68HC11 instructions.  */
 112   M6811_DAA,
 113   M6811_EMUL_SYSCALL,
 114   M6811_ILLEGAL,
 115   M6811_RTI,
 116   M6811_STOP,
 117   M6811_SWI,
 118   M6811_TEST,
 119   M6811_WAI,
 120
 121   /* 68HC12 instructions.  */
 122   M6812_BGND,
 123   M6812_CALL,
 124   M6812_CALL_INDIRECT,
 125   M6812_IDIVS,
 126   M6812_EDIV,
 127   M6812_EDIVS,
 128   M6812_EMACS,
 129   M6812_EMUL,
 130   M6812_EMULS,
 131   M6812_ETBL,
 132   M6812_MEM,
 133   M6812_REV,
 134   M6812_REVW,
 135   M6812_RTC,
 136   M6812_RTI,
 137   M6812_WAV
 138 };
 139
 140 #define M6811_MAX_PORTS (0x03f+1)
 141 #define M6812_MAX_PORTS (0x3ff+1)
 142 #define MAX_PORTS       (M6812_MAX_PORTS)
 143
 144 struct _sim_cpu;
 145
 146 typedef void (* cpu_interp) (struct _sim_cpu*);
 147
 148 struct _sim_cpu {
 149   /* CPU registers.  */
 150   struct m6811_regs     cpu_regs;
 151
 152   /* CPU interrupts.  */
 153   struct interrupts     cpu_interrupts;
 154
 155   /* Pointer to the interpretor routine.  */
 156   cpu_interp            cpu_interpretor;
 157
 158   /* Pointer to the architecture currently configured in the simulator.  */
 159   const struct bfd_arch_info  *cpu_configured_arch;
 160
 161   /* CPU absolute cycle time.  The cycle time is updated after
 162      each instruction, by the number of cycles taken by the instruction.
 163      It is cleared only when reset occurs.  */
 164   signed64              cpu_absolute_cycle;
 165
 166   /* Number of cycles to increment after the current instruction.
 167      This is also the number of ticks for the generic event scheduler.  */
 168   uint8                 cpu_current_cycle;
 169   int                   cpu_emul_syscall;
 170   int                   cpu_is_initialized;
 171   int                   cpu_running;
 172   int                   cpu_check_memory;
 173   int                   cpu_stop_on_interrupt;
 174
 175   /* When this is set, start execution of program at address specified
 176      in the ELF header.  This is used for testing some programs that do not
 177      have an interrupt table linked with them.  Programs created during the
 178      GCC validation are like this. A normal 68HC11 does not behave like
 179      this (unless there is some OS or downloadable feature).  */
 180   int                   cpu_use_elf_start;
 181
 182   /* The starting address specified in ELF header.  */
 183   int                   cpu_elf_start;
 184
 185   uint16                cpu_insn_pc;
 186
 187   /* CPU frequency.  This is the quartz frequency.  It is divided by 4 to
 188      get the cycle time.  This is used for the timer rate and for the baud
 189      rate generation.  */
 190   unsigned long         cpu_frequency;
 191
 192   /* The mode in which the CPU is configured (MODA and MODB pins).  */
 193   unsigned int          cpu_mode;
 194   const char*           cpu_start_mode;
 195
 196   /* The cpu being configured.  */
 197   enum cpu_type         cpu_type;
 198
 199   /* Initial value of the CONFIG register.  */
 200   uint8                 cpu_config;
 201   uint8                 cpu_use_local_config;
 202
 203   uint8                 ios[MAX_PORTS];
 204
 205   /* Memory bank parameters which describe how the memory bank window
 206      is mapped in memory and how to convert it in virtual address.  */
 207   uint16                bank_start;
 208   uint16                bank_end;
 209   address_word          bank_virtual;
 210   unsigned              bank_shift;
 211
 212
 213   struct hw            *hw_cpu;
 214
 215   /* ... base type ... */
 216   sim_cpu_base base;
 217 };
 218
 219 /* Returns the cpu absolute cycle time (A virtual counter incremented
 220    at each 68HC11 E clock).  */
 221 #define cpu_current_cycle(cpu)    ((cpu)->cpu_absolute_cycle)
 222 #define cpu_add_cycles(cpu, T)    ((cpu)->cpu_current_cycle += (signed64) (T))
 223 #define cpu_is_running(cpu)       ((cpu)->cpu_running)
 224
 225 /* Get the IO/RAM base addresses depending on the M6811_INIT register.  */
 226 #define cpu_get_io_base(cpu) \
 227   (((uint16)(((cpu)->ios[M6811_INIT]) & 0x0F)) << 12)
 228 #define cpu_get_reg_base(cpu) \
 229   (((uint16)(((cpu)->ios[M6811_INIT]) & 0xF0)) << 8)
 230
 231 /* Returns the different CPU registers.  */
 232 #define cpu_get_ccr(cpu)          ((cpu)->cpu_regs.ccr)
 233 #define cpu_get_pc(cpu)           ((cpu)->cpu_regs.pc)
 234 #define cpu_get_d(cpu)            ((cpu)->cpu_regs.d)
 235 #define cpu_get_x(cpu)            ((cpu)->cpu_regs.ix)
 236 #define cpu_get_y(cpu)            ((cpu)->cpu_regs.iy)
 237 #define cpu_get_sp(cpu)           ((cpu)->cpu_regs.sp)
 238 #define cpu_get_a(cpu)            (((cpu)->cpu_regs.d >> 8) & 0x0FF)
 239 #define cpu_get_b(cpu)            ((cpu)->cpu_regs.d & 0x0FF)
 240 #define cpu_get_page(cpu)         ((cpu)->cpu_regs.page)
 241
 242 /* 68HC12 specific and Motorola internal registers.  */
 243 #define cpu_get_tmp3(cpu)         (0)
 244 #define cpu_get_tmp2(cpu)         (0)
 245
 246 #define cpu_set_d(cpu, val)       ((cpu)->cpu_regs.d = (val))
 247 #define cpu_set_x(cpu, val)       ((cpu)->cpu_regs.ix = (val))
 248 #define cpu_set_y(cpu, val)       ((cpu)->cpu_regs.iy = (val))
 249 #define cpu_set_page(cpu, val)    ((cpu)->cpu_regs.page = (val))
 250
 251 /* 68HC12 specific and Motorola internal registers.  */
 252 #define cpu_set_tmp3(cpu, val)    (0)
 253 #define cpu_set_tmp2(cpu, val)    (void) (0)
 254
 255 #if 0
 256 /* This is a function in m68hc11_sim.c to keep track of the frame.  */
 257 #define cpu_set_sp(cpu, val)      ((cpu)->cpu_regs.sp = (val))
 258 #endif
 259
 260 #define cpu_set_pc(cpu, val)      ((cpu)->cpu_regs.pc = (val))
 261
 262 #define cpu_set_a(cpu, val)  \
 263   cpu_set_d(cpu, ((val) << 8) | cpu_get_b (cpu))
 264 #define cpu_set_b(cpu, val)  \
 265   cpu_set_d(cpu, ((cpu_get_a (cpu)) << 8) | ((val) & 0x0FF))
 266
 267 #define cpu_set_ccr(cpu, val)     ((cpu)->cpu_regs.ccr = (val))
 268 #define cpu_get_ccr_H(cpu)        ((cpu_get_ccr (cpu) & M6811_H_BIT) ? 1 : 0)
 269 #define cpu_get_ccr_X(cpu)        ((cpu_get_ccr (cpu) & M6811_X_BIT) ? 1 : 0)
 270 #define cpu_get_ccr_S(cpu)        ((cpu_get_ccr (cpu) & M6811_S_BIT) ? 1 : 0)
 271 #define cpu_get_ccr_N(cpu)        ((cpu_get_ccr (cpu) & M6811_N_BIT) ? 1 : 0)
 272 #define cpu_get_ccr_V(cpu)        ((cpu_get_ccr (cpu) & M6811_V_BIT) ? 1 : 0)
 273 #define cpu_get_ccr_C(cpu)        ((cpu_get_ccr (cpu) & M6811_C_BIT) ? 1 : 0)
 274 #define cpu_get_ccr_Z(cpu)        ((cpu_get_ccr (cpu) & M6811_Z_BIT) ? 1 : 0)
 275 #define cpu_get_ccr_I(cpu)        ((cpu_get_ccr (cpu) & M6811_I_BIT) ? 1 : 0)
 276
 277 #define cpu_set_ccr_flag(S, B, V) \
 278   cpu_set_ccr (S, (cpu_get_ccr (S) & ~(B)) | ((V) ? (B) : 0))
 279
 280 #define cpu_set_ccr_H(cpu, val)   cpu_set_ccr_flag (cpu, M6811_H_BIT, val)
 281 #define cpu_set_ccr_X(cpu, val)   cpu_set_ccr_flag (cpu, M6811_X_BIT, val)
 282 #define cpu_set_ccr_S(cpu, val)   cpu_set_ccr_flag (cpu, M6811_S_BIT, val)
 283 #define cpu_set_ccr_N(cpu, val)   cpu_set_ccr_flag (cpu, M6811_N_BIT, val)
 284 #define cpu_set_ccr_V(cpu, val)   cpu_set_ccr_flag (cpu, M6811_V_BIT, val)
 285 #define cpu_set_ccr_C(cpu, val)   cpu_set_ccr_flag (cpu, M6811_C_BIT, val)
 286 #define cpu_set_ccr_Z(cpu, val)   cpu_set_ccr_flag (cpu, M6811_Z_BIT, val)
 287 #define cpu_set_ccr_I(cpu, val)   cpu_set_ccr_flag (cpu, M6811_I_BIT, val)
 288
 289 extern void cpu_memory_exception (sim_cpu *cpu,
 290                                   SIM_SIGNAL excep,
 291                                   uint16 addr,
 292                                   const char *message);
 293
 294 STATIC_INLINE address_word
 295 phys_to_virt (sim_cpu *cpu, address_word addr)
 296 {
 297   if (addr >= cpu->bank_start && addr < cpu->bank_end)
 298     return ((address_word) (addr - cpu->bank_start)
 299             + (((address_word) cpu->cpu_regs.page) << cpu->bank_shift)
 300             + cpu->bank_virtual);
 301   else
 302     return (address_word) (addr);
 303 }
 304
 305 STATIC_INLINE uint8
 306 memory_read8 (sim_cpu *cpu, uint16 addr)
 307 {
 308   uint8 val;
 309
 310   if (sim_core_read_buffer (CPU_STATE (cpu), cpu, 0, &val, addr, 1) != 1)
 311     {
 312       cpu_memory_exception (cpu, SIM_SIGSEGV, addr,
 313                             "Read error");
 314     }
 315   return val;
 316 }
 317
 318 STATIC_INLINE void
 319 memory_write8 (sim_cpu *cpu, uint16 addr, uint8 val)
 320 {
 321   if (sim_core_write_buffer (CPU_STATE (cpu), cpu, 0, &val, addr, 1) != 1)
 322     {
 323       cpu_memory_exception (cpu, SIM_SIGSEGV, addr,
 324                             "Write error");
 325     }
 326 }
 327
 328 STATIC_INLINE uint16
 329 memory_read16 (sim_cpu *cpu, uint16 addr)
 330 {
 331   uint8 b[2];
 332
 333   if (sim_core_read_buffer (CPU_STATE (cpu), cpu, 0, b, addr, 2) != 2)
 334     {
 335       cpu_memory_exception (cpu, SIM_SIGSEGV, addr,
 336                             "Read error");
 337     }
 338   return (((uint16) (b[0])) << 8) | ((uint16) b[1]);
 339 }
 340
 341 STATIC_INLINE void
 342 memory_write16 (sim_cpu *cpu, uint16 addr, uint16 val)
 343 {
 344   uint8 b[2];
 345
 346   b[0] = val >> 8;
 347   b[1] = val;
 348   if (sim_core_write_buffer (CPU_STATE (cpu), cpu, 0, b, addr, 2) != 2)
 349     {
 350       cpu_memory_exception (cpu, SIM_SIGSEGV, addr,
 351                             "Write error");
 352     }
 353 }
 354 extern void
 355 cpu_ccr_update_tst8 (sim_cpu *cpu, uint8 val);
 356
 357 STATIC_INLINE void
 358 cpu_ccr_update_tst16 (sim_cpu *cpu, uint16 val)
 359 {
 360   cpu_set_ccr_V (cpu, 0);
 361   cpu_set_ccr_N (cpu, val & 0x8000 ? 1 : 0);
 362   cpu_set_ccr_Z (cpu, val == 0 ? 1 : 0);
 363 }
 364
 365 STATIC_INLINE void
 366 cpu_ccr_update_shift8 (sim_cpu *cpu, uint8 val)
 367 {
 368   cpu_set_ccr_N (cpu, val & 0x80 ? 1 : 0);
 369   cpu_set_ccr_Z (cpu, val == 0 ? 1 : 0);
 370   cpu_set_ccr_V (cpu, cpu_get_ccr_N (cpu) ^ cpu_get_ccr_C (cpu));
 371 }
 372
 373 STATIC_INLINE void
 374 cpu_ccr_update_shift16 (sim_cpu *cpu, uint16 val)
 375 {
 376   cpu_set_ccr_N (cpu, val & 0x8000 ? 1 : 0);
 377   cpu_set_ccr_Z (cpu, val == 0 ? 1 : 0);
 378   cpu_set_ccr_V (cpu, cpu_get_ccr_N (cpu) ^ cpu_get_ccr_C (cpu));
 379 }
 380
 381 STATIC_INLINE void
 382 cpu_ccr_update_add8 (sim_cpu *cpu, uint8 r, uint8 a, uint8 b)
 383 {
 384   cpu_set_ccr_C (cpu, ((a & b) | (b & ~r) | (a & ~r)) & 0x80 ? 1 : 0);
 385   cpu_set_ccr_V (cpu, ((a & b & ~r) | (~a & ~b & r)) & 0x80 ? 1 : 0);
 386   cpu_set_ccr_Z (cpu, r == 0);
 387   cpu_set_ccr_N (cpu, r & 0x80 ? 1 : 0);
 388 }
 389
 390
 391 STATIC_INLINE void
 392 cpu_ccr_update_sub8 (sim_cpu *cpu, uint8 r, uint8 a, uint8 b)
 393 {
 394   cpu_set_ccr_C (cpu, ((~a & b) | (b & r) | (~a & r)) & 0x80 ? 1 : 0);
 395   cpu_set_ccr_V (cpu, ((a & ~b & ~r) | (~a & b & r)) & 0x80 ? 1 : 0);
 396   cpu_set_ccr_Z (cpu, r == 0);
 397   cpu_set_ccr_N (cpu, r & 0x80 ? 1 : 0);
 398 }
 399
 400 STATIC_INLINE void
 401 cpu_ccr_update_add16 (sim_cpu *cpu, uint16 r, uint16 a, uint16 b)
 402 {
 403   cpu_set_ccr_C (cpu, ((a & b) | (b & ~r) | (a & ~r)) & 0x8000 ? 1 : 0);
 404   cpu_set_ccr_V (cpu, ((a & b & ~r) | (~a & ~b & r)) & 0x8000 ? 1 : 0);
 405   cpu_set_ccr_Z (cpu, r == 0);
 406   cpu_set_ccr_N (cpu, r & 0x8000 ? 1 : 0);
 407 }
 408
 409 STATIC_INLINE void
 410 cpu_ccr_update_sub16 (sim_cpu *cpu, uint16 r, uint16 a, uint16 b)
 411 {
 412   cpu_set_ccr_C (cpu, ((~a & b) | (b & r) | (~a & r)) & 0x8000 ? 1 : 0);
 413   cpu_set_ccr_V (cpu, ((a & ~b & ~r) | (~a & b & r)) & 0x8000 ? 1 : 0);
 414   cpu_set_ccr_Z (cpu, r == 0);
 415   cpu_set_ccr_N (cpu, r & 0x8000 ? 1 : 0);
 416 }
 417
 418 /* Push and pop instructions for 68HC11 (next-available stack mode).  */
 419 STATIC_INLINE void
 420 cpu_m68hc11_push_uint8 (sim_cpu *cpu, uint8 val)
 421 {
 422   uint16 addr = cpu->cpu_regs.sp;
 423
 424   memory_write8 (cpu, addr, val);
 425   cpu->cpu_regs.sp = addr - 1;
 426 }
 427
 428 STATIC_INLINE void
 429 cpu_m68hc11_push_uint16 (sim_cpu *cpu, uint16 val)
 430 {
 431   uint16 addr = cpu->cpu_regs.sp - 1;
 432
 433   memory_write16 (cpu, addr, val);
 434   cpu->cpu_regs.sp = addr - 1;
 435 }
 436
 437 STATIC_INLINE uint8
 438 cpu_m68hc11_pop_uint8 (sim_cpu *cpu)
 439 {
 440   uint16 addr = cpu->cpu_regs.sp;
 441   uint8 val;
 442
 443   val = memory_read8 (cpu, addr + 1);
 444   cpu->cpu_regs.sp = addr + 1;
 445   return val;
 446 }
 447
 448 STATIC_INLINE uint16
 449 cpu_m68hc11_pop_uint16 (sim_cpu *cpu)
 450 {
 451   uint16 addr = cpu->cpu_regs.sp;
 452   uint16 val;
 453
 454   val = memory_read16 (cpu, addr + 1);
 455   cpu->cpu_regs.sp = addr + 2;
 456   return val;
 457 }
 458
 459 /* Push and pop instructions for 68HC12 (last-used stack mode).  */
 460 STATIC_INLINE void
 461 cpu_m68hc12_push_uint8 (sim_cpu *cpu, uint8 val)
 462 {
 463   uint16 addr = cpu->cpu_regs.sp;
 464
 465   addr --;
 466   memory_write8 (cpu, addr, val);
 467   cpu->cpu_regs.sp = addr;
 468 }
 469
 470 STATIC_INLINE void
 471 cpu_m68hc12_push_uint16 (sim_cpu *cpu, uint16 val)
 472 {
 473   uint16 addr = cpu->cpu_regs.sp;
 474
 475   addr -= 2;
 476   memory_write16 (cpu, addr, val);
 477   cpu->cpu_regs.sp = addr;
 478 }
 479
 480 STATIC_INLINE uint8
 481 cpu_m68hc12_pop_uint8 (sim_cpu *cpu)
 482 {
 483   uint16 addr = cpu->cpu_regs.sp;
 484   uint8 val;
 485
 486   val = memory_read8 (cpu, addr);
 487   cpu->cpu_regs.sp = addr + 1;
 488   return val;
 489 }
 490
 491 STATIC_INLINE uint16
 492 cpu_m68hc12_pop_uint16 (sim_cpu *cpu)
 493 {
 494   uint16 addr = cpu->cpu_regs.sp;
 495   uint16 val;
 496
 497   val = memory_read16 (cpu, addr);
 498   cpu->cpu_regs.sp = addr + 2;
 499   return val;
 500 }
 501
 502 /* Fetch a 8/16 bit value and update the PC.  */
 503 STATIC_INLINE uint8
 504 cpu_fetch8 (sim_cpu *cpu)
 505 {
 506   uint16 addr = cpu->cpu_regs.pc;
 507   uint8 val;
 508
 509   val = memory_read8 (cpu, addr);
 510   cpu->cpu_regs.pc = addr + 1;
 511   return val;
 512 }
 513
 514 STATIC_INLINE uint16
 515 cpu_fetch16 (sim_cpu *cpu)
 516 {
 517   uint16 addr = cpu->cpu_regs.pc;
 518   uint16 val;
 519
 520   val = memory_read16 (cpu, addr);
 521   cpu->cpu_regs.pc = addr + 2;
 522   return val;
 523 }
 524
 525 extern void cpu_call (sim_cpu *cpu, uint16 addr);
 526 extern void cpu_exg (sim_cpu *cpu, uint8 code);
 527 extern void cpu_dbcc (sim_cpu *cpu);
 528 extern void cpu_special (sim_cpu *cpu, enum M6811_Special special);
 529 extern void cpu_move8 (sim_cpu *cpu, uint8 op);
 530 extern void cpu_move16 (sim_cpu *cpu, uint8 op);
 531
 532 extern uint16 cpu_fetch_relbranch (sim_cpu *cpu);
 533 extern uint16 cpu_fetch_relbranch16 (sim_cpu *cpu);
 534 extern void cpu_push_all (sim_cpu *cpu);
 535 extern void cpu_single_step (sim_cpu *cpu);
 536
 537 extern void cpu_info (SIM_DESC sd, sim_cpu *cpu);
 538
 539 extern int cpu_initialize (SIM_DESC sd, sim_cpu *cpu);
 540
 541 /* Returns the address of a 68HC12 indexed operand.
 542    Pre and post modifications are handled on the source register.  */
 543 extern uint16 cpu_get_indexed_operand_addr (sim_cpu *cpu, int restricted);
 544
 545 extern void cpu_return (sim_cpu *cpu);
 546 extern void cpu_set_sp (sim_cpu *cpu, uint16 val);
 547 extern int cpu_reset (sim_cpu *cpu);
 548 extern int cpu_restart (sim_cpu *cpu);
 549 extern void sim_memory_error (sim_cpu *cpu, SIM_SIGNAL excep,
 550                               uint16 addr, const char *message, ...);
 551 extern void emul_os (int op, sim_cpu *cpu);
 552 extern void cpu_interp_m6811 (sim_cpu *cpu);
 553 extern void cpu_interp_m6812 (sim_cpu *cpu);
 554
 555 extern int m68hc11cpu_set_oscillator (SIM_DESC sd, const char *port,
 556                                       double ton, double toff,
 557                                       signed64 repeat);
 558 extern int m68hc11cpu_clear_oscillator (SIM_DESC sd, const char *port);
 559 extern void m68hc11cpu_set_port (struct hw *me, sim_cpu *cpu,
 560                                  unsigned addr, uint8 val);
 561
 562 extern void sim_board_reset (SIM_DESC sd);
 563
 564 #define PRINT_TIME  0x01
 565 #define PRINT_CYCLE 0x02
 566 extern const char *cycle_to_string (sim_cpu *cpu, signed64 t, int flags);
 567
 568 #endif
 569
 570