sim/m68hc11/sim-main.h

   1 /* sim-main.h -- Simulator for Motorola 68HC11 & 68HC12
   2    Copyright (C) 1999, 2000, 2001, 2002, 2003 Free Software Foundation, Inc.
   3    Written by Stephane Carrez (stcarrez@nerim.fr)
   4
   5 This file is part of GDB, the GNU debugger.
   6
   7 This program is free software; you can redistribute it and/or modify
   8 it under the terms of the GNU General Public License as published by
   9 the Free Software Foundation; either version 2, or (at your option)
  10 any later version.
  11
  12 This program is distributed in the hope that it will be useful,
  13 but WITHOUT ANY WARRANTY; without even the implied warranty of
  14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15 GNU General Public License for more details.
  16
  17 You should have received a copy of the GNU General Public License along
  18 with this program; if not, write to the Free Software Foundation, Inc.,
  19 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
  20
  21 #ifndef _SIM_MAIN_H
  22 #define _SIM_MAIN_H
  23
  24 #define WITH_MODULO_MEMORY 1
  25 #define WITH_WATCHPOINTS 1
  26 #define SIM_HANDLES_LMA 1
  27
  28 #include "sim-basics.h"
  29
  30 typedef address_word sim_cia;
  31
  32 #include "sim-signal.h"
  33 #include "sim-base.h"
  34
  35 #include "bfd.h"
  36
  37 #include "opcode/m68hc11.h"
  38
  39 #include "gdb/callback.h"
  40 #include "gdb/remote-sim.h"
  41 #include "opcode/m68hc11.h"
  42 #include "sim-types.h"
  43
  44 typedef unsigned8 uint8;
  45 typedef unsigned16 uint16;
  46 typedef signed16 int16;
  47 typedef unsigned32 uint32;
  48 typedef signed32 int32;
  49 typedef unsigned64 uint64;
  50 typedef signed64 int64;
  51
  52 struct _sim_cpu;
  53
  54 #include "interrupts.h"
  55 #include <setjmp.h>
  56
  57 /* Specifies the level of mapping for the IO, EEprom, nvram and external
  58    RAM.  IO registers are mapped over everything and the external RAM
  59    is last (ie, it can be hidden by everything above it in the list).  */
  60 enum m68hc11_map_level
  61 {
  62   M6811_IO_LEVEL,
  63   M6811_EEPROM_LEVEL,
  64   M6811_NVRAM_LEVEL,
  65   M6811_RAM_LEVEL
  66 };
  67
  68 enum cpu_type
  69 {
  70   CPU_M6811,
  71   CPU_M6812
  72 };
  73
  74 #define X_REGNUM        0
  75 #define D_REGNUM        1
  76 #define Y_REGNUM        2
  77 #define SP_REGNUM       3
  78 #define PC_REGNUM       4
  79 #define A_REGNUM        5
  80 #define B_REGNUM        6
  81 #define PSW_REGNUM      7
  82 #define PAGE_REGNUM     8
  83 #define Z_REGNUM        9
  84
  85 typedef struct m6811_regs {
  86     unsigned short      d;
  87     unsigned short      ix;
  88     unsigned short      iy;
  89     unsigned short      sp;
  90     unsigned short      pc;
  91     unsigned char       ccr;
  92   unsigned short      page;
  93 } m6811_regs;
  94
  95
  96 /* Description of 68HC11 IO registers.  Such description is only provided
  97    for the info command to display the current setting of IO registers
  98    from GDB.  */
  99 struct io_reg_desc
 100 {
 101   int        mask;
 102   const char *short_name;
 103   const char *long_name;
 104 };
 105 typedef struct io_reg_desc io_reg_desc;
 106
 107 extern void print_io_reg_desc (SIM_DESC sd, io_reg_desc *desc, int val,
 108                                int mode);
 109 extern void print_io_byte (SIM_DESC sd, const char *name,
 110                            io_reg_desc *desc, uint8 val, uint16 addr);
 111 extern void print_io_word (SIM_DESC sd, const char *name,
 112                            io_reg_desc *desc, uint16 val, uint16 addr);
 113
 114
 115 /* List of special 68HC11&68HC12 instructions that are not handled by the
 116    'gencode.c' generator.  These complex instructions are implemented
 117    by 'cpu_special'.  */
 118 enum M6811_Special
 119 {
 120   /* 68HC11 instructions.  */
 121   M6811_DAA,
 122   M6811_EMUL_SYSCALL,
 123   M6811_ILLEGAL,
 124   M6811_RTI,
 125   M6811_STOP,
 126   M6811_SWI,
 127   M6811_TEST,
 128   M6811_WAI,
 129
 130   /* 68HC12 instructions.  */
 131   M6812_BGND,
 132   M6812_CALL,
 133   M6812_CALL_INDIRECT,
 134   M6812_IDIVS,
 135   M6812_EDIV,
 136   M6812_EDIVS,
 137   M6812_EMACS,
 138   M6812_EMUL,
 139   M6812_EMULS,
 140   M6812_ETBL,
 141   M6812_MEM,
 142   M6812_REV,
 143   M6812_REVW,
 144   M6812_RTC,
 145   M6812_RTI,
 146   M6812_WAV
 147 };
 148
 149 #define M6811_MAX_PORTS (0x03f+1)
 150 #define M6812_MAX_PORTS (0x3ff+1)
 151 #define MAX_PORTS       (M6812_MAX_PORTS)
 152
 153 struct _sim_cpu;
 154
 155 typedef void (* cpu_interp) (struct _sim_cpu*);
 156
 157 struct _sim_cpu {
 158   /* CPU registers.  */
 159   struct m6811_regs     cpu_regs;
 160
 161   /* CPU interrupts.  */
 162   struct interrupts     cpu_interrupts;
 163
 164   /* Pointer to the interpretor routine.  */
 165   cpu_interp            cpu_interpretor;
 166
 167   /* Pointer to the architecture currently configured in the simulator.  */
 168   const struct bfd_arch_info  *cpu_configured_arch;
 169
 170   /* CPU absolute cycle time.  The cycle time is updated after
 171      each instruction, by the number of cycles taken by the instruction.
 172      It is cleared only when reset occurs.  */
 173   signed64              cpu_absolute_cycle;
 174
 175   /* Number of cycles to increment after the current instruction.
 176      This is also the number of ticks for the generic event scheduler.  */
 177   uint8                 cpu_current_cycle;
 178   int                   cpu_emul_syscall;
 179   int                   cpu_is_initialized;
 180   int                   cpu_running;
 181   int                   cpu_check_memory;
 182   int                   cpu_stop_on_interrupt;
 183
 184   /* When this is set, start execution of program at address specified
 185      in the ELF header.  This is used for testing some programs that do not
 186      have an interrupt table linked with them.  Programs created during the
 187      GCC validation are like this. A normal 68HC11 does not behave like
 188      this (unless there is some OS or downloadable feature).  */
 189   int                   cpu_use_elf_start;
 190
 191   /* The starting address specified in ELF header.  */
 192   int                   cpu_elf_start;
 193
 194   uint16                cpu_insn_pc;
 195
 196   /* CPU frequency.  This is the quartz frequency.  It is divided by 4 to
 197      get the cycle time.  This is used for the timer rate and for the baud
 198      rate generation.  */
 199   unsigned long         cpu_frequency;
 200
 201   /* The mode in which the CPU is configured (MODA and MODB pins).  */
 202   unsigned int          cpu_mode;
 203
 204   /* The cpu being configured.  */
 205   enum cpu_type         cpu_type;
 206
 207   /* Initial value of the CONFIG register.  */
 208   uint8                 cpu_config;
 209   uint8                 cpu_use_local_config;
 210
 211   uint8                 ios[MAX_PORTS];
 212
 213   struct hw            *hw_cpu;
 214
 215   /* ... base type ... */
 216   sim_cpu_base base;
 217 };
 218
 219 /* Returns the cpu absolute cycle time (A virtual counter incremented
 220    at each 68HC11 E clock).  */
 221 #define cpu_current_cycle(PROC) ((PROC)->cpu_absolute_cycle)
 222 #define cpu_add_cycles(PROC,T)  ((PROC)->cpu_current_cycle += (signed64) (T))
 223 #define cpu_is_running(PROC)    ((PROC)->cpu_running)
 224
 225 /* Get the IO/RAM base addresses depending on the M6811_INIT register.  */
 226 #define cpu_get_io_base(PROC) \
 227         (((uint16)(((PROC)->ios[M6811_INIT]) & 0x0F))<<12)
 228 #define cpu_get_reg_base(PROC) \
 229         (((uint16)(((PROC)->ios[M6811_INIT]) & 0xF0))<<8)
 230
 231 /* Returns the different CPU registers.  */
 232 #define cpu_get_ccr(PROC)          ((PROC)->cpu_regs.ccr)
 233 #define cpu_get_pc(PROC)           ((PROC)->cpu_regs.pc)
 234 #define cpu_get_d(PROC)            ((PROC)->cpu_regs.d)
 235 #define cpu_get_x(PROC)            ((PROC)->cpu_regs.ix)
 236 #define cpu_get_y(PROC)            ((PROC)->cpu_regs.iy)
 237 #define cpu_get_sp(PROC)           ((PROC)->cpu_regs.sp)
 238 #define cpu_get_a(PROC)            ((PROC->cpu_regs.d >> 8) & 0x0FF)
 239 #define cpu_get_b(PROC)            ((PROC->cpu_regs.d) & 0x0FF)
 240 #define cpu_get_page(PROC)         (PROC->cpu_regs.page)
 241
 242 /* 68HC12 specific and Motorola internal registers.  */
 243 #define cpu_get_tmp3(PROC)         (0)
 244 #define cpu_get_tmp2(PROC)         (0)
 245
 246 #define cpu_set_d(PROC,VAL)        (((PROC)->cpu_regs.d) = (VAL))
 247 #define cpu_set_x(PROC,VAL)        (((PROC)->cpu_regs.ix) = (VAL))
 248 #define cpu_set_y(PROC,VAL)        (((PROC)->cpu_regs.iy) = (VAL))
 249 #define cpu_set_page(PROC,VAL)     ((PROC->cpu_regs.page) = (VAL))
 250
 251 /* 68HC12 specific and Motorola internal registers.  */
 252 #define cpu_set_tmp3(PROC,VAL)     (0)
 253 #define cpu_set_tmp2(PROC,VAL)     (void) (0)
 254
 255 #if 0
 256 /* This is a function in m68hc11_sim.c to keep track of the frame.  */
 257 #define cpu_set_sp(PROC,VAL)       (((PROC)->cpu_regs.sp) = (VAL))
 258 #endif
 259
 260 #define cpu_set_pc(PROC,VAL)       (((PROC)->cpu_regs.pc) = (VAL))
 261
 262 #define cpu_set_a(PROC,VAL)  \
 263       cpu_set_d(PROC,((VAL) << 8) | cpu_get_b(PROC))
 264 #define cpu_set_b(PROC,VAL)  \
 265       cpu_set_d(PROC,((cpu_get_a(PROC)) << 8)|(VAL & 0x0FF))
 266
 267 #define cpu_set_ccr(PROC,VAL)      ((PROC)->cpu_regs.ccr = (VAL))
 268 #define cpu_get_ccr_H(PROC)        ((cpu_get_ccr(PROC) & M6811_H_BIT) ? 1: 0)
 269 #define cpu_get_ccr_X(PROC)        ((cpu_get_ccr(PROC) & M6811_X_BIT) ? 1: 0)
 270 #define cpu_get_ccr_S(PROC)        ((cpu_get_ccr(PROC) & M6811_S_BIT) ? 1: 0)
 271 #define cpu_get_ccr_N(PROC)        ((cpu_get_ccr(PROC) & M6811_N_BIT) ? 1: 0)
 272 #define cpu_get_ccr_V(PROC)        ((cpu_get_ccr(PROC) & M6811_V_BIT) ? 1: 0)
 273 #define cpu_get_ccr_C(PROC)        ((cpu_get_ccr(PROC) & M6811_C_BIT) ? 1: 0)
 274 #define cpu_get_ccr_Z(PROC)        ((cpu_get_ccr(PROC) & M6811_Z_BIT) ? 1: 0)
 275 #define cpu_get_ccr_I(PROC)        ((cpu_get_ccr(PROC) & M6811_I_BIT) ? 1: 0)
 276
 277 #define cpu_set_ccr_flag(S,B,V) \
 278 cpu_set_ccr(S,(cpu_get_ccr(S) & ~(B)) | ((V) ? B : 0))
 279
 280 #define cpu_set_ccr_H(PROC,VAL)    cpu_set_ccr_flag(PROC, M6811_H_BIT, VAL)
 281 #define cpu_set_ccr_X(PROC,VAL)    cpu_set_ccr_flag(PROC, M6811_X_BIT, VAL)
 282 #define cpu_set_ccr_S(PROC,VAL)    cpu_set_ccr_flag(PROC, M6811_S_BIT, VAL)
 283 #define cpu_set_ccr_N(PROC,VAL)    cpu_set_ccr_flag(PROC, M6811_N_BIT, VAL)
 284 #define cpu_set_ccr_V(PROC,VAL)    cpu_set_ccr_flag(PROC, M6811_V_BIT, VAL)
 285 #define cpu_set_ccr_C(PROC,VAL)    cpu_set_ccr_flag(PROC, M6811_C_BIT, VAL)
 286 #define cpu_set_ccr_Z(PROC,VAL)    cpu_set_ccr_flag(PROC, M6811_Z_BIT, VAL)
 287 #define cpu_set_ccr_I(PROC,VAL)    cpu_set_ccr_flag(PROC, M6811_I_BIT, VAL)
 288
 289 #undef inline
 290 #define inline static __inline__
 291
 292 extern void cpu_memory_exception (struct _sim_cpu *proc,
 293                                   SIM_SIGNAL excep,
 294                                   uint16 addr,
 295                                   const char *message);
 296
 297 inline address_word
 298 phys_to_virt (sim_cpu *cpu, address_word addr)
 299 {
 300   if (addr >= 0x8000 && addr < 0xc000)
 301     return ((address_word) (addr) - 0x8000)
 302       + (((address_word) cpu->cpu_regs.page) << 14) + 0x01000000;
 303   else
 304     return (address_word) (addr);
 305 }
 306
 307 inline uint8
 308 memory_read8 (sim_cpu *cpu, uint16 addr)
 309 {
 310   uint8 val;
 311
 312   if (sim_core_read_buffer (CPU_STATE (cpu), cpu, 0, &val, addr, 1) != 1)
 313     {
 314       cpu_memory_exception (cpu, SIM_SIGSEGV, addr,
 315                             "Read error");
 316     }
 317   return val;
 318 }
 319
 320 inline void
 321 memory_write8 (sim_cpu *cpu, uint16 addr, uint8 val)
 322 {
 323   if (sim_core_write_buffer (CPU_STATE (cpu), cpu, 0, &val, addr, 1) != 1)
 324     {
 325       cpu_memory_exception (cpu, SIM_SIGSEGV, addr,
 326                             "Write error");
 327     }
 328 }
 329
 330 inline uint16
 331 memory_read16 (sim_cpu *cpu, uint16 addr)
 332 {
 333   uint8 b[2];
 334
 335   if (sim_core_read_buffer (CPU_STATE (cpu), cpu, 0, b, addr, 2) != 2)
 336     {
 337       cpu_memory_exception (cpu, SIM_SIGSEGV, addr,
 338                             "Read error");
 339     }
 340   return (((uint16) (b[0])) << 8) | ((uint16) b[1]);
 341 }
 342
 343 inline void
 344 memory_write16 (sim_cpu *cpu, uint16 addr, uint16 val)
 345 {
 346   uint8 b[2];
 347
 348   b[0] = val >> 8;
 349   b[1] = val;
 350   if (sim_core_write_buffer (CPU_STATE (cpu), cpu, 0, b, addr, 2) != 2)
 351     {
 352       cpu_memory_exception (cpu, SIM_SIGSEGV, addr,
 353                             "Write error");
 354     }
 355 }
 356 extern void
 357 cpu_ccr_update_tst8 (sim_cpu *proc, uint8 val);
 358
 359      inline void
 360 cpu_ccr_update_tst16 (sim_cpu *proc, uint16 val)
 361 {
 362   cpu_set_ccr_V (proc, 0);
 363   cpu_set_ccr_N (proc, val & 0x8000 ? 1 : 0);
 364   cpu_set_ccr_Z (proc, val == 0 ? 1 : 0);
 365 }
 366
 367      inline void
 368 cpu_ccr_update_shift8 (sim_cpu *proc, uint8 val)
 369 {
 370   cpu_set_ccr_N (proc, val & 0x80 ? 1 : 0);
 371   cpu_set_ccr_Z (proc, val == 0 ? 1 : 0);
 372   cpu_set_ccr_V (proc, cpu_get_ccr_N (proc) ^ cpu_get_ccr_C (proc));
 373 }
 374
 375      inline void
 376 cpu_ccr_update_shift16 (sim_cpu *proc, uint16 val)
 377 {
 378   cpu_set_ccr_N (proc, val & 0x8000 ? 1 : 0);
 379   cpu_set_ccr_Z (proc, val == 0 ? 1 : 0);
 380   cpu_set_ccr_V (proc, cpu_get_ccr_N (proc) ^ cpu_get_ccr_C (proc));
 381 }
 382
 383 inline void
 384 cpu_ccr_update_add8 (sim_cpu *proc, uint8 r, uint8 a, uint8 b)
 385 {
 386   cpu_set_ccr_C (proc, ((a & b) | (b & ~r) | (a & ~r)) & 0x80 ? 1 : 0);
 387   cpu_set_ccr_V (proc, ((a & b & ~r) | (~a & ~b & r)) & 0x80 ? 1 : 0);
 388   cpu_set_ccr_Z (proc, r == 0);
 389   cpu_set_ccr_N (proc, r & 0x80 ? 1 : 0);
 390 }
 391
 392
 393 inline void
 394 cpu_ccr_update_sub8 (sim_cpu *proc, uint8 r, uint8 a, uint8 b)
 395 {
 396   cpu_set_ccr_C (proc, ((~a & b) | (b & r) | (~a & r)) & 0x80 ? 1 : 0);
 397   cpu_set_ccr_V (proc, ((a & ~b & ~r) | (~a & b & r)) & 0x80 ? 1 : 0);
 398   cpu_set_ccr_Z (proc, r == 0);
 399   cpu_set_ccr_N (proc, r & 0x80 ? 1 : 0);
 400 }
 401
 402 inline void
 403 cpu_ccr_update_add16 (sim_cpu *proc, uint16 r, uint16 a, uint16 b)
 404 {
 405   cpu_set_ccr_C (proc, ((a & b) | (b & ~r) | (a & ~r)) & 0x8000 ? 1 : 0);
 406   cpu_set_ccr_V (proc, ((a & b & ~r) | (~a & ~b & r)) & 0x8000 ? 1 : 0);
 407   cpu_set_ccr_Z (proc, r == 0);
 408   cpu_set_ccr_N (proc, r & 0x8000 ? 1 : 0);
 409 }
 410
 411 inline void
 412 cpu_ccr_update_sub16 (sim_cpu *proc, uint16 r, uint16 a, uint16 b)
 413 {
 414   cpu_set_ccr_C (proc, ((~a & b) | (b & r) | (~a & r)) & 0x8000 ? 1 : 0);
 415   cpu_set_ccr_V (proc, ((a & ~b & ~r) | (~a & b & r)) & 0x8000 ? 1 : 0);
 416   cpu_set_ccr_Z (proc, r == 0);
 417   cpu_set_ccr_N (proc, r & 0x8000 ? 1 : 0);
 418 }
 419
 420 /* Push and pop instructions for 68HC11 (next-available stack mode).  */
 421 inline void
 422 cpu_m68hc11_push_uint8 (sim_cpu *proc, uint8 val)
 423 {
 424   uint16 addr = proc->cpu_regs.sp;
 425
 426   memory_write8 (proc, addr, val);
 427   proc->cpu_regs.sp = addr - 1;
 428 }
 429
 430 inline void
 431 cpu_m68hc11_push_uint16 (sim_cpu *proc, uint16 val)
 432 {
 433   uint16 addr = proc->cpu_regs.sp - 1;
 434
 435   memory_write16 (proc, addr, val);
 436   proc->cpu_regs.sp = addr - 1;
 437 }
 438
 439 inline uint8
 440 cpu_m68hc11_pop_uint8 (sim_cpu *proc)
 441 {
 442   uint16 addr = proc->cpu_regs.sp;
 443   uint8 val;
 444
 445   val = memory_read8 (proc, addr + 1);
 446   proc->cpu_regs.sp = addr + 1;
 447   return val;
 448 }
 449
 450 inline uint16
 451 cpu_m68hc11_pop_uint16 (sim_cpu *proc)
 452 {
 453   uint16 addr = proc->cpu_regs.sp;
 454   uint16 val;
 455
 456   val = memory_read16 (proc, addr + 1);
 457   proc->cpu_regs.sp = addr + 2;
 458   return val;
 459 }
 460
 461 /* Push and pop instructions for 68HC12 (last-used stack mode).  */
 462 inline void
 463 cpu_m68hc12_push_uint8 (sim_cpu *proc, uint8 val)
 464 {
 465   uint16 addr = proc->cpu_regs.sp;
 466
 467   addr --;
 468   memory_write8 (proc, addr, val);
 469   proc->cpu_regs.sp = addr;
 470 }
 471
 472 inline void
 473 cpu_m68hc12_push_uint16 (sim_cpu *proc, uint16 val)
 474 {
 475   uint16 addr = proc->cpu_regs.sp;
 476
 477   addr -= 2;
 478   memory_write16 (proc, addr, val);
 479   proc->cpu_regs.sp = addr;
 480 }
 481
 482 inline uint8
 483 cpu_m68hc12_pop_uint8 (sim_cpu *proc)
 484 {
 485   uint16 addr = proc->cpu_regs.sp;
 486   uint8 val;
 487
 488   val = memory_read8 (proc, addr);
 489   proc->cpu_regs.sp = addr + 1;
 490   return val;
 491 }
 492
 493 inline uint16
 494 cpu_m68hc12_pop_uint16 (sim_cpu *proc)
 495 {
 496   uint16 addr = proc->cpu_regs.sp;
 497   uint16 val;
 498
 499   val = memory_read16 (proc, addr);
 500   proc->cpu_regs.sp = addr + 2;
 501   return val;
 502 }
 503
 504 /* Fetch a 8/16 bit value and update the PC.  */
 505 inline uint8
 506 cpu_fetch8 (sim_cpu *proc)
 507 {
 508   uint16 addr = proc->cpu_regs.pc;
 509   uint8 val;
 510
 511   val = memory_read8 (proc, addr);
 512   proc->cpu_regs.pc = addr + 1;
 513   return val;
 514 }
 515
 516 inline uint16
 517 cpu_fetch16 (sim_cpu *proc)
 518 {
 519   uint16 addr = proc->cpu_regs.pc;
 520   uint16 val;
 521
 522   val = memory_read16 (proc, addr);
 523   proc->cpu_regs.pc = addr + 2;
 524   return val;
 525 }
 526
 527 extern void cpu_call (sim_cpu* proc, uint16 addr);
 528 extern void cpu_exg (sim_cpu* proc, uint8 code);
 529 extern void cpu_dbcc (sim_cpu* proc);
 530 extern void cpu_special (sim_cpu *proc, enum M6811_Special special);
 531 extern void cpu_move8 (sim_cpu *proc, uint8 op);
 532 extern void cpu_move16 (sim_cpu *proc, uint8 op);
 533
 534 extern uint16 cpu_fetch_relbranch (sim_cpu *proc);
 535 extern uint16 cpu_fetch_relbranch16 (sim_cpu *proc);
 536 extern void cpu_push_all (sim_cpu *proc);
 537 extern void cpu_single_step (sim_cpu *proc);
 538
 539 extern void cpu_info (SIM_DESC sd, sim_cpu *proc);
 540
 541 extern int cpu_initialize (SIM_DESC sd, sim_cpu *cpu);
 542
 543 /* Returns the address of a 68HC12 indexed operand.
 544    Pre and post modifications are handled on the source register.  */
 545 extern uint16 cpu_get_indexed_operand_addr (sim_cpu* cpu, int restrict);
 546
 547 extern void cpu_return (sim_cpu *cpu);
 548 extern void cpu_set_sp (sim_cpu *cpu, uint16 val);
 549 extern int cpu_reset (sim_cpu *cpu);
 550 extern int cpu_restart (sim_cpu *cpu);
 551 extern void sim_memory_error (sim_cpu *cpu, SIM_SIGNAL excep,
 552                               uint16 addr, const char *message, ...);
 553 extern void emul_os (int op, sim_cpu *cpu);
 554 extern void cpu_interp_m6811 (sim_cpu *cpu);
 555 extern void cpu_interp_m6812 (sim_cpu *cpu);
 556
 557 extern int m68hc11cpu_set_oscillator (SIM_DESC sd, const char *port,
 558                                       double ton, double toff,
 559                                       signed64 repeat);
 560 extern int m68hc11cpu_clear_oscillator (SIM_DESC sd, const char *port);
 561 extern void m68hc11cpu_set_port (struct hw *me, sim_cpu *cpu,
 562                                  unsigned addr, uint8 val);
 563
 564 /* The current state of the processor; registers, memory, etc.  */
 565
 566 #define CIA_GET(CPU)      (cpu_get_pc (CPU))
 567 #define CIA_SET(CPU,VAL)  (cpu_set_pc ((CPU), (VAL)))
 568
 569 #if (WITH_SMP)
 570 #define STATE_CPU(sd,n) (&(sd)->cpu[n])
 571 #else
 572 #define STATE_CPU(sd,n) (&(sd)->cpu[0])
 573 #endif
 574
 575 struct sim_state {
 576   sim_cpu        cpu[MAX_NR_PROCESSORS];
 577   device         *devices;
 578   sim_state_base base;
 579 };
 580
 581 extern void sim_set_profile (int n);
 582 extern void sim_set_profile_size (int n);
 583 extern void sim_board_reset (SIM_DESC sd);
 584
 585 extern const char *cycle_to_string (sim_cpu *cpu, signed64 t);
 586
 587 #endif
 588
 589