sim/microblaze/sim-main.h

   1 /* Copyright 2009-2015 Free Software Foundation, Inc.
   2
   3    This file is part of the Xilinx MicroBlaze simulator.
   4
   5    This library is free software; you can redistribute it and/or modify
   6    it under the terms of the GNU General Public License as published by
   7    the Free Software Foundation; either version 3 of the License, or
   8    (at your option) any later version.
   9
  10    This program is distributed in the hope that it will be useful,
  11    but WITHOUT ANY WARRANTY; without even the implied warranty of
  12    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13    GNU General Public License for more details.
  14
  15    You should have received a copy of the GNU General Public License
  16    along with this program; if not, see <http://www.gnu.org/licenses/>.  */
  17
  18 #ifndef MICROBLAZE_SIM_MAIN
  19 #define MICROBLAZE_SIM_MAIN
  20
  21 #include "microblaze.h"
  22 #include "sim-basics.h"
  23
  24 typedef address_word sim_cia;
  25
  26 #define CIA_GET(cpu) (cpu)->microblaze_cpu.spregs[0]
  27 #define CIA_SET(cpu,val) (cpu)->microblaze_cpu.spregs[0] = (val)
  28
  29 typedef struct _sim_cpu SIM_CPU;
  30
  31 #include "sim-base.h"
  32
  33 /* The machine state.
  34    This state is maintained in host byte order.  The
  35    fetch/store register functions must translate between host
  36    byte order and the target processor byte order.
  37    Keeping this data in target byte order simplifies the register
  38    read/write functions.  Keeping this data in native order improves
  39    the performance of the simulator.  Simulation speed is deemed more
  40    important.  */
  41
  42 /* The ordering of the microblaze_regset structure is matched in the
  43    gdb/config/microblaze/tm-microblaze.h file in the REGISTER_NAMES macro.  */
  44  struct microblaze_regset
  45 {
  46   word            regs[32];             /* primary registers */
  47   word            spregs[2];            /* pc + msr */
  48   int             cycles;
  49   int             insts;
  50   int             exception;
  51   unsigned long   msize;
  52   unsigned char  *memory;
  53   ubyte           imm_enable;
  54   half            imm_high;
  55 };
  56
  57 struct _sim_cpu {
  58   struct microblaze_regset microblaze_cpu;
  59   sim_cpu_base base;
  60 };
  61
  62 struct sim_state {
  63
  64   sim_cpu *cpu[MAX_NR_PROCESSORS];
  65 #if (WITH_SMP)
  66 #define STATE_CPU(sd,n) ((sd)->cpu[n])
  67 #else
  68 #define STATE_CPU(sd,n) ((sd)->cpu[0])
  69 #endif
  70
  71   sim_state_base base;
  72 };
  73
  74 #endif /* MICROBLAZE_SIM_MAIN */