sim/mips/ChangeLog

   1 2007-03-01  Thiemo Seufer  <ths@mips.com>
   2
   3         * mips.igen (MFHI, MFLO, MTHI, MTLO): Restore support for mips32
   4         and mips64.
   5
   6 2007-02-20  Thiemo Seufer  <ths@mips.com>
   7
   8         * dsp.igen: Update copyright notice.
   9         * dsp2.igen: Fix copyright notice.
  10
  11 2007-02-20  Thiemo Seufer  <ths@mips.com>
  12             Chao-Ying Fu  <fu@mips.com>
  13
  14         * Makefile.in (IGEN_INCLUDE): Add dsp2.igen.
  15         * configure.ac (mips*-sde-elf*, mipsisa32r2*-*-*, mipsisa64r2*-*-*):
  16         Add dsp2 to sim_igen_machine.
  17         * configure: Regenerate.
  18         * dsp.igen (do_ph_op): Add MUL support when op = 2.
  19         (do_ph_mulq): New function to support mulq_rs.ph and mulq_s.ph.
  20         (mulq_rs.ph): Use do_ph_mulq.
  21         (MFHI, MFLO, MTHI, MTLO): Move these instructions to mips.igen.
  22         * mips.igen: Add dsp2 model and include dsp2.igen.
  23         (MFHI, MFLO, MTHI, MTLO): Extend these instructions for
  24         for *mips32r2, *mips64r2, *dsp.
  25         (MADD, MADDU, MSUB, MSUBU, MULT, MULTU): Extend these instructions
  26         for *mips32r2, *mips64r2, *dsp2.
  27         * dsp2.igen: New file for MIPS DSP REV 2 ASE.
  28
  29 2007-02-19  Thiemo Seufer  <ths@mips.com>
  30             Nigel Stephens  <nigel@mips.com>
  31
  32         * mips.igen (jalr.hb, jr.hb): Add decoder for mip32r2/mips64r2
  33         jumps with hazard barrier.
  34
  35 2007-02-19  Thiemo Seufer  <ths@mips.com>
  36             Nigel Stephens  <nigel@mips.com>
  37
  38         * interp.c (sim_monitor): Flush stdout and stderr file descriptors
  39         after each call to sim_io_write.
  40
  41 2007-02-19  Thiemo Seufer  <ths@mips.com>
  42             Nigel Stephens  <nigel@mips.com>
  43
  44         * interp.c (ColdReset): Set CP0 Config0 to reflect the address size
  45         supported by this simulator.
  46         (decode_coproc): Recognise additional CP0 Config registers
  47         correctly.
  48
  49 2007-02-19  Thiemo Seufer  <ths@mips.com>
  50             Nigel Stephens  <nigel@mips.com>
  51             David Ung  <davidu@mips.com>
  52
  53         * cp1.c (value_fpr): Don't inherit existing FPR_STATE for
  54         uninterpreted formats. If fmt is one of the uninterpreted types
  55         don't update the FPR_STATE. Handle fmt_uninterpreted_32 like
  56         fmt_word, and fmt_uninterpreted_64 like fmt_long.
  57         (store_fpr): When writing an invalid odd register, set the
  58         matching even register to fmt_unknown, not the following register.
  59         * interp.c (sim_open): If STATE_MEM_SIZE isn't set then set it to
  60         the the memory window at offset 0 set by --memory-size command
  61         line option.
  62         (sim_store_register): Handle storing 4 bytes to an 8 byte floating
  63         point register.
  64         (sim_fetch_register): Likewise for reading 4 bytes from an 8 byte
  65         register.
  66         (sim_monitor): When returning the memory size to the MIPS
  67         application, use the value in STATE_MEM_SIZE, not an arbitrary
  68         hardcoded value.
  69         (cop_lw): Don' mess around with FPR_STATE, just pass
  70         fmt_uninterpreted_32 to StoreFPR.
  71         (cop_sw): Similarly.
  72         (cop_ld): Pass fmt_uninterpreted_64 not fmt_uninterpreted.
  73         (cop_sd): Similarly.
  74         * mips.igen (not_word_value): Single version for mips32, mips64
  75         and mips16.
  76
  77 2007-02-19  Thiemo Seufer <ths@mips.com>
  78             Nigel Stephens  <nigel@mips.com>
  79
  80         * interp.c (MEM_SIZE): Increase default memory size from 2 to 8
  81         MBytes.
  82
  83 2007-02-17  Thiemo Seufer  <ths@mips.com>
  84
  85         * configure.ac (mips*-sde-elf*): Move in front of generic machine
  86         configuration.
  87         * configure: Regenerate.
  88
  89 2007-02-17  Thiemo Seufer  <ths@mips.com>
  90
  91         * configure.ac (mips*-sde-elf*, mipsisa32r2*-*-*, mipsisa64r2*-*-*):
  92         Add mdmx to sim_igen_machine.
  93         (mipsisa64*-*-*): Likewise. Remove dsp.
  94         (mipsisa32*-*-*): Remove dsp.
  95         * configure: Regenerate.
  96
  97 2007-02-13  Thiemo Seufer  <ths@mips.com>
  98
  99         * configure.ac: Add mips*-sde-elf* target.
 100         * configure: Regenerate.
 101
 102 2006-12-21  Hans-Peter Nilsson  <hp@axis.com>
 103
 104         * acconfig.h: Remove.
 105         * config.in, configure: Regenerate.
 106
 107 2006-11-07  Thiemo Seufer  <ths@mips.com>
 108
 109         * dsp.igen (do_w_op): Fix compiler warning.
 110
 111 2006-08-29  Thiemo Seufer  <ths@mips.com>
 112             David Ung  <davidu@mips.com>
 113
 114         * configure.ac (mipsisa32r2*-*-*, mipsisa32*-*-*): Add smartmips to
 115         sim_igen_machine.
 116         * configure: Regenerate.
 117         * mips.igen (model): Add smartmips.
 118         (MADDU): Increment ACX if carry.
 119         (do_mult): Clear ACX.
 120         (ROR,RORV): Add smartmips.
 121         (include): Include smartmips.igen.
 122         * sim-main.h (ACX): Set to REGISTERS[89].
 123         * smartmips.igen: New file.
 124
 125 2006-08-29  Thiemo Seufer  <ths@mips.com>
 126             David Ung  <davidu@mips.com>
 127
 128         * Makefile.in (IGEN_INCLUDE): Add missing includes for m16e.igen and
 129         mips3264r2.igen. Add missing dependency rules.
 130         * m16e.igen: Support for mips16e save/restore instructions.
 131
 132 2006-06-13  Richard Earnshaw  <rearnsha@arm.com>
 133
 134         * configure: Regenerated.
 135
 136 2006-06-05  Daniel Jacobowitz  <dan@codesourcery.com>
 137
 138         * configure: Regenerated.
 139
 140 2006-05-31  Daniel Jacobowitz  <dan@codesourcery.com>
 141
 142         * configure: Regenerated.
 143
 144 2006-05-15 Chao-ying Fu  <fu@mips.com>
 145
 146         * dsp.igen (do_ph_shift, do_w_shra): Fix bugs for rounding instructions.
 147
 148 2006-04-18  Nick Clifton  <nickc@redhat.com>
 149
 150         * dv-tx3904tmr.c (deliver_tx3904tmr_tick): Add missing break
 151         statement.
 152
 153 2006-03-29  Hans-Peter Nilsson  <hp@axis.com>
 154
 155         * configure: Regenerate.
 156
 157 2005-12-14  Chao-ying Fu  <fu@mips.com>
 158
 159         * Makefile.in (SIM_OBJS): Add dsp.o.
 160         (dsp.o): New dependency.
 161         (IGEN_INCLUDE): Add dsp.igen.
 162         * configure.ac (mipsisa32r2*-*-*, mipsisa32*-*-*, mipsisa64r2*-*-*,
 163         mipsisa64*-*-*): Add dsp to sim_igen_machine.
 164         * configure: Regenerate.
 165         * mips.igen: Add dsp model and include dsp.igen.
 166         (MFHI, MFLO, MTHI, MTLO): Remove mips32, mips32r2, mips64, mips64r2,
 167         because these instructions are extended in DSP ASE.
 168         * sim-main.h (LAST_EMBED_REGNUM): Change from 89 to 96 because of
 169         adding 6 DSP accumulator registers and 1 DSP control register.
 170         (AC0LOIDX, AC0HIIDX, AC1LOIDX, AC1HIIDX, AC2LOIDX, AC2HIIDX, AC3LOIDX,
 171         AC3HIIDX, DSPLO, DSPHI, DSPCRIDX, DSPCR, DSPCR_POS_SHIFT,
 172         DSPCR_POS_MASK, DSPCR_POS_SMASK, DSPCR_SCOUNT_SHIFT, DSPCR_SCOUNT_MASK,
 173         DSPCR_SCOUNT_SMASK, DSPCR_CARRY_SHIFT, DSPCR_CARRY_MASK,
 174         DSPCR_CARRY_SMASK, DSPCR_CARRY, DSPCR_EFI_SHIFT, DSPCR_EFI_MASK,
 175         DSPCR_EFI_SMASK, DSPCR_EFI, DSPCR_OUFLAG_SHIFT, DSPCR_OUFLAG_MASK,
 176         DSPCR_OUFLAG_SMASK, DSPCR_OUFLAG4, DSPCR_OUFLAG5, DSPCR_OUFLAG6,
 177         DSPCR_OUFLAG7, DSPCR_CCOND_SHIFT, DSPCR_CCOND_MASK,
 178         DSPCR_CCOND_SMASK): New define.
 179         (DSPLO_REGNUM, DSPHI_REGNUM): New array for DSP accumulators.
 180         * dsp.c, dsp.igen: New files for MIPS DSP ASE.
 181
 182 2005-07-08  Ian Lance Taylor  <ian@airs.com>
 183
 184         * tconfig.in (SIM_QUIET_NAN_NEGATED): Define.
 185
 186 2005-06-16  David Ung  <davidu@mips.com>
 187             Nigel Stephens  <nigel@mips.com>
 188
 189         * mips.igen: New mips16e model and include m16e.igen.
 190         (check_u64): Add mips16e tag.
 191         * m16e.igen: New file for MIPS16e instructions.
 192         * configure.ac (mipsisa32*-*-*, mipsisa32r2*-*-*, mipsisa64*-*-*,
 193         mipsisa64r2*-*-*): Change sim_gen to M16, add mips16 and mips16e
 194         models.
 195         * configure: Regenerate.
 196
 197 2005-05-26  David Ung  <davidu@mips.com>
 198
 199         * mips.igen (mips32r2, mips64r2): New ISA models.  Add new model
 200         tags to all instructions which are applicable to the new ISAs.
 201         (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
 202         vr.igen.
 203         * mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
 204         instructions.
 205         * vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
 206         to mips.igen.
 207         * configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
 208         * configure: Regenerate.
 209
 210 2005-03-23  Mark Kettenis  <kettenis@gnu.org>
 211
 212         * configure: Regenerate.
 213
 214 2005-01-14  Andrew Cagney  <cagney@gnu.org>
 215
 216         * configure.ac: Sinclude aclocal.m4 before common.m4.  Add
 217         explicit call to AC_CONFIG_HEADER.
 218         * configure: Regenerate.
 219
 220 2005-01-12  Andrew Cagney  <cagney@gnu.org>
 221
 222         * configure.ac: Update to use ../common/common.m4.
 223         * configure: Re-generate.
 224
 225 2005-01-11  Andrew Cagney  <cagney@localhost.localdomain>
 226
 227         * configure: Regenerated to track ../common/aclocal.m4 changes.
 228
 229 2005-01-07  Andrew Cagney  <cagney@gnu.org>
 230
 231         * configure.ac: Rename configure.in, require autoconf 2.59.
 232         * configure: Re-generate.
 233
 234 2004-12-08  Hans-Peter Nilsson  <hp@axis.com>
 235
 236         * configure: Regenerate for ../common/aclocal.m4 update.
 237
 238 2004-09-24  Monika Chaddha  <monika@acmet.com>
 239
 240         Committed by Andrew Cagney.
 241         * m16.igen (CMP, CMPI): Fix assembler.
 242
 243 2004-08-18  Chris Demetriou  <cgd@broadcom.com>
 244
 245         * configure.in (mipsisa64sb1*-*-*): Add mips3d to sim_igen_machine.
 246         * configure: Regenerate.
 247
 248 2004-06-25  Chris Demetriou  <cgd@broadcom.com>
 249
 250         * configure.in (sim_m16_machine): Include mipsIII.
 251         * configure: Regenerate.
 252
 253 2004-05-11  Maciej W. Rozycki  <macro@ds2.pg.gda.pl>
 254
 255         * mips/interp.c (decode_coproc): Sign-extend the address retrieved
 256         from COP0_BADVADDR.
 257         * mips/sim-main.h (COP0_BADVADDR): Remove a cast.
 258
 259 2004-04-10  Chris Demetriou  <cgd@broadcom.com>
 260
 261         * sb1.igen (DIV.PS, RECIP.PS, RSQRT.PS, SQRT.PS): New.
 262
 263 2004-04-09  Chris Demetriou  <cgd@broadcom.com>
 264
 265         * mips.igen (check_fmt): Remove.
 266         (ABS.fmt, ADD.fmt, C.cond.fmta, C.cond.fmtb, CEIL.L.fmt, CEIL.W)
 267         (CVT.D.fmt, CVT.L.fmt, CVT.S.fmt, CVT.W.fmt, DIV.fmt, FLOOR.L.fmt)
 268         (FLOOR.W.fmt, MADD.fmt, MOV.fmt, MOVtf.fmt, MOVN.fmt, MOVZ.fmt)
 269         (MSUB.fmt, MUL.fmt, NEG.fmt, NMADD.fmt, NMSUB.fmt, RECIP.fmt)
 270         (ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt, SQRT.fmt, SUB.fmt)
 271         (TRUNC.L.fmt, TRUNC.W): Explicitly specify allowed FPU formats.
 272         (check_fmt_p, CEIL.L.fmt, CEIL.W, DIV.fmt, FLOOR.L.fmt)
 273         (FLOOR.W.fmt, RECIP.fmt, ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt)
 274         (SQRT.fmt, TRUNC.L.fmt, TRUNC.W): Remove all uses of check_fmt.
 275         (C.cnd.fmta): Remove incorrect call to check_fmt_p.
 276
 277 2004-04-09  Chris Demetriou  <cgd@broadcom.com>
 278
 279         * sb1.igen (check_sbx): New function.
 280         (PABSDIFF.fmt, PABSDIFC.fmt, PAVG.fmt): Use check_sbx.
 281
 282 2004-03-29  Chris Demetriou  <cgd@broadcom.com>
 283             Richard Sandiford  <rsandifo@redhat.com>
 284
 285         * sim-main.h (MIPS_MACH_HAS_MT_HILO_HAZARD)
 286         (MIPS_MACH_HAS_MULT_HILO_HAZARD, MIPS_MACH_HAS_DIV_HILO_HAZARD): New.
 287         * mips.igen (check_mt_hilo, check_mult_hilo, check_div_hilo): Provide
 288         separate implementations for mipsIV and mipsV.  Use new macros to
 289         determine whether the restrictions apply.
 290
 291 2004-01-19  Chris Demetriou  <cgd@broadcom.com>
 292
 293         * mips.igen (check_mf_cycles, check_mt_hilo, check_mf_hilo)
 294         (check_mult_hilo): Improve comments.
 295         (check_div_hilo): Likewise.  Also, fork off a new version
 296         to handle mips32/mips64 (since there are no hazards to check
 297         in MIPS32/MIPS64).
 298
 299 2003-06-17  Richard Sandiford  <rsandifo@redhat.com>
 300
 301         * mips.igen (do_dmultx): Fix check for negative operands.
 302
 303 2003-05-16  Ian Lance Taylor  <ian@airs.com>
 304
 305         * Makefile.in (SHELL): Make sure this is defined.
 306         (various): Use $(SHELL) whenever we invoke move-if-change.
 307
 308 2003-05-03  Chris Demetriou  <cgd@broadcom.com>
 309
 310         * cp1.c: Tweak attribution slightly.
 311         * cp1.h: Likewise.
 312         * mdmx.c: Likewise.
 313         * mdmx.igen: Likewise.
 314         * mips3d.igen: Likewise.
 315         * sb1.igen: Likewise.
 316
 317 2003-04-15  Richard Sandiford  <rsandifo@redhat.com>
 318
 319         * vr.igen (do_vr_mul_op): Zero-extend the low 32 bits of
 320         unsigned operands.
 321
 322 2003-02-27  Andrew Cagney  <cagney@redhat.com>
 323
 324         * interp.c (sim_open): Rename _bfd to bfd.
 325         (sim_create_inferior): Ditto.
 326
 327 2003-01-14  Chris Demetriou  <cgd@broadcom.com>
 328
 329         * mips.igen (LUXC1, SUXC1): New, for mipsV and mips64.
 330
 331 2003-01-14  Chris Demetriou  <cgd@broadcom.com>
 332
 333         * mips.igen (EI, DI): Remove.
 334
 335 2003-01-05  Richard Sandiford  <rsandifo@redhat.com>
 336
 337         * Makefile.in (tmp-run-multi): Fix mips16 filter.
 338
 339 2003-01-04  Richard Sandiford  <rsandifo@redhat.com>
 340             Andrew Cagney  <ac131313@redhat.com>
 341             Gavin Romig-Koch  <gavin@redhat.com>
 342             Graydon Hoare  <graydon@redhat.com>
 343             Aldy Hernandez  <aldyh@redhat.com>
 344             Dave Brolley  <brolley@redhat.com>
 345             Chris Demetriou  <cgd@broadcom.com>
 346
 347         * configure.in (mips64vr*): Define TARGET_ENABLE_FR to 1.
 348         (sim_mach_default): New variable.
 349         (mips64vr-*-*, mips64vrel-*-*): New configurations.
 350         Add a new simulator generator, MULTI.
 351         * configure: Regenerate.
 352         * Makefile.in (SIM_MULTI_OBJ, SIM_EXTRA_DISTCLEAN): New variables.
 353         (multi-run.o): New dependency.
 354         (SIM_MULTI_ALL, SIM_MULTI_IGEN_CONFIGS): New variables.
 355         (tmp-mach-multi, tmp-itable-multi, tmp-run-multi): New rules.
 356         (tmp-multi): Combine them.
 357         (BUILT_SRC_FROM_MULTI): New variable.  Depend on tmp-multi.
 358         (clean-extra): Remove sources in BUILT_SRC_FROM_MULTI.
 359         (distclean-extra): New rule.
 360         * sim-main.h: Include bfd.h.
 361         (MIPS_MACH): New macro.
 362         * mips.igen (vr4120, vr5400, vr5500): New models.
 363         (clo, clz, dclo, dclz, madd, maddu, msub, msub, mul): Add *vr5500.
 364         * vr.igen: Replace with new version.
 365
 366 2003-01-04  Chris Demetriou  <cgd@broadcom.com>
 367
 368         * configure.in: Use SIM_AC_OPTION_RESERVED_BITS(1).
 369         * configure: Regenerate.
 370
 371 2002-12-31  Chris Demetriou  <cgd@broadcom.com>
 372
 373         * sim-main.h (check_branch_bug, mark_branch_bug): Remove.
 374         * mips.igen: Remove all invocations of check_branch_bug and
 375         mark_branch_bug.
 376
 377 2002-12-16  Chris Demetriou  <cgd@broadcom.com>
 378
 379         * tconfig.in: Include "gdb/callback.h" and "gdb/remote-sim.h".
 380
 381 2002-07-30  Chris Demetriou  <cgd@broadcom.com>
 382
 383         * mips.igen (do_load_double, do_store_double): New functions.
 384         (LDC1, SDC1): Rename to...
 385         (LDC1b, SDC1b): respectively.
 386         (LDC1a, SDC1a): New instructions for MIPS II and MIPS32 support.
 387
 388 2002-07-29  Michael Snyder  <msnyder@redhat.com>
 389
 390         * cp1.c (fp_recip2): Modify initialization expression so that
 391         GCC will recognize it as constant.
 392
 393 2002-06-18  Chris Demetriou  <cgd@broadcom.com>
 394
 395         * mdmx.c (SD_): Delete.
 396         (Unpredictable): Re-define, for now, to directly invoke
 397         unpredictable_action().
 398         (mdmx_acc_op): Fix error in .ob immediate handling.
 399
 400 2002-06-18  Andrew Cagney  <cagney@redhat.com>
 401
 402         * interp.c (sim_firmware_command): Initialize `address'.
 403
 404 2002-06-16  Andrew Cagney  <ac131313@redhat.com>
 405
 406         * configure: Regenerated to track ../common/aclocal.m4 changes.
 407
 408 2002-06-14  Chris Demetriou  <cgd@broadcom.com>
 409             Ed Satterthwaite  <ehs@broadcom.com>
 410
 411         * mips3d.igen: New file which contains MIPS-3D ASE instructions.
 412         * Makefile.in (IGEN_INCLUDE): Add mips3d.igen.
 413         * mips.igen: Include mips3d.igen.
 414         (mips3d): New model name for MIPS-3D ASE instructions.
 415         (CVT.W.fmt): Don't use this instruction for word (source) format
 416         instructions.
 417         * cp1.c (fp_binary_r, fp_add_r, fp_mul_r, fpu_inv1, fpu_inv1_32)
 418         (fpu_inv1_64, fp_recip1, fp_recip2, fpu_inv_sqrt1, fpu_inv_sqrt1_32)
 419         (fpu_inv_sqrt1_64, fp_rsqrt1, fp_rsqrt2): New functions.
 420         (NR_FRAC_GUARD, IMPLICIT_1): New macros.
 421         * sim-main.h (fmt_pw, CompareAbs, AddR, MultiplyR, Recip1, Recip2)
 422         (RSquareRoot1, RSquareRoot2): New macros.
 423         (fp_add_r, fp_mul_r, fp_recip1, fp_recip2, fp_rsqrt1)
 424         (fp_rsqrt2): New functions.
 425         * configure.in: Add MIPS-3D support to mipsisa64 simulator.
 426         * configure: Regenerate.
 427
 428 2002-06-13  Chris Demetriou  <cgd@broadcom.com>
 429             Ed Satterthwaite  <ehs@broadcom.com>
 430
 431         * cp1.c (FP_PS_upper, FP_PS_lower, FP_PS_cat, FPQNaN_PS): New macros.
 432         (value_fpr, store_fpr, fp_cmp, fp_unary, fp_binary, fp_mac)
 433         (fp_inv_sqrt, fpu_format_name): Add paired-single support.
 434         (convert): Note that this function is not used for paired-single
 435         format conversions.
 436         (ps_lower, ps_upper, pack_ps, convert_ps): New functions.
 437         * mips.igen (FMT, MOVtf.fmt): Add paired-single support.
 438         (check_fmt_p): Enable paired-single support.
 439         (ALNV.PS, CVT.PS.S, CVT.S.PL, CVT.S.PU, PLL.PS, PLU.PS, PUL.PS)
 440         (PUU.PS): New instructions.
 441         (CVT.S.fmt): Don't use this instruction for paired-single format
 442         destinations.
 443         * sim-main.h (FP_formats): New value 'fmt_ps.'
 444         (ps_lower, ps_upper, pack_ps, convert_ps): New prototypes.
 445         (PSLower, PSUpper, PackPS, ConvertPS): New macros.
 446
 447 2002-06-12  Chris Demetriou  <cgd@broadcom.com>
 448
 449         * mips.igen: Fix formatting of function calls in
 450         many FP operations.
 451
 452 2002-06-12  Chris Demetriou  <cgd@broadcom.com>
 453
 454         * mips.igen (MOVN, MOVZ): Trace result.
 455         (TNEI): Print "tnei" as the opcode name in traces.
 456         (CEIL.W): Add disassembly string for traces.
 457         (RSQRT.fmt): Make location of disassembly string consistent
 458         with other instructions.
 459
 460 2002-06-12  Chris Demetriou  <cgd@broadcom.com>
 461
 462         * mips.igen (X): Delete unused function.
 463
 464 2002-06-08  Andrew Cagney  <cagney@redhat.com>
 465
 466         * interp.c: Include "gdb/callback.h" and "gdb/remote-sim.h".
 467
 468 2002-06-07  Chris Demetriou  <cgd@broadcom.com>
 469             Ed Satterthwaite  <ehs@broadcom.com>
 470
 471         * cp1.c (inner_mac, fp_mac, inner_rsqrt, fp_inv_sqrt)
 472         (fp_rsqrt, fp_madd, fp_msub, fp_nmadd, fp_nmsub): New functions.
 473         * sim-main.h (fp_rsqrt, fp_madd, fp_msub, fp_nmadd)
 474         (fp_nmsub): New prototypes.
 475         (RSquareRoot, MultiplyAdd, MultiplySub, NegMultiplyAdd)
 476         (NegMultiplySub): New defines.
 477         * mips.igen (RSQRT.fmt): Use RSquareRoot().
 478         (MADD.D, MADD.S): Replace with...
 479         (MADD.fmt): New instruction.
 480         (MSUB.D, MSUB.S): Replace with...
 481         (MSUB.fmt): New instruction.
 482         (NMADD.D, NMADD.S): Replace with...
 483         (NMADD.fmt): New instruction.
 484         (NMSUB.D, MSUB.S): Replace with...
 485         (NMSUB.fmt): New instruction.
 486
 487 2002-06-07  Chris Demetriou  <cgd@broadcom.com>
 488             Ed Satterthwaite  <ehs@broadcom.com>
 489
 490         * cp1.c: Fix more comment spelling and formatting.
 491         (value_fcr, store_fcr): Use fenr_FS rather than hard-coding value.
 492         (denorm_mode): New function.
 493         (fpu_unary, fpu_binary): Round results after operation, collect
 494         status from rounding operations, and update the FCSR.
 495         (convert): Collect status from integer conversions and rounding
 496         operations, and update the FCSR.  Adjust NaN values that result
 497         from conversions.  Convert to use sim_io_eprintf rather than
 498         fprintf, and remove some debugging code.
 499         * cp1.h (fenr_FS): New define.
 500
 501 2002-06-07  Chris Demetriou  <cgd@broadcom.com>
 502
 503         * cp1.c (convert): Remove unusable debugging code, and move MIPS
 504         rounding mode to sim FP rounding mode flag conversion code into...
 505         (rounding_mode): New function.
 506
 507 2002-06-07  Chris Demetriou  <cgd@broadcom.com>
 508
 509         * cp1.c: Clean up formatting of a few comments.
 510         (value_fpr): Reformat switch statement.
 511
 512 2002-06-06  Chris Demetriou  <cgd@broadcom.com>
 513             Ed Satterthwaite  <ehs@broadcom.com>
 514
 515         * cp1.h: New file.
 516         * sim-main.h: Include cp1.h.
 517         (SETFCC, GETFCC, IR, UF, OF, DX, IO, UO, FP_FLAGS, FP_ENABLE)
 518         (FP_CAUSE, GETFS, FP_RM_NEAREST, FP_RM_TOZERO, FP_RM_TOPINF)
 519         (FP_RM_TOMINF, GETRM): Remove.  Moved to cp1.h.
 520         (FP_FS, FP_MASK_RM, FP_SH_RM, Nan, Less, Equal): Remove.
 521         (value_fcr, store_fcr, test_fcsr, fp_cmp): New prototypes.
 522         (ValueFCR, StoreFCR, TestFCSR, Compare): New macros.
 523         * cp1.c: Don't include sim-fpu.h; already included by
 524         sim-main.h.  Clean up formatting of some comments.
 525         (NaN, Equal, Less): Remove.
 526         (test_fcsr, value_fcr, store_fcr, update_fcsr, fp_test)
 527         (fp_cmp): New functions.
 528         * mips.igen (do_c_cond_fmt): Remove.
 529         (C.cond.fmta, C.cond.fmtb): Replace uses of do_c_cond_fmt_a with
 530         Compare.  Add result tracing.
 531         (CxC1): Remove, replace with...
 532         (CFC1a, CFC1b, CFC1c, CTC1a, CTC1b, CTC1c): New instructions.
 533         (DMxC1): Remove, replace with...
 534         (DMFC1a, DMFC1b, DMTC1a, DMTC1b): New instructions.
 535         (MxC1): Remove, replace with...
 536         (MFC1a, MFC1b, MTC1a, MTC1b): New instructions.
 537
 538 2002-06-04  Chris Demetriou  <cgd@broadcom.com>
 539
 540         * sim-main.h (FGRIDX): Remove, replace all uses with...
 541         (FGR_BASE): New macro.
 542         (FP0_REGNUM, FCRCS_REGNUM, FCRIR_REGNUM): New macros.
 543         (_sim_cpu): Move 'fgr' member to be right before 'fpr_state' member.
 544         (NR_FGR, FGR): Likewise.
 545         * interp.c: Replace all uses of FGRIDX with FGR_BASE.
 546         * mips.igen: Likewise.
 547
 548 2002-06-04  Chris Demetriou  <cgd@broadcom.com>
 549
 550         * cp1.c: Add an FSF Copyright notice to this file.
 551
 552 2002-06-04  Chris Demetriou  <cgd@broadcom.com>
 553             Ed Satterthwaite  <ehs@broadcom.com>
 554
 555         * cp1.c (Infinity): Remove.
 556         * sim-main.h (Infinity): Likewise.
 557
 558         * cp1.c (fp_unary, fp_binary): New functions.
 559         (fp_abs, fp_neg, fp_add, fp_sub, fp_mul, fp_div, fp_recip)
 560         (fp_sqrt): New functions, implemented in terms of the above.
 561         (AbsoluteValue, Negate, Add, Sub, Multiply, Divide)
 562         (Recip, SquareRoot): Remove (replaced by functions above).
 563         * sim-main.h (fp_abs, fp_neg, fp_add, fp_sub, fp_mul, fp_div)
 564         (fp_recip, fp_sqrt): New prototypes.
 565         (AbsoluteValue, Negate, Add, Sub, Multiply, Divide)
 566         (Recip, SquareRoot): Replace prototypes with #defines which
 567         invoke the functions above.
 568
 569 2002-06-03  Chris Demetriou  <cgd@broadcom.com>
 570
 571         * sim-main.h (Nan, Infinity, Less, Equal, AbsoluteValue, Negate)
 572         (Add, Sub, Multiply, Divide, Recip, SquareRoot): Move lower in
 573         file, remove PARAMS from prototypes.
 574         (value_fpr, store_fpr, convert): Likewise.  Use SIM_STATE to provide
 575         simulator state arguments.
 576         (ValueFPR, StoreFPR, Convert): Move lower in file.  Use SIM_ARGS to
 577         pass simulator state arguments.
 578         * cp1.c (SD): Redefine as CPU_STATE(cpu).
 579         (store_fpr, convert): Remove 'sd' argument.
 580         (value_fpr): Likewise.  Convert to use 'SD' instead.
 581
 582 2002-06-03  Chris Demetriou  <cgd@broadcom.com>
 583
 584         * cp1.c (Min, Max): Remove #if 0'd functions.
 585         * sim-main.h (Min, Max): Remove.
 586
 587 2002-06-03  Chris Demetriou  <cgd@broadcom.com>
 588
 589         * cp1.c: fix formatting of switch case and default labels.
 590         * interp.c: Likewise.
 591         * sim-main.c: Likewise.
 592
 593 2002-06-03  Chris Demetriou  <cgd@broadcom.com>
 594
 595         * cp1.c: Clean up comments which describe FP formats.
 596          (FPQNaN_DOUBLE, FPQNaN_LONG): Generate using UNSIGNED64.
 597
 598 2002-06-03  Chris Demetriou  <cgd@broadcom.com>
 599             Ed Satterthwaite  <ehs@broadcom.com>
 600
 601         * configure.in (mipsisa64sb1*-*-*): New target for supporting
 602         Broadcom SiByte SB-1 processor configurations.
 603         * configure: Regenerate.
 604         * sb1.igen: New file.
 605         * mips.igen: Include sb1.igen.
 606         (sb1): New model.
 607         * Makefile.in (IGEN_INCLUDE): Add sb1.igen.
 608         * mdmx.igen: Add "sb1" model to all appropriate functions and
 609         instructions.
 610         * mdmx.c (AbsDiffOB, AvgOB, AccAbsDiffOB): New functions.
 611         (ob_func, ob_acc): Reference the above.
 612         (qh_acc): Adjust to keep the same size as ob_acc.
 613         * sim-main.h (status_SBX, MX_VECT_ABSD, MX_VECT_AVG, MX_AbsDiff)
 614         (MX_Avg, MX_VECT_ABSDA, MX_AbsDiffC): New macros.
 615
 616 2002-06-03  Chris Demetriou  <cgd@broadcom.com>
 617
 618         * Makefile.in (IGEN_INCLUDE): Add mdmx.igen.
 619
 620 2002-06-02  Chris Demetriou  <cgd@broadcom.com>
 621             Ed Satterthwaite  <ehs@broadcom.com>
 622
 623         * mips.igen (mdmx): New (pseudo-)model.
 624         * mdmx.c, mdmx.igen: New files.
 625         * Makefile.in (SIM_OBJS): Add mdmx.o.
 626         * sim-main.h (MDMX_accumulator, MX_fmtsel, signed24, signed48):
 627         New typedefs.
 628         (ACC, MX_Add, MX_AddA, MX_AddL, MX_And, MX_C_EQ, MX_C_LT, MX_Comp)
 629         (MX_FMT_OB, MX_FMT_QH, MX_Max, MX_Min, MX_Msgn, MX_Mul, MX_MulA)
 630         (MX_MulL, MX_MulS, MX_MulSL, MX_Nor, MX_Or, MX_Pick, MX_RAC)
 631         (MX_RAC_H, MX_RAC_L, MX_RAC_M, MX_RNAS, MX_RNAU, MX_RND_AS)
 632         (MX_RND_AU, MX_RND_ES, MX_RND_EU, MX_RND_ZS, MX_RND_ZU, MX_RNES)
 633         (MX_RNEU, MX_RZS, MX_RZU, MX_SHFL, MX_ShiftLeftLogical)
 634         (MX_ShiftRightArith, MX_ShiftRightLogical, MX_Sub, MX_SubA, MX_SubL)
 635         (MX_VECT_ADD, MX_VECT_ADDA, MX_VECT_ADDL, MX_VECT_AND)
 636         (MX_VECT_MAX, MX_VECT_MIN, MX_VECT_MSGN, MX_VECT_MUL, MX_VECT_MULA)
 637         (MX_VECT_MULL, MX_VECT_MULS, MX_VECT_MULSL, MX_VECT_NOR)
 638         (MX_VECT_OR, MX_VECT_SLL, MX_VECT_SRA, MX_VECT_SRL, MX_VECT_SUB)
 639         (MX_VECT_SUBA, MX_VECT_SUBL, MX_VECT_XOR, MX_WACH, MX_WACL, MX_Xor)
 640         (SIM_ARGS, SIM_STATE, UnpredictableResult, fmt_mdmx, ob_fmtsel)
 641         (qh_fmtsel): New macros.
 642         (_sim_cpu): New member "acc".
 643         (mdmx_acc_op, mdmx_cc_op, mdmx_cpr_op, mdmx_pick_op, mdmx_rac_op)
 644         (mdmx_round_op, mdmx_shuffle, mdmx_wach, mdmx_wacl): New functions.
 645
 646 2002-05-01  Chris Demetriou  <cgd@broadcom.com>
 647
 648         * interp.c: Use 'deprecated' rather than 'depreciated.'
 649         * sim-main.h: Likewise.
 650
 651 2002-05-01  Chris Demetriou  <cgd@broadcom.com>
 652
 653         * cp1.c (store_fpr): Remove #ifdef'd out call to UndefinedResult
 654         which wouldn't compile anyway.
 655         * sim-main.h (unpredictable_action): New function prototype.
 656         (Unpredictable): Define to call igen function unpredictable().
 657         (NotWordValue): New macro to call igen function not_word_value().
 658         (UndefinedResult): Remove.
 659         * interp.c (undefined_result): Remove.
 660         (unpredictable_action): New function.
 661         * mips.igen (not_word_value, unpredictable): New functions.
 662         (ADD, ADDI, do_addiu, do_addu, BGEZAL, BGEZALL, BLTZAL, BLTZALL)
 663         (CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, do_mult, do_multu)
 664         (do_sra, do_srav, do_srl, do_srlv, SUB, do_subu): Invoke
 665         NotWordValue() to check for unpredictable inputs, then
 666         Unpredictable() to handle them.
 667
 668 2002-02-24  Chris Demetriou  <cgd@broadcom.com>
 669
 670         * mips.igen: Fix formatting of calls to Unpredictable().
 671
 672 2002-04-20  Andrew Cagney  <ac131313@redhat.com>
 673
 674         * interp.c (sim_open): Revert previous change.
 675
 676 2002-04-18  Alexandre Oliva  <aoliva@redhat.com>
 677
 678         * interp.c (sim_open): Disable chunk of code that wrote code in
 679         vector table entries.
 680
 681 2002-03-19  Chris Demetriou  <cgd@broadcom.com>
 682
 683         * cp1.c (FP_S_s, FP_D_s, FP_S_be, FP_D_be, FP_S_e, FP_D_e, FP_S_f)
 684         (FP_D_f, FP_S_fb, FP_D_fb, FPINF_SINGLE, FPINF_DOUBLE): Remove
 685         unused definitions.
 686
 687 2002-03-19  Chris Demetriou  <cgd@broadcom.com>
 688
 689         * cp1.c: Fix many formatting issues.
 690
 691 2002-03-19  Chris G. Demetriou  <cgd@broadcom.com>
 692
 693         * cp1.c (fpu_format_name): New function to replace...
 694         (DOFMT): This.  Delete, and update all callers.
 695         (fpu_rounding_mode_name): New function to replace...
 696         (RMMODE): This.  Delete, and update all callers.
 697
 698 2002-03-19  Chris G. Demetriou  <cgd@broadcom.com>
 699
 700         * interp.c: Move FPU support routines from here to...
 701         * cp1.c: Here.  New file.
 702         * Makefile.in (SIM_OBJS): Add cp1.o to object list.
 703         (cp1.o): New target.
 704
 705 2002-03-12  Chris Demetriou  <cgd@broadcom.com>
 706
 707         * configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
 708         * mips.igen (mips32, mips64): New models, add to all instructions
 709         and functions as appropriate.
 710         (loadstore_ea, check_u64): New variant for model mips64.
 711         (check_fmt_p): New variant for models mipsV and mips64, remove
 712         mipsV model marking fro other variant.
 713         (SLL) Rename to...
 714         (SLLa) this.
 715         (CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
 716         for mips32 and mips64.
 717         (DCLO, DCLZ): New instructions for mips64.
 718
 719 2002-03-07  Chris Demetriou  <cgd@broadcom.com>
 720
 721         * mips.igen (BREAK, LUI, ORI, SYSCALL, XORI): Print
 722         immediate or code as a hex value with the "%#lx" format.
 723         (ANDI): Likewise, and fix printed instruction name.
 724
 725 2002-03-05  Chris Demetriou  <cgd@broadcom.com>
 726
 727         * sim-main.h (UndefinedResult, Unpredictable): New macros
 728         which currently do nothing.
 729
 730 2002-03-05  Chris Demetriou  <cgd@broadcom.com>
 731
 732         * sim-main.h (status_UX, status_SX, status_KX, status_TS)
 733         (status_PX, status_MX, status_CU0, status_CU1, status_CU2)
 734         (status_CU3): New definitions.
 735
 736         * sim-main.h (ExceptionCause): Add new values for MIPS32
 737         and MIPS64: MDMX, MCheck, CacheErr.  Update comments
 738         for DebugBreakPoint and NMIReset to note their status in
 739         MIPS32 and MIPS64.
 740         (SignalExceptionMDMX, SignalExceptionWatch, SignalExceptionMCheck)
 741         (SignalExceptionCacheErr): New exception macros.
 742
 743 2002-03-05  Chris Demetriou  <cgd@broadcom.com>
 744
 745         * mips.igen (check_fpu): Enable check for coprocessor 1 usability.
 746         * sim-main.h (COP_Usable): Define, but for now coprocessor 1
 747         is always enabled.
 748         (SignalExceptionCoProcessorUnusable): Take as argument the
 749         unusable coprocessor number.
 750
 751 2002-03-05  Chris Demetriou  <cgd@broadcom.com>
 752
 753         * mips.igen: Fix formatting of all SignalException calls.
 754
 755 2002-03-05  Chris Demetriou  <cgd@broadcom.com>
 756
 757         * sim-main.h (SIGNEXTEND): Remove.
 758
 759 2002-03-04  Chris Demetriou  <cgd@broadcom.com>
 760
 761         * mips.igen: Remove gencode comment from top of file, fix
 762         spelling in another comment.
 763
 764 2002-03-04  Chris Demetriou  <cgd@broadcom.com>
 765
 766         * mips.igen (check_fmt, check_fmt_p): New functions to check
 767         whether specific floating point formats are usable.
 768         (ABS.fmt, ADD.fmt, CEIL.L.fmt, CEIL.W, DIV.fmt, FLOOR.L.fmt)
 769         (FLOOR.W.fmt, MOV.fmt, MUL.fmt, NEG.fmt, RECIP.fmt, ROUND.L.fmt)
 770         (ROUND.W.fmt, RSQRT.fmt, SQRT.fmt, SUB.fmt, TRUNC.L.fmt, TRUNC.W):
 771         Use the new functions.
 772         (do_c_cond_fmt): Remove format checks...
 773         (C.cond.fmta, C.cond.fmtb): And move them into all callers.
 774
 775 2002-03-03  Chris Demetriou  <cgd@broadcom.com>
 776
 777         * mips.igen: Fix formatting of check_fpu calls.
 778
 779 2002-03-03  Chris Demetriou  <cgd@broadcom.com>
 780
 781         * mips.igen (FLOOR.L.fmt): Store correct destination register.
 782
 783 2002-03-03  Chris Demetriou  <cgd@broadcom.com>
 784
 785         * mips.igen: Remove whitespace at end of lines.
 786
 787 2002-03-02  Chris Demetriou  <cgd@broadcom.com>
 788
 789         * mips.igen (loadstore_ea): New function to do effective
 790         address calculations.
 791         (do_load, do_load_left, do_load_right, LL, LDD, PREF, do_store,
 792         do_store_left, do_store_right, SC, SCD, PREFX, SWC1, SWXC1,
 793         CACHE): Use loadstore_ea to do effective address computations.
 794
 795 2002-03-02  Chris Demetriou  <cgd@broadcom.com>
 796
 797         * interp.c (load_word): Use EXTEND32 rather than SIGNEXTEND.
 798         * mips.igen (LL, CxC1, MxC1): Likewise.
 799
 800 2002-03-02  Chris Demetriou  <cgd@broadcom.com>
 801
 802         * mips.igen (LL, LLD, PREF, SC, SCD, ABS.fmt, ADD.fmt, CEIL.L.fmt,
 803         CEIL.W, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt, CVT.W.fmt, DIV.fmt,
 804         FLOOR.L.fmt, FLOOR.W.fmt, MADD.D, MADD.S, MOV.fmt, MOVtf.fmt,
 805         MSUB.D, MSUB.S, MUL.fmt, NEG.fmt, NMADD.D, NMADD.S, NMSUB.D,
 806         NMSUB.S, PREFX, RECIP.fmt, ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt,
 807         SQRT.fmt, SUB.fmt, SWC1, SWXC1, TRUNC.L.fmt, TRUNC.W, CACHE):
 808         Don't split opcode fields by hand, use the opcode field values
 809         provided by igen.
 810
 811 2002-03-01  Chris Demetriou  <cgd@broadcom.com>
 812
 813         * mips.igen (do_divu): Fix spacing.
 814
 815         * mips.igen (do_dsllv): Move to be right before DSLLV,
 816         to match the rest of the do_<shift> functions.
 817
 818 2002-03-01  Chris Demetriou  <cgd@broadcom.com>
 819
 820         * mips.igen (do_dsll, do_dsllv, DSLL32, do_dsra, DSRA32, do_dsrl,
 821         DSRL32, do_dsrlv): Trace inputs and results.
 822
 823 2002-03-01  Chris Demetriou  <cgd@broadcom.com>
 824
 825         * mips.igen (CACHE): Provide instruction-printing string.
 826
 827         * interp.c (signal_exception): Comment tokens after #endif.
 828
 829 2002-02-28  Chris Demetriou  <cgd@broadcom.com>
 830
 831         * mips.igen (LWXC1): Mark with filter "64,f", rather than just "32".
 832         (MOVtf, MxC1, MxC1, DMxC1, DMxC1, CxC1, CxC1, SQRT.fmt, MOV.fmt,
 833         NEG.fmt, ROUND.L.fmt, TRUNC.L.fmt, CEIL.L.fmt, FLOOR.L.fmt,
 834         ROUND.W.fmt, TRUNC.W, CEIL.W, FLOOR.W.fmt, RECIP.fmt, RSQRT.fmt,
 835         CVT.S.fmt, CVT.D.fmt, CVT.W.fmt, CVT.L.fmt, MOVtf.fmt, C.cond.fmta,
 836         C.cond.fmtb, SUB.fmt, MUL.fmt, DIV.fmt, MOVZ.fmt, MOVN.fmt, LDXC1,
 837         SWXC1, SDXC1, MSUB.D, MSUB.S, NMADD.S, NMADD.D, NMSUB.S, NMSUB.D,
 838         LWC1, SWC1): Add "f" to filter, since these are FP instructions.
 839
 840 2002-02-28  Chris Demetriou  <cgd@broadcom.com>
 841
 842         * mips.igen (DSRA32, DSRAV): Fix order of arguments in
 843         instruction-printing string.
 844         (LWU): Use '64' as the filter flag.
 845
 846 2002-02-28  Chris Demetriou  <cgd@broadcom.com>
 847
 848         * mips.igen (SDXC1): Fix instruction-printing string.
 849
 850 2002-02-28  Chris Demetriou  <cgd@broadcom.com>
 851
 852         * mips.igen (LDC1, SDC1): Remove mipsI model, and mark with
 853         filter flags "32,f".
 854
 855 2002-02-27  Chris Demetriou  <cgd@broadcom.com>
 856
 857         * mips.igen (PREFX): This is a 64-bit instruction, use '64'
 858         as the filter flag.
 859
 860 2002-02-27  Chris Demetriou  <cgd@broadcom.com>
 861
 862         * mips.igen (PREFX): Tweak instruction opcode fields (i.e.,
 863         add a comma) so that it more closely match the MIPS ISA
 864         documentation opcode partitioning.
 865         (PREF): Put useful names on opcode fields, and include
 866         instruction-printing string.
 867
 868 2002-02-27  Chris Demetriou  <cgd@broadcom.com>
 869
 870         * mips.igen (check_u64): New function which in the future will
 871         check whether 64-bit instructions are usable and signal an
 872         exception if not.  Currently a no-op.
 873         (DADD, DADDI, DADDIU, DADDU, DDIV, DDIVU, DMULT, DMULTU, DSLL,
 874         DSLL32, DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB,
 875         DSUBU, LD, LDL, LDR, LLD, LWU, SCD, SD, SDL, SDR, DMxC1, LDXC1,
 876         LWXC1, SDXC1, SWXC1, DMFC0, DMTC0): Use check_u64.
 877
 878         * mips.igen (check_fpu): New function which in the future will
 879         check whether FPU instructions are usable and signal an exception
 880         if not.  Currently a no-op.
 881         (ABS.fmt, ADD.fmt, BC1a, BC1b, C.cond.fmta, C.cond.fmtb,
 882         CEIL.L.fmt, CEIL.W, CxC1, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt,
 883         CVT.W.fmt, DIV.fmt, DMxC1, DMxC1, FLOOR.L.fmt, FLOOR.W.fmt, LDC1,
 884         LDXC1, LWC1, LWXC1, MADD.D, MADD.S, MxC1, MOV.fmt, MOVtf,
 885         MOVtf.fmt, MOVN.fmt, MOVZ.fmt, MSUB.D, MSUB.S, MUL.fmt, NEG.fmt,
 886         NMADD.D, NMADD.S, NMSUB.D, NMSUB.S, RECIP.fmt, ROUND.L.fmt,
 887         ROUND.W.fmt, RSQRT.fmt, SDC1, SDXC1, SQRT.fmt, SUB.fmt, SWC1,
 888         SWXC1, TRUNC.L.fmt, TRUNC.W): Use check_fpu.
 889
 890 2002-02-27  Chris Demetriou  <cgd@broadcom.com>
 891
 892         * mips.igen (do_load_left, do_load_right): Move to be immediately
 893         following do_load.
 894         (do_store_left, do_store_right): Move to be immediately following
 895         do_store.
 896
 897 2002-02-27  Chris Demetriou  <cgd@broadcom.com>
 898
 899         * mips.igen (mipsV): New model name.  Also, add it to
 900         all instructions and functions where it is appropriate.
 901
 902 2002-02-18  Chris Demetriou  <cgd@broadcom.com>
 903
 904         * mips.igen: For all functions and instructions, list model
 905         names that support that instruction one per line.
 906
 907 2002-02-11  Chris Demetriou  <cgd@broadcom.com>
 908
 909         * mips.igen: Add some additional comments about supported
 910         models, and about which instructions go where.
 911         (BC1b, MFC0, MTC0, RFE): Sort supported models in the same
 912         order as is used in the rest of the file.
 913
 914 2002-02-11  Chris Demetriou  <cgd@broadcom.com>
 915
 916         * mips.igen (ADD, ADDI, DADDI, DSUB, SUB): Add comment
 917         indicating that ALU32_END or ALU64_END are there to check
 918         for overflow.
 919         (DADD): Likewise, but also remove previous comment about
 920         overflow checking.
 921
 922 2002-02-10  Chris Demetriou  <cgd@broadcom.com>
 923
 924         * mips.igen (DDIV, DIV, DIVU, DMULT, DMULTU, DSLL, DSLL32,
 925         DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB, DSUBU,
 926         JALR, JR, MOVN, MOVZ, MTLO, MULT, MULTU, SLL, SLLV, SLT, SLTU,
 927         SRAV, SRLV, SUB, SUBU, SYNC, XOR, MOVtf, DI, DMFC0, DMTC0, EI,
 928         ERET, RFE, TLBP, TLBR, TLBWI, TLBWR): Tweak instruction opcode
 929         fields (i.e., add and move commas) so that they more closely
 930         match the MIPS ISA documentation opcode partitioning.
 931
 932 2002-02-10  Chris Demetriou  <cgd@broadcom.com>
 933
 934         * mips.igen (ADDI): Print immediate value.
 935         (BREAK): Print code.
 936         (DADDIU, DSRAV, DSRLV): Print correct instruction name.
 937         (SLL): Print "nop" specially, and don't run the code
 938         that does the shift for the "nop" case.
 939
 940 2001-11-17  Fred Fish  <fnf@redhat.com>
 941
 942         * sim-main.h (float_operation): Move enum declaration outside
 943         of _sim_cpu struct declaration.
 944
 945 2001-04-12  Jim Blandy  <jimb@redhat.com>
 946
 947         * mips.igen (CFC1, CTC1): Pass the correct register numbers to
 948         PENDING_FILL.  Use PENDING_SCHED directly to handle the pending
 949         set of the FCSR.
 950         * sim-main.h (COCIDX): Remove definition; this isn't supported by
 951         PENDING_FILL, and you can get the intended effect gracefully by
 952         calling PENDING_SCHED directly.
 953
 954 2001-02-23  Ben Elliston  <bje@redhat.com>
 955
 956         * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Only define if not
 957         already defined elsewhere.
 958
 959 2001-02-19  Ben Elliston  <bje@redhat.com>
 960
 961         * sim-main.h (sim_monitor): Return an int.
 962         * interp.c (sim_monitor): Add return values.
 963         (signal_exception): Handle error conditions from sim_monitor.
 964
 965 2001-02-08  Ben Elliston  <bje@redhat.com>
 966
 967         * sim-main.c (load_memory): Pass cia to sim_core_read* functions.
 968         (store_memory): Likewise, pass cia to sim_core_write*.
 969
 970 2000-10-19  Frank Ch. Eigler  <fche@redhat.com>
 971
 972         On advice from Chris G. Demetriou <cgd@sibyte.com>:
 973         * sim-main.h (GPR_CLEAR): Remove unused alternative macro.
 974
 975 Thu Jul 27 22:02:05 2000  Andrew Cagney  <cagney@b1.cygnus.com>
 976
 977         From Maciej W. Rozycki <macro@ds2.pg.gda.pl>:
 978         * Makefile.in: Don't delete *.igen when cleaning directory.
 979
 980 Wed Jul 19 18:50:51 2000  Andrew Cagney  <cagney@b1.cygnus.com>
 981
 982         * m16.igen (break): Call SignalException not sim_engine_halt.
 983
 984 Mon Jul  3 11:13:20 2000  Andrew Cagney  <cagney@b1.cygnus.com>
 985
 986         From Jason Eckhardt:
 987         * mips.igen (MOVZ.fmt, MOVN.fmt): Move conditional on GPR[RT].
 988
 989 Tue Jun 13 20:52:07 2000  Andrew Cagney  <cagney@b1.cygnus.com>
 990
 991         * mips.igen (MxC1, DMxC1): Fix printf formatting.
 992
 993 2000-05-24  Michael Hayes  <mhayes@cygnus.com>
 994
 995         * mips.igen (do_dmultx): Fix typo.
 996
 997 Tue May 23 21:39:23 2000  Andrew Cagney  <cagney@b1.cygnus.com>
 998
 999         * configure: Regenerated to track ../common/aclocal.m4 changes.
1000
1001 Fri Apr 28 20:48:36 2000  Andrew Cagney  <cagney@b1.cygnus.com>
1002
1003         * mips.igen (DMxC1): Fix format arguments for sim_io_eprintf call.
1004
1005 2000-04-12  Frank Ch. Eigler  <fche@redhat.com>
1006
1007         * sim-main.h (GPR_CLEAR): Define macro.
1008
1009 Mon Apr 10 00:07:09 2000  Andrew Cagney  <cagney@b1.cygnus.com>
1010
1011         * interp.c (decode_coproc): Output long using %lx and not %s.
1012
1013 2000-03-21  Frank Ch. Eigler  <fche@redhat.com>
1014
1015         * interp.c (sim_open): Sort & extend dummy memory regions for
1016         --board=jmr3904 for eCos.
1017
1018 2000-03-02  Frank Ch. Eigler  <fche@redhat.com>
1019
1020         * configure: Regenerated.
1021
1022 Tue Feb  8 18:35:01 2000  Donald Lindsay  <dlindsay@hound.cygnus.com>
1023
1024         * interp.c, mips.igen: all 5 DEADC0DE situations now have sim_io_eprintf
1025         calls, conditional on the simulator being in verbose mode.
1026
1027 Fri Feb  4 09:45:15 2000  Donald Lindsay  <dlindsay@cygnus.com>
1028
1029         * sim-main.c (cache_op): Added case arm so that CACHE ops to a secondary
1030         cache don't get ReservedInstruction traps.
1031
1032 1999-11-29  Mark Salter  <msalter@cygnus.com>
1033
1034         * dv-tx3904sio.c (tx3904sio_io_write_buffer): Use write value as a mask
1035         to clear status bits in sdisr register. This is how the hardware works.
1036
1037         * interp.c (sim_open): Added more memory aliases for jmr3904 hardware
1038         being used by cygmon.
1039
1040 1999-11-11  Andrew Haley  <aph@cygnus.com>
1041
1042         * interp.c (decode_coproc): Correctly handle DMFC0 and DMTC0
1043         instructions.
1044
1045 Thu Sep  9 15:12:08 1999  Geoffrey Keating  <geoffk@cygnus.com>
1046
1047         * mips.igen (MULT): Correct previous mis-applied patch.
1048
1049 Tue Sep  7 13:34:54 1999  Geoffrey Keating  <geoffk@cygnus.com>
1050
1051         * mips.igen (delayslot32): Handle sequence like
1052         mtc1 $at,$f12 ; jal fp_add ; mov.s $f13,$f12
1053         correctly by calling ENGINE_ISSUE_PREFIX_HOOK() before issue.
1054         (MULT): Actually pass the third register...
1055
1056 1999-09-03  Mark Salter  <msalter@cygnus.com>
1057
1058         * interp.c (sim_open): Added more memory aliases for additional
1059         hardware being touched by cygmon on jmr3904 board.
1060
1061 Thu Sep  2 18:15:53 1999  Andrew Cagney  <cagney@b1.cygnus.com>
1062
1063         * configure: Regenerated to track ../common/aclocal.m4 changes.
1064
1065 Tue Jul 27 16:36:51 1999  Andrew Cagney  <cagney@amy.cygnus.com>
1066
1067         * interp.c (sim_store_register): Handle case where client - GDB -
1068         specifies that a 4 byte register is 8 bytes in size.
1069         (sim_fetch_register): Ditto.
1070
1071 1999-07-14  Frank Ch. Eigler  <fche@cygnus.com>
1072
1073         Implement "sim firmware" option, inspired by jimb's version of 1998-01.
1074         * interp.c (firmware_option_p): New global flag: "sim firmware" given.
1075         (idt_monitor_base): Base address for IDT monitor traps.
1076         (pmon_monitor_base): Ditto for PMON.
1077         (lsipmon_monitor_base): Ditto for LSI PMON.
1078         (MONITOR_BASE, MONITOR_SIZE): Removed macros.
1079         (mips_option): Add "firmware" option with new OPTION_FIRMWARE key.
1080         (sim_firmware_command): New function.
1081         (mips_option_handler): Call it for OPTION_FIRMWARE.
1082         (sim_open): Allocate memory for idt_monitor region.  If "--board"
1083         option was given, add no monitor by default.  Add BREAK hooks only if
1084         monitors are also there.
1085
1086 Mon Jul 12 00:02:27 1999  Andrew Cagney  <cagney@amy.cygnus.com>
1087
1088         * interp.c (sim_monitor): Flush output before reading input.
1089
1090 Sun Jul 11 19:28:11 1999  Andrew Cagney  <cagney@b1.cygnus.com>
1091
1092         * tconfig.in (SIM_HANDLES_LMA): Always define.
1093
1094 Thu Jul  8 16:06:59 1999  Andrew Cagney  <cagney@b1.cygnus.com>
1095
1096         From Mark Salter <msalter@cygnus.com>:
1097         * interp.c (BOARD_BSP): Define.  Add to list of possible boards.
1098         (sim_open): Add setup for BSP board.
1099
1100 Wed Jul  7 12:45:58 1999  Andrew Cagney  <cagney@b1.cygnus.com>
1101
1102         * mips.igen (MULT, MULTU): Add syntax for two operand version.
1103         (DMFC0, DMTC0): Recognize.  Call DecodeCoproc which will report
1104         them as unimplemented.
1105
1106 1999-05-08  Felix Lee  <flee@cygnus.com>
1107
1108         * configure: Regenerated to track ../common/aclocal.m4 changes.
1109
1110 1999-04-21  Frank Ch. Eigler  <fche@cygnus.com>
1111
1112         * mips.igen (bc0f): For the TX39 only, decode this as a no-op stub.
1113
1114 Thu Apr 15 14:15:17 1999  Andrew Cagney  <cagney@amy.cygnus.com>
1115
1116         * configure.in: Any mips64vr5*-*-* target should have
1117         -DTARGET_ENABLE_FR=1.
1118         (default_endian): Any mips64vr*el-*-* target should default to
1119         LITTLE_ENDIAN.
1120         * configure: Re-generate.
1121
1122 1999-02-19  Gavin Romig-Koch  <gavin@cygnus.com>
1123
1124         * mips.igen (ldl): Extend from _16_, not 32.
1125
1126 Wed Jan 27 18:51:38 1999  Andrew Cagney  <cagney@chook.cygnus.com>
1127
1128         * interp.c (sim_store_register): Force registers written to by GDB
1129         into an un-interpreted state.
1130
1131 1999-02-05  Frank Ch. Eigler  <fche@cygnus.com>
1132
1133         * dv-tx3904sio.c (tx3904sio_tickle): After a polled I/O from the
1134         CPU, start periodic background I/O polls.
1135         (tx3904sio_poll): New function: periodic I/O poller.
1136
1137 1998-12-30  Frank Ch. Eigler  <fche@cygnus.com>
1138
1139         * mips.igen (BREAK): Call signal_exception instead of sim_engine_halt.
1140
1141 Tue Dec 29 16:03:53 1998  Rainer Orth  <ro@TechFak.Uni-Bielefeld.DE>
1142
1143         * configure.in, configure (mips64vr5*-*-*): Added missing ;; in
1144         case statement.
1145
1146 1998-12-29  Frank Ch. Eigler  <fche@cygnus.com>
1147
1148         * interp.c (sim_open): Allocate jm3904 memory in smaller chunks.
1149         (load_word): Call SIM_CORE_SIGNAL hook on error.
1150         (signal_exception): Call SIM_CPU_EXCEPTION_TRIGGER hook before
1151         starting.  For exception dispatching, pass PC instead of NULL_CIA.
1152         (decode_coproc): Use COP0_BADVADDR to store faulting address.
1153         * sim-main.h (COP0_BADVADDR): Define.
1154         (SIM_CORE_SIGNAL): Define hook to call mips_core_signal.
1155         (SIM_CPU_EXCEPTION*): Define hooks to call mips_cpu_exception*().
1156         (_sim_cpu): Add exc_* fields to store register value snapshots.
1157         * mips.igen (*): Replace memory-related SignalException* calls
1158         with references to SIM_CORE_SIGNAL hook.
1159
1160         * dv-tx3904irc.c (tx3904irc_port_event): printf format warning
1161         fix.
1162         * sim-main.c (*): Minor warning cleanups.
1163
1164 1998-12-24  Gavin Romig-Koch  <gavin@cygnus.com>
1165
1166         * m16.igen (DADDIU5): Correct type-o.
1167
1168 Mon Dec 21 10:34:48 1998  Andrew Cagney  <cagney@chook>
1169
1170         * mips.igen (do_ddiv, do_ddivu): Pacify GCC. Update hi/lo via tmp
1171         variables.
1172
1173 Wed Dec 16 18:20:28 1998  Andrew Cagney  <cagney@chook>
1174
1175         * Makefile.in (SIM_EXTRA_CFLAGS): No longer need to add .../newlib
1176         to include path.
1177         (interp.o): Add dependency on itable.h
1178         (oengine.c, gencode): Delete remaining references.
1179         (BUILT_SRC_FROM_GEN): Clean up.
1180
1181 1998-12-16  Gavin Romig-Koch  <gavin@cygnus.com>
1182
1183         * vr4run.c: New.
1184         * Makefile.in (SIM_HACK_OBJ,HACK_OBJS,HACK_GEN_SRCS,libhack.a,
1185         tmp-hack,tmp-m32-hack,tmp-m16-hack,tmp-itable-hack,
1186         tmp-run-hack) : New.
1187         * m16.igen (LD,DADDIU,DADDUI5,DADJSP,DADDIUSP,DADDI,DADDU,DSUBU,
1188         DSLL,DSRL,DSRA,DSLLV,DSRAV,DMULT,DMULTU,DDIV,DDIVU,JALX32,JALX):
1189         Drop the "64" qualifier to get the HACK generator working.
1190         Use IMMEDIATE rather than IMMED.  Use SHAMT rather than SHIFT.
1191         * mips.igen (do_daddiu,do_ddiv,do_divu): Remove the 64-only
1192         qualifier to get the hack generator working.
1193         (do_dsll,do_dsllv,do_dsra,do_dsrl,do_dsrlv): New.
1194         (DSLL): Use do_dsll.
1195         (DSLLV): Use do_dsllv.
1196         (DSRA): Use do_dsra.
1197         (DSRL): Use do_dsrl.
1198         (DSRLV): Use do_dsrlv.
1199         (BC1): Move *vr4100 to get the HACK generator working.
1200         (CxC1, DMxC1, MxC1,MACCU,MACCHI,MACCHIU): Rename to
1201         get the HACK generator working.
1202         (MACC) Rename to get the HACK generator working.
1203         (DMACC,MACCS,DMACCS): Add the 64.
1204
1205 1998-12-12  Gavin Romig-Koch  <gavin@cygnus.com>
1206
1207         * mips.igen (BC1): Renamed to BC1a and BC1b to avoid conflicts.
1208         * sim-main.h (SizeFGR): Handle TARGET_ENABLE_FR.
1209
1210 1998-12-11  Gavin Romig-Koch  <gavin@cygnus.com>
1211
1212     * mips/interp.c (DEBUG): Cleanups.
1213
1214 1998-12-10  Frank Ch. Eigler  <fche@cygnus.com>
1215
1216         * dv-tx3904sio.c (tx3904sio_io_read_buffer): Endianness fixes.
1217         (tx3904sio_tickle): fflush after a stdout character output.
1218
1219 1998-12-03  Frank Ch. Eigler  <fche@cygnus.com>
1220
1221         * interp.c (sim_close): Uninstall modules.
1222
1223 Wed Nov 25 13:41:03 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1224
1225         * sim-main.h, interp.c (sim_monitor): Change to global
1226         function.
1227
1228 Wed Nov 25 17:33:24 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1229
1230         * configure.in (vr4100): Only include vr4100 instructions in
1231         simulator.
1232         * configure: Re-generate.
1233         * m16.igen (*): Tag all mips16 instructions as also being vr4100.
1234
1235 Mon Nov 23 18:20:36 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1236
1237         * Makefile.in (SIM_CFLAGS): Do not define WITH_IGEN.
1238         * sim-main.h, sim-main.c, interp.c: Delete #if WITH_IGEN keeping
1239         true alternative.
1240
1241         * configure.in (sim_default_gen, sim_use_gen): Replace with
1242         sim_gen.
1243         (--enable-sim-igen): Delete config option. Always using IGEN.
1244         * configure: Re-generate.
1245
1246         * Makefile.in (gencode): Kill, kill, kill.
1247         * gencode.c: Ditto.
1248
1249 Mon Nov 23 18:07:36 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1250
1251         * configure.in: Configure mips64vr4100-elf nee mips64vr41* as a 64
1252         bit mips16 igen simulator.
1253         * configure: Re-generate.
1254
1255         * mips.igen (check_div_hilo, check_mult_hilo, check_mf_hilo): Mark
1256         as part of vr4100 ISA.
1257         * vr.igen: Mark all instructions as 64 bit only.
1258
1259 Mon Nov 23 17:07:37 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1260
1261         * interp.c (get_cell, sim_monitor, fetch_str, CoProcPresent):
1262         Pacify GCC.
1263
1264 Mon Nov 23 13:23:40 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1265
1266         * configure.in: Configure mips-lsi-elf nee mips*lsi* as a
1267         mipsIII/mips16 igen simulator.  Fix sim_gen VS sim_igen typos.
1268         * configure: Re-generate.
1269
1270         * m16.igen (BREAK): Define breakpoint instruction.
1271         (JALX32): Mark instruction as mips16 and not r3900.
1272         * mips.igen (C.cond.fmt): Fix typo in instruction format.
1273
1274         * sim-main.h (PENDING_FILL): Wrap C statements in do/while.
1275
1276 Sat Nov  7 09:54:38 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1277
1278         * gencode.c (build_instruction - BREAK): For MIPS16, handle BREAK
1279         insn as a debug breakpoint.
1280
1281         * sim-main.h (PENDING_SLOT_BIT): Fix, was incorrectly defined as
1282         pending.slot_size.
1283         (PENDING_SCHED): Clean up trace statement.
1284         (PENDING_SCHED): Increment PENDING_IN and PENDING_TOTAL.
1285         (PENDING_FILL): Delay write by only one cycle.
1286         (PENDING_FILL): For FSRs, write fmt_uninterpreted to FPR_STATE.
1287
1288         * sim-main.c (pending_tick): Clean up trace statements. Add trace
1289         of pending writes.
1290         (pending_tick): Fix sizes in switch statements, 4 & 8 instead of
1291         32 & 64.
1292         (pending_tick): Move incrementing of index to FOR statement.
1293         (pending_tick): Only update PENDING_OUT after a write has occured.
1294
1295         * configure.in: Add explicit mips-lsi-* target.  Use gencode to
1296         build simulator.
1297         * configure: Re-generate.
1298
1299         * interp.c (sim_engine_run OLD): Delete explicit call to
1300         PENDING_TICK. Now called via ENGINE_ISSUE_PREFIX_HOOK.
1301
1302 Sat Oct 30 09:49:10 1998  Frank Ch. Eigler  <fche@cygnus.com>
1303
1304         * dv-tx3904cpu.c (deliver_tx3904cpu_interrupt): Add dummy
1305         interrupt level number to match changed SignalExceptionInterrupt
1306         macro.
1307
1308 Fri Oct  9 18:02:25 1998  Doug Evans  <devans@canuck.cygnus.com>
1309
1310         * interp.c: #include "itable.h" if WITH_IGEN.
1311         (get_insn_name): New function.
1312         (sim_open): Initialize CPU_INSN_NAME,CPU_MAX_INSNS.
1313         * sim-main.h (MAX_INSNS,INSN_NAME): Delete.
1314
1315 Mon Sep 14 12:36:44 1998  Frank Ch. Eigler  <fche@cygnus.com>
1316
1317         * configure: Rebuilt to inhale new common/aclocal.m4.
1318
1319 Tue Sep  1 15:39:18 1998  Frank Ch. Eigler  <fche@cygnus.com>
1320
1321         * dv-tx3904sio.c: Include sim-assert.h.
1322
1323 Tue Aug 25 12:49:46 1998  Frank Ch. Eigler  <fche@cygnus.com>
1324
1325         * dv-tx3904sio.c: New file: tx3904 serial I/O module.
1326         * configure.in: Add dv-tx3904sio, dv-sockser for tx39 target.
1327         Reorganize target-specific sim-hardware checks.
1328         * configure: rebuilt.
1329         * interp.c (sim_open): For tx39 target boards, set
1330         OPERATING_ENVIRONMENT, add tx3904sio devices.
1331         * tconfig.in: For tx39 target, set SIM_HANDLES_LMA for loading
1332         ROM executables.  Install dv-sockser into sim-modules list.
1333
1334         * dv-tx3904irc.c: Compiler warning clean-up.
1335         * dv-tx3904tmr.c: Compiler warning clean-up.  Remove particularly
1336         frequent hw-trace messages.
1337
1338 Fri Jul 31 18:14:16 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1339
1340         * vr.igen (MulAcc): Identify as a vr4100 specific function.
1341
1342 Sat Jul 25 16:03:14 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1343
1344         * Makefile.in (IGEN_INCLUDE): Add vr.igen.
1345
1346         * vr.igen: New file.
1347         (MAC/MADD16, DMAC/DMADD16): Implement using code from gencode.c.
1348         * mips.igen: Define vr4100 model. Include vr.igen.
1349 Mon Jun 29 09:21:07 1998  Gavin Koch  <gavin@cygnus.com>
1350
1351         * mips.igen (check_mf_hilo): Correct check.
1352
1353 Wed Jun 17 12:20:49 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1354
1355         * sim-main.h (interrupt_event): Add prototype.
1356
1357         * dv-tx3904tmr.c (tx3904tmr_io_write_buffer): Delete unused
1358         register_ptr, register_value.
1359         (deliver_tx3904tmr_tick): Fix types passed to printf fmt.
1360
1361         * sim-main.h (tracefh): Make extern.
1362
1363 Tue Jun 16 14:39:00 1998  Frank Ch. Eigler  <fche@cygnus.com>
1364
1365         * dv-tx3904tmr.c: Deschedule timer event after dispatching.
1366         Reduce unnecessarily high timer event frequency.
1367         * dv-tx3904cpu.c: Ditto for interrupt event.
1368
1369 Wed Jun 10 13:22:32 1998  Frank Ch. Eigler  <fche@cygnus.com>
1370
1371         * interp.c (decode_coproc): For TX39, add stub COP0 register #7,
1372         to allay warnings.
1373         (interrupt_event): Made non-static.
1374
1375         * dv-tx3904tmr.c (deliver_tx3904tmr_tick): Correct accidental
1376         interchange of configuration values for external vs. internal
1377         clock dividers.
1378
1379 Tue Jun  9 12:46:24 1998  Ian Carmichael  <iancarm@cygnus.com>
1380
1381         * mips.igen (BREAK): Moved code to here for
1382         simulator-reserved break instructions.
1383         * gencode.c (build_instruction): Ditto.
1384         * interp.c (signal_exception): Code moved from here.  Non-
1385         reserved instructions now use exception vector, rather
1386         than halting sim.
1387         * sim-main.h: Moved magic constants to here.
1388
1389 Tue Jun  9 12:29:50 1998  Frank Ch. Eigler  <fche@cygnus.com>
1390
1391         * dv-tx3904cpu.c (deliver_*_interrupt,*_port_event): Set the CAUSE
1392         register upon non-zero interrupt event level, clear upon zero
1393         event value.
1394         * dv-tx3904irc.c (*_port_event): Handle deactivated interrupt signal
1395         by passing zero event value.
1396         (*_io_{read,write}_buffer): Endianness fixes.
1397         * dv-tx3904tmr.c (*_io_{read,write}_buffer): Endianness fixes.
1398         (deliver_*_tick): Reduce sim event interval to 75% of count interval.
1399
1400         * interp.c (sim_open): Added jmr3904pal board type that adds PAL-based
1401         serial I/O and timer module at base address 0xFFFF0000.
1402
1403 Tue Jun  9 11:52:29 1998  Gavin Koch  <gavin@cygnus.com>
1404
1405         * mips.igen (SWC1) : Correct the handling of ReverseEndian
1406         and BigEndianCPU.
1407
1408 Tue Jun  9 11:40:57 1998  Gavin Koch  <gavin@cygnus.com>
1409
1410         * configure.in (mips_fpu_bitsize) : Set this correctly for 32-bit mips
1411         parts.
1412         * configure: Update.
1413
1414 Thu Jun  4 15:37:33 1998  Frank Ch. Eigler  <fche@cygnus.com>
1415
1416         * dv-tx3904tmr.c: New file - implements tx3904 timer.
1417         * dv-tx3904{irc,cpu}.c: Mild reformatting.
1418         * configure.in: Include tx3904tmr in hw_device list.
1419         * configure: Rebuilt.
1420         * interp.c (sim_open): Instantiate three timer instances.
1421         Fix address typo of tx3904irc instance.
1422
1423 Tue Jun  2 15:48:02 1998  Ian Carmichael  <iancarm@cygnus.com>
1424
1425         * interp.c (signal_exception): SystemCall exception now uses
1426         the exception vector.
1427
1428 Mon Jun  1 18:18:26 1998  Frank Ch. Eigler  <fche@cygnus.com>
1429
1430         * interp.c (decode_coproc): For TX39, add stub COP0 register #3,
1431         to allay warnings.
1432
1433 Fri May 29 11:40:39 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1434
1435         * configure.in (sim_igen_filter): Match mips*tx39 not mipst*tx39.
1436
1437 Mon May 25 20:47:45 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1438
1439         * dv-tx3904cpu.c, dv-tx3904irc.c: Rename *_callback to *_method.
1440
1441         * dv-tx3904cpu.c, dv-tx3904irc.c: Include hw-main.h and
1442         sim-main.h. Declare a struct hw_descriptor instead of struct
1443         hw_device_descriptor.
1444
1445 Mon May 25 12:41:38 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1446
1447         * mips.igen (do_store_left, do_load_left): Compute nr of left and
1448         right bits and then re-align left hand bytes to correct byte
1449         lanes.  Fix incorrect computation in do_store_left when loading
1450         bytes from second word.
1451
1452 Fri May 22 13:34:20 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1453
1454         * configure.in (SIM_AC_OPTION_HARDWARE): Only enable when tx3904.
1455         * interp.c (sim_open): Only create a device tree when HW is
1456         enabled.
1457
1458         * dv-tx3904irc.c (tx3904irc_finish): Pacify GCC.
1459         * interp.c (signal_exception): Ditto.
1460
1461 Thu May 21 14:24:11 1998  Gavin Koch  <gavin@cygnus.com>
1462
1463         * gencode.c: Mark BEGEZALL as LIKELY.
1464
1465 Thu May 21 18:57:19 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1466
1467         * sim-main.h (ALU32_END): Sign extend 32 bit results.
1468         * mips.igen (ADD, SUB, ADDI, DADD, DSUB): Trace.
1469
1470 Mon May 18 18:22:42 1998  Frank Ch. Eigler  <fche@cygnus.com>
1471
1472         * configure.in (SIM_AC_OPTION_HARDWARE): Added common hardware
1473         modules.  Recognize TX39 target with "mips*tx39" pattern.
1474         * configure: Rebuilt.
1475         * sim-main.h (*): Added many macros defining bits in
1476         TX39 control registers.
1477         (SignalInterrupt): Send actual PC instead of NULL.
1478         (SignalNMIReset): New exception type.
1479         * interp.c (board): New variable for future use to identify
1480         a particular board being simulated.
1481         (mips_option_handler,mips_options): Added "--board" option.
1482         (interrupt_event): Send actual PC.
1483         (sim_open): Make memory layout conditional on board setting.
1484         (signal_exception): Initial implementation of hardware interrupt
1485         handling.  Accept another break instruction variant for simulator
1486         exit.
1487         (decode_coproc): Implement RFE instruction for TX39.
1488         (mips.igen): Decode RFE instruction as such.
1489         * configure.in (tx3904cpu,tx3904irc): Added devices for tx3904.
1490         * interp.c: Define "jmr3904" and "jmr3904debug" board types and
1491         bbegin to implement memory map.
1492         * dv-tx3904cpu.c: New file.
1493         * dv-tx3904irc.c: New file.
1494
1495 Wed May 13 14:40:11 1998  Gavin Koch  <gavin@cygnus.com>
1496
1497         * mips.igen (check_mt_hilo): Create a separate r3900 version.
1498
1499 Wed May 13 14:11:46 1998  Gavin Koch  <gavin@cygnus.com>
1500
1501         * tx.igen (madd,maddu):  Replace calls to check_op_hilo
1502         with calls to check_div_hilo.
1503
1504 Wed May 13 09:59:27 1998  Gavin Koch  <gavin@cygnus.com>
1505
1506         * mips/mips.igen (check_op_hilo,check_mult_hilo,check_div_hilo):
1507         Replace check_op_hilo with check_mult_hilo and check_div_hilo.
1508         Add special r3900 version of do_mult_hilo.
1509         (do_dmultx,do_mult,do_multu): Replace calls to check_op_hilo
1510         with calls to check_mult_hilo.
1511         (do_ddiv,do_ddivu,do_div,do_divu): Replace calls to check_op_hilo
1512         with calls to check_div_hilo.
1513
1514 Tue May 12 15:22:11 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1515
1516         * configure.in (SUBTARGET_R3900): Define for mipstx39 target.
1517         Document a replacement.
1518
1519 Fri May  8 17:48:19 1998  Ian Carmichael  <iancarm@cygnus.com>
1520
1521         * interp.c (sim_monitor): Make mon_printf work.
1522
1523 Wed May  6 19:42:19 1998  Doug Evans  <devans@canuck.cygnus.com>
1524
1525         * sim-main.h (INSN_NAME): New arg `cpu'.
1526
1527 Tue Apr 28 18:33:31 1998  Geoffrey Noer  <noer@cygnus.com>
1528
1529         * configure: Regenerated to track ../common/aclocal.m4 changes.
1530
1531 Sun Apr 26 15:31:55 1998  Tom Tromey  <tromey@creche>
1532
1533         * configure: Regenerated to track ../common/aclocal.m4 changes.
1534         * config.in: Ditto.
1535
1536 Sun Apr 26 15:20:01 1998  Tom Tromey  <tromey@cygnus.com>
1537
1538         * acconfig.h: New file.
1539         * configure.in: Reverted change of Apr 24; use sinclude again.
1540
1541 Fri Apr 24 14:16:40 1998  Tom Tromey  <tromey@creche>
1542
1543         * configure: Regenerated to track ../common/aclocal.m4 changes.
1544         * config.in: Ditto.
1545
1546 Fri Apr 24 11:19:20 1998  Tom Tromey  <tromey@cygnus.com>
1547
1548         * configure.in: Don't call sinclude.
1549
1550 Fri Apr 24 11:35:01 1998  Andrew Cagney  <cagney@chook.cygnus.com>
1551
1552         * mips.igen (do_store_left): Pass 0 not NULL to store_memory.
1553
1554 Tue Apr 21 11:59:50 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1555
1556         * mips.igen (ERET): Implement.
1557
1558         * interp.c (decode_coproc): Return sign-extended EPC.
1559
1560         * mips.igen (ANDI, LUI, MFC0): Add tracing code.
1561
1562         * interp.c (signal_exception): Do not ignore Trap.
1563         (signal_exception): On TRAP, restart at exception address.
1564         (HALT_INSTRUCTION, HALT_INSTRUCTION_MASK): Define.
1565         (signal_exception): Update.
1566         (sim_open): Patch V_COMMON interrupt vector with an abort sequence
1567         so that TRAP instructions are caught.
1568
1569 Mon Apr 20 11:26:55 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1570
1571         * sim-main.h (struct hilo_access, struct hilo_history): Define,
1572         contains HI/LO access history.
1573         (struct _sim_cpu): Make hiaccess and loaccess of type hilo_access.
1574         (HIACCESS, LOACCESS): Delete, replace with
1575         (HIHISTORY, LOHISTORY): New macros.
1576         (CHECKHILO): Delete all, moved to mips.igen
1577
1578         * gencode.c (build_instruction): Do not generate checks for
1579         correct HI/LO register usage.
1580
1581         * interp.c (old_engine_run): Delete checks for correct HI/LO
1582         register usage.
1583
1584         * mips.igen (check_mt_hilo, check_mf_hilo, check_op_hilo,
1585         check_mf_cycles): New functions.
1586         (do_mfhi, do_mflo, "mthi", "mtlo", do_ddiv, do_ddivu, do_div,
1587         do_divu, domultx, do_mult, do_multu): Use.
1588
1589         * tx.igen ("madd", "maddu"): Use.
1590
1591 Wed Apr 15 18:31:54 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1592
1593         * mips.igen (DSRAV): Use function do_dsrav.
1594         (SRAV): Use new function do_srav.
1595
1596         * m16.igen (BEQZ, BNEZ): Compare GPR[TRX] not GPR[RX].
1597         (B): Sign extend 11 bit immediate.
1598         (EXT-B*): Shift 16 bit immediate left by 1.
1599         (ADDIU*): Don't sign extend immediate value.
1600
1601 Wed Apr 15 10:32:15 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1602
1603         * m16run.c (sim_engine_run): Restore CIA after handling an event.
1604
1605         * sim-main.h (DELAY_SLOT, NULLIFY_NEXT_INSTRUCTION): For IGEN, use
1606         functions.
1607
1608         * mips.igen (delayslot32, nullify_next_insn): New functions.
1609         (m16.igen): Always include.
1610         (do_*): Add more tracing.
1611
1612         * m16.igen (delayslot16): Add NIA argument, could be called by a
1613         32 bit MIPS16 instruction.
1614
1615         * interp.c (ifetch16): Move function from here.
1616         * sim-main.c (ifetch16): To here.
1617
1618         * sim-main.c (ifetch16, ifetch32): Update to match current
1619         implementations of LH, LW.
1620         (signal_exception): Don't print out incorrect hex value of illegal
1621         instruction.
1622
1623 Wed Apr 15 00:17:25 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1624
1625         * m16run.c (sim_engine_run): Use IMEM16 and IMEM32 to fetch an
1626         instruction.
1627
1628         * m16.igen: Implement MIPS16 instructions.
1629
1630         * mips.igen (do_addiu, do_addu, do_and, do_daddiu, do_daddu,
1631         do_ddiv, do_ddivu, do_div, do_divu, do_dmultx, do_dmultu, do_srav,
1632         do_dsubu, do_mfhi, do_mflo, do_mult, do_multu, do_nor, do_or,
1633         do_sll, do_sllv, do_slt, do_slti, do_sltiu, do_sltu, do_sra,
1634         do_srl, do_srlv, do_subu, do_xor, do_xori): New functions.  Move
1635         bodies of corresponding code from 32 bit insn to these.  Also used
1636         by MIPS16 versions of functions.
1637
1638         * sim-main.h (RAIDX, T8IDX, T8, SPIDX): Define.
1639         (IMEM16): Drop NR argument from macro.
1640
1641 Sat Apr  4 22:39:50 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1642
1643         * Makefile.in (SIM_OBJS): Add sim-main.o.
1644
1645         * sim-main.h (address_translation, load_memory, store_memory,
1646         cache_op, sync_operation, prefetch, ifetch32, pending_tick): Mark
1647         as INLINE_SIM_MAIN.
1648         (pr_addr, pr_uword64): Declare.
1649         (sim-main.c): Include when H_REVEALS_MODULE_P.
1650
1651         * interp.c (address_translation, load_memory, store_memory,
1652         cache_op, sync_operation, prefetch, ifetch32, pending_tick): Move
1653         from here.
1654         * sim-main.c: To here. Fix compilation problems.
1655
1656         * configure.in: Enable inlining.
1657         * configure: Re-config.
1658
1659 Sat Apr  4 20:36:25 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1660
1661         * configure: Regenerated to track ../common/aclocal.m4 changes.
1662
1663 Fri Apr  3 04:32:35 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1664
1665         * mips.igen: Include tx.igen.
1666         * Makefile.in (IGEN_INCLUDE): Add tx.igen.
1667         * tx.igen: New file, contains MADD and MADDU.
1668
1669         * interp.c (load_memory): When shifting bytes, use LOADDRMASK not
1670         the hardwired constant `7'.
1671         (store_memory): Ditto.
1672         (LOADDRMASK): Move definition to sim-main.h.
1673
1674         mips.igen (MTC0): Enable for r3900.
1675         (ADDU): Add trace.
1676
1677         mips.igen (do_load_byte): Delete.
1678         (do_load, do_store, do_load_left, do_load_write, do_store_left,
1679         do_store_right): New functions.
1680         (SW*, LW*, SD*, LD*, SH, LH, SB, LB): Use.
1681
1682         configure.in: Let the tx39 use igen again.
1683         configure: Update.
1684
1685 Thu Apr  2 10:59:39 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1686
1687         * interp.c (sim_monitor): get_mem_info returns a 4 byte quantity,
1688         not an address sized quantity.  Return zero for cache sizes.
1689
1690 Wed Apr  1 23:47:53 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1691
1692         * mips.igen (r3900): r3900 does not support 64 bit integer
1693         operations.
1694
1695 Mon Mar 30 14:46:05 1998  Gavin Koch  <gavin@cygnus.com>
1696
1697         * configure.in (mipstx39*-*-*): Use gencode simulator rather
1698         than igen one.
1699         * configure : Rebuild.
1700
1701 Fri Mar 27 16:15:52 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1702
1703         * configure: Regenerated to track ../common/aclocal.m4 changes.
1704
1705 Fri Mar 27 15:01:50 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1706
1707         * interp.c (mips_option_handler): Iterate over MAX_NR_PROCESSORS.
1708
1709 Wed Mar 25 16:44:27 1998  Ian Carmichael  <iancarm@cygnus.com>
1710
1711         * configure: Regenerated to track ../common/aclocal.m4 changes.
1712         * config.in: Regenerated to track ../common/aclocal.m4 changes.
1713
1714 Wed Mar 25 12:35:29 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1715
1716         * configure: Regenerated to track ../common/aclocal.m4 changes.
1717
1718 Wed Mar 25 10:05:46 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1719
1720         * interp.c (Max, Min): Comment out functions. Not yet used.
1721
1722 Wed Mar 18 12:38:12 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1723
1724         * configure: Regenerated to track ../common/aclocal.m4 changes.
1725
1726 Tue Mar 17 19:05:20 1998  Frank Ch. Eigler  <fche@cygnus.com>
1727
1728         * Makefile.in (MIPS_EXTRA_LIBS, SIM_EXTRA_LIBS): Added
1729         configurable settings for stand-alone simulator.
1730
1731         * configure.in: Added X11 search, just in case.
1732
1733         * configure: Regenerated.
1734
1735 Wed Mar 11 14:09:10 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1736
1737         * interp.c (sim_write, sim_read, load_memory, store_memory):
1738         Replace sim_core_*_map with read_map, write_map, exec_map resp.
1739
1740 Tue Mar  3 13:58:43 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1741
1742         * sim-main.h (GETFCC): Return an unsigned value.
1743
1744 Tue Mar  3 13:21:37 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1745
1746         * mips.igen (DIV): Fix check for -1 / MIN_INT.
1747         (DADD): Result destination is RD not RT.
1748
1749 Fri Feb 27 13:49:49 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1750
1751         * sim-main.h (HIACCESS, LOACCESS): Always define.
1752
1753         * mdmx.igen (Maxi, Mini): Rename Max, Min.
1754
1755         * interp.c (sim_info): Delete.
1756
1757 Fri Feb 27 18:41:01 1998  Doug Evans  <devans@canuck.cygnus.com>
1758
1759         * interp.c (DECLARE_OPTION_HANDLER): Use it.
1760         (mips_option_handler): New argument `cpu'.
1761         (sim_open): Update call to sim_add_option_table.
1762
1763 Wed Feb 25 18:56:22 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1764
1765         * mips.igen (CxC1): Add tracing.
1766
1767 Fri Feb 20 17:43:21 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1768
1769         * sim-main.h (Max, Min): Declare.
1770
1771         * interp.c (Max, Min): New functions.
1772
1773         * mips.igen (BC1): Add tracing.
1774
1775 Thu Feb 19 14:50:00 1998  John Metzler  <jmetzler@cygnus.com>
1776
1777         * interp.c Added memory map for stack in vr4100
1778
1779 Thu Feb 19 10:21:21 1998  Gavin Koch  <gavin@cygnus.com>
1780
1781         * interp.c (load_memory): Add missing "break"'s.
1782
1783 Tue Feb 17 12:45:35 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1784
1785         * interp.c (sim_store_register, sim_fetch_register): Pass in
1786         length parameter.  Return -1.
1787
1788 Tue Feb 10 11:57:40 1998  Ian Carmichael  <iancarm@cygnus.com>
1789
1790         * interp.c: Added hardware init hook, fixed warnings.
1791
1792 Sat Feb  7 17:16:20 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1793
1794         * Makefile.in (itable.h itable.c): Depend on SIM_@sim_gen@_ALL.
1795
1796 Tue Feb  3 11:36:02 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1797
1798         * interp.c (ifetch16): New function.
1799
1800         * sim-main.h (IMEM32): Rename IMEM.
1801         (IMEM16_IMMED): Define.
1802         (IMEM16): Define.
1803         (DELAY_SLOT): Update.
1804
1805         * m16run.c (sim_engine_run): New file.
1806
1807         * m16.igen: All instructions except LB.
1808         (LB): Call do_load_byte.
1809         * mips.igen (do_load_byte): New function.
1810         (LB): Call do_load_byte.
1811
1812         * mips.igen: Move spec for insn bit size and high bit from here.
1813         * Makefile.in (tmp-igen, tmp-m16): To here.
1814
1815         * m16.dc: New file, decode mips16 instructions.
1816
1817         * Makefile.in (SIM_NO_ALL): Define.
1818         (tmp-m16): Generate both 16 bit and 32 bit simulator engines.
1819
1820 Tue Feb  3 11:28:00 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1821
1822         * configure.in (mips_fpu_bitsize): For tx39, restrict floating
1823         point unit to 32 bit registers.
1824         * configure: Re-generate.
1825
1826 Sun Feb  1 15:47:14 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1827
1828         * configure.in (sim_use_gen): Make IGEN the default simulator
1829         generator for generic 32 and 64 bit mips targets.
1830         * configure: Re-generate.
1831
1832 Sun Feb  1 16:52:37 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1833
1834         * sim-main.h (SizeFGR): Determine from floating-point and not gpr
1835         bitsize.
1836
1837         * interp.c (sim_fetch_register, sim_store_register): Read/write
1838         FGR from correct location.
1839         (sim_open): Set size of FGR's according to
1840         WITH_TARGET_FLOATING_POINT_BITSIZE.
1841
1842         * sim-main.h (FGR): Store floating point registers in a separate
1843         array.
1844
1845 Sun Feb  1 16:47:51 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1846
1847         * configure: Regenerated to track ../common/aclocal.m4 changes.
1848
1849 Tue Feb  3 00:10:50 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1850
1851         * interp.c (ColdReset): Call PENDING_INVALIDATE.
1852
1853         * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Call PENDING_TICK.
1854
1855         * interp.c (pending_tick): New function.  Deliver pending writes.
1856
1857         * sim-main.h (PENDING_FILL, PENDING_TICK, PENDING_SCHED,
1858         PENDING_BIT, PENDING_INVALIDATE): Re-write pipeline code so that
1859         it can handle mixed sized quantites and single bits.
1860
1861 Mon Feb  2 17:43:15 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1862
1863         * interp.c (oengine.h): Do not include when building with IGEN.
1864         (sim_open): Replace GPRLEN by WITH_TARGET_WORD_BITSIZE.
1865         (sim_info): Ditto for PROCESSOR_64BIT.
1866         (sim_monitor): Replace ut_reg with unsigned_word.
1867         (*): Ditto for t_reg.
1868         (LOADDRMASK): Define.
1869         (sim_open): Remove defunct check that host FP is IEEE compliant,
1870         using software to emulate floating point.
1871         (value_fpr, ...): Always compile, was conditional on HASFPU.
1872
1873 Sun Feb  1 11:15:29 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1874
1875         * sim-main.h (sim_state): Make the cpu array MAX_NR_PROCESSORS in
1876         size.
1877
1878         * interp.c (SD, CPU): Define.
1879         (mips_option_handler): Set flags in each CPU.
1880         (interrupt_event): Assume CPU 0 is the one being iterrupted.
1881         (sim_close): Do not clear STATE, deleted anyway.
1882         (sim_write, sim_read): Assume CPU zero's vm should be used for
1883         data transfers.
1884         (sim_create_inferior): Set the PC for all processors.
1885         (sim_monitor, store_word, load_word, mips16_entry): Add cpu
1886         argument.
1887         (mips16_entry): Pass correct nr of args to store_word, load_word.
1888         (ColdReset): Cold reset all cpu's.
1889         (signal_exception): Pass cpu to sim_monitor & mips16_entry.
1890         (sim_monitor, load_memory, store_memory, signal_exception): Use
1891         `CPU' instead of STATE_CPU.
1892
1893
1894         * sim-main.h: Replace uses of STATE_CPU with CPU. Replace sd with
1895         SD or CPU_.
1896
1897         * sim-main.h (signal_exception): Add sim_cpu arg.
1898         (SignalException*): Pass both SD and CPU to signal_exception.
1899         * interp.c (signal_exception): Update.
1900
1901         * sim-main.h (value_fpr, store_fpr, dotrace, ifetch32), interp.c:
1902         Ditto
1903         (sync_operation, prefetch, cache_op, store_memory, load_memory,
1904         address_translation): Ditto
1905         (decode_coproc, cop_lw, cop_ld, cop_sw, cop_sd): Ditto.
1906
1907 Sat Jan 31 18:15:41 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1908
1909         * configure: Regenerated to track ../common/aclocal.m4 changes.
1910
1911 Sat Jan 31 14:49:24 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1912
1913         * interp.c (sim_engine_run): Add `nr_cpus' argument.
1914
1915         * mips.igen (model): Map processor names onto BFD name.
1916
1917         * sim-main.h (CPU_CIA): Delete.
1918         (SET_CIA, GET_CIA): Define
1919
1920 Wed Jan 21 16:16:27 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1921
1922         * sim-main.h (GPR_SET): Define, used by igen when zeroing a
1923         regiser.
1924
1925         * configure.in (default_endian): Configure a big-endian simulator
1926         by default.
1927         * configure: Re-generate.
1928
1929 Mon Jan 19 22:26:29 1998  Doug Evans  <devans@seba>
1930
1931         * configure: Regenerated to track ../common/aclocal.m4 changes.
1932
1933 Mon Jan  5 20:38:54 1998  Mark Alexander  <marka@cygnus.com>
1934
1935         * interp.c (sim_monitor): Handle Densan monitor outbyte
1936         and inbyte functions.
1937
1938 1997-12-29  Felix Lee  <flee@cygnus.com>
1939
1940         * interp.c (sim_engine_run): msvc cpp barfs on #if (a==b!=c).
1941
1942 Wed Dec 17 14:48:20 1997  Jeffrey A Law  (law@cygnus.com)
1943
1944         * Makefile.in (tmp-igen): Arrange for $zero to always be
1945         reset to zero after every instruction.
1946
1947 Mon Dec 15 23:17:11 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1948
1949         * configure: Regenerated to track ../common/aclocal.m4 changes.
1950         * config.in: Ditto.
1951
1952 Wed Dec 10 17:10:45 1997  Jeffrey A Law  (law@cygnus.com)
1953
1954         * mips.igen (MSUB): Fix to work like MADD.
1955         * gencode.c (MSUB): Similarly.
1956
1957 Thu Dec  4 09:21:05 1997  Doug Evans  <devans@canuck.cygnus.com>
1958
1959         * configure: Regenerated to track ../common/aclocal.m4 changes.
1960
1961 Wed Nov 26 11:00:23 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1962
1963         * mips.igen (LWC1): Correct assembler - lwc1 not swc1.
1964
1965 Sun Nov 23 01:45:20 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1966
1967         * sim-main.h (sim-fpu.h): Include.
1968
1969         * interp.c (convert, SquareRoot, Recip, Divide, Multiply, Sub,
1970         Add, Negate, AbsoluteValue, Equal, Less, Infinity, NaN): Rewrite
1971         using host independant sim_fpu module.
1972
1973 Thu Nov 20 19:56:22 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1974
1975         * interp.c (signal_exception): Report internal errors with SIGABRT
1976         not SIGQUIT.
1977
1978         * sim-main.h (C0_CONFIG): New register.
1979         (signal.h): No longer include.
1980
1981         * interp.c (decode_coproc): Allow access C0_CONFIG to register.
1982
1983 Tue Nov 18 15:33:48 1997  Doug Evans  <devans@canuck.cygnus.com>
1984
1985         * Makefile.in (SIM_OBJS): Use $(SIM_NEW_COMMON_OBJS).
1986
1987 Fri Nov 14 11:56:48 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1988
1989         * mips.igen: Tag vr5000 instructions.
1990         (ANDI): Was missing mipsIV model, fix assembler syntax.
1991         (do_c_cond_fmt): New function.
1992         (C.cond.fmt): Handle mips I-III which do not support CC field
1993         separatly.
1994         (bc1): Handle mips IV which do not have a delaed FCC separatly.
1995         (SDR): Mask paddr when BigEndianMem, not the converse as specified
1996         in IV3.2 spec.
1997         (DMULT, DMULTU): Force use of hosts 64bit multiplication.  Handle
1998         vr5000 which saves LO in a GPR separatly.
1999
2000         * configure.in (enable-sim-igen): For vr5000, select vr5000
2001         specific instructions.
2002         * configure: Re-generate.
2003
2004 Wed Nov 12 14:42:52 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2005
2006         * Makefile.in (SIM_OBJS): Add sim-fpu module.
2007
2008         * interp.c (store_fpr), sim-main.h: Add separate fmt_uninterpreted_32 and
2009         fmt_uninterpreted_64 bit cases to switch.  Convert to
2010         fmt_formatted,
2011
2012         * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Define,
2013
2014         * mips.igen (SWR): Mask paddr when BigEndianMem, not the converse
2015         as specified in IV3.2 spec.
2016         (MTC1, DMTC1): Call StoreFPR to store the GPR in the FPR.
2017
2018 Tue Nov 11 12:38:23 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2019
2020         * mips.igen: Delay slot branches add OFFSET to NIA not CIA.
2021         (MFC0, MTC0, SWC1, LWC1, SDC1, LDC1): Implement.
2022         (MTC1, MFC1, DMTC1, DMFC1, CFC1, CTC1): Implement separate non
2023         PENDING_FILL versions of instructions.  Simplify.
2024         (X): New function.
2025         (MULT, MULTU): Implement separate RD==0 and RD!=0 versions of
2026         instructions.
2027         (BEQZ, ..., SLT, SLTI, TLT, TLE, TLI, ...): Explicitly cast GPR to
2028         a signed value.
2029         (MTHI, MFHI): Disable code checking HI-LO.
2030
2031         * sim-main.h (dotrace,tracefh), interp.c: Make dotrace & tracefh
2032         global.
2033         (NULLIFY_NEXT_INSTRUCTION): Call dotrace.
2034
2035 Thu Nov  6 16:36:35 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2036
2037         * gencode.c (build_mips16_operands): Replace IPC with cia.
2038
2039         * interp.c (sim_monitor, signal_exception, cache_op, store_fpr,
2040         value_fpr, cop_ld, cop_lw, cop_sw, cop_sd, decode_coproc): Replace
2041         IPC to `cia'.
2042         (UndefinedResult): Replace function with macro/function
2043         combination.
2044         (sim_engine_run): Don't save PC in IPC.
2045
2046         * sim-main.h (IPC): Delete.
2047
2048
2049         * interp.c (signal_exception, store_word, load_word,
2050         address_translation, load_memory, store_memory, cache_op,
2051         prefetch, sync_operation, ifetch, value_fpr, store_fpr, convert,
2052         cop_lw, cop_ld, cop_sw, cop_sd, decode_coproc, sim_monitor): Add
2053         current instruction address - cia - argument.
2054         (sim_read, sim_write): Call address_translation directly.
2055         (sim_engine_run): Rename variable vaddr to cia.
2056         (signal_exception): Pass cia to sim_monitor
2057
2058         * sim-main.h (SignalException, LoadWord, StoreWord, CacheOp,
2059         Prefetch, SyncOperation, ValueFPR, StoreFPR, Convert, COP_LW,
2060         COP_LD, COP_SW, COP_SD, DecodeCoproc): Update.
2061
2062         * sim-main.h (SignalExceptionSimulatorFault): Delete definition.
2063         * interp.c (sim_open): Replace SignalExceptionSimulatorFault with
2064         SIM_ASSERT.
2065
2066         * interp.c (signal_exception): Pass restart address to
2067         sim_engine_restart.
2068
2069         * Makefile.in (semantics.o, engine.o, support.o, itable.o,
2070         idecode.o): Add dependency.
2071
2072         * sim-main.h (SIM_ENGINE_HALT_HOOK, SIM_ENGINE_RESUME_HOOK):
2073         Delete definitions
2074         (DELAY_SLOT): Update NIA not PC with branch address.
2075         (NULLIFY_NEXT_INSTRUCTION): Set NIA to instruction after next.
2076
2077         * mips.igen: Use CIA not PC in branch calculations.
2078         (illegal): Call SignalException.
2079         (BEQ, ADDIU): Fix assembler.
2080
2081 Wed Nov  5 12:19:56 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2082
2083         * m16.igen (JALX): Was missing.
2084
2085         * configure.in (enable-sim-igen): New configuration option.
2086         * configure: Re-generate.
2087
2088         * sim-main.h (MAX_INSNS, INSN_NAME): Define.
2089
2090         * interp.c (load_memory, store_memory): Delete parameter RAW.
2091         (sim_read, sim_write): Use sim_core_{read,write}_buffer directly
2092         bypassing {load,store}_memory.
2093
2094         * sim-main.h (ByteSwapMem): Delete definition.
2095
2096         * Makefile.in (SIM_OBJS): Add sim-memopt module.
2097
2098         * interp.c (sim_do_command, sim_commands): Delete mips specific
2099         commands.  Handled by module sim-options.
2100
2101         * sim-main.h (SIM_HAVE_FLATMEM): Undefine, use sim-core.o module.
2102         (WITH_MODULO_MEMORY): Define.
2103
2104         * interp.c (sim_info): Delete code printing memory size.
2105
2106         * interp.c (mips_size): Nee sim_size, delete function.
2107         (power2): Delete.
2108         (monitor, monitor_base, monitor_size): Delete global variables.
2109         (sim_open, sim_close): Delete code creating monitor and other
2110         memory regions.  Use sim-memopts module, via sim_do_commandf, to
2111         manage memory regions.
2112         (load_memory, store_memory): Use sim-core for memory model.
2113
2114         * interp.c (address_translation): Delete all memory map code
2115         except line forcing 32 bit addresses.
2116
2117 Wed Nov  5 11:21:11 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2118
2119         * sim-main.h (WITH_TRACE): Delete definition.  Enables common
2120         trace options.
2121
2122         * interp.c (logfh, logfile): Delete globals.
2123         (sim_open, sim_close): Delete code opening & closing log file.
2124         (mips_option_handler): Delete -l and -n options.
2125         (OPTION mips_options): Ditto.
2126
2127         * interp.c (OPTION mips_options): Rename option trace to dinero.
2128         (mips_option_handler): Update.
2129
2130 Wed Nov  5 09:35:59 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2131
2132         * interp.c (fetch_str): New function.
2133         (sim_monitor): Rewrite using sim_read & sim_write.
2134         (sim_open): Check magic number.
2135         (sim_open): Write monitor vectors into memory using sim_write.
2136         (MONITOR_BASE, MONITOR_SIZE, MEM_SIZE): Define.
2137         (sim_read, sim_write): Simplify - transfer data one byte at a
2138         time.
2139         (load_memory, store_memory): Clarify meaning of parameter RAW.
2140
2141         * sim-main.h (isHOST): Defete definition.
2142         (isTARGET): Mark as depreciated.
2143         (address_translation): Delete parameter HOST.
2144
2145         * interp.c (address_translation): Delete parameter HOST.
2146
2147 Wed Oct 29 11:13:56 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2148
2149         * mips.igen:
2150
2151         * Makefile.in (IGEN_INCLUDE): Files included by mips.igen.
2152         (tmp-igen, tmp-m16): Depend on IGEN_INCLUDE.
2153
2154 Tue Oct 28 11:06:47 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2155
2156         * mips.igen: Add model filter field to records.
2157
2158 Mon Oct 27 17:53:59 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2159
2160         * Makefile.in (SIM_NO_CFLAGS): Define.  Define WITH_IGEN=0.
2161
2162         interp.c (sim_engine_run): Do not compile function sim_engine_run
2163         when WITH_IGEN == 1.
2164
2165         * configure.in (sim_igen_flags, sim_m16_flags): Set according to
2166         target architecture.
2167
2168         Makefile.in (tmp-igen, tmp-m16): Drop -F and -M options to
2169         igen. Replace with configuration variables sim_igen_flags /
2170         sim_m16_flags.
2171
2172         * m16.igen: New file.  Copy mips16 insns here.
2173         * mips.igen: From here.
2174
2175 Mon Oct 27 13:53:59 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2176
2177         * Makefile.in (SIM_NO_OBJ): Define, move SIM_M16_OBJ, SIM_IGEN_OBJ
2178         to top.
2179         (tmp-igen, tmp-m16): Pass -I srcdir to igen.
2180
2181 Sat Oct 25 16:51:40 1997  Gavin Koch  <gavin@cygnus.com>
2182
2183         * gencode.c (build_instruction): Follow sim_write's lead in using
2184         BigEndianMem instead of !ByteSwapMem.
2185
2186 Fri Oct 24 17:41:49 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2187
2188         * configure.in (sim_gen): Dependent on target, select type of
2189         generator.  Always select old style generator.
2190
2191         configure: Re-generate.
2192
2193         Makefile.in (tmp-igen, tmp-m16, clean-m16, clean-igen): New
2194         targets.
2195         (SIM_M16_CFLAGS, SIM_M16_ALL, SIM_M16_OBJ, BUILT_SRC_FROM_M16,
2196         SIM_IGEN_CFLAGS, SIM_IGEN_ALL, SIM_IGEN_OBJ, BUILT_SRC_FROM_IGEN,
2197         IGEN_TRACE, IGEN_INSN, IGEN_DC): Define
2198         (SIM_EXTRA_CFLAGS, SIM_EXTRA_ALL, SIM_OBJS): Add member
2199         SIM_@sim_gen@_*, set by autoconf.
2200
2201 Wed Oct 22 12:52:06 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2202
2203         * sim-main.h (NULLIFY_NEXT_INSTRUCTION, DELAY_SLOT): Define.
2204
2205         * interp.c (ColdReset): Remove #ifdef HASFPU, check
2206         CURRENT_FLOATING_POINT instead.
2207
2208         * interp.c (ifetch32): New function. Fetch 32 bit instruction.
2209         (address_translation): Raise exception InstructionFetch when
2210         translation fails and isINSTRUCTION.
2211
2212         * interp.c (sim_open, sim_write, sim_monitor, store_word,
2213         sim_engine_run): Change type of of vaddr and paddr to
2214         address_word.
2215         (address_translation, prefetch, load_memory, store_memory,
2216         cache_op): Change type of vAddr and pAddr to address_word.
2217
2218         * gencode.c (build_instruction): Change type of vaddr and paddr to
2219         address_word.
2220
2221 Mon Oct 20 15:29:04 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2222
2223         * sim-main.h (ALU64_END, ALU32_END): Use ALU*_OVERFLOW_RESULT
2224         macro to obtain result of ALU op.
2225
2226 Tue Oct 21 17:39:14 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2227
2228         * interp.c (sim_info): Call profile_print.
2229
2230 Mon Oct 20 13:31:20 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2231
2232         * Makefile.in (SIM_OBJS): Add sim-profile.o module.
2233
2234         * sim-main.h (WITH_PROFILE): Do not define, defined in
2235         common/sim-config.h.  Use sim-profile module.
2236         (simPROFILE): Delete defintion.
2237
2238         * interp.c (PROFILE): Delete definition.
2239         (mips_option_handler): Delete 'p', 'y' and 'x' profile options.
2240         (sim_close): Delete code writing profile histogram.
2241         (mips_set_profile, mips_set_profile_size, writeout16, writeout32):
2242         Delete.
2243         (sim_engine_run): Delete code profiling the PC.
2244
2245 Mon Oct 20 13:31:20 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2246
2247         * sim-main.h (SIGNEXTEND): Force type of result to unsigned_word.
2248
2249         * interp.c (sim_monitor): Make register pointers of type
2250         unsigned_word*.
2251
2252         * sim-main.h: Make registers of type unsigned_word not
2253         signed_word.
2254
2255 Thu Oct 16 10:31:39 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2256
2257         * interp.c (sync_operation): Rename from SyncOperation, make
2258         global, add SD argument.
2259         (prefetch): Rename from Prefetch, make global, add SD argument.
2260         (decode_coproc): Make global.
2261
2262         * sim-main.h (SyncOperation, DecodeCoproc, Pefetch): Define.
2263
2264         * gencode.c (build_instruction): Generate DecodeCoproc not
2265         decode_coproc calls.
2266
2267         * interp.c (SETFCC, GETFCC, PREVCOC1): Move to sim-main.h
2268         (SizeFGR): Move to sim-main.h
2269         (simHALTEX, simHALTIN, simTRACE, simPROFILE, simDELAYSLOT,
2270         simSIGINT, simJALDELAYSLOT): Move to sim-main.h
2271         (FP_FLAGS, FP_ENABLE, FP_CAUSE, IR, UF, OF, DZ, IO, UO): Move to
2272         sim-main.h.
2273         (FP_FS, FP_MASK_RM, FP_SH_RM, FP_RM_NEAREST, FP_RM_TOPINF,
2274         FP_RM_TOMINF, GETRM): Move to sim-main.h.
2275         (Uncached, CachedNoncoherent, CachedCoherent, Cached,
2276         isINSTRUCTION, ..., AccessLength_BYTE, ...): Move to sim-main.h.
2277         (UserMode, BigEndianMem, ByteSwapMem, ReverseEndian,
2278         BigEndianCPU, status_KSU_mask, ...). Moved to sim-main.h
2279
2280         * sim-main.h (ALU32_END, ALU64_END): Define. When overflow raise
2281         exception.
2282         (sim-alu.h): Include.
2283         (NULLIFY_NIA, NULL_CIA, CPU_CIA): Define.
2284         (sim_cia): Typedef to instruction_address.
2285
2286 Thu Oct 16 10:31:41 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2287
2288         * Makefile.in (interp.o): Rename generated file engine.c to
2289         oengine.c.
2290
2291         * interp.c: Update.
2292
2293 Thu Oct 16 10:31:40 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2294
2295         * gencode.c (build_instruction): Use FPR_STATE not fpr_state.
2296
2297 Thu Oct 16 10:31:39 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2298
2299         * gencode.c (build_instruction): For "FPSQRT", output correct
2300         number of arguments to Recip.
2301
2302 Tue Oct 14 17:38:18 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2303
2304         * Makefile.in (interp.o): Depends on sim-main.h
2305
2306         * interp.c (mips16_entry, ColdReset,dotrace): Add SD argument. Use GPR not registers.
2307
2308         * sim-main.h (sim_cpu): Add registers, register_widths, fpr_state,
2309         ipc, dspc, pending_*, hiaccess, loaccess, state, dsstate fields.
2310         (REGISTERS, REGISTER_WIDTHS, FPR_STATE, IPC, DSPC, PENDING_*,
2311         STATE, DSSTATE): Define
2312         (GPR, FGRIDX, ..): Define.
2313
2314         * interp.c (registers, register_widths, fpr_state, ipc, dspc,
2315         pending_*, hiaccess, loaccess, state, dsstate): Delete globals.
2316         (GPR, FGRIDX, ...): Delete macros.
2317
2318         * interp.c: Update names to match defines from sim-main.h
2319
2320 Tue Oct 14 15:11:45 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2321
2322         * interp.c (sim_monitor): Add SD argument.
2323         (sim_warning): Delete.  Replace calls with calls to
2324         sim_io_eprintf.
2325         (sim_error): Delete. Replace calls with sim_io_error.
2326         (open_trace, writeout32, writeout16, getnum): Add SD argument.
2327         (mips_set_profile): Rename from sim_set_profile. Add SD argument.
2328         (mips_set_profile_size): Rename from sim_set_profile_size. Add SD
2329         argument.
2330         (mips_size): Rename from sim_size. Add SD argument.
2331
2332         * interp.c (simulator): Delete global variable.
2333         (callback): Delete global variable.
2334         (mips_option_handler, sim_open, sim_write, sim_read,
2335         sim_store_register, sim_fetch_register, sim_info, sim_do_command,
2336         sim_size,sim_monitor): Use sim_io_* not callback->*.
2337         (sim_open): ZALLOC simulator struct.
2338         (PROFILE): Do not define.
2339
2340 Tue Oct 14 13:35:48 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2341
2342         * interp.c (sim_open), support.h: Replace CHECKSIM macro found in
2343         support.h with corresponding code.
2344
2345         * sim-main.h (word64, uword64), support.h: Move definition to
2346         sim-main.h.
2347         (WORD64LO, WORD64HI, SET64LO, SET64HI, WORD64, UWORD64): Ditto.
2348
2349         * support.h: Delete
2350         * Makefile.in: Update dependencies
2351         * interp.c: Do not include.
2352
2353 Tue Oct 14 13:35:48 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2354
2355         * interp.c (address_translation, load_memory, store_memory,
2356         cache_op): Rename to from AddressTranslation et.al., make global,
2357         add SD argument
2358
2359         * sim-main.h (AddressTranslation, LoadMemory, StoreMemory,
2360         CacheOp): Define.
2361
2362         * interp.c (SignalException): Rename to signal_exception, make
2363         global.
2364
2365         * interp.c (Interrupt, ...): Move definitions to sim-main.h.
2366
2367         * sim-main.h (SignalException, SignalExceptionInterrupt,
2368         SignalExceptionInstructionFetch, SignalExceptionAddressStore,
2369         SignalExceptionAddressLoad, SignalExceptionSimulatorFault,
2370         SignalExceptionIntegerOverflow, SignalExceptionCoProcessorUnusable):
2371         Define.
2372
2373         * interp.c, support.h: Use.
2374
2375 Tue Oct 14 13:19:20 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2376
2377         * interp.c (ValueFPR, StoreFPR), sim-main.h: Make global, rename
2378         to value_fpr / store_fpr. Add SD argument.
2379         (NaN, Infinity, Less, Equal, AbsoluteValue, Negate, Add, Sub,
2380         Multiply, Divide, Recip, SquareRoot, Convert): Make global.
2381
2382         * sim-main.h (ValueFPR, StoreFPR): Define.
2383
2384 Tue Oct 14 13:06:55 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2385
2386         * interp.c (sim_engine_run): Check consistency between configure
2387         WITH_TARGET_WORD_BITSIZE and WITH_FLOATING_POINT and gensim GPRLEN
2388         and HASFPU.
2389
2390         * configure.in (mips_bitsize): Configure WITH_TARGET_WORD_BITSIZE.
2391         (mips_fpu): Configure WITH_FLOATING_POINT.
2392         (mips_endian): Configure WITH_TARGET_ENDIAN.
2393         * configure: Update.
2394
2395 Fri Oct  3 09:28:00 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2396
2397         * configure: Regenerated to track ../common/aclocal.m4 changes.
2398
2399 Mon Sep 29 14:45:00 1997  Bob Manson  <manson@charmed.cygnus.com>
2400
2401         * configure: Regenerated.
2402
2403 Fri Sep 26 12:48:18 1997  Mark Alexander  <marka@cygnus.com>
2404
2405         * interp.c: Allow Debug, DEPC, and EPC registers to be examined in GDB.
2406
2407 Thu Sep 25 11:15:22 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2408
2409         * gencode.c (print_igen_insn_models): Assume certain architectures
2410         include all mips* instructions.
2411         (print_igen_insn_format): Use data_size==-1 as marker for MIPS16
2412         instruction.
2413
2414         * Makefile.in (tmp.igen): Add target. Generate igen input from
2415         gencode file.
2416
2417         * gencode.c (FEATURE_IGEN): Define.
2418         (main): Add --igen option.  Generate output in igen format.
2419         (process_instructions): Format output according to igen option.
2420         (print_igen_insn_format): New function.
2421         (print_igen_insn_models): New function.
2422         (process_instructions): Only issue warnings and ignore
2423         instructions when no FEATURE_IGEN.
2424
2425 Wed Sep 24 17:38:57 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2426
2427         * interp.c (COP_SD, COP_LD): Add UNUSED to pacify GCC for some
2428         MIPS targets.
2429
2430 Tue Sep 23 11:04:38 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2431
2432         * configure: Regenerated to track ../common/aclocal.m4 changes.
2433
2434 Tue Sep 23 10:19:51 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2435
2436         * Makefile.in (SIM_ALIGNMENT, SIM_ENDIAN, SIM_HOSTENDIAN,
2437         SIM_RESERVED_BITS): Delete, moved to common.
2438         (SIM_EXTRA_CFLAGS): Update.
2439
2440 Mon Sep 22 11:46:20 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2441
2442         * configure.in: Configure non-strict memory alignment.
2443         * configure: Regenerated to track ../common/aclocal.m4 changes.
2444
2445 Fri Sep 19 17:45:25 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2446
2447         * configure: Regenerated to track ../common/aclocal.m4 changes.
2448
2449 Sat Sep 20 14:07:28 1997  Gavin Koch  <gavin@cygnus.com>
2450
2451         * gencode.c (SDBBP,DERET): Added (3900) insns.
2452         (RFE): Turn on for 3900.
2453         * interp.c (DebugBreakPoint,DEPC,Debug,Debug_*): Added.
2454         (dsstate): Made global.
2455         (SUBTARGET_R3900): Added.
2456         (CANCELDELAYSLOT): New.
2457         (SignalException): Ignore SystemCall rather than ignore and
2458         terminate.  Add DebugBreakPoint handling.
2459         (decode_coproc): New insns RFE, DERET; and new registers Debug
2460         and DEPC protected by SUBTARGET_R3900.
2461         (sim_engine_run): Use CANCELDELAYSLOT rather than clearing
2462         bits explicitly.
2463         * Makefile.in,configure.in: Add mips subtarget option.
2464         * configure: Update.
2465
2466 Fri Sep 19 09:33:27 1997  Gavin Koch  <gavin@cygnus.com>
2467
2468         * gencode.c: Add r3900 (tx39).
2469
2470
2471 Tue Sep 16 15:52:04 1997  Gavin Koch  <gavin@cygnus.com>
2472
2473         * gencode.c (build_instruction): Don't need to subtract 4 for
2474         JALR, just 2.
2475
2476 Tue Sep 16 11:32:28 1997  Gavin Koch  <gavin@cygnus.com>
2477
2478         * interp.c: Correct some HASFPU problems.
2479
2480 Mon Sep 15 17:36:15 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2481
2482         * configure: Regenerated to track ../common/aclocal.m4 changes.
2483
2484 Fri Sep 12 12:01:39 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2485
2486         * interp.c (mips_options): Fix samples option short form, should
2487         be `x'.
2488
2489 Thu Sep 11 09:35:29 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2490
2491         * interp.c (sim_info): Enable info code.  Was just returning.
2492
2493 Tue Sep  9 17:30:57 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2494
2495         * interp.c (decode_coproc): Clarify warning about unsuported MTC0,
2496         MFC0.
2497
2498 Tue Sep  9 16:28:28 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2499
2500         * gencode.c (build_instruction): Use SIGNED64 for 64 bit
2501         constants.
2502         (build_instruction): Ditto for LL.
2503
2504 Thu Sep  4 17:21:23 1997  Doug Evans  <dje@seba>
2505
2506         * configure: Regenerated to track ../common/aclocal.m4 changes.
2507
2508 Wed Aug 27 18:13:22 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2509
2510         * configure: Regenerated to track ../common/aclocal.m4 changes.
2511         * config.in: Ditto.
2512
2513 Wed Aug 27 14:12:27 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2514
2515         * interp.c (sim_open): Add call to sim_analyze_program, update
2516         call to sim_config.
2517
2518 Tue Aug 26 10:40:07 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2519
2520         * interp.c (sim_kill): Delete.
2521         (sim_create_inferior): Add ABFD argument. Set PC from same.
2522         (sim_load): Move code initializing trap handlers from here.
2523         (sim_open): To here.
2524         (sim_load): Delete, use sim-hload.c.
2525
2526         * Makefile.in (SIM_OBJS): Add sim-hload.o module.
2527
2528 Mon Aug 25 17:50:22 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2529
2530         * configure: Regenerated to track ../common/aclocal.m4 changes.
2531         * config.in: Ditto.
2532
2533 Mon Aug 25 15:59:48 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2534
2535         * interp.c (sim_open): Add ABFD argument.
2536         (sim_load): Move call to sim_config from here.
2537         (sim_open): To here.  Check return status.
2538
2539 Fri Jul 25 15:00:45 1997  Gavin Koch  <gavin@cygnus.com>
2540
2541         * gencode.c (build_instruction): Two arg MADD should
2542         not assign result to $0.
2543
2544 Thu Jun 26 12:13:17 1997  Angela Marie Thomas (angela@cygnus.com)
2545
2546         * sim/mips/configure: Change default_sim_endian to 0 (bi-endian)
2547         * sim/mips/configure.in: Regenerate.
2548
2549 Wed Jul  9 10:29:21 1997  Andrew Cagney  <cagney@critters.cygnus.com>
2550
2551         * interp.c (SUB_REG_UW, SUB_REG_SW, SUB_REG_*): Use more explicit
2552         signed8, unsigned8 et.al. types.
2553
2554         * interp.c (SUB_REG_FETCH): Handle both little and big endian
2555         hosts when selecting subreg.
2556
2557 Wed Jul  2 11:54:10 1997  Jeffrey A Law  (law@cygnus.com)
2558
2559         * interp.c (sim_engine_run): Reset the ZERO register to zero
2560         regardless of FEATURE_WARN_ZERO.
2561         * gencode.c (FEATURE_WARNINGS): Remove FEATURE_WARN_ZERO.
2562
2563 Wed Jun  4 10:43:14 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2564
2565         * interp.c (decode_coproc): Implement MTC0 N, CAUSE.
2566         (SignalException): For BreakPoints ignore any mode bits and just
2567         save the PC.
2568         (SignalException): Always set the CAUSE register.
2569
2570 Tue Jun  3 05:00:33 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2571
2572         * interp.c (SignalException): Clear the simDELAYSLOT flag when an
2573         exception has been taken.
2574
2575         * interp.c: Implement the ERET and mt/f sr instructions.
2576
2577 Sat May 31 00:44:16 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2578
2579         * interp.c (SignalException): Don't bother restarting an
2580         interrupt.
2581
2582 Fri May 30 23:41:48 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2583
2584         * interp.c (SignalException): Really take an interrupt.
2585         (interrupt_event): Only deliver interrupts when enabled.
2586
2587 Tue May 27 20:08:06 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2588
2589         * interp.c (sim_info): Only print info when verbose.
2590         (sim_info) Use sim_io_printf for output.
2591
2592 Tue May 27 14:22:23 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2593
2594         * interp.c (CoProcPresent): Add UNUSED attribute - not used by all
2595         mips architectures.
2596
2597 Tue May 27 14:22:23 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2598
2599         * interp.c (sim_do_command): Check for common commands if a
2600         simulator specific command fails.
2601
2602 Thu May 22 09:32:03 1997  Gavin Koch  <gavin@cygnus.com>
2603
2604         * interp.c (sim_engine_run): ifdef out uses of simSTOP, simSTEP
2605         and simBE when DEBUG is defined.
2606
2607 Wed May 21 09:08:10 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2608
2609         * interp.c (interrupt_event): New function.  Pass exception event
2610         onto exception handler.
2611
2612         * configure.in: Check for stdlib.h.
2613         * configure: Regenerate.
2614
2615         * gencode.c (build_instruction): Add UNUSED attribute to tempS
2616         variable declaration.
2617         (build_instruction): Initialize memval1.
2618         (build_instruction): Add UNUSED attribute to byte, bigend,
2619         reverse.
2620         (build_operands): Ditto.
2621
2622         * interp.c: Fix GCC warnings.
2623         (sim_get_quit_code): Delete.
2624
2625         * configure.in: Add INLINE, ENDIAN, HOSTENDIAN and WARNINGS.
2626         * Makefile.in: Ditto.
2627         * configure: Re-generate.
2628
2629         * Makefile.in (SIM_OBJS): Add sim-watch.o module.
2630
2631 Tue May 20 15:08:56 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2632
2633         * interp.c (mips_option_handler): New function parse argumes using
2634         sim-options.
2635         (myname): Replace with STATE_MY_NAME.
2636         (sim_open): Delete check for host endianness - performed by
2637         sim_config.
2638         (simHOSTBE, simBE): Delete, replaced by sim-endian flags.
2639         (sim_open): Move much of the initialization from here.
2640         (sim_load): To here.  After the image has been loaded and
2641         endianness set.
2642         (sim_open): Move ColdReset from here.
2643         (sim_create_inferior): To here.
2644         (sim_open): Make FP check less dependant on host endianness.
2645
2646         * Makefile.in (SIM_RUN_OBJS): Set to nrun.o - use new version or
2647         run.
2648         * interp.c (sim_set_callbacks): Delete.
2649
2650         * interp.c (membank, membank_base, membank_size): Replace with
2651         STATE_MEMORY, STATE_MEM_SIZE, STATE_MEM_BASE.
2652         (sim_open): Remove call to callback->init. gdb/run do this.
2653
2654         * interp.c: Update
2655
2656         * sim-main.h (SIM_HAVE_FLATMEM): Define.
2657
2658         * interp.c (big_endian_p): Delete, replaced by
2659         current_target_byte_order.
2660
2661 Tue May 20 13:55:00 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2662
2663         * interp.c (host_read_long, host_read_word, host_swap_word,
2664         host_swap_long): Delete. Using common sim-endian.
2665         (sim_fetch_register, sim_store_register): Use H2T.
2666         (pipeline_ticks): Delete.  Handled by sim-events.
2667         (sim_info): Update.
2668         (sim_engine_run): Update.
2669
2670 Tue May 20 13:42:03 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2671
2672         * interp.c (sim_stop_reason): Move code determining simEXCEPTION
2673         reason from here.
2674         (SignalException): To here. Signal using sim_engine_halt.
2675         (sim_stop_reason): Delete, moved to common.
2676
2677 Tue May 20 10:19:48 1997  Andrew Cagney  <cagney@b2.cygnus.com>
2678
2679         * interp.c (sim_open): Add callback argument.
2680         (sim_set_callbacks): Delete SIM_DESC argument.
2681         (sim_size): Ditto.
2682
2683 Mon May 19 18:20:38 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2684
2685         * Makefile.in (SIM_OBJS): Add common modules.
2686
2687         * interp.c (sim_set_callbacks): Also set SD callback.
2688         (set_endianness, xfer_*, swap_*): Delete.
2689         (host_read_word, host_read_long, host_swap_word, host_swap_long):
2690         Change to functions using sim-endian macros.
2691         (control_c, sim_stop): Delete, use common version.
2692         (simulate): Convert into.
2693         (sim_engine_run): This function.
2694         (sim_resume): Delete.
2695
2696         * interp.c (simulation): New variable - the simulator object.
2697         (sim_kind): Delete global - merged into simulation.
2698         (sim_load): Cleanup.  Move PC assignment from here.
2699         (sim_create_inferior): To here.
2700
2701         * sim-main.h: New file.
2702         * interp.c (sim-main.h): Include.
2703
2704 Thu Apr 24 00:39:51 1997  Doug Evans  <dje@canuck.cygnus.com>
2705
2706         * configure: Regenerated to track ../common/aclocal.m4 changes.
2707
2708 Wed Apr 23 17:32:19 1997  Doug Evans  <dje@canuck.cygnus.com>
2709
2710         * tconfig.in (SIM_HAVE_BIENDIAN): Define.
2711
2712 Mon Apr 21 17:16:13 1997  Gavin Koch  <gavin@cygnus.com>
2713
2714         * gencode.c (build_instruction): DIV instructions: check
2715         for division by zero and integer overflow before using
2716         host's division operation.
2717
2718 Thu Apr 17 03:18:14 1997  Doug Evans  <dje@canuck.cygnus.com>
2719
2720         * Makefile.in (SIM_OBJS): Add sim-load.o.
2721         * interp.c: #include bfd.h.
2722         (target_byte_order): Delete.
2723         (sim_kind, myname, big_endian_p): New static locals.
2724         (sim_open): Set sim_kind, myname.  Move call to set_endianness to
2725         after argument parsing.  Recognize -E arg, set endianness accordingly.
2726         (sim_load): Return SIM_RC.  New arg abfd.  Call sim_load_file to
2727         load file into simulator.  Set PC from bfd.
2728         (sim_create_inferior): Return SIM_RC.  Delete arg start_address.
2729         (set_endianness): Use big_endian_p instead of target_byte_order.
2730
2731 Wed Apr 16 17:55:37 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2732
2733         * interp.c (sim_size): Delete prototype - conflicts with
2734         definition in remote-sim.h.  Correct definition.
2735
2736 Mon Apr  7 15:45:02 1997  Andrew Cagney  <cagney@kremvax.cygnus.com>
2737
2738         * configure: Regenerated to track ../common/aclocal.m4 changes.
2739         * config.in: Ditto.
2740
2741 Wed Apr  2 15:06:28 1997  Doug Evans  <dje@canuck.cygnus.com>
2742
2743         * interp.c (sim_open): New arg `kind'.
2744
2745         * configure: Regenerated to track ../common/aclocal.m4 changes.
2746
2747 Wed Apr  2 14:34:19 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
2748
2749         * configure: Regenerated to track ../common/aclocal.m4 changes.
2750
2751 Tue Mar 25 11:38:22 1997  Doug Evans  <dje@canuck.cygnus.com>
2752
2753         * interp.c (sim_open): Set optind to 0 before calling getopt.
2754
2755 Wed Mar 19 01:14:00 1997  Andrew Cagney  <cagney@kremvax.cygnus.com>
2756
2757         * configure: Regenerated to track ../common/aclocal.m4 changes.
2758
2759 Mon Mar 17 10:52:59 1997  Gavin Koch  <gavin@cetus.cygnus.com>
2760
2761         * interp.c : Replace uses of pr_addr with pr_uword64
2762         where the bit length is always 64 independent of SIM_ADDR.
2763         (pr_uword64) : added.
2764
2765 Mon Mar 17 15:10:07 1997  Andrew Cagney  <cagney@kremvax.cygnus.com>
2766
2767         * configure: Re-generate.
2768
2769 Fri Mar 14 10:34:11 1997  Michael Meissner  <meissner@cygnus.com>
2770
2771         * configure: Regenerate to track ../common/aclocal.m4 changes.
2772
2773 Thu Mar 13 12:51:36 1997  Doug Evans  <dje@canuck.cygnus.com>
2774
2775         * interp.c (sim_open): New SIM_DESC result.  Argument is now
2776         in argv form.
2777         (other sim_*): New SIM_DESC argument.
2778
2779 Mon Feb 24 22:47:14 1997  Dawn Perchik  <dawn@cygnus.com>
2780
2781         * interp.c: Fix printing of addresses for non-64-bit targets.
2782         (pr_addr): Add function to print address based on size.
2783
2784 Wed Feb 19 14:42:09 1997  Mark Alexander  <marka@cygnus.com>
2785
2786         * interp.c (simopen): Add support for LSI MiniRISC PMON vectors.
2787
2788 Thu Feb 13 14:08:30 1997  Ian Lance Taylor  <ian@cygnus.com>
2789
2790         * gencode.c (build_mips16_operands): Correct computation of base
2791         address for extended PC relative instruction.
2792
2793 Thu Feb  6 17:16:15 1997  Ian Lance Taylor  <ian@cygnus.com>
2794
2795         * interp.c (mips16_entry): Add support for floating point cases.
2796         (SignalException): Pass floating point cases to mips16_entry.
2797         (ValueFPR): Don't restrict fmt_single and fmt_word to even
2798         registers.
2799         (StoreFPR): Likewise.  Also, don't clobber fpr + 1 for fmt_single
2800         or fmt_word.
2801         (COP_LW): Pass fmt_word rather than fmt_uninterpreted to StoreFPR,
2802         and then set the state to fmt_uninterpreted.
2803         (COP_SW): Temporarily set the state to fmt_word while calling
2804         ValueFPR.
2805
2806 Tue Feb  4 16:48:25 1997  Ian Lance Taylor  <ian@cygnus.com>
2807
2808         * gencode.c (build_instruction): The high order may be set in the
2809         comparison flags at any ISA level, not just ISA 4.
2810
2811 Tue Feb  4 13:33:30 1997  Doug Evans  <dje@canuck.cygnus.com>
2812
2813         * Makefile.in (@COMMON_MAKEFILE_FRAG): Use
2814         COMMON_{PRE,POST}_CONFIG_FRAG instead.
2815         * configure.in: sinclude ../common/aclocal.m4.
2816         * configure: Regenerated.
2817
2818 Fri Jan 31 11:11:45 1997  Ian Lance Taylor  <ian@cygnus.com>
2819
2820         * configure: Rebuild after change to aclocal.m4.
2821
2822 Thu Jan 23 11:46:23 1997  Stu Grossman  (grossman@critters.cygnus.com)
2823
2824         * configure configure.in Makefile.in:  Update to new configure
2825         scheme which is more compatible with WinGDB builds.
2826         * configure.in:  Improve comment on how to run autoconf.
2827         * configure:  Re-run autoconf to get new ../common/aclocal.m4.
2828         * Makefile.in:  Use autoconf substitution to install common
2829         makefile fragment.
2830
2831 Wed Jan  8 12:39:03 1997  Jim Wilson  <wilson@cygnus.com>
2832
2833         * gencode.c (build_instruction): Use BigEndianCPU instead of
2834         ByteSwapMem.
2835
2836 Thu Jan 02 22:23:04 1997  Mark Alexander  <marka@cygnus.com>
2837
2838         * interp.c (sim_monitor): Make output to stdout visible in
2839         wingdb's I/O log window.
2840
2841 Tue Dec 31 07:04:00 1996  Mark Alexander  <marka@cygnus.com>
2842
2843         * support.h: Undo previous change to SIGTRAP
2844         and SIGQUIT values.
2845
2846 Mon Dec 30 17:36:06 1996  Ian Lance Taylor  <ian@cygnus.com>
2847
2848         * interp.c (store_word, load_word): New static functions.
2849         (mips16_entry): New static function.
2850         (SignalException): Look for mips16 entry and exit instructions.
2851         (simulate): Use the correct index when setting fpr_state after
2852         doing a pending move.
2853
2854 Sun Dec 29 09:37:18 1996  Mark Alexander  <marka@cygnus.com>
2855
2856         * interp.c: Fix byte-swapping code throughout to work on
2857         both little- and big-endian hosts.
2858
2859 Sun Dec 29 09:18:32 1996  Mark Alexander  <marka@cygnus.com>
2860
2861         * support.h: Make definitions of SIGTRAP and SIGQUIT consistent
2862         with gdb/config/i386/xm-windows.h.
2863
2864 Fri Dec 27 22:48:51 1996  Mark Alexander  <marka@cygnus.com>
2865
2866         * gencode.c (build_instruction): Work around MSVC++ code gen bug
2867         that messes up arithmetic shifts.
2868
2869 Fri Dec 20 11:04:05 1996  Stu Grossman  (grossman@critters.cygnus.com)
2870
2871         * support.h:  Use _WIN32 instead of __WIN32__.  Also add defs for
2872         SIGTRAP and SIGQUIT for _WIN32.
2873
2874 Thu Dec 19 14:07:27 1996  Ian Lance Taylor  <ian@cygnus.com>
2875
2876         * gencode.c (build_instruction) [MUL]: Cast operands to word64, to
2877         force a 64 bit multiplication.
2878         (build_instruction) [OR]: In mips16 mode, don't do anything if the
2879         destination register is 0, since that is the default mips16 nop
2880         instruction.
2881
2882 Mon Dec 16 14:59:38 1996  Ian Lance Taylor  <ian@cygnus.com>
2883
2884         * gencode.c (MIPS16_DECODE): SWRASP is I8, not RI.
2885         (build_endian_shift): Don't check proc64.
2886         (build_instruction): Always set memval to uword64.  Cast op2 to
2887         uword64 when shifting it left in memory instructions.  Always use
2888         the same code for stores--don't special case proc64.
2889
2890         * gencode.c (build_mips16_operands): Fix base PC value for PC
2891         relative operands.
2892         (build_instruction): Call JALDELAYSLOT rather than DELAYSLOT for a
2893         jal instruction.
2894         * interp.c (simJALDELAYSLOT): Define.
2895         (JALDELAYSLOT): Define.
2896         (INDELAYSLOT, INJALDELAYSLOT): Define.
2897         (simulate): Clear simJALDELAYSLOT when simDELAYSLOT is cleared.
2898
2899 Tue Dec 24 22:11:20 1996  Angela Marie Thomas (angela@cygnus.com)
2900
2901         * interp.c (sim_open): add flush_cache as a PMON routine
2902         (sim_monitor): handle flush_cache by ignoring it
2903
2904 Wed Dec 11 13:53:51 1996  Jim Wilson  <wilson@cygnus.com>
2905
2906         * gencode.c (build_instruction): Use !ByteSwapMem instead of
2907         BigEndianMem.
2908         * interp.c (CONFIG, config_EP_{mask,shift,D,DxxDxx, config_BE): Delete.
2909         (BigEndianMem): Rename to ByteSwapMem and change sense.
2910         (BigEndianCPU, sim_write, LoadMemory, StoreMemory): Change
2911         BigEndianMem references to !ByteSwapMem.
2912         (set_endianness): New function, with prototype.
2913         (sim_open): Call set_endianness.
2914         (sim_info): Use simBE instead of BigEndianMem.
2915         (xfer_direct_word, xfer_direct_long, swap_direct_word,
2916         swap_direct_long, xfer_big_word, xfer_big_long, xfer_little_word,
2917         xfer_little_long, swap_word, swap_long): Delete unnecessary MSC_VER
2918         ifdefs, keeping the prototype declaration.
2919         (swap_word): Rewrite correctly.
2920         (ColdReset): Delete references to CONFIG.  Delete endianness related
2921         code; moved to set_endianness.
2922
2923 Tue Dec 10 11:32:04 1996  Jim Wilson  <wilson@cygnus.com>
2924
2925         * gencode.c (build_instruction, case JUMP): Truncate PC to 32 bits.
2926         * interp.c (CHECKHILO): Define away.
2927         (simSIGINT): New macro.
2928         (membank_size): Increase from 1MB to 2MB.
2929         (control_c): New function.
2930         (sim_resume): Rename parameter signal to signal_number.  Add local
2931         variable prev.  Call signal before and after simulate.
2932         (sim_stop_reason): Add simSIGINT support.
2933         (sim_warning, sim_error, dotrace, SignalException): Define as stdarg
2934         functions always.
2935         (sim_warning): Delete call to SignalException.  Do call printf_filtered
2936         if logfh is NULL.
2937         (AddressTranslation): Add #ifdef DEBUG around debugging message and
2938         a call to sim_warning.
2939
2940 Wed Nov 27 11:53:50 1996  Ian Lance Taylor  <ian@cygnus.com>
2941
2942         * gencode.c (process_instructions): If ! proc64, skip DOUBLEWORD
2943         16 bit instructions.
2944
2945 Tue Nov 26 11:53:12 1996  Ian Lance Taylor  <ian@cygnus.com>
2946
2947         Add support for mips16 (16 bit MIPS implementation):
2948         * gencode.c (inst_type): Add mips16 instruction encoding types.
2949         (GETDATASIZEINSN): Define.
2950         (MIPS_DECODE): Add REG flag to dsllv, dsrav, and dsrlv.  Add
2951         jalx.  Add LEFT flag to mfhi and mflo.  Add RIGHT flag to mthi and
2952         mtlo.
2953         (MIPS16_DECODE): New table, for mips16 instructions.
2954         (bitmap_val): New static function.
2955         (struct mips16_op): Define.
2956         (mips16_op_table): New table, for mips16 operands.
2957         (build_mips16_operands): New static function.
2958         (process_instructions): If PC is odd, decode a mips16
2959         instruction.  Break out instruction handling into new
2960         build_instruction function.
2961         (build_instruction): New static function, broken out of
2962         process_instructions.  Check modifiers rather than flags for SHIFT
2963         bit count and m[ft]{hi,lo} direction.
2964         (usage): Pass program name to fprintf.
2965         (main): Remove unused variable this_option_optind.  Change
2966         ``*loptarg++'' to ``loptarg++''.
2967         (my_strtoul): Parenthesize && within ||.
2968         * interp.c (LoadMemory): Accept a halfword pAddr if vAddr is odd.
2969         (simulate): If PC is odd, fetch a 16 bit instruction, and
2970         increment PC by 2 rather than 4.
2971         * configure.in: Add case for mips16*-*-*.
2972         * configure: Rebuild.
2973
2974 Fri Nov 22 08:49:36 1996  Mark Alexander  <marka@cygnus.com>
2975
2976         * interp.c: Allow -t to enable tracing in standalone simulator.
2977         Fix garbage output in trace file and error messages.
2978
2979 Wed Nov 20 01:54:37 1996  Doug Evans  <dje@canuck.cygnus.com>
2980
2981         * Makefile.in: Delete stuff moved to ../common/Make-common.in.
2982         (SIM_{OBJS,EXTRA_CFLAGS,EXTRA_CLEAN}): Define.
2983         * configure.in: Simplify using macros in ../common/aclocal.m4.
2984         * configure: Regenerated.
2985         * tconfig.in: New file.
2986
2987 Tue Nov 12 13:34:00 1996  Dawn Perchik  <dawn@cygnus.com>
2988
2989         * interp.c: Fix bugs in 64-bit port.
2990         Use ansi function declarations for msvc compiler.
2991         Initialize and test file pointer in trace code.
2992         Prevent duplicate definition of LAST_EMED_REGNUM.
2993
2994 Tue Oct 15 11:07:06 1996  Mark Alexander  <marka@cygnus.com>
2995
2996         * interp.c (xfer_big_long): Prevent unwanted sign extension.
2997
2998 Thu Sep 26 17:35:00 1996  James G. Smith  <jsmith@cygnus.co.uk>
2999
3000         * interp.c (SignalException): Check for explicit terminating
3001         breakpoint value.
3002         * gencode.c: Pass instruction value through SignalException()
3003         calls for Trap, Breakpoint and Syscall.
3004
3005 Thu Sep 26 11:35:17 1996  James G. Smith  <jsmith@cygnus.co.uk>
3006
3007         * interp.c (SquareRoot): Add HAVE_SQRT check to ensure sqrt() is
3008         only used on those hosts that provide it.
3009         * configure.in: Add sqrt() to list of functions to be checked for.
3010         * config.in: Re-generated.
3011         * configure: Re-generated.
3012
3013 Fri Sep 20 15:47:12 1996  Ian Lance Taylor  <ian@cygnus.com>
3014
3015         * gencode.c (process_instructions): Call build_endian_shift when
3016         expanding STORE RIGHT, to fix swr.
3017         * support.h (SIGNEXTEND): If the sign bit is not set, explicitly
3018         clear the high bits.
3019         * interp.c (Convert): Fix fmt_single to fmt_long to not truncate.
3020         Fix float to int conversions to produce signed values.
3021
3022 Thu Sep 19 15:34:17 1996  Ian Lance Taylor  <ian@cygnus.com>
3023
3024         * gencode.c (MIPS_DECODE): Set UNSIGNED for multu instruction.
3025         (process_instructions): Correct handling of nor instruction.
3026         Correct shift count for 32 bit shift instructions. Correct sign
3027         extension for arithmetic shifts to not shift the number of bits in
3028         the type.  Fix 64 bit multiply high word calculation.  Fix 32 bit
3029         unsigned multiply.  Fix ldxc1 and friends to use coprocessor 1.
3030         Fix madd.
3031         * interp.c (CHECKHILO): Don't set HIACCESS, LOACCESS, or HLPC.
3032         It's OK to have a mult follow a mult.  What's not OK is to have a
3033         mult follow an mfhi.
3034         (Convert): Comment out incorrect rounding code.
3035
3036 Mon Sep 16 11:38:16 1996  James G. Smith  <jsmith@cygnus.co.uk>
3037
3038         * interp.c (sim_monitor): Improved monitor printf
3039         simulation. Tidied up simulator warnings, and added "--log" option
3040         for directing warning message output.
3041         * gencode.c: Use sim_warning() rather than WARNING macro.
3042
3043 Thu Aug 22 15:03:12 1996  Ian Lance Taylor  <ian@cygnus.com>
3044
3045         * Makefile.in (gencode): Depend upon gencode.o, getopt.o, and
3046         getopt1.o, rather than on gencode.c.  Link objects together.
3047         Don't link against -liberty.
3048         (gencode.o, getopt.o, getopt1.o): New targets.
3049         * gencode.c: Include <ctype.h> and "ansidecl.h".
3050         (AND): Undefine after including "ansidecl.h".
3051         (ULONG_MAX): Define if not defined.
3052         (OP_*): Don't define macros; now defined in opcode/mips.h.
3053         (main): Call my_strtoul rather than strtoul.
3054         (my_strtoul): New static function.
3055
3056 Wed Jul 17 18:12:38 1996  Stu Grossman  (grossman@critters.cygnus.com)
3057
3058         * gencode.c (process_instructions):  Generate word64 and uword64
3059         instead of `long long' and `unsigned long long' data types.
3060         * interp.c:  #include sysdep.h to get signals, and define default
3061         for SIGBUS.
3062         * (Convert):  Work around for Visual-C++ compiler bug with type
3063         conversion.
3064         * support.h:  Make things compile under Visual-C++ by using
3065         __int64 instead of `long long'.  Change many refs to long long
3066         into word64/uword64 typedefs.
3067
3068 Wed Jun 26 12:24:55 1996  Jason Molenda  (crash@godzilla.cygnus.co.jp)
3069
3070         * Makefile.in (bindir, libdir, datadir, mandir, infodir, includedir,
3071         INSTALL_PROGRAM, INSTALL_DATA): Use autoconf-set values.
3072         (docdir): Removed.
3073         * configure.in (AC_PREREQ): autoconf 2.5 or higher.
3074         (AC_PROG_INSTALL): Added.
3075         (AC_PROG_CC): Moved to before configure.host call.
3076         * configure: Rebuilt.
3077
3078 Wed Jun  5 08:28:13 1996  James G. Smith  <jsmith@cygnus.co.uk>
3079
3080         * configure.in: Define @SIMCONF@ depending on mips target.
3081         * configure: Rebuild.
3082         * Makefile.in (run): Add @SIMCONF@ to control simulator
3083         construction.
3084         * gencode.c: Change LOADDRMASK to 64bit memory model only.
3085         * interp.c: Remove some debugging, provide more detailed error
3086         messages, update memory accesses to use LOADDRMASK.
3087
3088 Mon Jun  3 11:55:03 1996  Ian Lance Taylor  <ian@cygnus.com>
3089
3090         * configure.in: Add calls to AC_CONFIG_HEADER, AC_CHECK_HEADERS,
3091         AC_CHECK_LIB, and AC_CHECK_FUNCS.  Change AC_OUTPUT to set
3092         stamp-h.
3093         * configure: Rebuild.
3094         * config.in: New file, generated by autoheader.
3095         * interp.c: Include "config.h".  Include <stdlib.h>, <string.h>,
3096         and <strings.h> if they exist.  Replace #ifdef sun with #ifdef
3097         HAVE_ANINT and HAVE_AINT, as appropriate.
3098         * Makefile.in (run): Use @LIBS@ rather than -lm.
3099         (interp.o): Depend upon config.h.
3100         (Makefile): Just rebuild Makefile.
3101         (clean): Remove stamp-h.
3102         (mostlyclean): Make the same as clean, not as distclean.
3103         (config.h, stamp-h): New targets.
3104
3105 Fri May 10 00:41:17 1996  James G. Smith  <jsmith@cygnus.co.uk>
3106
3107         * interp.c (ColdReset): Fix boolean test. Make all simulator
3108         globals static.
3109
3110 Wed May  8 15:12:58 1996  James G. Smith  <jsmith@cygnus.co.uk>
3111
3112         * interp.c (xfer_direct_word, xfer_direct_long,
3113         swap_direct_word, swap_direct_long, xfer_big_word,
3114         xfer_big_long, xfer_little_word, xfer_little_long,
3115         swap_word,swap_long): Added.
3116         * interp.c (ColdReset): Provide function indirection to
3117         host<->simulated_target transfer routines.
3118         * interp.c (sim_store_register, sim_fetch_register): Updated to
3119         make use of indirected transfer routines.
3120
3121 Fri Apr 19 15:48:24 1996  James G. Smith  <jsmith@cygnus.co.uk>
3122
3123         * gencode.c (process_instructions): Ensure FP ABS instruction
3124         recognised.
3125         * interp.c (AbsoluteValue): Add routine. Also provide simple PMON
3126         system call support.
3127
3128 Wed Apr 10 09:51:38 1996  James G. Smith  <jsmith@cygnus.co.uk>
3129
3130         * interp.c (sim_do_command): Complain if callback structure not
3131         initialised.
3132
3133 Thu Mar 28 13:50:51 1996  James G. Smith  <jsmith@cygnus.co.uk>
3134
3135         * interp.c (Convert): Provide round-to-nearest and round-to-zero
3136         support for Sun hosts.
3137         * Makefile.in (gencode): Ensure the host compiler and libraries
3138         used for cross-hosted build.
3139
3140 Wed Mar 27 14:42:12 1996  James G. Smith  <jsmith@cygnus.co.uk>
3141
3142         * interp.c, gencode.c: Some more (TODO) tidying.
3143
3144 Thu Mar  7 11:19:33 1996  James G. Smith  <jsmith@cygnus.co.uk>
3145
3146         * gencode.c, interp.c: Replaced explicit long long references with
3147         WORD64HI, WORD64LO, SET64HI and SET64LO macro calls.
3148         * support.h (SET64LO, SET64HI): Macros added.
3149
3150 Wed Feb 21 12:16:21 1996  Ian Lance Taylor  <ian@cygnus.com>
3151
3152         * configure: Regenerate with autoconf 2.7.
3153
3154 Tue Jan 30 08:48:18 1996  Fred Fish  <fnf@cygnus.com>
3155
3156         * interp.c (LoadMemory): Enclose text following #endif in /* */.
3157         * support.h: Remove superfluous "1" from #if.
3158         * support.h (CHECKSIM): Remove stray 'a' at end of line.
3159
3160 Mon Dec  4 11:44:40 1995  Jamie Smith  <jsmith@cygnus.com>
3161
3162         * interp.c (StoreFPR): Control UndefinedResult() call on
3163         WARN_RESULT manifest.
3164
3165 Fri Dec  1 16:37:19 1995  James G. Smith  <jsmith@cygnus.co.uk>
3166
3167         * gencode.c: Tidied instruction decoding, and added FP instruction
3168         support.
3169
3170         * interp.c: Added dineroIII, and BSD profiling support. Also
3171         run-time FP handling.
3172
3173 Sun Oct 22 00:57:18 1995  James G. Smith  <jsmith@pasanda.cygnus.co.uk>
3174
3175         * Changelog, Makefile.in, README.Cygnus, configure, configure.in,
3176         gencode.c, interp.c, support.h: created.