sim/mips/ChangeLog

   1 2008-06-06  Vladimir Prus  <vladimir@codesourcery.com>
   2             Daniel Jacobowitz  <dan@codesourcery.com>
   3             Joseph Myers  <joseph@codesourcery.com>
   4
   5         * configure: Regenerate.
   6
   7 2007-10-22  Richard Sandiford  <rsandifo@nildram.co.uk>
   8
   9         * mips.igen (check_fmt_p): Provide a separate mips32r2 definition
  10         that unconditionally allows fmt_ps.
  11         (ALNV.PS, CEIL.L.fmt, CVT.L.fmt, CVT.PS.S, CVT.S.PL, CVT.S.PU)
  12         (FLOOR.L.fmt, LWXC1, MADD.fmt, MSUB.fmt, NMADD.fmt, NMSUB.fmt)
  13         (PLL.PS, PLU.PS, PUL.PS, PUU.PS, ROUND.L.fmt, TRUNC.L.fmt): Change
  14         filter from 64,f to 32,f.
  15         (PREFX): Change filter from 64 to 32.
  16         (LDXC1, LUXC1): Provide separate mips32r2 implementations
  17         that use do_load_double instead of do_load.  Make both LUXC1
  18         versions unpredictable if SizeFGR () != 64.
  19         (SDXC1, SUXC1): Extend to mips32r2, using do_store_double
  20         instead of do_store.  Remove unused variable.  Make both SUXC1
  21         versions unpredictable if SizeFGR () != 64.
  22
  23 2007-10-07  Richard Sandiford  <rsandifo@nildram.co.uk>
  24
  25         * mips.igen (ll): Fix mask for WITH_TARGET_WORD_BITSIZE == 32.
  26         (sc, swxc1): Likewise.  Also fix big-endian and reverse-endian
  27         shifts for that case.
  28
  29 2007-09-04  Nick Clifton  <nickc@redhat.com>
  30
  31         * interp.c (options enum): Add OPTION_INFO_MEMORY.
  32         (display_mem_info): New static variable.
  33         (mips_option_handler): Handle OPTION_INFO_MEMORY.
  34         (mips_options): Add info-memory and memory-info.
  35         (sim_open): After processing the command line and board
  36         specification, check display_mem_info.  If it is set then
  37         call the real handler for the --memory-info command line
  38         switch.
  39
  40 2007-08-24  Joel Brobecker  <brobecker@adacore.com>
  41
  42         * configure.ac: Change license of multi-run.c to GPL version 3.
  43         * configure: Regenerate.
  44
  45 2007-06-28  Richard Sandiford  <richard@codesourcery.com>
  46
  47         * configure.ac, configure: Revert last patch.
  48
  49 2007-06-26  Richard Sandiford  <richard@codesourcery.com>
  50
  51         * configure.ac (sim_mipsisa3264_configs): New variable.
  52         (mipsis32*-*-, mipsisa32r2*-*-*, mips64*-*-*, mips64r2*-*-*): Make
  53         every configuration support all four targets, using the triplet to
  54         determine the default.
  55         * configure: Regenerate.
  56
  57 2007-06-25  Richard Sandiford  <richard@codesourcery.com>
  58
  59         * Makefile.in (m16run.o): New rule.
  60
  61 2007-05-15  Thiemo Seufer  <ths@mips.com>
  62
  63         * mips3264r2.igen (DSHD): Fix compile warning.
  64
  65 2007-05-14  Thiemo Seufer  <ths@mips.com>
  66
  67         * mips.igen (ALNV.PS, CEIL.L.fmt, CVT.L.fmt, CVT.PS.S, CVT.S.PL,
  68         CVT.S.PU, FLOOR.L.fmt, LDXC1, LUXC1, LWXC1, MADD.fmt, MSUB.fmt,
  69         NMADD.fmt, NMSUB.fmt, PLL.PS, PLU.PS, PREFX, PUL.PS, PUU.PS,
  70         RECIP.fmt, ROUND.L.fmt, RSQRT.fmt, SWXC1, TRUNC.L.fmt): Add support
  71         for mips32r2.
  72
  73 2007-03-01  Thiemo Seufer  <ths@mips.com>
  74
  75         * mips.igen (MFHI, MFLO, MTHI, MTLO): Restore support for mips32
  76         and mips64.
  77
  78 2007-02-20  Thiemo Seufer  <ths@mips.com>
  79
  80         * dsp.igen: Update copyright notice.
  81         * dsp2.igen: Fix copyright notice.
  82
  83 2007-02-20  Thiemo Seufer  <ths@mips.com>
  84             Chao-Ying Fu  <fu@mips.com>
  85
  86         * Makefile.in (IGEN_INCLUDE): Add dsp2.igen.
  87         * configure.ac (mips*-sde-elf*, mipsisa32r2*-*-*, mipsisa64r2*-*-*):
  88         Add dsp2 to sim_igen_machine.
  89         * configure: Regenerate.
  90         * dsp.igen (do_ph_op): Add MUL support when op = 2.
  91         (do_ph_mulq): New function to support mulq_rs.ph and mulq_s.ph.
  92         (mulq_rs.ph): Use do_ph_mulq.
  93         (MFHI, MFLO, MTHI, MTLO): Move these instructions to mips.igen.
  94         * mips.igen: Add dsp2 model and include dsp2.igen.
  95         (MFHI, MFLO, MTHI, MTLO): Extend these instructions for
  96         for *mips32r2, *mips64r2, *dsp.
  97         (MADD, MADDU, MSUB, MSUBU, MULT, MULTU): Extend these instructions
  98         for *mips32r2, *mips64r2, *dsp2.
  99         * dsp2.igen: New file for MIPS DSP REV 2 ASE.
 100
 101 2007-02-19  Thiemo Seufer  <ths@mips.com>
 102             Nigel Stephens  <nigel@mips.com>
 103
 104         * mips.igen (jalr.hb, jr.hb): Add decoder for mip32r2/mips64r2
 105         jumps with hazard barrier.
 106
 107 2007-02-19  Thiemo Seufer  <ths@mips.com>
 108             Nigel Stephens  <nigel@mips.com>
 109
 110         * interp.c (sim_monitor): Flush stdout and stderr file descriptors
 111         after each call to sim_io_write.
 112
 113 2007-02-19  Thiemo Seufer  <ths@mips.com>
 114             Nigel Stephens  <nigel@mips.com>
 115
 116         * interp.c (ColdReset): Set CP0 Config0 to reflect the address size
 117         supported by this simulator.
 118         (decode_coproc): Recognise additional CP0 Config registers
 119         correctly.
 120
 121 2007-02-19  Thiemo Seufer  <ths@mips.com>
 122             Nigel Stephens  <nigel@mips.com>
 123             David Ung  <davidu@mips.com>
 124
 125         * cp1.c (value_fpr): Don't inherit existing FPR_STATE for
 126         uninterpreted formats. If fmt is one of the uninterpreted types
 127         don't update the FPR_STATE. Handle fmt_uninterpreted_32 like
 128         fmt_word, and fmt_uninterpreted_64 like fmt_long.
 129         (store_fpr): When writing an invalid odd register, set the
 130         matching even register to fmt_unknown, not the following register.
 131         * interp.c (sim_open): If STATE_MEM_SIZE isn't set then set it to
 132         the the memory window at offset 0 set by --memory-size command
 133         line option.
 134         (sim_store_register): Handle storing 4 bytes to an 8 byte floating
 135         point register.
 136         (sim_fetch_register): Likewise for reading 4 bytes from an 8 byte
 137         register.
 138         (sim_monitor): When returning the memory size to the MIPS
 139         application, use the value in STATE_MEM_SIZE, not an arbitrary
 140         hardcoded value.
 141         (cop_lw): Don' mess around with FPR_STATE, just pass
 142         fmt_uninterpreted_32 to StoreFPR.
 143         (cop_sw): Similarly.
 144         (cop_ld): Pass fmt_uninterpreted_64 not fmt_uninterpreted.
 145         (cop_sd): Similarly.
 146         * mips.igen (not_word_value): Single version for mips32, mips64
 147         and mips16.
 148
 149 2007-02-19  Thiemo Seufer <ths@mips.com>
 150             Nigel Stephens  <nigel@mips.com>
 151
 152         * interp.c (MEM_SIZE): Increase default memory size from 2 to 8
 153         MBytes.
 154
 155 2007-02-17  Thiemo Seufer  <ths@mips.com>
 156
 157         * configure.ac (mips*-sde-elf*): Move in front of generic machine
 158         configuration.
 159         * configure: Regenerate.
 160
 161 2007-02-17  Thiemo Seufer  <ths@mips.com>
 162
 163         * configure.ac (mips*-sde-elf*, mipsisa32r2*-*-*, mipsisa64r2*-*-*):
 164         Add mdmx to sim_igen_machine.
 165         (mipsisa64*-*-*): Likewise. Remove dsp.
 166         (mipsisa32*-*-*): Remove dsp.
 167         * configure: Regenerate.
 168
 169 2007-02-13  Thiemo Seufer  <ths@mips.com>
 170
 171         * configure.ac: Add mips*-sde-elf* target.
 172         * configure: Regenerate.
 173
 174 2006-12-21  Hans-Peter Nilsson  <hp@axis.com>
 175
 176         * acconfig.h: Remove.
 177         * config.in, configure: Regenerate.
 178
 179 2006-11-07  Thiemo Seufer  <ths@mips.com>
 180
 181         * dsp.igen (do_w_op): Fix compiler warning.
 182
 183 2006-08-29  Thiemo Seufer  <ths@mips.com>
 184             David Ung  <davidu@mips.com>
 185
 186         * configure.ac (mipsisa32r2*-*-*, mipsisa32*-*-*): Add smartmips to
 187         sim_igen_machine.
 188         * configure: Regenerate.
 189         * mips.igen (model): Add smartmips.
 190         (MADDU): Increment ACX if carry.
 191         (do_mult): Clear ACX.
 192         (ROR,RORV): Add smartmips.
 193         (include): Include smartmips.igen.
 194         * sim-main.h (ACX): Set to REGISTERS[89].
 195         * smartmips.igen: New file.
 196
 197 2006-08-29  Thiemo Seufer  <ths@mips.com>
 198             David Ung  <davidu@mips.com>
 199
 200         * Makefile.in (IGEN_INCLUDE): Add missing includes for m16e.igen and
 201         mips3264r2.igen. Add missing dependency rules.
 202         * m16e.igen: Support for mips16e save/restore instructions.
 203
 204 2006-06-13  Richard Earnshaw  <rearnsha@arm.com>
 205
 206         * configure: Regenerated.
 207
 208 2006-06-05  Daniel Jacobowitz  <dan@codesourcery.com>
 209
 210         * configure: Regenerated.
 211
 212 2006-05-31  Daniel Jacobowitz  <dan@codesourcery.com>
 213
 214         * configure: Regenerated.
 215
 216 2006-05-15 Chao-ying Fu  <fu@mips.com>
 217
 218         * dsp.igen (do_ph_shift, do_w_shra): Fix bugs for rounding instructions.
 219
 220 2006-04-18  Nick Clifton  <nickc@redhat.com>
 221
 222         * dv-tx3904tmr.c (deliver_tx3904tmr_tick): Add missing break
 223         statement.
 224
 225 2006-03-29  Hans-Peter Nilsson  <hp@axis.com>
 226
 227         * configure: Regenerate.
 228
 229 2005-12-14  Chao-ying Fu  <fu@mips.com>
 230
 231         * Makefile.in (SIM_OBJS): Add dsp.o.
 232         (dsp.o): New dependency.
 233         (IGEN_INCLUDE): Add dsp.igen.
 234         * configure.ac (mipsisa32r2*-*-*, mipsisa32*-*-*, mipsisa64r2*-*-*,
 235         mipsisa64*-*-*): Add dsp to sim_igen_machine.
 236         * configure: Regenerate.
 237         * mips.igen: Add dsp model and include dsp.igen.
 238         (MFHI, MFLO, MTHI, MTLO): Remove mips32, mips32r2, mips64, mips64r2,
 239         because these instructions are extended in DSP ASE.
 240         * sim-main.h (LAST_EMBED_REGNUM): Change from 89 to 96 because of
 241         adding 6 DSP accumulator registers and 1 DSP control register.
 242         (AC0LOIDX, AC0HIIDX, AC1LOIDX, AC1HIIDX, AC2LOIDX, AC2HIIDX, AC3LOIDX,
 243         AC3HIIDX, DSPLO, DSPHI, DSPCRIDX, DSPCR, DSPCR_POS_SHIFT,
 244         DSPCR_POS_MASK, DSPCR_POS_SMASK, DSPCR_SCOUNT_SHIFT, DSPCR_SCOUNT_MASK,
 245         DSPCR_SCOUNT_SMASK, DSPCR_CARRY_SHIFT, DSPCR_CARRY_MASK,
 246         DSPCR_CARRY_SMASK, DSPCR_CARRY, DSPCR_EFI_SHIFT, DSPCR_EFI_MASK,
 247         DSPCR_EFI_SMASK, DSPCR_EFI, DSPCR_OUFLAG_SHIFT, DSPCR_OUFLAG_MASK,
 248         DSPCR_OUFLAG_SMASK, DSPCR_OUFLAG4, DSPCR_OUFLAG5, DSPCR_OUFLAG6,
 249         DSPCR_OUFLAG7, DSPCR_CCOND_SHIFT, DSPCR_CCOND_MASK,
 250         DSPCR_CCOND_SMASK): New define.
 251         (DSPLO_REGNUM, DSPHI_REGNUM): New array for DSP accumulators.
 252         * dsp.c, dsp.igen: New files for MIPS DSP ASE.
 253
 254 2005-07-08  Ian Lance Taylor  <ian@airs.com>
 255
 256         * tconfig.in (SIM_QUIET_NAN_NEGATED): Define.
 257
 258 2005-06-16  David Ung  <davidu@mips.com>
 259             Nigel Stephens  <nigel@mips.com>
 260
 261         * mips.igen: New mips16e model and include m16e.igen.
 262         (check_u64): Add mips16e tag.
 263         * m16e.igen: New file for MIPS16e instructions.
 264         * configure.ac (mipsisa32*-*-*, mipsisa32r2*-*-*, mipsisa64*-*-*,
 265         mipsisa64r2*-*-*): Change sim_gen to M16, add mips16 and mips16e
 266         models.
 267         * configure: Regenerate.
 268
 269 2005-05-26  David Ung  <davidu@mips.com>
 270
 271         * mips.igen (mips32r2, mips64r2): New ISA models.  Add new model
 272         tags to all instructions which are applicable to the new ISAs.
 273         (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
 274         vr.igen.
 275         * mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
 276         instructions.
 277         * vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
 278         to mips.igen.
 279         * configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
 280         * configure: Regenerate.
 281
 282 2005-03-23  Mark Kettenis  <kettenis@gnu.org>
 283
 284         * configure: Regenerate.
 285
 286 2005-01-14  Andrew Cagney  <cagney@gnu.org>
 287
 288         * configure.ac: Sinclude aclocal.m4 before common.m4.  Add
 289         explicit call to AC_CONFIG_HEADER.
 290         * configure: Regenerate.
 291
 292 2005-01-12  Andrew Cagney  <cagney@gnu.org>
 293
 294         * configure.ac: Update to use ../common/common.m4.
 295         * configure: Re-generate.
 296
 297 2005-01-11  Andrew Cagney  <cagney@localhost.localdomain>
 298
 299         * configure: Regenerated to track ../common/aclocal.m4 changes.
 300
 301 2005-01-07  Andrew Cagney  <cagney@gnu.org>
 302
 303         * configure.ac: Rename configure.in, require autoconf 2.59.
 304         * configure: Re-generate.
 305
 306 2004-12-08  Hans-Peter Nilsson  <hp@axis.com>
 307
 308         * configure: Regenerate for ../common/aclocal.m4 update.
 309
 310 2004-09-24  Monika Chaddha  <monika@acmet.com>
 311
 312         Committed by Andrew Cagney.
 313         * m16.igen (CMP, CMPI): Fix assembler.
 314
 315 2004-08-18  Chris Demetriou  <cgd@broadcom.com>
 316
 317         * configure.in (mipsisa64sb1*-*-*): Add mips3d to sim_igen_machine.
 318         * configure: Regenerate.
 319
 320 2004-06-25  Chris Demetriou  <cgd@broadcom.com>
 321
 322         * configure.in (sim_m16_machine): Include mipsIII.
 323         * configure: Regenerate.
 324
 325 2004-05-11  Maciej W. Rozycki  <macro@ds2.pg.gda.pl>
 326
 327         * mips/interp.c (decode_coproc): Sign-extend the address retrieved
 328         from COP0_BADVADDR.
 329         * mips/sim-main.h (COP0_BADVADDR): Remove a cast.
 330
 331 2004-04-10  Chris Demetriou  <cgd@broadcom.com>
 332
 333         * sb1.igen (DIV.PS, RECIP.PS, RSQRT.PS, SQRT.PS): New.
 334
 335 2004-04-09  Chris Demetriou  <cgd@broadcom.com>
 336
 337         * mips.igen (check_fmt): Remove.
 338         (ABS.fmt, ADD.fmt, C.cond.fmta, C.cond.fmtb, CEIL.L.fmt, CEIL.W)
 339         (CVT.D.fmt, CVT.L.fmt, CVT.S.fmt, CVT.W.fmt, DIV.fmt, FLOOR.L.fmt)
 340         (FLOOR.W.fmt, MADD.fmt, MOV.fmt, MOVtf.fmt, MOVN.fmt, MOVZ.fmt)
 341         (MSUB.fmt, MUL.fmt, NEG.fmt, NMADD.fmt, NMSUB.fmt, RECIP.fmt)
 342         (ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt, SQRT.fmt, SUB.fmt)
 343         (TRUNC.L.fmt, TRUNC.W): Explicitly specify allowed FPU formats.
 344         (check_fmt_p, CEIL.L.fmt, CEIL.W, DIV.fmt, FLOOR.L.fmt)
 345         (FLOOR.W.fmt, RECIP.fmt, ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt)
 346         (SQRT.fmt, TRUNC.L.fmt, TRUNC.W): Remove all uses of check_fmt.
 347         (C.cnd.fmta): Remove incorrect call to check_fmt_p.
 348
 349 2004-04-09  Chris Demetriou  <cgd@broadcom.com>
 350
 351         * sb1.igen (check_sbx): New function.
 352         (PABSDIFF.fmt, PABSDIFC.fmt, PAVG.fmt): Use check_sbx.
 353
 354 2004-03-29  Chris Demetriou  <cgd@broadcom.com>
 355             Richard Sandiford  <rsandifo@redhat.com>
 356
 357         * sim-main.h (MIPS_MACH_HAS_MT_HILO_HAZARD)
 358         (MIPS_MACH_HAS_MULT_HILO_HAZARD, MIPS_MACH_HAS_DIV_HILO_HAZARD): New.
 359         * mips.igen (check_mt_hilo, check_mult_hilo, check_div_hilo): Provide
 360         separate implementations for mipsIV and mipsV.  Use new macros to
 361         determine whether the restrictions apply.
 362
 363 2004-01-19  Chris Demetriou  <cgd@broadcom.com>
 364
 365         * mips.igen (check_mf_cycles, check_mt_hilo, check_mf_hilo)
 366         (check_mult_hilo): Improve comments.
 367         (check_div_hilo): Likewise.  Also, fork off a new version
 368         to handle mips32/mips64 (since there are no hazards to check
 369         in MIPS32/MIPS64).
 370
 371 2003-06-17  Richard Sandiford  <rsandifo@redhat.com>
 372
 373         * mips.igen (do_dmultx): Fix check for negative operands.
 374
 375 2003-05-16  Ian Lance Taylor  <ian@airs.com>
 376
 377         * Makefile.in (SHELL): Make sure this is defined.
 378         (various): Use $(SHELL) whenever we invoke move-if-change.
 379
 380 2003-05-03  Chris Demetriou  <cgd@broadcom.com>
 381
 382         * cp1.c: Tweak attribution slightly.
 383         * cp1.h: Likewise.
 384         * mdmx.c: Likewise.
 385         * mdmx.igen: Likewise.
 386         * mips3d.igen: Likewise.
 387         * sb1.igen: Likewise.
 388
 389 2003-04-15  Richard Sandiford  <rsandifo@redhat.com>
 390
 391         * vr.igen (do_vr_mul_op): Zero-extend the low 32 bits of
 392         unsigned operands.
 393
 394 2003-02-27  Andrew Cagney  <cagney@redhat.com>
 395
 396         * interp.c (sim_open): Rename _bfd to bfd.
 397         (sim_create_inferior): Ditto.
 398
 399 2003-01-14  Chris Demetriou  <cgd@broadcom.com>
 400
 401         * mips.igen (LUXC1, SUXC1): New, for mipsV and mips64.
 402
 403 2003-01-14  Chris Demetriou  <cgd@broadcom.com>
 404
 405         * mips.igen (EI, DI): Remove.
 406
 407 2003-01-05  Richard Sandiford  <rsandifo@redhat.com>
 408
 409         * Makefile.in (tmp-run-multi): Fix mips16 filter.
 410
 411 2003-01-04  Richard Sandiford  <rsandifo@redhat.com>
 412             Andrew Cagney  <ac131313@redhat.com>
 413             Gavin Romig-Koch  <gavin@redhat.com>
 414             Graydon Hoare  <graydon@redhat.com>
 415             Aldy Hernandez  <aldyh@redhat.com>
 416             Dave Brolley  <brolley@redhat.com>
 417             Chris Demetriou  <cgd@broadcom.com>
 418
 419         * configure.in (mips64vr*): Define TARGET_ENABLE_FR to 1.
 420         (sim_mach_default): New variable.
 421         (mips64vr-*-*, mips64vrel-*-*): New configurations.
 422         Add a new simulator generator, MULTI.
 423         * configure: Regenerate.
 424         * Makefile.in (SIM_MULTI_OBJ, SIM_EXTRA_DISTCLEAN): New variables.
 425         (multi-run.o): New dependency.
 426         (SIM_MULTI_ALL, SIM_MULTI_IGEN_CONFIGS): New variables.
 427         (tmp-mach-multi, tmp-itable-multi, tmp-run-multi): New rules.
 428         (tmp-multi): Combine them.
 429         (BUILT_SRC_FROM_MULTI): New variable.  Depend on tmp-multi.
 430         (clean-extra): Remove sources in BUILT_SRC_FROM_MULTI.
 431         (distclean-extra): New rule.
 432         * sim-main.h: Include bfd.h.
 433         (MIPS_MACH): New macro.
 434         * mips.igen (vr4120, vr5400, vr5500): New models.
 435         (clo, clz, dclo, dclz, madd, maddu, msub, msub, mul): Add *vr5500.
 436         * vr.igen: Replace with new version.
 437
 438 2003-01-04  Chris Demetriou  <cgd@broadcom.com>
 439
 440         * configure.in: Use SIM_AC_OPTION_RESERVED_BITS(1).
 441         * configure: Regenerate.
 442
 443 2002-12-31  Chris Demetriou  <cgd@broadcom.com>
 444
 445         * sim-main.h (check_branch_bug, mark_branch_bug): Remove.
 446         * mips.igen: Remove all invocations of check_branch_bug and
 447         mark_branch_bug.
 448
 449 2002-12-16  Chris Demetriou  <cgd@broadcom.com>
 450
 451         * tconfig.in: Include "gdb/callback.h" and "gdb/remote-sim.h".
 452
 453 2002-07-30  Chris Demetriou  <cgd@broadcom.com>
 454
 455         * mips.igen (do_load_double, do_store_double): New functions.
 456         (LDC1, SDC1): Rename to...
 457         (LDC1b, SDC1b): respectively.
 458         (LDC1a, SDC1a): New instructions for MIPS II and MIPS32 support.
 459
 460 2002-07-29  Michael Snyder  <msnyder@redhat.com>
 461
 462         * cp1.c (fp_recip2): Modify initialization expression so that
 463         GCC will recognize it as constant.
 464
 465 2002-06-18  Chris Demetriou  <cgd@broadcom.com>
 466
 467         * mdmx.c (SD_): Delete.
 468         (Unpredictable): Re-define, for now, to directly invoke
 469         unpredictable_action().
 470         (mdmx_acc_op): Fix error in .ob immediate handling.
 471
 472 2002-06-18  Andrew Cagney  <cagney@redhat.com>
 473
 474         * interp.c (sim_firmware_command): Initialize `address'.
 475
 476 2002-06-16  Andrew Cagney  <ac131313@redhat.com>
 477
 478         * configure: Regenerated to track ../common/aclocal.m4 changes.
 479
 480 2002-06-14  Chris Demetriou  <cgd@broadcom.com>
 481             Ed Satterthwaite  <ehs@broadcom.com>
 482
 483         * mips3d.igen: New file which contains MIPS-3D ASE instructions.
 484         * Makefile.in (IGEN_INCLUDE): Add mips3d.igen.
 485         * mips.igen: Include mips3d.igen.
 486         (mips3d): New model name for MIPS-3D ASE instructions.
 487         (CVT.W.fmt): Don't use this instruction for word (source) format
 488         instructions.
 489         * cp1.c (fp_binary_r, fp_add_r, fp_mul_r, fpu_inv1, fpu_inv1_32)
 490         (fpu_inv1_64, fp_recip1, fp_recip2, fpu_inv_sqrt1, fpu_inv_sqrt1_32)
 491         (fpu_inv_sqrt1_64, fp_rsqrt1, fp_rsqrt2): New functions.
 492         (NR_FRAC_GUARD, IMPLICIT_1): New macros.
 493         * sim-main.h (fmt_pw, CompareAbs, AddR, MultiplyR, Recip1, Recip2)
 494         (RSquareRoot1, RSquareRoot2): New macros.
 495         (fp_add_r, fp_mul_r, fp_recip1, fp_recip2, fp_rsqrt1)
 496         (fp_rsqrt2): New functions.
 497         * configure.in: Add MIPS-3D support to mipsisa64 simulator.
 498         * configure: Regenerate.
 499
 500 2002-06-13  Chris Demetriou  <cgd@broadcom.com>
 501             Ed Satterthwaite  <ehs@broadcom.com>
 502
 503         * cp1.c (FP_PS_upper, FP_PS_lower, FP_PS_cat, FPQNaN_PS): New macros.
 504         (value_fpr, store_fpr, fp_cmp, fp_unary, fp_binary, fp_mac)
 505         (fp_inv_sqrt, fpu_format_name): Add paired-single support.
 506         (convert): Note that this function is not used for paired-single
 507         format conversions.
 508         (ps_lower, ps_upper, pack_ps, convert_ps): New functions.
 509         * mips.igen (FMT, MOVtf.fmt): Add paired-single support.
 510         (check_fmt_p): Enable paired-single support.
 511         (ALNV.PS, CVT.PS.S, CVT.S.PL, CVT.S.PU, PLL.PS, PLU.PS, PUL.PS)
 512         (PUU.PS): New instructions.
 513         (CVT.S.fmt): Don't use this instruction for paired-single format
 514         destinations.
 515         * sim-main.h (FP_formats): New value 'fmt_ps.'
 516         (ps_lower, ps_upper, pack_ps, convert_ps): New prototypes.
 517         (PSLower, PSUpper, PackPS, ConvertPS): New macros.
 518
 519 2002-06-12  Chris Demetriou  <cgd@broadcom.com>
 520
 521         * mips.igen: Fix formatting of function calls in
 522         many FP operations.
 523
 524 2002-06-12  Chris Demetriou  <cgd@broadcom.com>
 525
 526         * mips.igen (MOVN, MOVZ): Trace result.
 527         (TNEI): Print "tnei" as the opcode name in traces.
 528         (CEIL.W): Add disassembly string for traces.
 529         (RSQRT.fmt): Make location of disassembly string consistent
 530         with other instructions.
 531
 532 2002-06-12  Chris Demetriou  <cgd@broadcom.com>
 533
 534         * mips.igen (X): Delete unused function.
 535
 536 2002-06-08  Andrew Cagney  <cagney@redhat.com>
 537
 538         * interp.c: Include "gdb/callback.h" and "gdb/remote-sim.h".
 539
 540 2002-06-07  Chris Demetriou  <cgd@broadcom.com>
 541             Ed Satterthwaite  <ehs@broadcom.com>
 542
 543         * cp1.c (inner_mac, fp_mac, inner_rsqrt, fp_inv_sqrt)
 544         (fp_rsqrt, fp_madd, fp_msub, fp_nmadd, fp_nmsub): New functions.
 545         * sim-main.h (fp_rsqrt, fp_madd, fp_msub, fp_nmadd)
 546         (fp_nmsub): New prototypes.
 547         (RSquareRoot, MultiplyAdd, MultiplySub, NegMultiplyAdd)
 548         (NegMultiplySub): New defines.
 549         * mips.igen (RSQRT.fmt): Use RSquareRoot().
 550         (MADD.D, MADD.S): Replace with...
 551         (MADD.fmt): New instruction.
 552         (MSUB.D, MSUB.S): Replace with...
 553         (MSUB.fmt): New instruction.
 554         (NMADD.D, NMADD.S): Replace with...
 555         (NMADD.fmt): New instruction.
 556         (NMSUB.D, MSUB.S): Replace with...
 557         (NMSUB.fmt): New instruction.
 558
 559 2002-06-07  Chris Demetriou  <cgd@broadcom.com>
 560             Ed Satterthwaite  <ehs@broadcom.com>
 561
 562         * cp1.c: Fix more comment spelling and formatting.
 563         (value_fcr, store_fcr): Use fenr_FS rather than hard-coding value.
 564         (denorm_mode): New function.
 565         (fpu_unary, fpu_binary): Round results after operation, collect
 566         status from rounding operations, and update the FCSR.
 567         (convert): Collect status from integer conversions and rounding
 568         operations, and update the FCSR.  Adjust NaN values that result
 569         from conversions.  Convert to use sim_io_eprintf rather than
 570         fprintf, and remove some debugging code.
 571         * cp1.h (fenr_FS): New define.
 572
 573 2002-06-07  Chris Demetriou  <cgd@broadcom.com>
 574
 575         * cp1.c (convert): Remove unusable debugging code, and move MIPS
 576         rounding mode to sim FP rounding mode flag conversion code into...
 577         (rounding_mode): New function.
 578
 579 2002-06-07  Chris Demetriou  <cgd@broadcom.com>
 580
 581         * cp1.c: Clean up formatting of a few comments.
 582         (value_fpr): Reformat switch statement.
 583
 584 2002-06-06  Chris Demetriou  <cgd@broadcom.com>
 585             Ed Satterthwaite  <ehs@broadcom.com>
 586
 587         * cp1.h: New file.
 588         * sim-main.h: Include cp1.h.
 589         (SETFCC, GETFCC, IR, UF, OF, DX, IO, UO, FP_FLAGS, FP_ENABLE)
 590         (FP_CAUSE, GETFS, FP_RM_NEAREST, FP_RM_TOZERO, FP_RM_TOPINF)
 591         (FP_RM_TOMINF, GETRM): Remove.  Moved to cp1.h.
 592         (FP_FS, FP_MASK_RM, FP_SH_RM, Nan, Less, Equal): Remove.
 593         (value_fcr, store_fcr, test_fcsr, fp_cmp): New prototypes.
 594         (ValueFCR, StoreFCR, TestFCSR, Compare): New macros.
 595         * cp1.c: Don't include sim-fpu.h; already included by
 596         sim-main.h.  Clean up formatting of some comments.
 597         (NaN, Equal, Less): Remove.
 598         (test_fcsr, value_fcr, store_fcr, update_fcsr, fp_test)
 599         (fp_cmp): New functions.
 600         * mips.igen (do_c_cond_fmt): Remove.
 601         (C.cond.fmta, C.cond.fmtb): Replace uses of do_c_cond_fmt_a with
 602         Compare.  Add result tracing.
 603         (CxC1): Remove, replace with...
 604         (CFC1a, CFC1b, CFC1c, CTC1a, CTC1b, CTC1c): New instructions.
 605         (DMxC1): Remove, replace with...
 606         (DMFC1a, DMFC1b, DMTC1a, DMTC1b): New instructions.
 607         (MxC1): Remove, replace with...
 608         (MFC1a, MFC1b, MTC1a, MTC1b): New instructions.
 609
 610 2002-06-04  Chris Demetriou  <cgd@broadcom.com>
 611
 612         * sim-main.h (FGRIDX): Remove, replace all uses with...
 613         (FGR_BASE): New macro.
 614         (FP0_REGNUM, FCRCS_REGNUM, FCRIR_REGNUM): New macros.
 615         (_sim_cpu): Move 'fgr' member to be right before 'fpr_state' member.
 616         (NR_FGR, FGR): Likewise.
 617         * interp.c: Replace all uses of FGRIDX with FGR_BASE.
 618         * mips.igen: Likewise.
 619
 620 2002-06-04  Chris Demetriou  <cgd@broadcom.com>
 621
 622         * cp1.c: Add an FSF Copyright notice to this file.
 623
 624 2002-06-04  Chris Demetriou  <cgd@broadcom.com>
 625             Ed Satterthwaite  <ehs@broadcom.com>
 626
 627         * cp1.c (Infinity): Remove.
 628         * sim-main.h (Infinity): Likewise.
 629
 630         * cp1.c (fp_unary, fp_binary): New functions.
 631         (fp_abs, fp_neg, fp_add, fp_sub, fp_mul, fp_div, fp_recip)
 632         (fp_sqrt): New functions, implemented in terms of the above.
 633         (AbsoluteValue, Negate, Add, Sub, Multiply, Divide)
 634         (Recip, SquareRoot): Remove (replaced by functions above).
 635         * sim-main.h (fp_abs, fp_neg, fp_add, fp_sub, fp_mul, fp_div)
 636         (fp_recip, fp_sqrt): New prototypes.
 637         (AbsoluteValue, Negate, Add, Sub, Multiply, Divide)
 638         (Recip, SquareRoot): Replace prototypes with #defines which
 639         invoke the functions above.
 640
 641 2002-06-03  Chris Demetriou  <cgd@broadcom.com>
 642
 643         * sim-main.h (Nan, Infinity, Less, Equal, AbsoluteValue, Negate)
 644         (Add, Sub, Multiply, Divide, Recip, SquareRoot): Move lower in
 645         file, remove PARAMS from prototypes.
 646         (value_fpr, store_fpr, convert): Likewise.  Use SIM_STATE to provide
 647         simulator state arguments.
 648         (ValueFPR, StoreFPR, Convert): Move lower in file.  Use SIM_ARGS to
 649         pass simulator state arguments.
 650         * cp1.c (SD): Redefine as CPU_STATE(cpu).
 651         (store_fpr, convert): Remove 'sd' argument.
 652         (value_fpr): Likewise.  Convert to use 'SD' instead.
 653
 654 2002-06-03  Chris Demetriou  <cgd@broadcom.com>
 655
 656         * cp1.c (Min, Max): Remove #if 0'd functions.
 657         * sim-main.h (Min, Max): Remove.
 658
 659 2002-06-03  Chris Demetriou  <cgd@broadcom.com>
 660
 661         * cp1.c: fix formatting of switch case and default labels.
 662         * interp.c: Likewise.
 663         * sim-main.c: Likewise.
 664
 665 2002-06-03  Chris Demetriou  <cgd@broadcom.com>
 666
 667         * cp1.c: Clean up comments which describe FP formats.
 668          (FPQNaN_DOUBLE, FPQNaN_LONG): Generate using UNSIGNED64.
 669
 670 2002-06-03  Chris Demetriou  <cgd@broadcom.com>
 671             Ed Satterthwaite  <ehs@broadcom.com>
 672
 673         * configure.in (mipsisa64sb1*-*-*): New target for supporting
 674         Broadcom SiByte SB-1 processor configurations.
 675         * configure: Regenerate.
 676         * sb1.igen: New file.
 677         * mips.igen: Include sb1.igen.
 678         (sb1): New model.
 679         * Makefile.in (IGEN_INCLUDE): Add sb1.igen.
 680         * mdmx.igen: Add "sb1" model to all appropriate functions and
 681         instructions.
 682         * mdmx.c (AbsDiffOB, AvgOB, AccAbsDiffOB): New functions.
 683         (ob_func, ob_acc): Reference the above.
 684         (qh_acc): Adjust to keep the same size as ob_acc.
 685         * sim-main.h (status_SBX, MX_VECT_ABSD, MX_VECT_AVG, MX_AbsDiff)
 686         (MX_Avg, MX_VECT_ABSDA, MX_AbsDiffC): New macros.
 687
 688 2002-06-03  Chris Demetriou  <cgd@broadcom.com>
 689
 690         * Makefile.in (IGEN_INCLUDE): Add mdmx.igen.
 691
 692 2002-06-02  Chris Demetriou  <cgd@broadcom.com>
 693             Ed Satterthwaite  <ehs@broadcom.com>
 694
 695         * mips.igen (mdmx): New (pseudo-)model.
 696         * mdmx.c, mdmx.igen: New files.
 697         * Makefile.in (SIM_OBJS): Add mdmx.o.
 698         * sim-main.h (MDMX_accumulator, MX_fmtsel, signed24, signed48):
 699         New typedefs.
 700         (ACC, MX_Add, MX_AddA, MX_AddL, MX_And, MX_C_EQ, MX_C_LT, MX_Comp)
 701         (MX_FMT_OB, MX_FMT_QH, MX_Max, MX_Min, MX_Msgn, MX_Mul, MX_MulA)
 702         (MX_MulL, MX_MulS, MX_MulSL, MX_Nor, MX_Or, MX_Pick, MX_RAC)
 703         (MX_RAC_H, MX_RAC_L, MX_RAC_M, MX_RNAS, MX_RNAU, MX_RND_AS)
 704         (MX_RND_AU, MX_RND_ES, MX_RND_EU, MX_RND_ZS, MX_RND_ZU, MX_RNES)
 705         (MX_RNEU, MX_RZS, MX_RZU, MX_SHFL, MX_ShiftLeftLogical)
 706         (MX_ShiftRightArith, MX_ShiftRightLogical, MX_Sub, MX_SubA, MX_SubL)
 707         (MX_VECT_ADD, MX_VECT_ADDA, MX_VECT_ADDL, MX_VECT_AND)
 708         (MX_VECT_MAX, MX_VECT_MIN, MX_VECT_MSGN, MX_VECT_MUL, MX_VECT_MULA)
 709         (MX_VECT_MULL, MX_VECT_MULS, MX_VECT_MULSL, MX_VECT_NOR)
 710         (MX_VECT_OR, MX_VECT_SLL, MX_VECT_SRA, MX_VECT_SRL, MX_VECT_SUB)
 711         (MX_VECT_SUBA, MX_VECT_SUBL, MX_VECT_XOR, MX_WACH, MX_WACL, MX_Xor)
 712         (SIM_ARGS, SIM_STATE, UnpredictableResult, fmt_mdmx, ob_fmtsel)
 713         (qh_fmtsel): New macros.
 714         (_sim_cpu): New member "acc".
 715         (mdmx_acc_op, mdmx_cc_op, mdmx_cpr_op, mdmx_pick_op, mdmx_rac_op)
 716         (mdmx_round_op, mdmx_shuffle, mdmx_wach, mdmx_wacl): New functions.
 717
 718 2002-05-01  Chris Demetriou  <cgd@broadcom.com>
 719
 720         * interp.c: Use 'deprecated' rather than 'depreciated.'
 721         * sim-main.h: Likewise.
 722
 723 2002-05-01  Chris Demetriou  <cgd@broadcom.com>
 724
 725         * cp1.c (store_fpr): Remove #ifdef'd out call to UndefinedResult
 726         which wouldn't compile anyway.
 727         * sim-main.h (unpredictable_action): New function prototype.
 728         (Unpredictable): Define to call igen function unpredictable().
 729         (NotWordValue): New macro to call igen function not_word_value().
 730         (UndefinedResult): Remove.
 731         * interp.c (undefined_result): Remove.
 732         (unpredictable_action): New function.
 733         * mips.igen (not_word_value, unpredictable): New functions.
 734         (ADD, ADDI, do_addiu, do_addu, BGEZAL, BGEZALL, BLTZAL, BLTZALL)
 735         (CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, do_mult, do_multu)
 736         (do_sra, do_srav, do_srl, do_srlv, SUB, do_subu): Invoke
 737         NotWordValue() to check for unpredictable inputs, then
 738         Unpredictable() to handle them.
 739
 740 2002-02-24  Chris Demetriou  <cgd@broadcom.com>
 741
 742         * mips.igen: Fix formatting of calls to Unpredictable().
 743
 744 2002-04-20  Andrew Cagney  <ac131313@redhat.com>
 745
 746         * interp.c (sim_open): Revert previous change.
 747
 748 2002-04-18  Alexandre Oliva  <aoliva@redhat.com>
 749
 750         * interp.c (sim_open): Disable chunk of code that wrote code in
 751         vector table entries.
 752
 753 2002-03-19  Chris Demetriou  <cgd@broadcom.com>
 754
 755         * cp1.c (FP_S_s, FP_D_s, FP_S_be, FP_D_be, FP_S_e, FP_D_e, FP_S_f)
 756         (FP_D_f, FP_S_fb, FP_D_fb, FPINF_SINGLE, FPINF_DOUBLE): Remove
 757         unused definitions.
 758
 759 2002-03-19  Chris Demetriou  <cgd@broadcom.com>
 760
 761         * cp1.c: Fix many formatting issues.
 762
 763 2002-03-19  Chris G. Demetriou  <cgd@broadcom.com>
 764
 765         * cp1.c (fpu_format_name): New function to replace...
 766         (DOFMT): This.  Delete, and update all callers.
 767         (fpu_rounding_mode_name): New function to replace...
 768         (RMMODE): This.  Delete, and update all callers.
 769
 770 2002-03-19  Chris G. Demetriou  <cgd@broadcom.com>
 771
 772         * interp.c: Move FPU support routines from here to...
 773         * cp1.c: Here.  New file.
 774         * Makefile.in (SIM_OBJS): Add cp1.o to object list.
 775         (cp1.o): New target.
 776
 777 2002-03-12  Chris Demetriou  <cgd@broadcom.com>
 778
 779         * configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
 780         * mips.igen (mips32, mips64): New models, add to all instructions
 781         and functions as appropriate.
 782         (loadstore_ea, check_u64): New variant for model mips64.
 783         (check_fmt_p): New variant for models mipsV and mips64, remove
 784         mipsV model marking fro other variant.
 785         (SLL) Rename to...
 786         (SLLa) this.
 787         (CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
 788         for mips32 and mips64.
 789         (DCLO, DCLZ): New instructions for mips64.
 790
 791 2002-03-07  Chris Demetriou  <cgd@broadcom.com>
 792
 793         * mips.igen (BREAK, LUI, ORI, SYSCALL, XORI): Print
 794         immediate or code as a hex value with the "%#lx" format.
 795         (ANDI): Likewise, and fix printed instruction name.
 796
 797 2002-03-05  Chris Demetriou  <cgd@broadcom.com>
 798
 799         * sim-main.h (UndefinedResult, Unpredictable): New macros
 800         which currently do nothing.
 801
 802 2002-03-05  Chris Demetriou  <cgd@broadcom.com>
 803
 804         * sim-main.h (status_UX, status_SX, status_KX, status_TS)
 805         (status_PX, status_MX, status_CU0, status_CU1, status_CU2)
 806         (status_CU3): New definitions.
 807
 808         * sim-main.h (ExceptionCause): Add new values for MIPS32
 809         and MIPS64: MDMX, MCheck, CacheErr.  Update comments
 810         for DebugBreakPoint and NMIReset to note their status in
 811         MIPS32 and MIPS64.
 812         (SignalExceptionMDMX, SignalExceptionWatch, SignalExceptionMCheck)
 813         (SignalExceptionCacheErr): New exception macros.
 814
 815 2002-03-05  Chris Demetriou  <cgd@broadcom.com>
 816
 817         * mips.igen (check_fpu): Enable check for coprocessor 1 usability.
 818         * sim-main.h (COP_Usable): Define, but for now coprocessor 1
 819         is always enabled.
 820         (SignalExceptionCoProcessorUnusable): Take as argument the
 821         unusable coprocessor number.
 822
 823 2002-03-05  Chris Demetriou  <cgd@broadcom.com>
 824
 825         * mips.igen: Fix formatting of all SignalException calls.
 826
 827 2002-03-05  Chris Demetriou  <cgd@broadcom.com>
 828
 829         * sim-main.h (SIGNEXTEND): Remove.
 830
 831 2002-03-04  Chris Demetriou  <cgd@broadcom.com>
 832
 833         * mips.igen: Remove gencode comment from top of file, fix
 834         spelling in another comment.
 835
 836 2002-03-04  Chris Demetriou  <cgd@broadcom.com>
 837
 838         * mips.igen (check_fmt, check_fmt_p): New functions to check
 839         whether specific floating point formats are usable.
 840         (ABS.fmt, ADD.fmt, CEIL.L.fmt, CEIL.W, DIV.fmt, FLOOR.L.fmt)
 841         (FLOOR.W.fmt, MOV.fmt, MUL.fmt, NEG.fmt, RECIP.fmt, ROUND.L.fmt)
 842         (ROUND.W.fmt, RSQRT.fmt, SQRT.fmt, SUB.fmt, TRUNC.L.fmt, TRUNC.W):
 843         Use the new functions.
 844         (do_c_cond_fmt): Remove format checks...
 845         (C.cond.fmta, C.cond.fmtb): And move them into all callers.
 846
 847 2002-03-03  Chris Demetriou  <cgd@broadcom.com>
 848
 849         * mips.igen: Fix formatting of check_fpu calls.
 850
 851 2002-03-03  Chris Demetriou  <cgd@broadcom.com>
 852
 853         * mips.igen (FLOOR.L.fmt): Store correct destination register.
 854
 855 2002-03-03  Chris Demetriou  <cgd@broadcom.com>
 856
 857         * mips.igen: Remove whitespace at end of lines.
 858
 859 2002-03-02  Chris Demetriou  <cgd@broadcom.com>
 860
 861         * mips.igen (loadstore_ea): New function to do effective
 862         address calculations.
 863         (do_load, do_load_left, do_load_right, LL, LDD, PREF, do_store,
 864         do_store_left, do_store_right, SC, SCD, PREFX, SWC1, SWXC1,
 865         CACHE): Use loadstore_ea to do effective address computations.
 866
 867 2002-03-02  Chris Demetriou  <cgd@broadcom.com>
 868
 869         * interp.c (load_word): Use EXTEND32 rather than SIGNEXTEND.
 870         * mips.igen (LL, CxC1, MxC1): Likewise.
 871
 872 2002-03-02  Chris Demetriou  <cgd@broadcom.com>
 873
 874         * mips.igen (LL, LLD, PREF, SC, SCD, ABS.fmt, ADD.fmt, CEIL.L.fmt,
 875         CEIL.W, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt, CVT.W.fmt, DIV.fmt,
 876         FLOOR.L.fmt, FLOOR.W.fmt, MADD.D, MADD.S, MOV.fmt, MOVtf.fmt,
 877         MSUB.D, MSUB.S, MUL.fmt, NEG.fmt, NMADD.D, NMADD.S, NMSUB.D,
 878         NMSUB.S, PREFX, RECIP.fmt, ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt,
 879         SQRT.fmt, SUB.fmt, SWC1, SWXC1, TRUNC.L.fmt, TRUNC.W, CACHE):
 880         Don't split opcode fields by hand, use the opcode field values
 881         provided by igen.
 882
 883 2002-03-01  Chris Demetriou  <cgd@broadcom.com>
 884
 885         * mips.igen (do_divu): Fix spacing.
 886
 887         * mips.igen (do_dsllv): Move to be right before DSLLV,
 888         to match the rest of the do_<shift> functions.
 889
 890 2002-03-01  Chris Demetriou  <cgd@broadcom.com>
 891
 892         * mips.igen (do_dsll, do_dsllv, DSLL32, do_dsra, DSRA32, do_dsrl,
 893         DSRL32, do_dsrlv): Trace inputs and results.
 894
 895 2002-03-01  Chris Demetriou  <cgd@broadcom.com>
 896
 897         * mips.igen (CACHE): Provide instruction-printing string.
 898
 899         * interp.c (signal_exception): Comment tokens after #endif.
 900
 901 2002-02-28  Chris Demetriou  <cgd@broadcom.com>
 902
 903         * mips.igen (LWXC1): Mark with filter "64,f", rather than just "32".
 904         (MOVtf, MxC1, MxC1, DMxC1, DMxC1, CxC1, CxC1, SQRT.fmt, MOV.fmt,
 905         NEG.fmt, ROUND.L.fmt, TRUNC.L.fmt, CEIL.L.fmt, FLOOR.L.fmt,
 906         ROUND.W.fmt, TRUNC.W, CEIL.W, FLOOR.W.fmt, RECIP.fmt, RSQRT.fmt,
 907         CVT.S.fmt, CVT.D.fmt, CVT.W.fmt, CVT.L.fmt, MOVtf.fmt, C.cond.fmta,
 908         C.cond.fmtb, SUB.fmt, MUL.fmt, DIV.fmt, MOVZ.fmt, MOVN.fmt, LDXC1,
 909         SWXC1, SDXC1, MSUB.D, MSUB.S, NMADD.S, NMADD.D, NMSUB.S, NMSUB.D,
 910         LWC1, SWC1): Add "f" to filter, since these are FP instructions.
 911
 912 2002-02-28  Chris Demetriou  <cgd@broadcom.com>
 913
 914         * mips.igen (DSRA32, DSRAV): Fix order of arguments in
 915         instruction-printing string.
 916         (LWU): Use '64' as the filter flag.
 917
 918 2002-02-28  Chris Demetriou  <cgd@broadcom.com>
 919
 920         * mips.igen (SDXC1): Fix instruction-printing string.
 921
 922 2002-02-28  Chris Demetriou  <cgd@broadcom.com>
 923
 924         * mips.igen (LDC1, SDC1): Remove mipsI model, and mark with
 925         filter flags "32,f".
 926
 927 2002-02-27  Chris Demetriou  <cgd@broadcom.com>
 928
 929         * mips.igen (PREFX): This is a 64-bit instruction, use '64'
 930         as the filter flag.
 931
 932 2002-02-27  Chris Demetriou  <cgd@broadcom.com>
 933
 934         * mips.igen (PREFX): Tweak instruction opcode fields (i.e.,
 935         add a comma) so that it more closely match the MIPS ISA
 936         documentation opcode partitioning.
 937         (PREF): Put useful names on opcode fields, and include
 938         instruction-printing string.
 939
 940 2002-02-27  Chris Demetriou  <cgd@broadcom.com>
 941
 942         * mips.igen (check_u64): New function which in the future will
 943         check whether 64-bit instructions are usable and signal an
 944         exception if not.  Currently a no-op.
 945         (DADD, DADDI, DADDIU, DADDU, DDIV, DDIVU, DMULT, DMULTU, DSLL,
 946         DSLL32, DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB,
 947         DSUBU, LD, LDL, LDR, LLD, LWU, SCD, SD, SDL, SDR, DMxC1, LDXC1,
 948         LWXC1, SDXC1, SWXC1, DMFC0, DMTC0): Use check_u64.
 949
 950         * mips.igen (check_fpu): New function which in the future will
 951         check whether FPU instructions are usable and signal an exception
 952         if not.  Currently a no-op.
 953         (ABS.fmt, ADD.fmt, BC1a, BC1b, C.cond.fmta, C.cond.fmtb,
 954         CEIL.L.fmt, CEIL.W, CxC1, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt,
 955         CVT.W.fmt, DIV.fmt, DMxC1, DMxC1, FLOOR.L.fmt, FLOOR.W.fmt, LDC1,
 956         LDXC1, LWC1, LWXC1, MADD.D, MADD.S, MxC1, MOV.fmt, MOVtf,
 957         MOVtf.fmt, MOVN.fmt, MOVZ.fmt, MSUB.D, MSUB.S, MUL.fmt, NEG.fmt,
 958         NMADD.D, NMADD.S, NMSUB.D, NMSUB.S, RECIP.fmt, ROUND.L.fmt,
 959         ROUND.W.fmt, RSQRT.fmt, SDC1, SDXC1, SQRT.fmt, SUB.fmt, SWC1,
 960         SWXC1, TRUNC.L.fmt, TRUNC.W): Use check_fpu.
 961
 962 2002-02-27  Chris Demetriou  <cgd@broadcom.com>
 963
 964         * mips.igen (do_load_left, do_load_right): Move to be immediately
 965         following do_load.
 966         (do_store_left, do_store_right): Move to be immediately following
 967         do_store.
 968
 969 2002-02-27  Chris Demetriou  <cgd@broadcom.com>
 970
 971         * mips.igen (mipsV): New model name.  Also, add it to
 972         all instructions and functions where it is appropriate.
 973
 974 2002-02-18  Chris Demetriou  <cgd@broadcom.com>
 975
 976         * mips.igen: For all functions and instructions, list model
 977         names that support that instruction one per line.
 978
 979 2002-02-11  Chris Demetriou  <cgd@broadcom.com>
 980
 981         * mips.igen: Add some additional comments about supported
 982         models, and about which instructions go where.
 983         (BC1b, MFC0, MTC0, RFE): Sort supported models in the same
 984         order as is used in the rest of the file.
 985
 986 2002-02-11  Chris Demetriou  <cgd@broadcom.com>
 987
 988         * mips.igen (ADD, ADDI, DADDI, DSUB, SUB): Add comment
 989         indicating that ALU32_END or ALU64_END are there to check
 990         for overflow.
 991         (DADD): Likewise, but also remove previous comment about
 992         overflow checking.
 993
 994 2002-02-10  Chris Demetriou  <cgd@broadcom.com>
 995
 996         * mips.igen (DDIV, DIV, DIVU, DMULT, DMULTU, DSLL, DSLL32,
 997         DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB, DSUBU,
 998         JALR, JR, MOVN, MOVZ, MTLO, MULT, MULTU, SLL, SLLV, SLT, SLTU,
 999         SRAV, SRLV, SUB, SUBU, SYNC, XOR, MOVtf, DI, DMFC0, DMTC0, EI,
1000         ERET, RFE, TLBP, TLBR, TLBWI, TLBWR): Tweak instruction opcode
1001         fields (i.e., add and move commas) so that they more closely
1002         match the MIPS ISA documentation opcode partitioning.
1003
1004 2002-02-10  Chris Demetriou  <cgd@broadcom.com>
1005
1006         * mips.igen (ADDI): Print immediate value.
1007         (BREAK): Print code.
1008         (DADDIU, DSRAV, DSRLV): Print correct instruction name.
1009         (SLL): Print "nop" specially, and don't run the code
1010         that does the shift for the "nop" case.
1011
1012 2001-11-17  Fred Fish  <fnf@redhat.com>
1013
1014         * sim-main.h (float_operation): Move enum declaration outside
1015         of _sim_cpu struct declaration.
1016
1017 2001-04-12  Jim Blandy  <jimb@redhat.com>
1018
1019         * mips.igen (CFC1, CTC1): Pass the correct register numbers to
1020         PENDING_FILL.  Use PENDING_SCHED directly to handle the pending
1021         set of the FCSR.
1022         * sim-main.h (COCIDX): Remove definition; this isn't supported by
1023         PENDING_FILL, and you can get the intended effect gracefully by
1024         calling PENDING_SCHED directly.
1025
1026 2001-02-23  Ben Elliston  <bje@redhat.com>
1027
1028         * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Only define if not
1029         already defined elsewhere.
1030
1031 2001-02-19  Ben Elliston  <bje@redhat.com>
1032
1033         * sim-main.h (sim_monitor): Return an int.
1034         * interp.c (sim_monitor): Add return values.
1035         (signal_exception): Handle error conditions from sim_monitor.
1036
1037 2001-02-08  Ben Elliston  <bje@redhat.com>
1038
1039         * sim-main.c (load_memory): Pass cia to sim_core_read* functions.
1040         (store_memory): Likewise, pass cia to sim_core_write*.
1041
1042 2000-10-19  Frank Ch. Eigler  <fche@redhat.com>
1043
1044         On advice from Chris G. Demetriou <cgd@sibyte.com>:
1045         * sim-main.h (GPR_CLEAR): Remove unused alternative macro.
1046
1047 Thu Jul 27 22:02:05 2000  Andrew Cagney  <cagney@b1.cygnus.com>
1048
1049         From Maciej W. Rozycki <macro@ds2.pg.gda.pl>:
1050         * Makefile.in: Don't delete *.igen when cleaning directory.
1051
1052 Wed Jul 19 18:50:51 2000  Andrew Cagney  <cagney@b1.cygnus.com>
1053
1054         * m16.igen (break): Call SignalException not sim_engine_halt.
1055
1056 Mon Jul  3 11:13:20 2000  Andrew Cagney  <cagney@b1.cygnus.com>
1057
1058         From Jason Eckhardt:
1059         * mips.igen (MOVZ.fmt, MOVN.fmt): Move conditional on GPR[RT].
1060
1061 Tue Jun 13 20:52:07 2000  Andrew Cagney  <cagney@b1.cygnus.com>
1062
1063         * mips.igen (MxC1, DMxC1): Fix printf formatting.
1064
1065 2000-05-24  Michael Hayes  <mhayes@cygnus.com>
1066
1067         * mips.igen (do_dmultx): Fix typo.
1068
1069 Tue May 23 21:39:23 2000  Andrew Cagney  <cagney@b1.cygnus.com>
1070
1071         * configure: Regenerated to track ../common/aclocal.m4 changes.
1072
1073 Fri Apr 28 20:48:36 2000  Andrew Cagney  <cagney@b1.cygnus.com>
1074
1075         * mips.igen (DMxC1): Fix format arguments for sim_io_eprintf call.
1076
1077 2000-04-12  Frank Ch. Eigler  <fche@redhat.com>
1078
1079         * sim-main.h (GPR_CLEAR): Define macro.
1080
1081 Mon Apr 10 00:07:09 2000  Andrew Cagney  <cagney@b1.cygnus.com>
1082
1083         * interp.c (decode_coproc): Output long using %lx and not %s.
1084
1085 2000-03-21  Frank Ch. Eigler  <fche@redhat.com>
1086
1087         * interp.c (sim_open): Sort & extend dummy memory regions for
1088         --board=jmr3904 for eCos.
1089
1090 2000-03-02  Frank Ch. Eigler  <fche@redhat.com>
1091
1092         * configure: Regenerated.
1093
1094 Tue Feb  8 18:35:01 2000  Donald Lindsay  <dlindsay@hound.cygnus.com>
1095
1096         * interp.c, mips.igen: all 5 DEADC0DE situations now have sim_io_eprintf
1097         calls, conditional on the simulator being in verbose mode.
1098
1099 Fri Feb  4 09:45:15 2000  Donald Lindsay  <dlindsay@cygnus.com>
1100
1101         * sim-main.c (cache_op): Added case arm so that CACHE ops to a secondary
1102         cache don't get ReservedInstruction traps.
1103
1104 1999-11-29  Mark Salter  <msalter@cygnus.com>
1105
1106         * dv-tx3904sio.c (tx3904sio_io_write_buffer): Use write value as a mask
1107         to clear status bits in sdisr register. This is how the hardware works.
1108
1109         * interp.c (sim_open): Added more memory aliases for jmr3904 hardware
1110         being used by cygmon.
1111
1112 1999-11-11  Andrew Haley  <aph@cygnus.com>
1113
1114         * interp.c (decode_coproc): Correctly handle DMFC0 and DMTC0
1115         instructions.
1116
1117 Thu Sep  9 15:12:08 1999  Geoffrey Keating  <geoffk@cygnus.com>
1118
1119         * mips.igen (MULT): Correct previous mis-applied patch.
1120
1121 Tue Sep  7 13:34:54 1999  Geoffrey Keating  <geoffk@cygnus.com>
1122
1123         * mips.igen (delayslot32): Handle sequence like
1124         mtc1 $at,$f12 ; jal fp_add ; mov.s $f13,$f12
1125         correctly by calling ENGINE_ISSUE_PREFIX_HOOK() before issue.
1126         (MULT): Actually pass the third register...
1127
1128 1999-09-03  Mark Salter  <msalter@cygnus.com>
1129
1130         * interp.c (sim_open): Added more memory aliases for additional
1131         hardware being touched by cygmon on jmr3904 board.
1132
1133 Thu Sep  2 18:15:53 1999  Andrew Cagney  <cagney@b1.cygnus.com>
1134
1135         * configure: Regenerated to track ../common/aclocal.m4 changes.
1136
1137 Tue Jul 27 16:36:51 1999  Andrew Cagney  <cagney@amy.cygnus.com>
1138
1139         * interp.c (sim_store_register): Handle case where client - GDB -
1140         specifies that a 4 byte register is 8 bytes in size.
1141         (sim_fetch_register): Ditto.
1142
1143 1999-07-14  Frank Ch. Eigler  <fche@cygnus.com>
1144
1145         Implement "sim firmware" option, inspired by jimb's version of 1998-01.
1146         * interp.c (firmware_option_p): New global flag: "sim firmware" given.
1147         (idt_monitor_base): Base address for IDT monitor traps.
1148         (pmon_monitor_base): Ditto for PMON.
1149         (lsipmon_monitor_base): Ditto for LSI PMON.
1150         (MONITOR_BASE, MONITOR_SIZE): Removed macros.
1151         (mips_option): Add "firmware" option with new OPTION_FIRMWARE key.
1152         (sim_firmware_command): New function.
1153         (mips_option_handler): Call it for OPTION_FIRMWARE.
1154         (sim_open): Allocate memory for idt_monitor region.  If "--board"
1155         option was given, add no monitor by default.  Add BREAK hooks only if
1156         monitors are also there.
1157
1158 Mon Jul 12 00:02:27 1999  Andrew Cagney  <cagney@amy.cygnus.com>
1159
1160         * interp.c (sim_monitor): Flush output before reading input.
1161
1162 Sun Jul 11 19:28:11 1999  Andrew Cagney  <cagney@b1.cygnus.com>
1163
1164         * tconfig.in (SIM_HANDLES_LMA): Always define.
1165
1166 Thu Jul  8 16:06:59 1999  Andrew Cagney  <cagney@b1.cygnus.com>
1167
1168         From Mark Salter <msalter@cygnus.com>:
1169         * interp.c (BOARD_BSP): Define.  Add to list of possible boards.
1170         (sim_open): Add setup for BSP board.
1171
1172 Wed Jul  7 12:45:58 1999  Andrew Cagney  <cagney@b1.cygnus.com>
1173
1174         * mips.igen (MULT, MULTU): Add syntax for two operand version.
1175         (DMFC0, DMTC0): Recognize.  Call DecodeCoproc which will report
1176         them as unimplemented.
1177
1178 1999-05-08  Felix Lee  <flee@cygnus.com>
1179
1180         * configure: Regenerated to track ../common/aclocal.m4 changes.
1181
1182 1999-04-21  Frank Ch. Eigler  <fche@cygnus.com>
1183
1184         * mips.igen (bc0f): For the TX39 only, decode this as a no-op stub.
1185
1186 Thu Apr 15 14:15:17 1999  Andrew Cagney  <cagney@amy.cygnus.com>
1187
1188         * configure.in: Any mips64vr5*-*-* target should have
1189         -DTARGET_ENABLE_FR=1.
1190         (default_endian): Any mips64vr*el-*-* target should default to
1191         LITTLE_ENDIAN.
1192         * configure: Re-generate.
1193
1194 1999-02-19  Gavin Romig-Koch  <gavin@cygnus.com>
1195
1196         * mips.igen (ldl): Extend from _16_, not 32.
1197
1198 Wed Jan 27 18:51:38 1999  Andrew Cagney  <cagney@chook.cygnus.com>
1199
1200         * interp.c (sim_store_register): Force registers written to by GDB
1201         into an un-interpreted state.
1202
1203 1999-02-05  Frank Ch. Eigler  <fche@cygnus.com>
1204
1205         * dv-tx3904sio.c (tx3904sio_tickle): After a polled I/O from the
1206         CPU, start periodic background I/O polls.
1207         (tx3904sio_poll): New function: periodic I/O poller.
1208
1209 1998-12-30  Frank Ch. Eigler  <fche@cygnus.com>
1210
1211         * mips.igen (BREAK): Call signal_exception instead of sim_engine_halt.
1212
1213 Tue Dec 29 16:03:53 1998  Rainer Orth  <ro@TechFak.Uni-Bielefeld.DE>
1214
1215         * configure.in, configure (mips64vr5*-*-*): Added missing ;; in
1216         case statement.
1217
1218 1998-12-29  Frank Ch. Eigler  <fche@cygnus.com>
1219
1220         * interp.c (sim_open): Allocate jm3904 memory in smaller chunks.
1221         (load_word): Call SIM_CORE_SIGNAL hook on error.
1222         (signal_exception): Call SIM_CPU_EXCEPTION_TRIGGER hook before
1223         starting.  For exception dispatching, pass PC instead of NULL_CIA.
1224         (decode_coproc): Use COP0_BADVADDR to store faulting address.
1225         * sim-main.h (COP0_BADVADDR): Define.
1226         (SIM_CORE_SIGNAL): Define hook to call mips_core_signal.
1227         (SIM_CPU_EXCEPTION*): Define hooks to call mips_cpu_exception*().
1228         (_sim_cpu): Add exc_* fields to store register value snapshots.
1229         * mips.igen (*): Replace memory-related SignalException* calls
1230         with references to SIM_CORE_SIGNAL hook.
1231
1232         * dv-tx3904irc.c (tx3904irc_port_event): printf format warning
1233         fix.
1234         * sim-main.c (*): Minor warning cleanups.
1235
1236 1998-12-24  Gavin Romig-Koch  <gavin@cygnus.com>
1237
1238         * m16.igen (DADDIU5): Correct type-o.
1239
1240 Mon Dec 21 10:34:48 1998  Andrew Cagney  <cagney@chook>
1241
1242         * mips.igen (do_ddiv, do_ddivu): Pacify GCC. Update hi/lo via tmp
1243         variables.
1244
1245 Wed Dec 16 18:20:28 1998  Andrew Cagney  <cagney@chook>
1246
1247         * Makefile.in (SIM_EXTRA_CFLAGS): No longer need to add .../newlib
1248         to include path.
1249         (interp.o): Add dependency on itable.h
1250         (oengine.c, gencode): Delete remaining references.
1251         (BUILT_SRC_FROM_GEN): Clean up.
1252
1253 1998-12-16  Gavin Romig-Koch  <gavin@cygnus.com>
1254
1255         * vr4run.c: New.
1256         * Makefile.in (SIM_HACK_OBJ,HACK_OBJS,HACK_GEN_SRCS,libhack.a,
1257         tmp-hack,tmp-m32-hack,tmp-m16-hack,tmp-itable-hack,
1258         tmp-run-hack) : New.
1259         * m16.igen (LD,DADDIU,DADDUI5,DADJSP,DADDIUSP,DADDI,DADDU,DSUBU,
1260         DSLL,DSRL,DSRA,DSLLV,DSRAV,DMULT,DMULTU,DDIV,DDIVU,JALX32,JALX):
1261         Drop the "64" qualifier to get the HACK generator working.
1262         Use IMMEDIATE rather than IMMED.  Use SHAMT rather than SHIFT.
1263         * mips.igen (do_daddiu,do_ddiv,do_divu): Remove the 64-only
1264         qualifier to get the hack generator working.
1265         (do_dsll,do_dsllv,do_dsra,do_dsrl,do_dsrlv): New.
1266         (DSLL): Use do_dsll.
1267         (DSLLV): Use do_dsllv.
1268         (DSRA): Use do_dsra.
1269         (DSRL): Use do_dsrl.
1270         (DSRLV): Use do_dsrlv.
1271         (BC1): Move *vr4100 to get the HACK generator working.
1272         (CxC1, DMxC1, MxC1,MACCU,MACCHI,MACCHIU): Rename to
1273         get the HACK generator working.
1274         (MACC) Rename to get the HACK generator working.
1275         (DMACC,MACCS,DMACCS): Add the 64.
1276
1277 1998-12-12  Gavin Romig-Koch  <gavin@cygnus.com>
1278
1279         * mips.igen (BC1): Renamed to BC1a and BC1b to avoid conflicts.
1280         * sim-main.h (SizeFGR): Handle TARGET_ENABLE_FR.
1281
1282 1998-12-11  Gavin Romig-Koch  <gavin@cygnus.com>
1283
1284     * mips/interp.c (DEBUG): Cleanups.
1285
1286 1998-12-10  Frank Ch. Eigler  <fche@cygnus.com>
1287
1288         * dv-tx3904sio.c (tx3904sio_io_read_buffer): Endianness fixes.
1289         (tx3904sio_tickle): fflush after a stdout character output.
1290
1291 1998-12-03  Frank Ch. Eigler  <fche@cygnus.com>
1292
1293         * interp.c (sim_close): Uninstall modules.
1294
1295 Wed Nov 25 13:41:03 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1296
1297         * sim-main.h, interp.c (sim_monitor): Change to global
1298         function.
1299
1300 Wed Nov 25 17:33:24 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1301
1302         * configure.in (vr4100): Only include vr4100 instructions in
1303         simulator.
1304         * configure: Re-generate.
1305         * m16.igen (*): Tag all mips16 instructions as also being vr4100.
1306
1307 Mon Nov 23 18:20:36 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1308
1309         * Makefile.in (SIM_CFLAGS): Do not define WITH_IGEN.
1310         * sim-main.h, sim-main.c, interp.c: Delete #if WITH_IGEN keeping
1311         true alternative.
1312
1313         * configure.in (sim_default_gen, sim_use_gen): Replace with
1314         sim_gen.
1315         (--enable-sim-igen): Delete config option. Always using IGEN.
1316         * configure: Re-generate.
1317
1318         * Makefile.in (gencode): Kill, kill, kill.
1319         * gencode.c: Ditto.
1320
1321 Mon Nov 23 18:07:36 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1322
1323         * configure.in: Configure mips64vr4100-elf nee mips64vr41* as a 64
1324         bit mips16 igen simulator.
1325         * configure: Re-generate.
1326
1327         * mips.igen (check_div_hilo, check_mult_hilo, check_mf_hilo): Mark
1328         as part of vr4100 ISA.
1329         * vr.igen: Mark all instructions as 64 bit only.
1330
1331 Mon Nov 23 17:07:37 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1332
1333         * interp.c (get_cell, sim_monitor, fetch_str, CoProcPresent):
1334         Pacify GCC.
1335
1336 Mon Nov 23 13:23:40 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1337
1338         * configure.in: Configure mips-lsi-elf nee mips*lsi* as a
1339         mipsIII/mips16 igen simulator.  Fix sim_gen VS sim_igen typos.
1340         * configure: Re-generate.
1341
1342         * m16.igen (BREAK): Define breakpoint instruction.
1343         (JALX32): Mark instruction as mips16 and not r3900.
1344         * mips.igen (C.cond.fmt): Fix typo in instruction format.
1345
1346         * sim-main.h (PENDING_FILL): Wrap C statements in do/while.
1347
1348 Sat Nov  7 09:54:38 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1349
1350         * gencode.c (build_instruction - BREAK): For MIPS16, handle BREAK
1351         insn as a debug breakpoint.
1352
1353         * sim-main.h (PENDING_SLOT_BIT): Fix, was incorrectly defined as
1354         pending.slot_size.
1355         (PENDING_SCHED): Clean up trace statement.
1356         (PENDING_SCHED): Increment PENDING_IN and PENDING_TOTAL.
1357         (PENDING_FILL): Delay write by only one cycle.
1358         (PENDING_FILL): For FSRs, write fmt_uninterpreted to FPR_STATE.
1359
1360         * sim-main.c (pending_tick): Clean up trace statements. Add trace
1361         of pending writes.
1362         (pending_tick): Fix sizes in switch statements, 4 & 8 instead of
1363         32 & 64.
1364         (pending_tick): Move incrementing of index to FOR statement.
1365         (pending_tick): Only update PENDING_OUT after a write has occured.
1366
1367         * configure.in: Add explicit mips-lsi-* target.  Use gencode to
1368         build simulator.
1369         * configure: Re-generate.
1370
1371         * interp.c (sim_engine_run OLD): Delete explicit call to
1372         PENDING_TICK. Now called via ENGINE_ISSUE_PREFIX_HOOK.
1373
1374 Sat Oct 30 09:49:10 1998  Frank Ch. Eigler  <fche@cygnus.com>
1375
1376         * dv-tx3904cpu.c (deliver_tx3904cpu_interrupt): Add dummy
1377         interrupt level number to match changed SignalExceptionInterrupt
1378         macro.
1379
1380 Fri Oct  9 18:02:25 1998  Doug Evans  <devans@canuck.cygnus.com>
1381
1382         * interp.c: #include "itable.h" if WITH_IGEN.
1383         (get_insn_name): New function.
1384         (sim_open): Initialize CPU_INSN_NAME,CPU_MAX_INSNS.
1385         * sim-main.h (MAX_INSNS,INSN_NAME): Delete.
1386
1387 Mon Sep 14 12:36:44 1998  Frank Ch. Eigler  <fche@cygnus.com>
1388
1389         * configure: Rebuilt to inhale new common/aclocal.m4.
1390
1391 Tue Sep  1 15:39:18 1998  Frank Ch. Eigler  <fche@cygnus.com>
1392
1393         * dv-tx3904sio.c: Include sim-assert.h.
1394
1395 Tue Aug 25 12:49:46 1998  Frank Ch. Eigler  <fche@cygnus.com>
1396
1397         * dv-tx3904sio.c: New file: tx3904 serial I/O module.
1398         * configure.in: Add dv-tx3904sio, dv-sockser for tx39 target.
1399         Reorganize target-specific sim-hardware checks.
1400         * configure: rebuilt.
1401         * interp.c (sim_open): For tx39 target boards, set
1402         OPERATING_ENVIRONMENT, add tx3904sio devices.
1403         * tconfig.in: For tx39 target, set SIM_HANDLES_LMA for loading
1404         ROM executables.  Install dv-sockser into sim-modules list.
1405
1406         * dv-tx3904irc.c: Compiler warning clean-up.
1407         * dv-tx3904tmr.c: Compiler warning clean-up.  Remove particularly
1408         frequent hw-trace messages.
1409
1410 Fri Jul 31 18:14:16 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1411
1412         * vr.igen (MulAcc): Identify as a vr4100 specific function.
1413
1414 Sat Jul 25 16:03:14 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1415
1416         * Makefile.in (IGEN_INCLUDE): Add vr.igen.
1417
1418         * vr.igen: New file.
1419         (MAC/MADD16, DMAC/DMADD16): Implement using code from gencode.c.
1420         * mips.igen: Define vr4100 model. Include vr.igen.
1421 Mon Jun 29 09:21:07 1998  Gavin Koch  <gavin@cygnus.com>
1422
1423         * mips.igen (check_mf_hilo): Correct check.
1424
1425 Wed Jun 17 12:20:49 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1426
1427         * sim-main.h (interrupt_event): Add prototype.
1428
1429         * dv-tx3904tmr.c (tx3904tmr_io_write_buffer): Delete unused
1430         register_ptr, register_value.
1431         (deliver_tx3904tmr_tick): Fix types passed to printf fmt.
1432
1433         * sim-main.h (tracefh): Make extern.
1434
1435 Tue Jun 16 14:39:00 1998  Frank Ch. Eigler  <fche@cygnus.com>
1436
1437         * dv-tx3904tmr.c: Deschedule timer event after dispatching.
1438         Reduce unnecessarily high timer event frequency.
1439         * dv-tx3904cpu.c: Ditto for interrupt event.
1440
1441 Wed Jun 10 13:22:32 1998  Frank Ch. Eigler  <fche@cygnus.com>
1442
1443         * interp.c (decode_coproc): For TX39, add stub COP0 register #7,
1444         to allay warnings.
1445         (interrupt_event): Made non-static.
1446
1447         * dv-tx3904tmr.c (deliver_tx3904tmr_tick): Correct accidental
1448         interchange of configuration values for external vs. internal
1449         clock dividers.
1450
1451 Tue Jun  9 12:46:24 1998  Ian Carmichael  <iancarm@cygnus.com>
1452
1453         * mips.igen (BREAK): Moved code to here for
1454         simulator-reserved break instructions.
1455         * gencode.c (build_instruction): Ditto.
1456         * interp.c (signal_exception): Code moved from here.  Non-
1457         reserved instructions now use exception vector, rather
1458         than halting sim.
1459         * sim-main.h: Moved magic constants to here.
1460
1461 Tue Jun  9 12:29:50 1998  Frank Ch. Eigler  <fche@cygnus.com>
1462
1463         * dv-tx3904cpu.c (deliver_*_interrupt,*_port_event): Set the CAUSE
1464         register upon non-zero interrupt event level, clear upon zero
1465         event value.
1466         * dv-tx3904irc.c (*_port_event): Handle deactivated interrupt signal
1467         by passing zero event value.
1468         (*_io_{read,write}_buffer): Endianness fixes.
1469         * dv-tx3904tmr.c (*_io_{read,write}_buffer): Endianness fixes.
1470         (deliver_*_tick): Reduce sim event interval to 75% of count interval.
1471
1472         * interp.c (sim_open): Added jmr3904pal board type that adds PAL-based
1473         serial I/O and timer module at base address 0xFFFF0000.
1474
1475 Tue Jun  9 11:52:29 1998  Gavin Koch  <gavin@cygnus.com>
1476
1477         * mips.igen (SWC1) : Correct the handling of ReverseEndian
1478         and BigEndianCPU.
1479
1480 Tue Jun  9 11:40:57 1998  Gavin Koch  <gavin@cygnus.com>
1481
1482         * configure.in (mips_fpu_bitsize) : Set this correctly for 32-bit mips
1483         parts.
1484         * configure: Update.
1485
1486 Thu Jun  4 15:37:33 1998  Frank Ch. Eigler  <fche@cygnus.com>
1487
1488         * dv-tx3904tmr.c: New file - implements tx3904 timer.
1489         * dv-tx3904{irc,cpu}.c: Mild reformatting.
1490         * configure.in: Include tx3904tmr in hw_device list.
1491         * configure: Rebuilt.
1492         * interp.c (sim_open): Instantiate three timer instances.
1493         Fix address typo of tx3904irc instance.
1494
1495 Tue Jun  2 15:48:02 1998  Ian Carmichael  <iancarm@cygnus.com>
1496
1497         * interp.c (signal_exception): SystemCall exception now uses
1498         the exception vector.
1499
1500 Mon Jun  1 18:18:26 1998  Frank Ch. Eigler  <fche@cygnus.com>
1501
1502         * interp.c (decode_coproc): For TX39, add stub COP0 register #3,
1503         to allay warnings.
1504
1505 Fri May 29 11:40:39 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1506
1507         * configure.in (sim_igen_filter): Match mips*tx39 not mipst*tx39.
1508
1509 Mon May 25 20:47:45 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1510
1511         * dv-tx3904cpu.c, dv-tx3904irc.c: Rename *_callback to *_method.
1512
1513         * dv-tx3904cpu.c, dv-tx3904irc.c: Include hw-main.h and
1514         sim-main.h. Declare a struct hw_descriptor instead of struct
1515         hw_device_descriptor.
1516
1517 Mon May 25 12:41:38 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1518
1519         * mips.igen (do_store_left, do_load_left): Compute nr of left and
1520         right bits and then re-align left hand bytes to correct byte
1521         lanes.  Fix incorrect computation in do_store_left when loading
1522         bytes from second word.
1523
1524 Fri May 22 13:34:20 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1525
1526         * configure.in (SIM_AC_OPTION_HARDWARE): Only enable when tx3904.
1527         * interp.c (sim_open): Only create a device tree when HW is
1528         enabled.
1529
1530         * dv-tx3904irc.c (tx3904irc_finish): Pacify GCC.
1531         * interp.c (signal_exception): Ditto.
1532
1533 Thu May 21 14:24:11 1998  Gavin Koch  <gavin@cygnus.com>
1534
1535         * gencode.c: Mark BEGEZALL as LIKELY.
1536
1537 Thu May 21 18:57:19 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1538
1539         * sim-main.h (ALU32_END): Sign extend 32 bit results.
1540         * mips.igen (ADD, SUB, ADDI, DADD, DSUB): Trace.
1541
1542 Mon May 18 18:22:42 1998  Frank Ch. Eigler  <fche@cygnus.com>
1543
1544         * configure.in (SIM_AC_OPTION_HARDWARE): Added common hardware
1545         modules.  Recognize TX39 target with "mips*tx39" pattern.
1546         * configure: Rebuilt.
1547         * sim-main.h (*): Added many macros defining bits in
1548         TX39 control registers.
1549         (SignalInterrupt): Send actual PC instead of NULL.
1550         (SignalNMIReset): New exception type.
1551         * interp.c (board): New variable for future use to identify
1552         a particular board being simulated.
1553         (mips_option_handler,mips_options): Added "--board" option.
1554         (interrupt_event): Send actual PC.
1555         (sim_open): Make memory layout conditional on board setting.
1556         (signal_exception): Initial implementation of hardware interrupt
1557         handling.  Accept another break instruction variant for simulator
1558         exit.
1559         (decode_coproc): Implement RFE instruction for TX39.
1560         (mips.igen): Decode RFE instruction as such.
1561         * configure.in (tx3904cpu,tx3904irc): Added devices for tx3904.
1562         * interp.c: Define "jmr3904" and "jmr3904debug" board types and
1563         bbegin to implement memory map.
1564         * dv-tx3904cpu.c: New file.
1565         * dv-tx3904irc.c: New file.
1566
1567 Wed May 13 14:40:11 1998  Gavin Koch  <gavin@cygnus.com>
1568
1569         * mips.igen (check_mt_hilo): Create a separate r3900 version.
1570
1571 Wed May 13 14:11:46 1998  Gavin Koch  <gavin@cygnus.com>
1572
1573         * tx.igen (madd,maddu):  Replace calls to check_op_hilo
1574         with calls to check_div_hilo.
1575
1576 Wed May 13 09:59:27 1998  Gavin Koch  <gavin@cygnus.com>
1577
1578         * mips/mips.igen (check_op_hilo,check_mult_hilo,check_div_hilo):
1579         Replace check_op_hilo with check_mult_hilo and check_div_hilo.
1580         Add special r3900 version of do_mult_hilo.
1581         (do_dmultx,do_mult,do_multu): Replace calls to check_op_hilo
1582         with calls to check_mult_hilo.
1583         (do_ddiv,do_ddivu,do_div,do_divu): Replace calls to check_op_hilo
1584         with calls to check_div_hilo.
1585
1586 Tue May 12 15:22:11 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1587
1588         * configure.in (SUBTARGET_R3900): Define for mipstx39 target.
1589         Document a replacement.
1590
1591 Fri May  8 17:48:19 1998  Ian Carmichael  <iancarm@cygnus.com>
1592
1593         * interp.c (sim_monitor): Make mon_printf work.
1594
1595 Wed May  6 19:42:19 1998  Doug Evans  <devans@canuck.cygnus.com>
1596
1597         * sim-main.h (INSN_NAME): New arg `cpu'.
1598
1599 Tue Apr 28 18:33:31 1998  Geoffrey Noer  <noer@cygnus.com>
1600
1601         * configure: Regenerated to track ../common/aclocal.m4 changes.
1602
1603 Sun Apr 26 15:31:55 1998  Tom Tromey  <tromey@creche>
1604
1605         * configure: Regenerated to track ../common/aclocal.m4 changes.
1606         * config.in: Ditto.
1607
1608 Sun Apr 26 15:20:01 1998  Tom Tromey  <tromey@cygnus.com>
1609
1610         * acconfig.h: New file.
1611         * configure.in: Reverted change of Apr 24; use sinclude again.
1612
1613 Fri Apr 24 14:16:40 1998  Tom Tromey  <tromey@creche>
1614
1615         * configure: Regenerated to track ../common/aclocal.m4 changes.
1616         * config.in: Ditto.
1617
1618 Fri Apr 24 11:19:20 1998  Tom Tromey  <tromey@cygnus.com>
1619
1620         * configure.in: Don't call sinclude.
1621
1622 Fri Apr 24 11:35:01 1998  Andrew Cagney  <cagney@chook.cygnus.com>
1623
1624         * mips.igen (do_store_left): Pass 0 not NULL to store_memory.
1625
1626 Tue Apr 21 11:59:50 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1627
1628         * mips.igen (ERET): Implement.
1629
1630         * interp.c (decode_coproc): Return sign-extended EPC.
1631
1632         * mips.igen (ANDI, LUI, MFC0): Add tracing code.
1633
1634         * interp.c (signal_exception): Do not ignore Trap.
1635         (signal_exception): On TRAP, restart at exception address.
1636         (HALT_INSTRUCTION, HALT_INSTRUCTION_MASK): Define.
1637         (signal_exception): Update.
1638         (sim_open): Patch V_COMMON interrupt vector with an abort sequence
1639         so that TRAP instructions are caught.
1640
1641 Mon Apr 20 11:26:55 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1642
1643         * sim-main.h (struct hilo_access, struct hilo_history): Define,
1644         contains HI/LO access history.
1645         (struct _sim_cpu): Make hiaccess and loaccess of type hilo_access.
1646         (HIACCESS, LOACCESS): Delete, replace with
1647         (HIHISTORY, LOHISTORY): New macros.
1648         (CHECKHILO): Delete all, moved to mips.igen
1649
1650         * gencode.c (build_instruction): Do not generate checks for
1651         correct HI/LO register usage.
1652
1653         * interp.c (old_engine_run): Delete checks for correct HI/LO
1654         register usage.
1655
1656         * mips.igen (check_mt_hilo, check_mf_hilo, check_op_hilo,
1657         check_mf_cycles): New functions.
1658         (do_mfhi, do_mflo, "mthi", "mtlo", do_ddiv, do_ddivu, do_div,
1659         do_divu, domultx, do_mult, do_multu): Use.
1660
1661         * tx.igen ("madd", "maddu"): Use.
1662
1663 Wed Apr 15 18:31:54 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1664
1665         * mips.igen (DSRAV): Use function do_dsrav.
1666         (SRAV): Use new function do_srav.
1667
1668         * m16.igen (BEQZ, BNEZ): Compare GPR[TRX] not GPR[RX].
1669         (B): Sign extend 11 bit immediate.
1670         (EXT-B*): Shift 16 bit immediate left by 1.
1671         (ADDIU*): Don't sign extend immediate value.
1672
1673 Wed Apr 15 10:32:15 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1674
1675         * m16run.c (sim_engine_run): Restore CIA after handling an event.
1676
1677         * sim-main.h (DELAY_SLOT, NULLIFY_NEXT_INSTRUCTION): For IGEN, use
1678         functions.
1679
1680         * mips.igen (delayslot32, nullify_next_insn): New functions.
1681         (m16.igen): Always include.
1682         (do_*): Add more tracing.
1683
1684         * m16.igen (delayslot16): Add NIA argument, could be called by a
1685         32 bit MIPS16 instruction.
1686
1687         * interp.c (ifetch16): Move function from here.
1688         * sim-main.c (ifetch16): To here.
1689
1690         * sim-main.c (ifetch16, ifetch32): Update to match current
1691         implementations of LH, LW.
1692         (signal_exception): Don't print out incorrect hex value of illegal
1693         instruction.
1694
1695 Wed Apr 15 00:17:25 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1696
1697         * m16run.c (sim_engine_run): Use IMEM16 and IMEM32 to fetch an
1698         instruction.
1699
1700         * m16.igen: Implement MIPS16 instructions.
1701
1702         * mips.igen (do_addiu, do_addu, do_and, do_daddiu, do_daddu,
1703         do_ddiv, do_ddivu, do_div, do_divu, do_dmultx, do_dmultu, do_srav,
1704         do_dsubu, do_mfhi, do_mflo, do_mult, do_multu, do_nor, do_or,
1705         do_sll, do_sllv, do_slt, do_slti, do_sltiu, do_sltu, do_sra,
1706         do_srl, do_srlv, do_subu, do_xor, do_xori): New functions.  Move
1707         bodies of corresponding code from 32 bit insn to these.  Also used
1708         by MIPS16 versions of functions.
1709
1710         * sim-main.h (RAIDX, T8IDX, T8, SPIDX): Define.
1711         (IMEM16): Drop NR argument from macro.
1712
1713 Sat Apr  4 22:39:50 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1714
1715         * Makefile.in (SIM_OBJS): Add sim-main.o.
1716
1717         * sim-main.h (address_translation, load_memory, store_memory,
1718         cache_op, sync_operation, prefetch, ifetch32, pending_tick): Mark
1719         as INLINE_SIM_MAIN.
1720         (pr_addr, pr_uword64): Declare.
1721         (sim-main.c): Include when H_REVEALS_MODULE_P.
1722
1723         * interp.c (address_translation, load_memory, store_memory,
1724         cache_op, sync_operation, prefetch, ifetch32, pending_tick): Move
1725         from here.
1726         * sim-main.c: To here. Fix compilation problems.
1727
1728         * configure.in: Enable inlining.
1729         * configure: Re-config.
1730
1731 Sat Apr  4 20:36:25 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1732
1733         * configure: Regenerated to track ../common/aclocal.m4 changes.
1734
1735 Fri Apr  3 04:32:35 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1736
1737         * mips.igen: Include tx.igen.
1738         * Makefile.in (IGEN_INCLUDE): Add tx.igen.
1739         * tx.igen: New file, contains MADD and MADDU.
1740
1741         * interp.c (load_memory): When shifting bytes, use LOADDRMASK not
1742         the hardwired constant `7'.
1743         (store_memory): Ditto.
1744         (LOADDRMASK): Move definition to sim-main.h.
1745
1746         mips.igen (MTC0): Enable for r3900.
1747         (ADDU): Add trace.
1748
1749         mips.igen (do_load_byte): Delete.
1750         (do_load, do_store, do_load_left, do_load_write, do_store_left,
1751         do_store_right): New functions.
1752         (SW*, LW*, SD*, LD*, SH, LH, SB, LB): Use.
1753
1754         configure.in: Let the tx39 use igen again.
1755         configure: Update.
1756
1757 Thu Apr  2 10:59:39 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1758
1759         * interp.c (sim_monitor): get_mem_info returns a 4 byte quantity,
1760         not an address sized quantity.  Return zero for cache sizes.
1761
1762 Wed Apr  1 23:47:53 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1763
1764         * mips.igen (r3900): r3900 does not support 64 bit integer
1765         operations.
1766
1767 Mon Mar 30 14:46:05 1998  Gavin Koch  <gavin@cygnus.com>
1768
1769         * configure.in (mipstx39*-*-*): Use gencode simulator rather
1770         than igen one.
1771         * configure : Rebuild.
1772
1773 Fri Mar 27 16:15:52 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1774
1775         * configure: Regenerated to track ../common/aclocal.m4 changes.
1776
1777 Fri Mar 27 15:01:50 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1778
1779         * interp.c (mips_option_handler): Iterate over MAX_NR_PROCESSORS.
1780
1781 Wed Mar 25 16:44:27 1998  Ian Carmichael  <iancarm@cygnus.com>
1782
1783         * configure: Regenerated to track ../common/aclocal.m4 changes.
1784         * config.in: Regenerated to track ../common/aclocal.m4 changes.
1785
1786 Wed Mar 25 12:35:29 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1787
1788         * configure: Regenerated to track ../common/aclocal.m4 changes.
1789
1790 Wed Mar 25 10:05:46 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1791
1792         * interp.c (Max, Min): Comment out functions. Not yet used.
1793
1794 Wed Mar 18 12:38:12 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1795
1796         * configure: Regenerated to track ../common/aclocal.m4 changes.
1797
1798 Tue Mar 17 19:05:20 1998  Frank Ch. Eigler  <fche@cygnus.com>
1799
1800         * Makefile.in (MIPS_EXTRA_LIBS, SIM_EXTRA_LIBS): Added
1801         configurable settings for stand-alone simulator.
1802
1803         * configure.in: Added X11 search, just in case.
1804
1805         * configure: Regenerated.
1806
1807 Wed Mar 11 14:09:10 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1808
1809         * interp.c (sim_write, sim_read, load_memory, store_memory):
1810         Replace sim_core_*_map with read_map, write_map, exec_map resp.
1811
1812 Tue Mar  3 13:58:43 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1813
1814         * sim-main.h (GETFCC): Return an unsigned value.
1815
1816 Tue Mar  3 13:21:37 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1817
1818         * mips.igen (DIV): Fix check for -1 / MIN_INT.
1819         (DADD): Result destination is RD not RT.
1820
1821 Fri Feb 27 13:49:49 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1822
1823         * sim-main.h (HIACCESS, LOACCESS): Always define.
1824
1825         * mdmx.igen (Maxi, Mini): Rename Max, Min.
1826
1827         * interp.c (sim_info): Delete.
1828
1829 Fri Feb 27 18:41:01 1998  Doug Evans  <devans@canuck.cygnus.com>
1830
1831         * interp.c (DECLARE_OPTION_HANDLER): Use it.
1832         (mips_option_handler): New argument `cpu'.
1833         (sim_open): Update call to sim_add_option_table.
1834
1835 Wed Feb 25 18:56:22 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1836
1837         * mips.igen (CxC1): Add tracing.
1838
1839 Fri Feb 20 17:43:21 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1840
1841         * sim-main.h (Max, Min): Declare.
1842
1843         * interp.c (Max, Min): New functions.
1844
1845         * mips.igen (BC1): Add tracing.
1846
1847 Thu Feb 19 14:50:00 1998  John Metzler  <jmetzler@cygnus.com>
1848
1849         * interp.c Added memory map for stack in vr4100
1850
1851 Thu Feb 19 10:21:21 1998  Gavin Koch  <gavin@cygnus.com>
1852
1853         * interp.c (load_memory): Add missing "break"'s.
1854
1855 Tue Feb 17 12:45:35 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1856
1857         * interp.c (sim_store_register, sim_fetch_register): Pass in
1858         length parameter.  Return -1.
1859
1860 Tue Feb 10 11:57:40 1998  Ian Carmichael  <iancarm@cygnus.com>
1861
1862         * interp.c: Added hardware init hook, fixed warnings.
1863
1864 Sat Feb  7 17:16:20 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1865
1866         * Makefile.in (itable.h itable.c): Depend on SIM_@sim_gen@_ALL.
1867
1868 Tue Feb  3 11:36:02 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1869
1870         * interp.c (ifetch16): New function.
1871
1872         * sim-main.h (IMEM32): Rename IMEM.
1873         (IMEM16_IMMED): Define.
1874         (IMEM16): Define.
1875         (DELAY_SLOT): Update.
1876
1877         * m16run.c (sim_engine_run): New file.
1878
1879         * m16.igen: All instructions except LB.
1880         (LB): Call do_load_byte.
1881         * mips.igen (do_load_byte): New function.
1882         (LB): Call do_load_byte.
1883
1884         * mips.igen: Move spec for insn bit size and high bit from here.
1885         * Makefile.in (tmp-igen, tmp-m16): To here.
1886
1887         * m16.dc: New file, decode mips16 instructions.
1888
1889         * Makefile.in (SIM_NO_ALL): Define.
1890         (tmp-m16): Generate both 16 bit and 32 bit simulator engines.
1891
1892 Tue Feb  3 11:28:00 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1893
1894         * configure.in (mips_fpu_bitsize): For tx39, restrict floating
1895         point unit to 32 bit registers.
1896         * configure: Re-generate.
1897
1898 Sun Feb  1 15:47:14 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1899
1900         * configure.in (sim_use_gen): Make IGEN the default simulator
1901         generator for generic 32 and 64 bit mips targets.
1902         * configure: Re-generate.
1903
1904 Sun Feb  1 16:52:37 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1905
1906         * sim-main.h (SizeFGR): Determine from floating-point and not gpr
1907         bitsize.
1908
1909         * interp.c (sim_fetch_register, sim_store_register): Read/write
1910         FGR from correct location.
1911         (sim_open): Set size of FGR's according to
1912         WITH_TARGET_FLOATING_POINT_BITSIZE.
1913
1914         * sim-main.h (FGR): Store floating point registers in a separate
1915         array.
1916
1917 Sun Feb  1 16:47:51 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1918
1919         * configure: Regenerated to track ../common/aclocal.m4 changes.
1920
1921 Tue Feb  3 00:10:50 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1922
1923         * interp.c (ColdReset): Call PENDING_INVALIDATE.
1924
1925         * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Call PENDING_TICK.
1926
1927         * interp.c (pending_tick): New function.  Deliver pending writes.
1928
1929         * sim-main.h (PENDING_FILL, PENDING_TICK, PENDING_SCHED,
1930         PENDING_BIT, PENDING_INVALIDATE): Re-write pipeline code so that
1931         it can handle mixed sized quantites and single bits.
1932
1933 Mon Feb  2 17:43:15 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1934
1935         * interp.c (oengine.h): Do not include when building with IGEN.
1936         (sim_open): Replace GPRLEN by WITH_TARGET_WORD_BITSIZE.
1937         (sim_info): Ditto for PROCESSOR_64BIT.
1938         (sim_monitor): Replace ut_reg with unsigned_word.
1939         (*): Ditto for t_reg.
1940         (LOADDRMASK): Define.
1941         (sim_open): Remove defunct check that host FP is IEEE compliant,
1942         using software to emulate floating point.
1943         (value_fpr, ...): Always compile, was conditional on HASFPU.
1944
1945 Sun Feb  1 11:15:29 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1946
1947         * sim-main.h (sim_state): Make the cpu array MAX_NR_PROCESSORS in
1948         size.
1949
1950         * interp.c (SD, CPU): Define.
1951         (mips_option_handler): Set flags in each CPU.
1952         (interrupt_event): Assume CPU 0 is the one being iterrupted.
1953         (sim_close): Do not clear STATE, deleted anyway.
1954         (sim_write, sim_read): Assume CPU zero's vm should be used for
1955         data transfers.
1956         (sim_create_inferior): Set the PC for all processors.
1957         (sim_monitor, store_word, load_word, mips16_entry): Add cpu
1958         argument.
1959         (mips16_entry): Pass correct nr of args to store_word, load_word.
1960         (ColdReset): Cold reset all cpu's.
1961         (signal_exception): Pass cpu to sim_monitor & mips16_entry.
1962         (sim_monitor, load_memory, store_memory, signal_exception): Use
1963         `CPU' instead of STATE_CPU.
1964
1965
1966         * sim-main.h: Replace uses of STATE_CPU with CPU. Replace sd with
1967         SD or CPU_.
1968
1969         * sim-main.h (signal_exception): Add sim_cpu arg.
1970         (SignalException*): Pass both SD and CPU to signal_exception.
1971         * interp.c (signal_exception): Update.
1972
1973         * sim-main.h (value_fpr, store_fpr, dotrace, ifetch32), interp.c:
1974         Ditto
1975         (sync_operation, prefetch, cache_op, store_memory, load_memory,
1976         address_translation): Ditto
1977         (decode_coproc, cop_lw, cop_ld, cop_sw, cop_sd): Ditto.
1978
1979 Sat Jan 31 18:15:41 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1980
1981         * configure: Regenerated to track ../common/aclocal.m4 changes.
1982
1983 Sat Jan 31 14:49:24 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1984
1985         * interp.c (sim_engine_run): Add `nr_cpus' argument.
1986
1987         * mips.igen (model): Map processor names onto BFD name.
1988
1989         * sim-main.h (CPU_CIA): Delete.
1990         (SET_CIA, GET_CIA): Define
1991
1992 Wed Jan 21 16:16:27 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1993
1994         * sim-main.h (GPR_SET): Define, used by igen when zeroing a
1995         regiser.
1996
1997         * configure.in (default_endian): Configure a big-endian simulator
1998         by default.
1999         * configure: Re-generate.
2000
2001 Mon Jan 19 22:26:29 1998  Doug Evans  <devans@seba>
2002
2003         * configure: Regenerated to track ../common/aclocal.m4 changes.
2004
2005 Mon Jan  5 20:38:54 1998  Mark Alexander  <marka@cygnus.com>
2006
2007         * interp.c (sim_monitor): Handle Densan monitor outbyte
2008         and inbyte functions.
2009
2010 1997-12-29  Felix Lee  <flee@cygnus.com>
2011
2012         * interp.c (sim_engine_run): msvc cpp barfs on #if (a==b!=c).
2013
2014 Wed Dec 17 14:48:20 1997  Jeffrey A Law  (law@cygnus.com)
2015
2016         * Makefile.in (tmp-igen): Arrange for $zero to always be
2017         reset to zero after every instruction.
2018
2019 Mon Dec 15 23:17:11 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2020
2021         * configure: Regenerated to track ../common/aclocal.m4 changes.
2022         * config.in: Ditto.
2023
2024 Wed Dec 10 17:10:45 1997  Jeffrey A Law  (law@cygnus.com)
2025
2026         * mips.igen (MSUB): Fix to work like MADD.
2027         * gencode.c (MSUB): Similarly.
2028
2029 Thu Dec  4 09:21:05 1997  Doug Evans  <devans@canuck.cygnus.com>
2030
2031         * configure: Regenerated to track ../common/aclocal.m4 changes.
2032
2033 Wed Nov 26 11:00:23 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2034
2035         * mips.igen (LWC1): Correct assembler - lwc1 not swc1.
2036
2037 Sun Nov 23 01:45:20 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2038
2039         * sim-main.h (sim-fpu.h): Include.
2040
2041         * interp.c (convert, SquareRoot, Recip, Divide, Multiply, Sub,
2042         Add, Negate, AbsoluteValue, Equal, Less, Infinity, NaN): Rewrite
2043         using host independant sim_fpu module.
2044
2045 Thu Nov 20 19:56:22 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2046
2047         * interp.c (signal_exception): Report internal errors with SIGABRT
2048         not SIGQUIT.
2049
2050         * sim-main.h (C0_CONFIG): New register.
2051         (signal.h): No longer include.
2052
2053         * interp.c (decode_coproc): Allow access C0_CONFIG to register.
2054
2055 Tue Nov 18 15:33:48 1997  Doug Evans  <devans@canuck.cygnus.com>
2056
2057         * Makefile.in (SIM_OBJS): Use $(SIM_NEW_COMMON_OBJS).
2058
2059 Fri Nov 14 11:56:48 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2060
2061         * mips.igen: Tag vr5000 instructions.
2062         (ANDI): Was missing mipsIV model, fix assembler syntax.
2063         (do_c_cond_fmt): New function.
2064         (C.cond.fmt): Handle mips I-III which do not support CC field
2065         separatly.
2066         (bc1): Handle mips IV which do not have a delaed FCC separatly.
2067         (SDR): Mask paddr when BigEndianMem, not the converse as specified
2068         in IV3.2 spec.
2069         (DMULT, DMULTU): Force use of hosts 64bit multiplication.  Handle
2070         vr5000 which saves LO in a GPR separatly.
2071
2072         * configure.in (enable-sim-igen): For vr5000, select vr5000
2073         specific instructions.
2074         * configure: Re-generate.
2075
2076 Wed Nov 12 14:42:52 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2077
2078         * Makefile.in (SIM_OBJS): Add sim-fpu module.
2079
2080         * interp.c (store_fpr), sim-main.h: Add separate fmt_uninterpreted_32 and
2081         fmt_uninterpreted_64 bit cases to switch.  Convert to
2082         fmt_formatted,
2083
2084         * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Define,
2085
2086         * mips.igen (SWR): Mask paddr when BigEndianMem, not the converse
2087         as specified in IV3.2 spec.
2088         (MTC1, DMTC1): Call StoreFPR to store the GPR in the FPR.
2089
2090 Tue Nov 11 12:38:23 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2091
2092         * mips.igen: Delay slot branches add OFFSET to NIA not CIA.
2093         (MFC0, MTC0, SWC1, LWC1, SDC1, LDC1): Implement.
2094         (MTC1, MFC1, DMTC1, DMFC1, CFC1, CTC1): Implement separate non
2095         PENDING_FILL versions of instructions.  Simplify.
2096         (X): New function.
2097         (MULT, MULTU): Implement separate RD==0 and RD!=0 versions of
2098         instructions.
2099         (BEQZ, ..., SLT, SLTI, TLT, TLE, TLI, ...): Explicitly cast GPR to
2100         a signed value.
2101         (MTHI, MFHI): Disable code checking HI-LO.
2102
2103         * sim-main.h (dotrace,tracefh), interp.c: Make dotrace & tracefh
2104         global.
2105         (NULLIFY_NEXT_INSTRUCTION): Call dotrace.
2106
2107 Thu Nov  6 16:36:35 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2108
2109         * gencode.c (build_mips16_operands): Replace IPC with cia.
2110
2111         * interp.c (sim_monitor, signal_exception, cache_op, store_fpr,
2112         value_fpr, cop_ld, cop_lw, cop_sw, cop_sd, decode_coproc): Replace
2113         IPC to `cia'.
2114         (UndefinedResult): Replace function with macro/function
2115         combination.
2116         (sim_engine_run): Don't save PC in IPC.
2117
2118         * sim-main.h (IPC): Delete.
2119
2120
2121         * interp.c (signal_exception, store_word, load_word,
2122         address_translation, load_memory, store_memory, cache_op,
2123         prefetch, sync_operation, ifetch, value_fpr, store_fpr, convert,
2124         cop_lw, cop_ld, cop_sw, cop_sd, decode_coproc, sim_monitor): Add
2125         current instruction address - cia - argument.
2126         (sim_read, sim_write): Call address_translation directly.
2127         (sim_engine_run): Rename variable vaddr to cia.
2128         (signal_exception): Pass cia to sim_monitor
2129
2130         * sim-main.h (SignalException, LoadWord, StoreWord, CacheOp,
2131         Prefetch, SyncOperation, ValueFPR, StoreFPR, Convert, COP_LW,
2132         COP_LD, COP_SW, COP_SD, DecodeCoproc): Update.
2133
2134         * sim-main.h (SignalExceptionSimulatorFault): Delete definition.
2135         * interp.c (sim_open): Replace SignalExceptionSimulatorFault with
2136         SIM_ASSERT.
2137
2138         * interp.c (signal_exception): Pass restart address to
2139         sim_engine_restart.
2140
2141         * Makefile.in (semantics.o, engine.o, support.o, itable.o,
2142         idecode.o): Add dependency.
2143
2144         * sim-main.h (SIM_ENGINE_HALT_HOOK, SIM_ENGINE_RESUME_HOOK):
2145         Delete definitions
2146         (DELAY_SLOT): Update NIA not PC with branch address.
2147         (NULLIFY_NEXT_INSTRUCTION): Set NIA to instruction after next.
2148
2149         * mips.igen: Use CIA not PC in branch calculations.
2150         (illegal): Call SignalException.
2151         (BEQ, ADDIU): Fix assembler.
2152
2153 Wed Nov  5 12:19:56 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2154
2155         * m16.igen (JALX): Was missing.
2156
2157         * configure.in (enable-sim-igen): New configuration option.
2158         * configure: Re-generate.
2159
2160         * sim-main.h (MAX_INSNS, INSN_NAME): Define.
2161
2162         * interp.c (load_memory, store_memory): Delete parameter RAW.
2163         (sim_read, sim_write): Use sim_core_{read,write}_buffer directly
2164         bypassing {load,store}_memory.
2165
2166         * sim-main.h (ByteSwapMem): Delete definition.
2167
2168         * Makefile.in (SIM_OBJS): Add sim-memopt module.
2169
2170         * interp.c (sim_do_command, sim_commands): Delete mips specific
2171         commands.  Handled by module sim-options.
2172
2173         * sim-main.h (SIM_HAVE_FLATMEM): Undefine, use sim-core.o module.
2174         (WITH_MODULO_MEMORY): Define.
2175
2176         * interp.c (sim_info): Delete code printing memory size.
2177
2178         * interp.c (mips_size): Nee sim_size, delete function.
2179         (power2): Delete.
2180         (monitor, monitor_base, monitor_size): Delete global variables.
2181         (sim_open, sim_close): Delete code creating monitor and other
2182         memory regions.  Use sim-memopts module, via sim_do_commandf, to
2183         manage memory regions.
2184         (load_memory, store_memory): Use sim-core for memory model.
2185
2186         * interp.c (address_translation): Delete all memory map code
2187         except line forcing 32 bit addresses.
2188
2189 Wed Nov  5 11:21:11 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2190
2191         * sim-main.h (WITH_TRACE): Delete definition.  Enables common
2192         trace options.
2193
2194         * interp.c (logfh, logfile): Delete globals.
2195         (sim_open, sim_close): Delete code opening & closing log file.
2196         (mips_option_handler): Delete -l and -n options.
2197         (OPTION mips_options): Ditto.
2198
2199         * interp.c (OPTION mips_options): Rename option trace to dinero.
2200         (mips_option_handler): Update.
2201
2202 Wed Nov  5 09:35:59 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2203
2204         * interp.c (fetch_str): New function.
2205         (sim_monitor): Rewrite using sim_read & sim_write.
2206         (sim_open): Check magic number.
2207         (sim_open): Write monitor vectors into memory using sim_write.
2208         (MONITOR_BASE, MONITOR_SIZE, MEM_SIZE): Define.
2209         (sim_read, sim_write): Simplify - transfer data one byte at a
2210         time.
2211         (load_memory, store_memory): Clarify meaning of parameter RAW.
2212
2213         * sim-main.h (isHOST): Defete definition.
2214         (isTARGET): Mark as depreciated.
2215         (address_translation): Delete parameter HOST.
2216
2217         * interp.c (address_translation): Delete parameter HOST.
2218
2219 Wed Oct 29 11:13:56 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2220
2221         * mips.igen:
2222
2223         * Makefile.in (IGEN_INCLUDE): Files included by mips.igen.
2224         (tmp-igen, tmp-m16): Depend on IGEN_INCLUDE.
2225
2226 Tue Oct 28 11:06:47 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2227
2228         * mips.igen: Add model filter field to records.
2229
2230 Mon Oct 27 17:53:59 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2231
2232         * Makefile.in (SIM_NO_CFLAGS): Define.  Define WITH_IGEN=0.
2233
2234         interp.c (sim_engine_run): Do not compile function sim_engine_run
2235         when WITH_IGEN == 1.
2236
2237         * configure.in (sim_igen_flags, sim_m16_flags): Set according to
2238         target architecture.
2239
2240         Makefile.in (tmp-igen, tmp-m16): Drop -F and -M options to
2241         igen. Replace with configuration variables sim_igen_flags /
2242         sim_m16_flags.
2243
2244         * m16.igen: New file.  Copy mips16 insns here.
2245         * mips.igen: From here.
2246
2247 Mon Oct 27 13:53:59 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2248
2249         * Makefile.in (SIM_NO_OBJ): Define, move SIM_M16_OBJ, SIM_IGEN_OBJ
2250         to top.
2251         (tmp-igen, tmp-m16): Pass -I srcdir to igen.
2252
2253 Sat Oct 25 16:51:40 1997  Gavin Koch  <gavin@cygnus.com>
2254
2255         * gencode.c (build_instruction): Follow sim_write's lead in using
2256         BigEndianMem instead of !ByteSwapMem.
2257
2258 Fri Oct 24 17:41:49 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2259
2260         * configure.in (sim_gen): Dependent on target, select type of
2261         generator.  Always select old style generator.
2262
2263         configure: Re-generate.
2264
2265         Makefile.in (tmp-igen, tmp-m16, clean-m16, clean-igen): New
2266         targets.
2267         (SIM_M16_CFLAGS, SIM_M16_ALL, SIM_M16_OBJ, BUILT_SRC_FROM_M16,
2268         SIM_IGEN_CFLAGS, SIM_IGEN_ALL, SIM_IGEN_OBJ, BUILT_SRC_FROM_IGEN,
2269         IGEN_TRACE, IGEN_INSN, IGEN_DC): Define
2270         (SIM_EXTRA_CFLAGS, SIM_EXTRA_ALL, SIM_OBJS): Add member
2271         SIM_@sim_gen@_*, set by autoconf.
2272
2273 Wed Oct 22 12:52:06 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2274
2275         * sim-main.h (NULLIFY_NEXT_INSTRUCTION, DELAY_SLOT): Define.
2276
2277         * interp.c (ColdReset): Remove #ifdef HASFPU, check
2278         CURRENT_FLOATING_POINT instead.
2279
2280         * interp.c (ifetch32): New function. Fetch 32 bit instruction.
2281         (address_translation): Raise exception InstructionFetch when
2282         translation fails and isINSTRUCTION.
2283
2284         * interp.c (sim_open, sim_write, sim_monitor, store_word,
2285         sim_engine_run): Change type of of vaddr and paddr to
2286         address_word.
2287         (address_translation, prefetch, load_memory, store_memory,
2288         cache_op): Change type of vAddr and pAddr to address_word.
2289
2290         * gencode.c (build_instruction): Change type of vaddr and paddr to
2291         address_word.
2292
2293 Mon Oct 20 15:29:04 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2294
2295         * sim-main.h (ALU64_END, ALU32_END): Use ALU*_OVERFLOW_RESULT
2296         macro to obtain result of ALU op.
2297
2298 Tue Oct 21 17:39:14 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2299
2300         * interp.c (sim_info): Call profile_print.
2301
2302 Mon Oct 20 13:31:20 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2303
2304         * Makefile.in (SIM_OBJS): Add sim-profile.o module.
2305
2306         * sim-main.h (WITH_PROFILE): Do not define, defined in
2307         common/sim-config.h.  Use sim-profile module.
2308         (simPROFILE): Delete defintion.
2309
2310         * interp.c (PROFILE): Delete definition.
2311         (mips_option_handler): Delete 'p', 'y' and 'x' profile options.
2312         (sim_close): Delete code writing profile histogram.
2313         (mips_set_profile, mips_set_profile_size, writeout16, writeout32):
2314         Delete.
2315         (sim_engine_run): Delete code profiling the PC.
2316
2317 Mon Oct 20 13:31:20 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2318
2319         * sim-main.h (SIGNEXTEND): Force type of result to unsigned_word.
2320
2321         * interp.c (sim_monitor): Make register pointers of type
2322         unsigned_word*.
2323
2324         * sim-main.h: Make registers of type unsigned_word not
2325         signed_word.
2326
2327 Thu Oct 16 10:31:39 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2328
2329         * interp.c (sync_operation): Rename from SyncOperation, make
2330         global, add SD argument.
2331         (prefetch): Rename from Prefetch, make global, add SD argument.
2332         (decode_coproc): Make global.
2333
2334         * sim-main.h (SyncOperation, DecodeCoproc, Pefetch): Define.
2335
2336         * gencode.c (build_instruction): Generate DecodeCoproc not
2337         decode_coproc calls.
2338
2339         * interp.c (SETFCC, GETFCC, PREVCOC1): Move to sim-main.h
2340         (SizeFGR): Move to sim-main.h
2341         (simHALTEX, simHALTIN, simTRACE, simPROFILE, simDELAYSLOT,
2342         simSIGINT, simJALDELAYSLOT): Move to sim-main.h
2343         (FP_FLAGS, FP_ENABLE, FP_CAUSE, IR, UF, OF, DZ, IO, UO): Move to
2344         sim-main.h.
2345         (FP_FS, FP_MASK_RM, FP_SH_RM, FP_RM_NEAREST, FP_RM_TOPINF,
2346         FP_RM_TOMINF, GETRM): Move to sim-main.h.
2347         (Uncached, CachedNoncoherent, CachedCoherent, Cached,
2348         isINSTRUCTION, ..., AccessLength_BYTE, ...): Move to sim-main.h.
2349         (UserMode, BigEndianMem, ByteSwapMem, ReverseEndian,
2350         BigEndianCPU, status_KSU_mask, ...). Moved to sim-main.h
2351
2352         * sim-main.h (ALU32_END, ALU64_END): Define. When overflow raise
2353         exception.
2354         (sim-alu.h): Include.
2355         (NULLIFY_NIA, NULL_CIA, CPU_CIA): Define.
2356         (sim_cia): Typedef to instruction_address.
2357
2358 Thu Oct 16 10:31:41 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2359
2360         * Makefile.in (interp.o): Rename generated file engine.c to
2361         oengine.c.
2362
2363         * interp.c: Update.
2364
2365 Thu Oct 16 10:31:40 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2366
2367         * gencode.c (build_instruction): Use FPR_STATE not fpr_state.
2368
2369 Thu Oct 16 10:31:39 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2370
2371         * gencode.c (build_instruction): For "FPSQRT", output correct
2372         number of arguments to Recip.
2373
2374 Tue Oct 14 17:38:18 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2375
2376         * Makefile.in (interp.o): Depends on sim-main.h
2377
2378         * interp.c (mips16_entry, ColdReset,dotrace): Add SD argument. Use GPR not registers.
2379
2380         * sim-main.h (sim_cpu): Add registers, register_widths, fpr_state,
2381         ipc, dspc, pending_*, hiaccess, loaccess, state, dsstate fields.
2382         (REGISTERS, REGISTER_WIDTHS, FPR_STATE, IPC, DSPC, PENDING_*,
2383         STATE, DSSTATE): Define
2384         (GPR, FGRIDX, ..): Define.
2385
2386         * interp.c (registers, register_widths, fpr_state, ipc, dspc,
2387         pending_*, hiaccess, loaccess, state, dsstate): Delete globals.
2388         (GPR, FGRIDX, ...): Delete macros.
2389
2390         * interp.c: Update names to match defines from sim-main.h
2391
2392 Tue Oct 14 15:11:45 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2393
2394         * interp.c (sim_monitor): Add SD argument.
2395         (sim_warning): Delete.  Replace calls with calls to
2396         sim_io_eprintf.
2397         (sim_error): Delete. Replace calls with sim_io_error.
2398         (open_trace, writeout32, writeout16, getnum): Add SD argument.
2399         (mips_set_profile): Rename from sim_set_profile. Add SD argument.
2400         (mips_set_profile_size): Rename from sim_set_profile_size. Add SD
2401         argument.
2402         (mips_size): Rename from sim_size. Add SD argument.
2403
2404         * interp.c (simulator): Delete global variable.
2405         (callback): Delete global variable.
2406         (mips_option_handler, sim_open, sim_write, sim_read,
2407         sim_store_register, sim_fetch_register, sim_info, sim_do_command,
2408         sim_size,sim_monitor): Use sim_io_* not callback->*.
2409         (sim_open): ZALLOC simulator struct.
2410         (PROFILE): Do not define.
2411
2412 Tue Oct 14 13:35:48 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2413
2414         * interp.c (sim_open), support.h: Replace CHECKSIM macro found in
2415         support.h with corresponding code.
2416
2417         * sim-main.h (word64, uword64), support.h: Move definition to
2418         sim-main.h.
2419         (WORD64LO, WORD64HI, SET64LO, SET64HI, WORD64, UWORD64): Ditto.
2420
2421         * support.h: Delete
2422         * Makefile.in: Update dependencies
2423         * interp.c: Do not include.
2424
2425 Tue Oct 14 13:35:48 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2426
2427         * interp.c (address_translation, load_memory, store_memory,
2428         cache_op): Rename to from AddressTranslation et.al., make global,
2429         add SD argument
2430
2431         * sim-main.h (AddressTranslation, LoadMemory, StoreMemory,
2432         CacheOp): Define.
2433
2434         * interp.c (SignalException): Rename to signal_exception, make
2435         global.
2436
2437         * interp.c (Interrupt, ...): Move definitions to sim-main.h.
2438
2439         * sim-main.h (SignalException, SignalExceptionInterrupt,
2440         SignalExceptionInstructionFetch, SignalExceptionAddressStore,
2441         SignalExceptionAddressLoad, SignalExceptionSimulatorFault,
2442         SignalExceptionIntegerOverflow, SignalExceptionCoProcessorUnusable):
2443         Define.
2444
2445         * interp.c, support.h: Use.
2446
2447 Tue Oct 14 13:19:20 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2448
2449         * interp.c (ValueFPR, StoreFPR), sim-main.h: Make global, rename
2450         to value_fpr / store_fpr. Add SD argument.
2451         (NaN, Infinity, Less, Equal, AbsoluteValue, Negate, Add, Sub,
2452         Multiply, Divide, Recip, SquareRoot, Convert): Make global.
2453
2454         * sim-main.h (ValueFPR, StoreFPR): Define.
2455
2456 Tue Oct 14 13:06:55 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2457
2458         * interp.c (sim_engine_run): Check consistency between configure
2459         WITH_TARGET_WORD_BITSIZE and WITH_FLOATING_POINT and gensim GPRLEN
2460         and HASFPU.
2461
2462         * configure.in (mips_bitsize): Configure WITH_TARGET_WORD_BITSIZE.
2463         (mips_fpu): Configure WITH_FLOATING_POINT.
2464         (mips_endian): Configure WITH_TARGET_ENDIAN.
2465         * configure: Update.
2466
2467 Fri Oct  3 09:28:00 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2468
2469         * configure: Regenerated to track ../common/aclocal.m4 changes.
2470
2471 Mon Sep 29 14:45:00 1997  Bob Manson  <manson@charmed.cygnus.com>
2472
2473         * configure: Regenerated.
2474
2475 Fri Sep 26 12:48:18 1997  Mark Alexander  <marka@cygnus.com>
2476
2477         * interp.c: Allow Debug, DEPC, and EPC registers to be examined in GDB.
2478
2479 Thu Sep 25 11:15:22 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2480
2481         * gencode.c (print_igen_insn_models): Assume certain architectures
2482         include all mips* instructions.
2483         (print_igen_insn_format): Use data_size==-1 as marker for MIPS16
2484         instruction.
2485
2486         * Makefile.in (tmp.igen): Add target. Generate igen input from
2487         gencode file.
2488
2489         * gencode.c (FEATURE_IGEN): Define.
2490         (main): Add --igen option.  Generate output in igen format.
2491         (process_instructions): Format output according to igen option.
2492         (print_igen_insn_format): New function.
2493         (print_igen_insn_models): New function.
2494         (process_instructions): Only issue warnings and ignore
2495         instructions when no FEATURE_IGEN.
2496
2497 Wed Sep 24 17:38:57 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2498
2499         * interp.c (COP_SD, COP_LD): Add UNUSED to pacify GCC for some
2500         MIPS targets.
2501
2502 Tue Sep 23 11:04:38 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2503
2504         * configure: Regenerated to track ../common/aclocal.m4 changes.
2505
2506 Tue Sep 23 10:19:51 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2507
2508         * Makefile.in (SIM_ALIGNMENT, SIM_ENDIAN, SIM_HOSTENDIAN,
2509         SIM_RESERVED_BITS): Delete, moved to common.
2510         (SIM_EXTRA_CFLAGS): Update.
2511
2512 Mon Sep 22 11:46:20 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2513
2514         * configure.in: Configure non-strict memory alignment.
2515         * configure: Regenerated to track ../common/aclocal.m4 changes.
2516
2517 Fri Sep 19 17:45:25 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2518
2519         * configure: Regenerated to track ../common/aclocal.m4 changes.
2520
2521 Sat Sep 20 14:07:28 1997  Gavin Koch  <gavin@cygnus.com>
2522
2523         * gencode.c (SDBBP,DERET): Added (3900) insns.
2524         (RFE): Turn on for 3900.
2525         * interp.c (DebugBreakPoint,DEPC,Debug,Debug_*): Added.
2526         (dsstate): Made global.
2527         (SUBTARGET_R3900): Added.
2528         (CANCELDELAYSLOT): New.
2529         (SignalException): Ignore SystemCall rather than ignore and
2530         terminate.  Add DebugBreakPoint handling.
2531         (decode_coproc): New insns RFE, DERET; and new registers Debug
2532         and DEPC protected by SUBTARGET_R3900.
2533         (sim_engine_run): Use CANCELDELAYSLOT rather than clearing
2534         bits explicitly.
2535         * Makefile.in,configure.in: Add mips subtarget option.
2536         * configure: Update.
2537
2538 Fri Sep 19 09:33:27 1997  Gavin Koch  <gavin@cygnus.com>
2539
2540         * gencode.c: Add r3900 (tx39).
2541
2542
2543 Tue Sep 16 15:52:04 1997  Gavin Koch  <gavin@cygnus.com>
2544
2545         * gencode.c (build_instruction): Don't need to subtract 4 for
2546         JALR, just 2.
2547
2548 Tue Sep 16 11:32:28 1997  Gavin Koch  <gavin@cygnus.com>
2549
2550         * interp.c: Correct some HASFPU problems.
2551
2552 Mon Sep 15 17:36:15 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2553
2554         * configure: Regenerated to track ../common/aclocal.m4 changes.
2555
2556 Fri Sep 12 12:01:39 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2557
2558         * interp.c (mips_options): Fix samples option short form, should
2559         be `x'.
2560
2561 Thu Sep 11 09:35:29 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2562
2563         * interp.c (sim_info): Enable info code.  Was just returning.
2564
2565 Tue Sep  9 17:30:57 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2566
2567         * interp.c (decode_coproc): Clarify warning about unsuported MTC0,
2568         MFC0.
2569
2570 Tue Sep  9 16:28:28 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2571
2572         * gencode.c (build_instruction): Use SIGNED64 for 64 bit
2573         constants.
2574         (build_instruction): Ditto for LL.
2575
2576 Thu Sep  4 17:21:23 1997  Doug Evans  <dje@seba>
2577
2578         * configure: Regenerated to track ../common/aclocal.m4 changes.
2579
2580 Wed Aug 27 18:13:22 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2581
2582         * configure: Regenerated to track ../common/aclocal.m4 changes.
2583         * config.in: Ditto.
2584
2585 Wed Aug 27 14:12:27 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2586
2587         * interp.c (sim_open): Add call to sim_analyze_program, update
2588         call to sim_config.
2589
2590 Tue Aug 26 10:40:07 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2591
2592         * interp.c (sim_kill): Delete.
2593         (sim_create_inferior): Add ABFD argument. Set PC from same.
2594         (sim_load): Move code initializing trap handlers from here.
2595         (sim_open): To here.
2596         (sim_load): Delete, use sim-hload.c.
2597
2598         * Makefile.in (SIM_OBJS): Add sim-hload.o module.
2599
2600 Mon Aug 25 17:50:22 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2601
2602         * configure: Regenerated to track ../common/aclocal.m4 changes.
2603         * config.in: Ditto.
2604
2605 Mon Aug 25 15:59:48 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2606
2607         * interp.c (sim_open): Add ABFD argument.
2608         (sim_load): Move call to sim_config from here.
2609         (sim_open): To here.  Check return status.
2610
2611 Fri Jul 25 15:00:45 1997  Gavin Koch  <gavin@cygnus.com>
2612
2613         * gencode.c (build_instruction): Two arg MADD should
2614         not assign result to $0.
2615
2616 Thu Jun 26 12:13:17 1997  Angela Marie Thomas (angela@cygnus.com)
2617
2618         * sim/mips/configure: Change default_sim_endian to 0 (bi-endian)
2619         * sim/mips/configure.in: Regenerate.
2620
2621 Wed Jul  9 10:29:21 1997  Andrew Cagney  <cagney@critters.cygnus.com>
2622
2623         * interp.c (SUB_REG_UW, SUB_REG_SW, SUB_REG_*): Use more explicit
2624         signed8, unsigned8 et.al. types.
2625
2626         * interp.c (SUB_REG_FETCH): Handle both little and big endian
2627         hosts when selecting subreg.
2628
2629 Wed Jul  2 11:54:10 1997  Jeffrey A Law  (law@cygnus.com)
2630
2631         * interp.c (sim_engine_run): Reset the ZERO register to zero
2632         regardless of FEATURE_WARN_ZERO.
2633         * gencode.c (FEATURE_WARNINGS): Remove FEATURE_WARN_ZERO.
2634
2635 Wed Jun  4 10:43:14 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2636
2637         * interp.c (decode_coproc): Implement MTC0 N, CAUSE.
2638         (SignalException): For BreakPoints ignore any mode bits and just
2639         save the PC.
2640         (SignalException): Always set the CAUSE register.
2641
2642 Tue Jun  3 05:00:33 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2643
2644         * interp.c (SignalException): Clear the simDELAYSLOT flag when an
2645         exception has been taken.
2646
2647         * interp.c: Implement the ERET and mt/f sr instructions.
2648
2649 Sat May 31 00:44:16 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2650
2651         * interp.c (SignalException): Don't bother restarting an
2652         interrupt.
2653
2654 Fri May 30 23:41:48 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2655
2656         * interp.c (SignalException): Really take an interrupt.
2657         (interrupt_event): Only deliver interrupts when enabled.
2658
2659 Tue May 27 20:08:06 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2660
2661         * interp.c (sim_info): Only print info when verbose.
2662         (sim_info) Use sim_io_printf for output.
2663
2664 Tue May 27 14:22:23 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2665
2666         * interp.c (CoProcPresent): Add UNUSED attribute - not used by all
2667         mips architectures.
2668
2669 Tue May 27 14:22:23 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2670
2671         * interp.c (sim_do_command): Check for common commands if a
2672         simulator specific command fails.
2673
2674 Thu May 22 09:32:03 1997  Gavin Koch  <gavin@cygnus.com>
2675
2676         * interp.c (sim_engine_run): ifdef out uses of simSTOP, simSTEP
2677         and simBE when DEBUG is defined.
2678
2679 Wed May 21 09:08:10 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2680
2681         * interp.c (interrupt_event): New function.  Pass exception event
2682         onto exception handler.
2683
2684         * configure.in: Check for stdlib.h.
2685         * configure: Regenerate.
2686
2687         * gencode.c (build_instruction): Add UNUSED attribute to tempS
2688         variable declaration.
2689         (build_instruction): Initialize memval1.
2690         (build_instruction): Add UNUSED attribute to byte, bigend,
2691         reverse.
2692         (build_operands): Ditto.
2693
2694         * interp.c: Fix GCC warnings.
2695         (sim_get_quit_code): Delete.
2696
2697         * configure.in: Add INLINE, ENDIAN, HOSTENDIAN and WARNINGS.
2698         * Makefile.in: Ditto.
2699         * configure: Re-generate.
2700
2701         * Makefile.in (SIM_OBJS): Add sim-watch.o module.
2702
2703 Tue May 20 15:08:56 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2704
2705         * interp.c (mips_option_handler): New function parse argumes using
2706         sim-options.
2707         (myname): Replace with STATE_MY_NAME.
2708         (sim_open): Delete check for host endianness - performed by
2709         sim_config.
2710         (simHOSTBE, simBE): Delete, replaced by sim-endian flags.
2711         (sim_open): Move much of the initialization from here.
2712         (sim_load): To here.  After the image has been loaded and
2713         endianness set.
2714         (sim_open): Move ColdReset from here.
2715         (sim_create_inferior): To here.
2716         (sim_open): Make FP check less dependant on host endianness.
2717
2718         * Makefile.in (SIM_RUN_OBJS): Set to nrun.o - use new version or
2719         run.
2720         * interp.c (sim_set_callbacks): Delete.
2721
2722         * interp.c (membank, membank_base, membank_size): Replace with
2723         STATE_MEMORY, STATE_MEM_SIZE, STATE_MEM_BASE.
2724         (sim_open): Remove call to callback->init. gdb/run do this.
2725
2726         * interp.c: Update
2727
2728         * sim-main.h (SIM_HAVE_FLATMEM): Define.
2729
2730         * interp.c (big_endian_p): Delete, replaced by
2731         current_target_byte_order.
2732
2733 Tue May 20 13:55:00 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2734
2735         * interp.c (host_read_long, host_read_word, host_swap_word,
2736         host_swap_long): Delete. Using common sim-endian.
2737         (sim_fetch_register, sim_store_register): Use H2T.
2738         (pipeline_ticks): Delete.  Handled by sim-events.
2739         (sim_info): Update.
2740         (sim_engine_run): Update.
2741
2742 Tue May 20 13:42:03 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2743
2744         * interp.c (sim_stop_reason): Move code determining simEXCEPTION
2745         reason from here.
2746         (SignalException): To here. Signal using sim_engine_halt.
2747         (sim_stop_reason): Delete, moved to common.
2748
2749 Tue May 20 10:19:48 1997  Andrew Cagney  <cagney@b2.cygnus.com>
2750
2751         * interp.c (sim_open): Add callback argument.
2752         (sim_set_callbacks): Delete SIM_DESC argument.
2753         (sim_size): Ditto.
2754
2755 Mon May 19 18:20:38 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2756
2757         * Makefile.in (SIM_OBJS): Add common modules.
2758
2759         * interp.c (sim_set_callbacks): Also set SD callback.
2760         (set_endianness, xfer_*, swap_*): Delete.
2761         (host_read_word, host_read_long, host_swap_word, host_swap_long):
2762         Change to functions using sim-endian macros.
2763         (control_c, sim_stop): Delete, use common version.
2764         (simulate): Convert into.
2765         (sim_engine_run): This function.
2766         (sim_resume): Delete.
2767
2768         * interp.c (simulation): New variable - the simulator object.
2769         (sim_kind): Delete global - merged into simulation.
2770         (sim_load): Cleanup.  Move PC assignment from here.
2771         (sim_create_inferior): To here.
2772
2773         * sim-main.h: New file.
2774         * interp.c (sim-main.h): Include.
2775
2776 Thu Apr 24 00:39:51 1997  Doug Evans  <dje@canuck.cygnus.com>
2777
2778         * configure: Regenerated to track ../common/aclocal.m4 changes.
2779
2780 Wed Apr 23 17:32:19 1997  Doug Evans  <dje@canuck.cygnus.com>
2781
2782         * tconfig.in (SIM_HAVE_BIENDIAN): Define.
2783
2784 Mon Apr 21 17:16:13 1997  Gavin Koch  <gavin@cygnus.com>
2785
2786         * gencode.c (build_instruction): DIV instructions: check
2787         for division by zero and integer overflow before using
2788         host's division operation.
2789
2790 Thu Apr 17 03:18:14 1997  Doug Evans  <dje@canuck.cygnus.com>
2791
2792         * Makefile.in (SIM_OBJS): Add sim-load.o.
2793         * interp.c: #include bfd.h.
2794         (target_byte_order): Delete.
2795         (sim_kind, myname, big_endian_p): New static locals.
2796         (sim_open): Set sim_kind, myname.  Move call to set_endianness to
2797         after argument parsing.  Recognize -E arg, set endianness accordingly.
2798         (sim_load): Return SIM_RC.  New arg abfd.  Call sim_load_file to
2799         load file into simulator.  Set PC from bfd.
2800         (sim_create_inferior): Return SIM_RC.  Delete arg start_address.
2801         (set_endianness): Use big_endian_p instead of target_byte_order.
2802
2803 Wed Apr 16 17:55:37 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2804
2805         * interp.c (sim_size): Delete prototype - conflicts with
2806         definition in remote-sim.h.  Correct definition.
2807
2808 Mon Apr  7 15:45:02 1997  Andrew Cagney  <cagney@kremvax.cygnus.com>
2809
2810         * configure: Regenerated to track ../common/aclocal.m4 changes.
2811         * config.in: Ditto.
2812
2813 Wed Apr  2 15:06:28 1997  Doug Evans  <dje@canuck.cygnus.com>
2814
2815         * interp.c (sim_open): New arg `kind'.
2816
2817         * configure: Regenerated to track ../common/aclocal.m4 changes.
2818
2819 Wed Apr  2 14:34:19 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
2820
2821         * configure: Regenerated to track ../common/aclocal.m4 changes.
2822
2823 Tue Mar 25 11:38:22 1997  Doug Evans  <dje@canuck.cygnus.com>
2824
2825         * interp.c (sim_open): Set optind to 0 before calling getopt.
2826
2827 Wed Mar 19 01:14:00 1997  Andrew Cagney  <cagney@kremvax.cygnus.com>
2828
2829         * configure: Regenerated to track ../common/aclocal.m4 changes.
2830
2831 Mon Mar 17 10:52:59 1997  Gavin Koch  <gavin@cetus.cygnus.com>
2832
2833         * interp.c : Replace uses of pr_addr with pr_uword64
2834         where the bit length is always 64 independent of SIM_ADDR.
2835         (pr_uword64) : added.
2836
2837 Mon Mar 17 15:10:07 1997  Andrew Cagney  <cagney@kremvax.cygnus.com>
2838
2839         * configure: Re-generate.
2840
2841 Fri Mar 14 10:34:11 1997  Michael Meissner  <meissner@cygnus.com>
2842
2843         * configure: Regenerate to track ../common/aclocal.m4 changes.
2844
2845 Thu Mar 13 12:51:36 1997  Doug Evans  <dje@canuck.cygnus.com>
2846
2847         * interp.c (sim_open): New SIM_DESC result.  Argument is now
2848         in argv form.
2849         (other sim_*): New SIM_DESC argument.
2850
2851 Mon Feb 24 22:47:14 1997  Dawn Perchik  <dawn@cygnus.com>
2852
2853         * interp.c: Fix printing of addresses for non-64-bit targets.
2854         (pr_addr): Add function to print address based on size.
2855
2856 Wed Feb 19 14:42:09 1997  Mark Alexander  <marka@cygnus.com>
2857
2858         * interp.c (simopen): Add support for LSI MiniRISC PMON vectors.
2859
2860 Thu Feb 13 14:08:30 1997  Ian Lance Taylor  <ian@cygnus.com>
2861
2862         * gencode.c (build_mips16_operands): Correct computation of base
2863         address for extended PC relative instruction.
2864
2865 Thu Feb  6 17:16:15 1997  Ian Lance Taylor  <ian@cygnus.com>
2866
2867         * interp.c (mips16_entry): Add support for floating point cases.
2868         (SignalException): Pass floating point cases to mips16_entry.
2869         (ValueFPR): Don't restrict fmt_single and fmt_word to even
2870         registers.
2871         (StoreFPR): Likewise.  Also, don't clobber fpr + 1 for fmt_single
2872         or fmt_word.
2873         (COP_LW): Pass fmt_word rather than fmt_uninterpreted to StoreFPR,
2874         and then set the state to fmt_uninterpreted.
2875         (COP_SW): Temporarily set the state to fmt_word while calling
2876         ValueFPR.
2877
2878 Tue Feb  4 16:48:25 1997  Ian Lance Taylor  <ian@cygnus.com>
2879
2880         * gencode.c (build_instruction): The high order may be set in the
2881         comparison flags at any ISA level, not just ISA 4.
2882
2883 Tue Feb  4 13:33:30 1997  Doug Evans  <dje@canuck.cygnus.com>
2884
2885         * Makefile.in (@COMMON_MAKEFILE_FRAG): Use
2886         COMMON_{PRE,POST}_CONFIG_FRAG instead.
2887         * configure.in: sinclude ../common/aclocal.m4.
2888         * configure: Regenerated.
2889
2890 Fri Jan 31 11:11:45 1997  Ian Lance Taylor  <ian@cygnus.com>
2891
2892         * configure: Rebuild after change to aclocal.m4.
2893
2894 Thu Jan 23 11:46:23 1997  Stu Grossman  (grossman@critters.cygnus.com)
2895
2896         * configure configure.in Makefile.in:  Update to new configure
2897         scheme which is more compatible with WinGDB builds.
2898         * configure.in:  Improve comment on how to run autoconf.
2899         * configure:  Re-run autoconf to get new ../common/aclocal.m4.
2900         * Makefile.in:  Use autoconf substitution to install common
2901         makefile fragment.
2902
2903 Wed Jan  8 12:39:03 1997  Jim Wilson  <wilson@cygnus.com>
2904
2905         * gencode.c (build_instruction): Use BigEndianCPU instead of
2906         ByteSwapMem.
2907
2908 Thu Jan 02 22:23:04 1997  Mark Alexander  <marka@cygnus.com>
2909
2910         * interp.c (sim_monitor): Make output to stdout visible in
2911         wingdb's I/O log window.
2912
2913 Tue Dec 31 07:04:00 1996  Mark Alexander  <marka@cygnus.com>
2914
2915         * support.h: Undo previous change to SIGTRAP
2916         and SIGQUIT values.
2917
2918 Mon Dec 30 17:36:06 1996  Ian Lance Taylor  <ian@cygnus.com>
2919
2920         * interp.c (store_word, load_word): New static functions.
2921         (mips16_entry): New static function.
2922         (SignalException): Look for mips16 entry and exit instructions.
2923         (simulate): Use the correct index when setting fpr_state after
2924         doing a pending move.
2925
2926 Sun Dec 29 09:37:18 1996  Mark Alexander  <marka@cygnus.com>
2927
2928         * interp.c: Fix byte-swapping code throughout to work on
2929         both little- and big-endian hosts.
2930
2931 Sun Dec 29 09:18:32 1996  Mark Alexander  <marka@cygnus.com>
2932
2933         * support.h: Make definitions of SIGTRAP and SIGQUIT consistent
2934         with gdb/config/i386/xm-windows.h.
2935
2936 Fri Dec 27 22:48:51 1996  Mark Alexander  <marka@cygnus.com>
2937
2938         * gencode.c (build_instruction): Work around MSVC++ code gen bug
2939         that messes up arithmetic shifts.
2940
2941 Fri Dec 20 11:04:05 1996  Stu Grossman  (grossman@critters.cygnus.com)
2942
2943         * support.h:  Use _WIN32 instead of __WIN32__.  Also add defs for
2944         SIGTRAP and SIGQUIT for _WIN32.
2945
2946 Thu Dec 19 14:07:27 1996  Ian Lance Taylor  <ian@cygnus.com>
2947
2948         * gencode.c (build_instruction) [MUL]: Cast operands to word64, to
2949         force a 64 bit multiplication.
2950         (build_instruction) [OR]: In mips16 mode, don't do anything if the
2951         destination register is 0, since that is the default mips16 nop
2952         instruction.
2953
2954 Mon Dec 16 14:59:38 1996  Ian Lance Taylor  <ian@cygnus.com>
2955
2956         * gencode.c (MIPS16_DECODE): SWRASP is I8, not RI.
2957         (build_endian_shift): Don't check proc64.
2958         (build_instruction): Always set memval to uword64.  Cast op2 to
2959         uword64 when shifting it left in memory instructions.  Always use
2960         the same code for stores--don't special case proc64.
2961
2962         * gencode.c (build_mips16_operands): Fix base PC value for PC
2963         relative operands.
2964         (build_instruction): Call JALDELAYSLOT rather than DELAYSLOT for a
2965         jal instruction.
2966         * interp.c (simJALDELAYSLOT): Define.
2967         (JALDELAYSLOT): Define.
2968         (INDELAYSLOT, INJALDELAYSLOT): Define.
2969         (simulate): Clear simJALDELAYSLOT when simDELAYSLOT is cleared.
2970
2971 Tue Dec 24 22:11:20 1996  Angela Marie Thomas (angela@cygnus.com)
2972
2973         * interp.c (sim_open): add flush_cache as a PMON routine
2974         (sim_monitor): handle flush_cache by ignoring it
2975
2976 Wed Dec 11 13:53:51 1996  Jim Wilson  <wilson@cygnus.com>
2977
2978         * gencode.c (build_instruction): Use !ByteSwapMem instead of
2979         BigEndianMem.
2980         * interp.c (CONFIG, config_EP_{mask,shift,D,DxxDxx, config_BE): Delete.
2981         (BigEndianMem): Rename to ByteSwapMem and change sense.
2982         (BigEndianCPU, sim_write, LoadMemory, StoreMemory): Change
2983         BigEndianMem references to !ByteSwapMem.
2984         (set_endianness): New function, with prototype.
2985         (sim_open): Call set_endianness.
2986         (sim_info): Use simBE instead of BigEndianMem.
2987         (xfer_direct_word, xfer_direct_long, swap_direct_word,
2988         swap_direct_long, xfer_big_word, xfer_big_long, xfer_little_word,
2989         xfer_little_long, swap_word, swap_long): Delete unnecessary MSC_VER
2990         ifdefs, keeping the prototype declaration.
2991         (swap_word): Rewrite correctly.
2992         (ColdReset): Delete references to CONFIG.  Delete endianness related
2993         code; moved to set_endianness.
2994
2995 Tue Dec 10 11:32:04 1996  Jim Wilson  <wilson@cygnus.com>
2996
2997         * gencode.c (build_instruction, case JUMP): Truncate PC to 32 bits.
2998         * interp.c (CHECKHILO): Define away.
2999         (simSIGINT): New macro.
3000         (membank_size): Increase from 1MB to 2MB.
3001         (control_c): New function.
3002         (sim_resume): Rename parameter signal to signal_number.  Add local
3003         variable prev.  Call signal before and after simulate.
3004         (sim_stop_reason): Add simSIGINT support.
3005         (sim_warning, sim_error, dotrace, SignalException): Define as stdarg
3006         functions always.
3007         (sim_warning): Delete call to SignalException.  Do call printf_filtered
3008         if logfh is NULL.
3009         (AddressTranslation): Add #ifdef DEBUG around debugging message and
3010         a call to sim_warning.
3011
3012 Wed Nov 27 11:53:50 1996  Ian Lance Taylor  <ian@cygnus.com>
3013
3014         * gencode.c (process_instructions): If ! proc64, skip DOUBLEWORD
3015         16 bit instructions.
3016
3017 Tue Nov 26 11:53:12 1996  Ian Lance Taylor  <ian@cygnus.com>
3018
3019         Add support for mips16 (16 bit MIPS implementation):
3020         * gencode.c (inst_type): Add mips16 instruction encoding types.
3021         (GETDATASIZEINSN): Define.
3022         (MIPS_DECODE): Add REG flag to dsllv, dsrav, and dsrlv.  Add
3023         jalx.  Add LEFT flag to mfhi and mflo.  Add RIGHT flag to mthi and
3024         mtlo.
3025         (MIPS16_DECODE): New table, for mips16 instructions.
3026         (bitmap_val): New static function.
3027         (struct mips16_op): Define.
3028         (mips16_op_table): New table, for mips16 operands.
3029         (build_mips16_operands): New static function.
3030         (process_instructions): If PC is odd, decode a mips16
3031         instruction.  Break out instruction handling into new
3032         build_instruction function.
3033         (build_instruction): New static function, broken out of
3034         process_instructions.  Check modifiers rather than flags for SHIFT
3035         bit count and m[ft]{hi,lo} direction.
3036         (usage): Pass program name to fprintf.
3037         (main): Remove unused variable this_option_optind.  Change
3038         ``*loptarg++'' to ``loptarg++''.
3039         (my_strtoul): Parenthesize && within ||.
3040         * interp.c (LoadMemory): Accept a halfword pAddr if vAddr is odd.
3041         (simulate): If PC is odd, fetch a 16 bit instruction, and
3042         increment PC by 2 rather than 4.
3043         * configure.in: Add case for mips16*-*-*.
3044         * configure: Rebuild.
3045
3046 Fri Nov 22 08:49:36 1996  Mark Alexander  <marka@cygnus.com>
3047
3048         * interp.c: Allow -t to enable tracing in standalone simulator.
3049         Fix garbage output in trace file and error messages.
3050
3051 Wed Nov 20 01:54:37 1996  Doug Evans  <dje@canuck.cygnus.com>
3052
3053         * Makefile.in: Delete stuff moved to ../common/Make-common.in.
3054         (SIM_{OBJS,EXTRA_CFLAGS,EXTRA_CLEAN}): Define.
3055         * configure.in: Simplify using macros in ../common/aclocal.m4.
3056         * configure: Regenerated.
3057         * tconfig.in: New file.
3058
3059 Tue Nov 12 13:34:00 1996  Dawn Perchik  <dawn@cygnus.com>
3060
3061         * interp.c: Fix bugs in 64-bit port.
3062         Use ansi function declarations for msvc compiler.
3063         Initialize and test file pointer in trace code.
3064         Prevent duplicate definition of LAST_EMED_REGNUM.
3065
3066 Tue Oct 15 11:07:06 1996  Mark Alexander  <marka@cygnus.com>
3067
3068         * interp.c (xfer_big_long): Prevent unwanted sign extension.
3069
3070 Thu Sep 26 17:35:00 1996  James G. Smith  <jsmith@cygnus.co.uk>
3071
3072         * interp.c (SignalException): Check for explicit terminating
3073         breakpoint value.
3074         * gencode.c: Pass instruction value through SignalException()
3075         calls for Trap, Breakpoint and Syscall.
3076
3077 Thu Sep 26 11:35:17 1996  James G. Smith  <jsmith@cygnus.co.uk>
3078
3079         * interp.c (SquareRoot): Add HAVE_SQRT check to ensure sqrt() is
3080         only used on those hosts that provide it.
3081         * configure.in: Add sqrt() to list of functions to be checked for.
3082         * config.in: Re-generated.
3083         * configure: Re-generated.
3084
3085 Fri Sep 20 15:47:12 1996  Ian Lance Taylor  <ian@cygnus.com>
3086
3087         * gencode.c (process_instructions): Call build_endian_shift when
3088         expanding STORE RIGHT, to fix swr.
3089         * support.h (SIGNEXTEND): If the sign bit is not set, explicitly
3090         clear the high bits.
3091         * interp.c (Convert): Fix fmt_single to fmt_long to not truncate.
3092         Fix float to int conversions to produce signed values.
3093
3094 Thu Sep 19 15:34:17 1996  Ian Lance Taylor  <ian@cygnus.com>
3095
3096         * gencode.c (MIPS_DECODE): Set UNSIGNED for multu instruction.
3097         (process_instructions): Correct handling of nor instruction.
3098         Correct shift count for 32 bit shift instructions. Correct sign
3099         extension for arithmetic shifts to not shift the number of bits in
3100         the type.  Fix 64 bit multiply high word calculation.  Fix 32 bit
3101         unsigned multiply.  Fix ldxc1 and friends to use coprocessor 1.
3102         Fix madd.
3103         * interp.c (CHECKHILO): Don't set HIACCESS, LOACCESS, or HLPC.
3104         It's OK to have a mult follow a mult.  What's not OK is to have a
3105         mult follow an mfhi.
3106         (Convert): Comment out incorrect rounding code.
3107
3108 Mon Sep 16 11:38:16 1996  James G. Smith  <jsmith@cygnus.co.uk>
3109
3110         * interp.c (sim_monitor): Improved monitor printf
3111         simulation. Tidied up simulator warnings, and added "--log" option
3112         for directing warning message output.
3113         * gencode.c: Use sim_warning() rather than WARNING macro.
3114
3115 Thu Aug 22 15:03:12 1996  Ian Lance Taylor  <ian@cygnus.com>
3116
3117         * Makefile.in (gencode): Depend upon gencode.o, getopt.o, and
3118         getopt1.o, rather than on gencode.c.  Link objects together.
3119         Don't link against -liberty.
3120         (gencode.o, getopt.o, getopt1.o): New targets.
3121         * gencode.c: Include <ctype.h> and "ansidecl.h".
3122         (AND): Undefine after including "ansidecl.h".
3123         (ULONG_MAX): Define if not defined.
3124         (OP_*): Don't define macros; now defined in opcode/mips.h.
3125         (main): Call my_strtoul rather than strtoul.
3126         (my_strtoul): New static function.
3127
3128 Wed Jul 17 18:12:38 1996  Stu Grossman  (grossman@critters.cygnus.com)
3129
3130         * gencode.c (process_instructions):  Generate word64 and uword64
3131         instead of `long long' and `unsigned long long' data types.
3132         * interp.c:  #include sysdep.h to get signals, and define default
3133         for SIGBUS.
3134         * (Convert):  Work around for Visual-C++ compiler bug with type
3135         conversion.
3136         * support.h:  Make things compile under Visual-C++ by using
3137         __int64 instead of `long long'.  Change many refs to long long
3138         into word64/uword64 typedefs.
3139
3140 Wed Jun 26 12:24:55 1996  Jason Molenda  (crash@godzilla.cygnus.co.jp)
3141
3142         * Makefile.in (bindir, libdir, datadir, mandir, infodir, includedir,
3143         INSTALL_PROGRAM, INSTALL_DATA): Use autoconf-set values.
3144         (docdir): Removed.
3145         * configure.in (AC_PREREQ): autoconf 2.5 or higher.
3146         (AC_PROG_INSTALL): Added.
3147         (AC_PROG_CC): Moved to before configure.host call.
3148         * configure: Rebuilt.
3149
3150 Wed Jun  5 08:28:13 1996  James G. Smith  <jsmith@cygnus.co.uk>
3151
3152         * configure.in: Define @SIMCONF@ depending on mips target.
3153         * configure: Rebuild.
3154         * Makefile.in (run): Add @SIMCONF@ to control simulator
3155         construction.
3156         * gencode.c: Change LOADDRMASK to 64bit memory model only.
3157         * interp.c: Remove some debugging, provide more detailed error
3158         messages, update memory accesses to use LOADDRMASK.
3159
3160 Mon Jun  3 11:55:03 1996  Ian Lance Taylor  <ian@cygnus.com>
3161
3162         * configure.in: Add calls to AC_CONFIG_HEADER, AC_CHECK_HEADERS,
3163         AC_CHECK_LIB, and AC_CHECK_FUNCS.  Change AC_OUTPUT to set
3164         stamp-h.
3165         * configure: Rebuild.
3166         * config.in: New file, generated by autoheader.
3167         * interp.c: Include "config.h".  Include <stdlib.h>, <string.h>,
3168         and <strings.h> if they exist.  Replace #ifdef sun with #ifdef
3169         HAVE_ANINT and HAVE_AINT, as appropriate.
3170         * Makefile.in (run): Use @LIBS@ rather than -lm.
3171         (interp.o): Depend upon config.h.
3172         (Makefile): Just rebuild Makefile.
3173         (clean): Remove stamp-h.
3174         (mostlyclean): Make the same as clean, not as distclean.
3175         (config.h, stamp-h): New targets.
3176
3177 Fri May 10 00:41:17 1996  James G. Smith  <jsmith@cygnus.co.uk>
3178
3179         * interp.c (ColdReset): Fix boolean test. Make all simulator
3180         globals static.
3181
3182 Wed May  8 15:12:58 1996  James G. Smith  <jsmith@cygnus.co.uk>
3183
3184         * interp.c (xfer_direct_word, xfer_direct_long,
3185         swap_direct_word, swap_direct_long, xfer_big_word,
3186         xfer_big_long, xfer_little_word, xfer_little_long,
3187         swap_word,swap_long): Added.
3188         * interp.c (ColdReset): Provide function indirection to
3189         host<->simulated_target transfer routines.
3190         * interp.c (sim_store_register, sim_fetch_register): Updated to
3191         make use of indirected transfer routines.
3192
3193 Fri Apr 19 15:48:24 1996  James G. Smith  <jsmith@cygnus.co.uk>
3194
3195         * gencode.c (process_instructions): Ensure FP ABS instruction
3196         recognised.
3197         * interp.c (AbsoluteValue): Add routine. Also provide simple PMON
3198         system call support.
3199
3200 Wed Apr 10 09:51:38 1996  James G. Smith  <jsmith@cygnus.co.uk>
3201
3202         * interp.c (sim_do_command): Complain if callback structure not
3203         initialised.
3204
3205 Thu Mar 28 13:50:51 1996  James G. Smith  <jsmith@cygnus.co.uk>
3206
3207         * interp.c (Convert): Provide round-to-nearest and round-to-zero
3208         support for Sun hosts.
3209         * Makefile.in (gencode): Ensure the host compiler and libraries
3210         used for cross-hosted build.
3211
3212 Wed Mar 27 14:42:12 1996  James G. Smith  <jsmith@cygnus.co.uk>
3213
3214         * interp.c, gencode.c: Some more (TODO) tidying.
3215
3216 Thu Mar  7 11:19:33 1996  James G. Smith  <jsmith@cygnus.co.uk>
3217
3218         * gencode.c, interp.c: Replaced explicit long long references with
3219         WORD64HI, WORD64LO, SET64HI and SET64LO macro calls.
3220         * support.h (SET64LO, SET64HI): Macros added.
3221
3222 Wed Feb 21 12:16:21 1996  Ian Lance Taylor  <ian@cygnus.com>
3223
3224         * configure: Regenerate with autoconf 2.7.
3225
3226 Tue Jan 30 08:48:18 1996  Fred Fish  <fnf@cygnus.com>
3227
3228         * interp.c (LoadMemory): Enclose text following #endif in /* */.
3229         * support.h: Remove superfluous "1" from #if.
3230         * support.h (CHECKSIM): Remove stray 'a' at end of line.
3231
3232 Mon Dec  4 11:44:40 1995  Jamie Smith  <jsmith@cygnus.com>
3233
3234         * interp.c (StoreFPR): Control UndefinedResult() call on
3235         WARN_RESULT manifest.
3236
3237 Fri Dec  1 16:37:19 1995  James G. Smith  <jsmith@cygnus.co.uk>
3238
3239         * gencode.c: Tidied instruction decoding, and added FP instruction
3240         support.
3241
3242         * interp.c: Added dineroIII, and BSD profiling support. Also
3243         run-time FP handling.
3244
3245 Sun Oct 22 00:57:18 1995  James G. Smith  <jsmith@pasanda.cygnus.co.uk>
3246
3247         * Changelog, Makefile.in, README.Cygnus, configure, configure.in,
3248         gencode.c, interp.c, support.h: created.