sim/mips/ChangeLog

   1 1999-02-05  Frank Ch. Eigler  <fche@cygnus.com>
   2
   3         * dv-tx3904sio.c (tx3904sio_tickle): After a polled I/O from the
   4         CPU, start periodic background I/O polls.
   5         (tx3904sio_poll): New function: periodic I/O poller.
   6
   7 start-sanitize-sky
   8 1999-01-04  Frank Ch. Eigler  <fche@cygnus.com>
   9
  10         * sim-main.h (SIM_CPU_EXCEPTION_*): #undef hooks for TARGET_SKY.
  11         * interp.c (signal_exception): Add BreakPoint handling case.
  12         Remove inactive SIM_CPU_EXCEPTION_TRIGGER call.
  13
  14 end-sanitize-sky
  15 1998-12-30  Frank Ch. Eigler  <fche@cygnus.com>
  16
  17         * mips.igen (BREAK): Call signal_exception instead of sim_engine_halt.
  18 start-sanitize-sky
  19         * interp.c (signal_exception): Call SIM_CPU_EXCEPTION_TRIGGER hook.
  20         Call sim_engine_halt on BreakPoint.
  21 end-sanitize-sky
  22
  23 Tue Dec 29 16:03:53 1998  Rainer Orth  <ro@TechFak.Uni-Bielefeld.DE>
  24
  25         * configure.in, configure (mips64vr5*-*-*): Added missing ;; in
  26         case statement.
  27
  28 1998-12-29  Frank Ch. Eigler  <fche@cygnus.com>
  29
  30         * interp.c (sim_open): Allocate jm3904 memory in smaller chunks.
  31         (load_word): Call SIM_CORE_SIGNAL hook on error.
  32         (signal_exception): Call SIM_CPU_EXCEPTION_TRIGGER hook before
  33         starting.  For exception dispatching, pass PC instead of NULL_CIA.
  34         (decode_coproc): Use COP0_BADVADDR to store faulting address.
  35         * sim-main.h (COP0_BADVADDR): Define.
  36         (SIM_CORE_SIGNAL): Define hook to call mips_core_signal.
  37         (SIM_CPU_EXCEPTION*): Define hooks to call mips_cpu_exception*().
  38         (_sim_cpu): Add exc_* fields to store register value snapshots.
  39         * mips.igen (*): Replace memory-related SignalException* calls
  40         with references to SIM_CORE_SIGNAL hook.
  41
  42         * dv-tx3904irc.c (tx3904irc_port_event): printf format warning
  43         fix.
  44         * sim-main.c (*): Minor warning cleanups.
  45
  46 1998-12-24  Gavin Romig-Koch  <gavin@cygnus.com>
  47
  48         * m16.igen (DADDIU5): Correct type-o.
  49
  50 Mon Dec 21 10:34:48 1998  Andrew Cagney  <cagney@chook>
  51
  52         * mips.igen (do_ddiv, do_ddivu): Pacify GCC. Update hi/lo via tmp
  53         variables.
  54
  55 start-sanitize-vr4xxx
  56 1998-12-17  Gavin Romig-Koch  <gavin@cygnus.com>
  57
  58         * vr4run.c (sim_engine_run): Enable the 4111.
  59
  60 end-sanitize-vr4xxx
  61 Wed Dec 16 18:20:28 1998  Andrew Cagney  <cagney@chook>
  62
  63         * Makefile.in (SIM_EXTRA_CFLAGS): No longer need to add .../newlib
  64         to include path.
  65         (interp.o): Add dependency on itable.h
  66         (oengine.c, gencode): Delete remaining references.
  67         (BUILT_SRC_FROM_GEN): Clean up.
  68 start-sanitize-vr4xxx
  69         (SIM_HACK_ALL): Define.
  70         (hack, libhack.a): Do not build.
  71 end-sanitize-vr4xxx
  72
  73 1998-12-16  Gavin Romig-Koch  <gavin@cygnus.com>
  74
  75         * vr4run.c: New.
  76         * Makefile.in (SIM_HACK_OBJ,HACK_OBJS,HACK_GEN_SRCS,libhack.a,
  77         tmp-hack,tmp-m32-hack,tmp-m16-hack,tmp-itable-hack,
  78         tmp-run-hack) : New.
  79 start-sanitize-vr4xxx
  80         * configure.in (mips64vr4xxx): Switch to using the HACK
  81         generator.  Set TARGET_ENABLE_FR.
  82 end-sanitize-vr4xxx
  83         * m16.igen (LD,DADDIU,DADDUI5,DADJSP,DADDIUSP,DADDI,DADDU,DSUBU,
  84         DSLL,DSRL,DSRA,DSLLV,DSRAV,DMULT,DMULTU,DDIV,DDIVU,JALX32,JALX):
  85         Drop the "64" qualifier to get the HACK generator working.
  86         Use IMMEDIATE rather than IMMED.  Use SHAMT rather than SHIFT.
  87         Add vr4121 where necessary.
  88         * mips.igen (do_daddiu,do_ddiv,do_divu): Remove the 64-only
  89         qualifier to get the hack generator working.
  90         (do_dsll,do_dsllv,do_dsra,do_dsrl,do_dsrlv): New.
  91         (DSLL): Use do_dsll.
  92         (DSLLV): Use do_dsllv.
  93         (DSRA): Use do_dsra.
  94         (DSRL): Use do_dsrl.
  95         (DSRLV): Use do_dsrlv.
  96         (BC1): Move *vr4100 to get the HACK generator working.
  97 start-sanitize-vr4xxx
  98         (BC1): Move *vr4121 to get the HACK generator working.
  99 end-sanitize-vr4xxx
 100         (CxC1, DMxC1, MxC1,MACCU,MACCHI,MACCHIU): Rename to
 101         get the HACK generator working.
 102 start-sanitize-vr4320
 103         * vr.igen: Add *vr4320 where missing.
 104 end-sanitize-vr4320
 105         (MACC) Rename to get the HACK generator working.
 106         (DMACC,MACCS,DMACCS): Add the 64.
 107
 108 start-sanitize-vr4320
 109 1998-12-14  Gavin Romig-Koch  <gavin@cygnus.com>
 110
 111         * vr.igen (Low32Bits): Add vr4320.
 112
 113 end-sanitize-vr4320
 114 start-sanitize-vr4xxx
 115 1998-12-14  Gavin Romig-Koch  <gavin@cygnus.com>
 116
 117         * configure.in: Add support for 5xxx and "el".
 118         * configure: Rebuild.
 119
 120 1998-12-13  Gavin Romig-Koch  <gavin@cygnus.com>
 121
 122         * configure.in,mips.igen,vr.igen: Add vr4121.
 123         * configure: Rebuilt.
 124
 125 end-sanitize-vr4xxx
 126 1998-12-12  Gavin Romig-Koch  <gavin@cygnus.com>
 127
 128 start-sanitize-vr4xxx
 129         * configure.in (mips64vr4xxx): Enable TARGET_ENABLE_FR.
 130         Set mips_fpu, and mips_fpu_bitsize.
 131         Set sim_gen, and sim_igen_machine.
 132         * configure: Rebuild.
 133
 134 end-sanitize-vr4xxx
 135         * mips.igen (BC1): Renamed to BC1a and BC1b to avoid conflicts.
 136         * sim-main.h (SizeFGR): Handle TARGET_ENABLE_FR.
 137
 138 1998-12-11  Gavin Romig-Koch  <gavin@cygnus.com>
 139
 140     * mips/interp.c (DEBUG): Cleanups.
 141
 142 1998-12-10  Frank Ch. Eigler  <fche@cygnus.com>
 143
 144         * dv-tx3904sio.c (tx3904sio_io_read_buffer): Endianness fixes.
 145         (tx3904sio_tickle): fflush after a stdout character output.
 146
 147 1998-12-03  Frank Ch. Eigler  <fche@cygnus.com>
 148
 149         * interp.c (sim_close): Uninstall modules.
 150
 151 start-sanitize-sky
 152 Tue Dec  1 18:40:30 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 153
 154         * sky-libvpe.c (FCmp): Abort when no result.
 155
 156 end-sanitize-sky
 157 Wed Nov 25 13:41:03 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 158
 159         * sim-main.h, interp.c (sim_monitor): Change to global
 160         function.
 161
 162 Wed Nov 25 17:33:24 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 163
 164         * configure.in (vr4100): Only include vr4100 instructions in
 165         simulator.
 166         * configure: Re-generate.
 167         * m16.igen (*): Tag all mips16 instructions as also being vr4100.
 168
 169 Mon Nov 23 18:20:36 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 170
 171         * Makefile.in (SIM_CFLAGS): Do not define WITH_IGEN.
 172         * sim-main.h, sim-main.c, interp.c: Delete #if WITH_IGEN keeping
 173         true alternative.
 174
 175         * configure.in (sim_default_gen, sim_use_gen): Replace with
 176         sim_gen.
 177         (--enable-sim-igen): Delete config option. Always using IGEN.
 178         * configure: Re-generate.
 179
 180         * Makefile.in (gencode): Kill, kill, kill.
 181         * gencode.c: Ditto.
 182
 183 Mon Nov 23 18:07:36 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 184
 185         * configure.in: Configure mips64vr4100-elf nee mips64vr41* as a 64
 186         bit mips16 igen simulator.
 187         * configure: Re-generate.
 188
 189         * mips.igen (check_div_hilo, check_mult_hilo, check_mf_hilo): Mark
 190         as part of vr4100 ISA.
 191         * vr.igen: Mark all instructions as 64 bit only.
 192
 193 Mon Nov 23 17:07:37 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 194
 195         * interp.c (get_cell, sim_monitor, fetch_str, CoProcPresent):
 196         Pacify GCC.
 197
 198 start-sanitize-tx19
 199 Mon Nov 23 16:51:02 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 200
 201         * configure.in (tx19): Reconize target mips-tx19-elf.
 202         * configure: Re-generate.
 203
 204 end-sanitize-tx19
 205 Mon Nov 23 13:23:40 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 206
 207         * configure.in: Configure mips-lsi-elf nee mips*lsi* as a
 208         mipsIII/mips16 igen simulator.  Fix sim_gen VS sim_igen typos.
 209         * configure: Re-generate.
 210
 211         * m16.igen (BREAK): Define breakpoint instruction.
 212         (JALX32): Mark instruction as mips16 and not r3900.
 213         * mips.igen (C.cond.fmt): Fix typo in instruction format.
 214
 215         * sim-main.h (PENDING_FILL): Wrap C statements in do/while.
 216
 217 start-sanitize-r5900
 218 Mon Nov 16 11:44:24 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 219
 220         * r5900.igen (CVT.W.S): Always round towards zero.
 221
 222 end-sanitize-r5900
 223 Sat Nov  7 09:54:38 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 224
 225         * gencode.c (build_instruction - BREAK): For MIPS16, handle BREAK
 226         insn as a debug breakpoint.
 227
 228         * sim-main.h (PENDING_SLOT_BIT): Fix, was incorrectly defined as
 229         pending.slot_size.
 230         (PENDING_SCHED): Clean up trace statement.
 231         (PENDING_SCHED): Increment PENDING_IN and PENDING_TOTAL.
 232         (PENDING_FILL): Delay write by only one cycle.
 233         (PENDING_FILL): For FSRs, write fmt_uninterpreted to FPR_STATE.
 234
 235         * sim-main.c (pending_tick): Clean up trace statements. Add trace
 236         of pending writes.
 237         (pending_tick): Fix sizes in switch statements, 4 & 8 instead of
 238         32 & 64.
 239         (pending_tick): Move incrementing of index to FOR statement.
 240         (pending_tick): Only update PENDING_OUT after a write has occured.
 241
 242         * configure.in: Add explicit mips-lsi-* target.  Use gencode to
 243         build simulator.
 244         * configure: Re-generate.
 245
 246         * interp.c (sim_engine_run OLD): Delete explicit call to
 247         PENDING_TICK. Now called via ENGINE_ISSUE_PREFIX_HOOK.
 248
 249 start-sanitize-r5900
 250 Wed Nov 11 16:53:57 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 251
 252         * r5900.igen (RSQRT): Set both I/SI and D/SD when div-0.
 253
 254 Thu Nov  5 10:29:42 EST 1998  Frank Ch. Eigler  <fche@cygnus.com>
 255
 256         * r5900.igen (r59fp_opdiv): Correct erroneous FGR[FD] reference.
 257
 258 Thu Nov  5 19:40:12 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 259
 260         * r5900.igen (DIV): Do not clear clear SO/SU when already set.
 261
 262         * r5900.igen (RSQRT.S): Do not compute 1/srqt(abs(T)) when T
 263         negative, compute S/sqrt(abs(T)) instead.  Correctly set FCSR
 264         bits.
 265
 266         * r5900.igen (RSQRT.S): Handle overflow/underflow better. Check
 267         sign of FT not FS.
 268         (r59fp_store): Clarify "bad value" abort messages.
 269
 270 end-sanitize-r5900
 271 Sat Oct 30 09:49:10 1998  Frank Ch. Eigler  <fche@cygnus.com>
 272
 273         * dv-tx3904cpu.c (deliver_tx3904cpu_interrupt): Add dummy
 274         interrupt level number to match changed SignalExceptionInterrupt
 275         macro.
 276
 277 start-sanitize-sky
 278 Thu Oct 29 12:47:46 1998  Frank Ch. Eigler  <fche@cygnus.com>
 279
 280         * sim-main.c (tlb_try_match): Include physical address in
 281         scratchpad non-mapping warning.
 282
 283 end-sanitize-sky
 284 start-sanitize-r5900
 285 Thu Oct 29 11:06:30 EST 1998  Frank Ch. Eigler <fche@cygnus.com>
 286
 287         * r5900.igen: Fix PSRLVW, MULTU1, PADSBH instructions,
 288         as per customer patch.
 289
 290 end-sanitize-r5900
 291 Fri Oct  9 18:02:25 1998  Doug Evans  <devans@canuck.cygnus.com>
 292
 293         * interp.c: #include "itable.h" if WITH_IGEN.
 294         (get_insn_name): New function.
 295         (sim_open): Initialize CPU_INSN_NAME,CPU_MAX_INSNS.
 296         * sim-main.h (MAX_INSNS,INSN_NAME): Delete.
 297
 298 start-sanitize-sky
 299 Tue Sep 22 10:35:37 1998  Frank Ch. Eigler  <fche@cygnus.com>
 300
 301         * sim-main.c (tlb_try_match): Specially match virtual
 302         pages mapped to scratchpad RAM, an unimplemented feature.
 303
 304 end-sanitize-sky
 305 start-sanitize-r5900
 306 Fri Sep 18 11:31:16 1998  Frank Ch. Eigler <fche@cygnus.com>
 307
 308         * r5900.igen (prot3w): Correct rotation sequence; patch
 309         from customer.
 310
 311 end-sanitize-r5900
 312 Mon Sep 14 12:36:44 1998  Frank Ch. Eigler  <fche@cygnus.com>
 313
 314         * configure: Rebuilt to inhale new common/aclocal.m4.
 315
 316 start-sanitize-r5900
 317 Thu Sep 10 11:50:54 1998  Doug Evans  <devans@canuck.cygnus.com>
 318
 319         * r5900.igen (plzcw): Make `i' signed.
 320
 321 Wed Sep  9 15:02:10 1998  Doug Evans  <devans@canuck.cygnus.com>
 322
 323         * sim-main.h (COP0_COUNT,COP0_COMPARE,status_IM7): New macros.
 324         * sky-engine.c (cpu_issue): Increment COP0_COUNT and signal an
 325         interrupt if == COP0_COMPARE and interrupt masks/enables allow it.
 326         * interp.c (signal_exception, sky version): Handle INT 2.
 327
 328 Wed Sep 9 11:28:20 1998  Ron Unrau <runrau@cygnus.com>
 329
 330         * sim-main.h: track COP0 registers
 331         * interp.c (sim_{fetch,store}_register): read/write COP0 registers
 332
 333 Fri Sep  4 10:37:57 1998  Frank Ch. Eigler  <fche@cygnus.com>
 334
 335         * r5900.igen (mtsab): Correct typo in input register.
 336
 337         * sim-main.h (TMP_*): New macros for accessing local 128-bit
 338         temporary for multimedia instructions.
 339         * r5900.igen (*): Convert most instructions to use new TMP
 340         macros to store output result during computation.
 341
 342 end-sanitize-r5900
 343 Tue Sep  1 15:39:18 1998  Frank Ch. Eigler  <fche@cygnus.com>
 344
 345         * dv-tx3904sio.c: Include sim-assert.h.
 346
 347 Tue Aug 25 12:49:46 1998  Frank Ch. Eigler  <fche@cygnus.com>
 348
 349         * dv-tx3904sio.c: New file: tx3904 serial I/O module.
 350         * configure.in: Add dv-tx3904sio, dv-sockser for tx39 target.
 351         Reorganize target-specific sim-hardware checks.
 352         * configure: rebuilt.
 353         * interp.c (sim_open): For tx39 target boards, set
 354         OPERATING_ENVIRONMENT, add tx3904sio devices.
 355         * tconfig.in: For tx39 target, set SIM_HANDLES_LMA for loading
 356         ROM executables.  Install dv-sockser into sim-modules list.
 357
 358         * dv-tx3904irc.c: Compiler warning clean-up.
 359         * dv-tx3904tmr.c: Compiler warning clean-up.  Remove particularly
 360         frequent hw-trace messages.
 361
 362 start-sanitize-sky
 363 Tue Aug 11 13:52:16 1998  Frank Ch. Eigler  <fche@cygnus.com>
 364
 365         * interp.c (signal_exception): Set IP3 bit in CAUSE on
 366         sky interrupt.
 367
 368 end-sanitize-sky
 369 Fri Jul 31 18:14:16 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 370
 371         * vr.igen (MulAcc): Identify as a vr4100 specific function.
 372
 373 Sat Jul 25 16:03:14 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 374
 375         * Makefile.in (IGEN_INCLUDE): Add vr.igen.
 376
 377         * vr.igen: New file.
 378         (MAC/MADD16, DMAC/DMADD16): Implement using code from gencode.c.
 379         * mips.igen: Define vr4100 model. Include vr.igen.
 380 start-sanitize-cygnus
 381         * vr5400.igen: Move instructions to vr.igen
 382         * Makefile.in (IGEN_INCLUDE): Remove vr5400.igen.
 383 end-sanitize-cygnus
 384 start-sanitize-vr4320
 385         * vr4320.igen: Move instructions to vr.igen.
 386         * Makefile.in (IGEN_INCLUDE): Remove vr5320.igen.
 387
 388 end-sanitize-vr4320
 389 start-sanitize-sky
 390 Fri Jul 24 16:01:03 1998  Ian Carmichael  <iancarm@cygnus.com>
 391
 392         * interp.c (MONITOR_SIZE): Make 1MB monitor for SKY.
 393         * mips.igen (BREAK): Fix 0xffff2 monitor call.  Slightly less
 394         confusing message if not enough --load-next options appear.
 395
 396         * sky-pke.h (VUx_MEMx_SRCADDR_START): Move to 0x19800000 range.
 397         * sim-main.c (GDB_COMM_AREA): Move to 0x19810000.
 398         * sky-gdb.c (init_fifo_bp_cache): Use VIO_BASE when reading GDB area.
 399         (resume_handler): Same.
 400         (suspend_handler): Same.
 401
 402 Wed Jul 22 13:04:13 1998  Frank Ch. Eigler  <fche@cygnus.com>
 403
 404         * mips.igen (break): Implement LOAD_INSTRUCTION ("break 0xffff1")
 405         to trigger multi-phase load.
 406
 407         * sim-main.c: Include sim-assert.h for ASSERT macro.
 408         * sim-main.h (PRINTF_INSTRUCTION): Correct bit pattern for
 409         "break 0xffff2".
 410
 411 Tue Jul 21 18:37:36 1998  Ian Carmichael  <iancarm@cygnus.com>
 412
 413         MMU support.
 414         * interp.c (sim_open): Initialize TLB.
 415         * interp.c (signal_exceptions): New 5900 handling.
 416         * r5900.igen (TLBWR, TLBWI, TLBR, TLBP): Make these work.
 417         * sim-main.c (tlb_try_match, tlb_lookup): New functions.
 418         (address_translation): Use the TLB.
 419         * sim-main.h (r4000_tlb_entry_t): New type.
 420         (TLB_*): New constants.
 421         (COP0_*): New register names.
 422
 423         Sky character I/O device.
 424         * sky-psio.c: New file.
 425         * sky-psio.h: New file.
 426         * Makefile.in: Add sky-psio.o.
 427
 428 end-sanitize-sky
 429 start-sanitize-r5900
 430 Tue Jul 14 16:10:45 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 431
 432         * r5900.igen (r59fp_overflow): Replace argument ANS with argument
 433         SIGN_P.
 434         (r59fp_zero): Ditto.
 435         (r59fp_store): Update calls.
 436         (DIV.S): Compute 0/0 sign from inputs. Ditto for X/0.
 437
 438 end-sanitize-r5900
 439 start-sanitize-branchbug4011
 440 Mon Jun 29 09:31:27 1998  Gavin Koch  <gavin@cygnus.com>
 441
 442         * interp.c (OPTION_BRANCH_BUG_4011): Add.
 443         (mips_option_handler): Handle OPTION_BRANCH_BUG_4011.
 444         (mips_options): Define the option.
 445         * mips.igen (check_4011_branch_bug): New.
 446         (mark_4011_branch_bug): New.
 447         (all branch insn): Call mark_branch_bug, and check_branch_bug.
 448         * sim-main.h (branchbug4011_option, branchbug4011_last_target,
 449         branchbug4011_last_cia, BRANCHBUG4011_OPTION,
 450         BRANCHBUG4011_LAST_TARGET, BRANCHBUG4011_LAST_CIA,
 451         check_branch_bug, mark_branch_bug): Define.
 452
 453 end-sanitize-branchbug4011
 454 Mon Jun 29 09:21:07 1998  Gavin Koch  <gavin@cygnus.com>
 455
 456         * mips.igen (check_mf_hilo): Correct check.
 457
 458 start-sanitize-r5900
 459 Fri Jun 19 14:44:46 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 460
 461         * sim-main.h (NR_COP0_GPR, COP0_GPR, cop0_gpr, NR_COP0_BP,
 462         COP0_BP, cop0_bp, NR_COP0_P, COP0_P, cop0_p): Add 32 COP0 general
 463         purpose registers, add 8 COP0 break-point registers, add 64 COP0
 464         performance registers.
 465
 466         * interp.c (decode_coproc): Accept any MTC0/MFC0, MTBP/MFBP, MTP*
 467         MFP* instructions.  Just transfer value to/from corresponding
 468         register.
 469
 470         * r5900.igen (BC0F, BC0FL, BC0T, BC0TL): Implement, assume COP0
 471         status is always true.
 472         (CACHE, TLBP, TPGWI, TLBWR): Treat as NOP.
 473         (EI, DI): Set/clear Status-EIE bit.
 474
 475 end-sanitize-r5900
 476 start-sanitize-sky
 477 Fri Jun 19 14:44:46 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 478
 479         * mips.igen (BC0F, BC0FL, BC0T, BC0TL): Move to sky code to
 480         r5900.igen.
 481
 482 end-sanitize-sky
 483 Wed Jun 17 12:20:49 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 484
 485 start-sanitize-sky
 486         * sky-vu.c (vu0_read_cop2_register, vu0_write_cop2_register): Call
 487         ASSERT not assert.
 488         * sky-gdb.c: Include "sim-assert.h".
 489
 490 end-sanitize-sky
 491         * sim-main.h (interrupt_event): Add prototype.
 492
 493         * dv-tx3904tmr.c (tx3904tmr_io_write_buffer): Delete unused
 494         register_ptr, register_value.
 495         (deliver_tx3904tmr_tick): Fix types passed to printf fmt.
 496
 497         * sim-main.h (tracefh): Make extern.
 498
 499 Tue Jun 16 14:39:00 1998  Frank Ch. Eigler  <fche@cygnus.com>
 500
 501         * dv-tx3904tmr.c: Deschedule timer event after dispatching.
 502         Reduce unnecessarily high timer event frequency.
 503         * dv-tx3904cpu.c: Ditto for interrupt event.
 504
 505 start-sanitize-sky
 506 Tue Jun 16 14:12:09 1998  Frank Ch. Eigler  <fche@cygnus.com>
 507
 508         * interp.c (decode_coproc): Removed COP2 branches.
 509         * r5900.igen: Moved COP2 branch instructions here.
 510         * mips.igen: Restricted COPz == COP2 bit pattern to
 511         exclude COP2 branches.
 512
 513 end-sanitize-sky
 514 Wed Jun 10 13:22:32 1998  Frank Ch. Eigler  <fche@cygnus.com>
 515
 516         * interp.c (decode_coproc): For TX39, add stub COP0 register #7,
 517         to allay warnings.
 518         (interrupt_event): Made non-static.
 519
 520         * dv-tx3904tmr.c (deliver_tx3904tmr_tick): Correct accidental
 521         interchange of configuration values for external vs. internal
 522         clock dividers.
 523
 524 Tue Jun  9 12:46:24 1998  Ian Carmichael  <iancarm@cygnus.com>
 525
 526         * mips.igen (BREAK): Moved code to here for
 527         simulator-reserved break instructions.
 528         * gencode.c (build_instruction): Ditto.
 529         * interp.c (signal_exception): Code moved from here.  Non-
 530         reserved instructions now use exception vector, rather
 531         than halting sim.
 532         * sim-main.h: Moved magic constants to here.
 533
 534 Tue Jun  9 12:29:50 1998  Frank Ch. Eigler  <fche@cygnus.com>
 535
 536         * dv-tx3904cpu.c (deliver_*_interrupt,*_port_event): Set the CAUSE
 537         register upon non-zero interrupt event level, clear upon zero
 538         event value.
 539         * dv-tx3904irc.c (*_port_event): Handle deactivated interrupt signal
 540         by passing zero event value.
 541         (*_io_{read,write}_buffer): Endianness fixes.
 542         * dv-tx3904tmr.c (*_io_{read,write}_buffer): Endianness fixes.
 543         (deliver_*_tick): Reduce sim event interval to 75% of count interval.
 544
 545         * interp.c (sim_open): Added jmr3904pal board type that adds PAL-based
 546         serial I/O and timer module at base address 0xFFFF0000.
 547
 548 Tue Jun  9 11:52:29 1998  Gavin Koch  <gavin@cygnus.com>
 549
 550         * mips.igen (SWC1) : Correct the handling of ReverseEndian
 551         and BigEndianCPU.
 552
 553 Tue Jun  9 11:40:57 1998  Gavin Koch  <gavin@cygnus.com>
 554
 555         * configure.in (mips_fpu_bitsize) : Set this correctly for 32-bit mips
 556         parts.
 557         * configure: Update.
 558
 559 Thu Jun  4 15:37:33 1998  Frank Ch. Eigler  <fche@cygnus.com>
 560
 561         * dv-tx3904tmr.c: New file - implements tx3904 timer.
 562         * dv-tx3904{irc,cpu}.c: Mild reformatting.
 563         * configure.in: Include tx3904tmr in hw_device list.
 564         * configure: Rebuilt.
 565         * interp.c (sim_open): Instantiate three timer instances.
 566         Fix address typo of tx3904irc instance.
 567
 568 start-sanitize-r5900
 569 Thu Jun  4 16:47:27 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 570
 571         * mips.igen (check_mt_hilo): 2.1 of r5900 spec stalls for HILO.
 572         Select corresponding check_mt_hilo function.
 573         (check_mult_hilo, check_div_hilo, check_mf_hilo, check_mt_hilo):
 574         Ditto.
 575
 576         * r5900.igen (check_mult_hilo_hi1lo1, check_div_hilo_hi1lo1): Mark
 577         as r5900 specific.
 578
 579 end-sanitize-r5900
 580 Tue Jun  2 15:48:02 1998  Ian Carmichael  <iancarm@cygnus.com>
 581
 582         * interp.c (signal_exception): SystemCall exception now uses
 583         the exception vector.
 584
 585 Mon Jun  1 18:18:26 1998  Frank Ch. Eigler  <fche@cygnus.com>
 586
 587         * interp.c (decode_coproc): For TX39, add stub COP0 register #3,
 588         to allay warnings.
 589
 590 start-sanitize-r5900
 591 Mon Jun  1 10:28:25 1998  Jeffrey A Law  (law@cygnus.com)
 592
 593         * r5900.igen (rsqrt.s): Update based on r5900 ISA manual version 2.1.
 594         (sqrt.s): Likewise.
 595
 596 end-sanitize-r5900
 597 Fri May 29 11:40:39 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 598
 599         * configure.in (sim_igen_filter): Match mips*tx39 not mipst*tx39.
 600
 601 Mon May 25 20:47:45 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 602
 603         * dv-tx3904cpu.c, dv-tx3904irc.c: Rename *_callback to *_method.
 604
 605         * dv-tx3904cpu.c, dv-tx3904irc.c: Include hw-main.h and
 606         sim-main.h. Declare a struct hw_descriptor instead of struct
 607         hw_device_descriptor.
 608
 609 Mon May 25 12:41:38 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 610
 611         * mips.igen (do_store_left, do_load_left): Compute nr of left and
 612         right bits and then re-align left hand bytes to correct byte
 613         lanes.  Fix incorrect computation in do_store_left when loading
 614         bytes from second word.
 615
 616 Fri May 22 13:34:20 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 617
 618         * configure.in (SIM_AC_OPTION_HARDWARE): Only enable when tx3904.
 619         * interp.c (sim_open): Only create a device tree when HW is
 620         enabled.
 621
 622         * dv-tx3904irc.c (tx3904irc_finish): Pacify GCC.
 623         * interp.c (signal_exception): Ditto.
 624
 625 Thu May 21 14:24:11 1998  Gavin Koch  <gavin@cygnus.com>
 626
 627         * gencode.c: Mark BEGEZALL as LIKELY.
 628
 629 Thu May 21 18:57:19 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 630
 631         * sim-main.h (ALU32_END): Sign extend 32 bit results.
 632         * mips.igen (ADD, SUB, ADDI, DADD, DSUB): Trace.
 633
 634 start-sanitize-r5900
 635 Thu May 21 17:15:39 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 636
 637         * interp.c (sim_fetch_register): Convert internal r5900 regs to
 638         target byte order
 639
 640 end-sanitize-r5900
 641 Mon May 18 18:22:42 1998  Frank Ch. Eigler  <fche@cygnus.com>
 642
 643         * configure.in (SIM_AC_OPTION_HARDWARE): Added common hardware
 644         modules.  Recognize TX39 target with "mips*tx39" pattern.
 645         * configure: Rebuilt.
 646         * sim-main.h (*): Added many macros defining bits in
 647         TX39 control registers.
 648         (SignalInterrupt): Send actual PC instead of NULL.
 649         (SignalNMIReset): New exception type.
 650         * interp.c (board): New variable for future use to identify
 651         a particular board being simulated.
 652         (mips_option_handler,mips_options): Added "--board" option.
 653         (interrupt_event): Send actual PC.
 654         (sim_open): Make memory layout conditional on board setting.
 655         (signal_exception): Initial implementation of hardware interrupt
 656         handling.  Accept another break instruction variant for simulator
 657         exit.
 658         (decode_coproc): Implement RFE instruction for TX39.
 659         (mips.igen): Decode RFE instruction as such.
 660         * configure.in (tx3904cpu,tx3904irc): Added devices for tx3904.
 661         * interp.c: Define "jmr3904" and "jmr3904debug" board types and
 662         bbegin to implement memory map.
 663         * dv-tx3904cpu.c: New file.
 664         * dv-tx3904irc.c: New file.
 665
 666 Wed May 13 14:40:11 1998  Gavin Koch  <gavin@cygnus.com>
 667
 668         * mips.igen (check_mt_hilo): Create a separate r3900 version.
 669
 670 start-sanitize-r5900
 671 Wed May 13 14:27:53 1998  Gavin Koch  <gavin@cygnus.com>
 672
 673         * r5900.igen: Replace the calls and the definition of the
 674         function check_op_hilo_hi1lo1 with the pair
 675         check_mult_hilo_hi1lo1 and check_mult_hilo_hi1lo1.
 676
 677 end-sanitize-r5900
 678 Wed May 13 14:11:46 1998  Gavin Koch  <gavin@cygnus.com>
 679
 680         * tx.igen (madd,maddu):  Replace calls to check_op_hilo
 681         with calls to check_div_hilo.
 682
 683 Wed May 13 09:59:27 1998  Gavin Koch  <gavin@cygnus.com>
 684
 685         * mips/mips.igen (check_op_hilo,check_mult_hilo,check_div_hilo):
 686         Replace check_op_hilo with check_mult_hilo and check_div_hilo.
 687         Add special r3900 version of do_mult_hilo.
 688         (do_dmultx,do_mult,do_multu): Replace calls to check_op_hilo
 689         with calls to check_mult_hilo.
 690         (do_ddiv,do_ddivu,do_div,do_divu): Replace calls to check_op_hilo
 691         with calls to check_div_hilo.
 692
 693 Tue May 12 15:22:11 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 694
 695         * configure.in (SUBTARGET_R3900): Define for mipstx39 target.
 696         Document a replacement.
 697
 698 Fri May  8 17:48:19 1998  Ian Carmichael  <iancarm@cygnus.com>
 699
 700         * interp.c (sim_monitor): Make mon_printf work.
 701
 702 Wed May  6 19:42:19 1998  Doug Evans  <devans@canuck.cygnus.com>
 703
 704         * sim-main.h (INSN_NAME): New arg `cpu'.
 705
 706 start-sanitize-sky
 707 Thu Apr 30 18:51:26 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 708
 709         * sky-libvpe.c (FMAdd, FMSub): Replace r59fp_op3 call with
 710         r59fp_mula.
 711
 712 end-sanitize-sky
 713 start-sanitize-r5900
 714 Wed Apr 29 22:54:45 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 715
 716         * sim-main.h (R5900_FP_MAX, R5900_FP_MIN): Define.
 717         * r5900.igen (r59fp_overflow): Use.
 718
 719         * r5900.igen (r59fp_op3): Rename to
 720         (r59fp_mula): This, delete opm argument.
 721         (MADD.S, MADDA.S, MSUB.S, MSUBS.S): Update.
 722         (r59fp_mula): Overflowing product propogates through to result.
 723         (r59fp_mula): ACC to the MAX propogates to result.
 724         (r59fp_mula): Underflow during multiply only sets SU.
 725
 726 end-sanitize-r5900
 727 Tue Apr 28 18:33:31 1998  Geoffrey Noer  <noer@cygnus.com>
 728
 729         * configure: Regenerated to track ../common/aclocal.m4 changes.
 730
 731 Sun Apr 26 15:31:55 1998  Tom Tromey  <tromey@creche>
 732
 733         * configure: Regenerated to track ../common/aclocal.m4 changes.
 734         * config.in: Ditto.
 735
 736 Sun Apr 26 15:20:01 1998  Tom Tromey  <tromey@cygnus.com>
 737
 738         * acconfig.h: New file.
 739         * configure.in: Reverted change of Apr 24; use sinclude again.
 740
 741 Fri Apr 24 14:16:40 1998  Tom Tromey  <tromey@creche>
 742
 743         * configure: Regenerated to track ../common/aclocal.m4 changes.
 744         * config.in: Ditto.
 745
 746 Fri Apr 24 11:19:20 1998  Tom Tromey  <tromey@cygnus.com>
 747
 748         * configure.in: Don't call sinclude.
 749
 750 Fri Apr 24 11:35:01 1998  Andrew Cagney  <cagney@chook.cygnus.com>
 751
 752         * mips.igen (do_store_left): Pass 0 not NULL to store_memory.
 753
 754 Tue Apr 21 11:59:50 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 755
 756         * mips.igen (ERET): Implement.
 757
 758         * interp.c (decode_coproc): Return sign-extended EPC.
 759
 760         * mips.igen (ANDI, LUI, MFC0): Add tracing code.
 761
 762         * interp.c (signal_exception): Do not ignore Trap.
 763         (signal_exception): On TRAP, restart at exception address.
 764         (HALT_INSTRUCTION, HALT_INSTRUCTION_MASK): Define.
 765         (signal_exception): Update.
 766         (sim_open): Patch V_COMMON interrupt vector with an abort sequence
 767         so that TRAP instructions are caught.
 768
 769 Mon Apr 20 11:26:55 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 770
 771         * sim-main.h (struct hilo_access, struct hilo_history): Define,
 772         contains HI/LO access history.
 773         (struct _sim_cpu): Make hiaccess and loaccess of type hilo_access.
 774         (HIACCESS, LOACCESS): Delete, replace with
 775         (HIHISTORY, LOHISTORY): New macros.
 776         (start-sanitize-r5900):
 777         (struct sim_5900_cpu): Make hi1access, lo1access of type
 778         hilo_access.
 779         (HI1ACCESS, LO1ACCESS): Delete, replace with
 780         (HI1HISTORY, LO1HISTORY): New macros.
 781         (end-sanitize-r5900):
 782         (CHECKHILO): Delete all, moved to mips.igen
 783
 784         * gencode.c (build_instruction): Do not generate checks for
 785         correct HI/LO register usage.
 786
 787         * interp.c (old_engine_run): Delete checks for correct HI/LO
 788         register usage.
 789
 790         * mips.igen (check_mt_hilo, check_mf_hilo, check_op_hilo,
 791         check_mf_cycles): New functions.
 792         (do_mfhi, do_mflo, "mthi", "mtlo", do_ddiv, do_ddivu, do_div,
 793         do_divu, domultx, do_mult, do_multu): Use.
 794
 795         * tx.igen ("madd", "maddu"): Use.
 796         (start-sanitize-r5900):
 797
 798         r5900.igen: Update all HI/LO checks.
 799         ("mfhi1", "mflo1", "mthi1", "mthi1", "pmfhi", "pmflo", "pmfhl",
 800         "pmthi", "pmtlo", "mpthl"): Check MF/MT HI/LO.
 801         ("mult1", "div1", "divu1", "multu1", "madd1", "maddu1", "pdivbw",
 802         "pdivuw", "pdivw", "phmaddh", "phmsubh", "pmaddh", "madduw",
 803         "pmaddw", "pmsubh", "pmsubw", "pmulth", "pmultuw", "pmultw"):
 804         Check HI/LO op.
 805         (end-sanitize-r5900):
 806
 807 start-sanitize-sky
 808 Mon Apr 20 18:39:47 1998  Frank Ch. Eigler  <fche@cygnus.com>
 809
 810         * interp.c (decode_coproc): Correct CMFC2/QMTC2
 811         GPR access.
 812
 813         * r5900.igen (LQ,SQ): Use a pair of 64-bit accesses
 814         instead of a single 128-bit access.
 815
 816 end-sanitize-sky
 817 start-sanitize-sky
 818 Fri Apr 17 14:50:39 1998  Frank Ch. Eigler  <fche@cygnus.com>
 819
 820         * r5900.igen (COP_[LS]Q): Transfer COP2 quadwords.
 821         * interp.c (cop_[ls]q): Fixes corresponding to above.
 822
 823 end-sanitize-sky
 824 start-sanitize-sky
 825 Thu Apr 16 15:24:14 1998  Frank Ch. Eigler  <fche@cygnus.com>
 826
 827         * interp.c (decode_coproc): Adapt COP2 micro interlock to
 828         clarified specs.  Reset "M" bit; exit also on "E" bit.
 829
 830 end-sanitize-sky
 831 start-sanitize-r5900
 832 Thu Apr 16 10:40:29 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 833
 834         * r5900.igen (CFC1, CTC1): Implement R5900 specific version.
 835         * mips.igen (CFC1, CTC1): R5900 des not use generic version.
 836
 837         * r5900.igen (r59fp_unpack): New function.
 838         (r59fp_op1, r59fp_op2, r59fp_op3, C.cond.S, CVT.S.W, DIV.S,
 839         RSQRT.S, SQRT.S): Use.
 840         (r59fp_zero): New function.
 841         (r59fp_overflow): Generate r5900 specific overflow value.
 842         (r59fp_store): Re-write, overflow to MAX_R5900_FP value, underflow
 843         to zero.
 844         (CVT.S.W, CVT.W.S): Exchange implementations.
 845
 846         * sim-main.h (R5900_EXPMAX, R5900_EXPMIN, R5900_EXPBIAS): Defile.
 847
 848 end-sanitize-r5900
 849 start-sanitize-tx19
 850 Thu Apr 16 09:14:44 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 851
 852         * configure.in (tx19, sim_use_gen): Switch to igen.
 853         * configure: Re-build.
 854
 855 end-sanitize-tx19
 856 start-sanitize-sky
 857 Wed Apr 15 12:41:18 1998  Frank Ch. Eigler  <fche@cygnus.com>
 858
 859         * interp.c (decode_coproc): Make COP2 branch code compile after
 860         igen signature changes.
 861
 862 end-sanitize-sky
 863 Wed Apr 15 18:31:54 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 864
 865         * mips.igen (DSRAV): Use function do_dsrav.
 866         (SRAV): Use new function do_srav.
 867
 868         * m16.igen (BEQZ, BNEZ): Compare GPR[TRX] not GPR[RX].
 869         (B): Sign extend 11 bit immediate.
 870         (EXT-B*): Shift 16 bit immediate left by 1.
 871         (ADDIU*): Don't sign extend immediate value.
 872
 873 Wed Apr 15 10:32:15 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 874
 875         * m16run.c (sim_engine_run): Restore CIA after handling an event.
 876
 877 start-sanitize-tx19
 878         * mips.igen (mtc0): Valid tx19 instruction.
 879
 880 end-sanitize-tx19
 881         * sim-main.h (DELAY_SLOT, NULLIFY_NEXT_INSTRUCTION): For IGEN, use
 882         functions.
 883
 884         * mips.igen (delayslot32, nullify_next_insn): New functions.
 885         (m16.igen): Always include.
 886         (do_*): Add more tracing.
 887
 888         * m16.igen (delayslot16): Add NIA argument, could be called by a
 889         32 bit MIPS16 instruction.
 890
 891         * interp.c (ifetch16): Move function from here.
 892         * sim-main.c (ifetch16): To here.
 893
 894         * sim-main.c (ifetch16, ifetch32): Update to match current
 895         implementations of LH, LW.
 896         (signal_exception): Don't print out incorrect hex value of illegal
 897         instruction.
 898
 899 Wed Apr 15 00:17:25 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 900
 901         * m16run.c (sim_engine_run): Use IMEM16 and IMEM32 to fetch an
 902         instruction.
 903
 904         * m16.igen: Implement MIPS16 instructions.
 905
 906         * mips.igen (do_addiu, do_addu, do_and, do_daddiu, do_daddu,
 907         do_ddiv, do_ddivu, do_div, do_divu, do_dmultx, do_dmultu, do_srav,
 908         do_dsubu, do_mfhi, do_mflo, do_mult, do_multu, do_nor, do_or,
 909         do_sll, do_sllv, do_slt, do_slti, do_sltiu, do_sltu, do_sra,
 910         do_srl, do_srlv, do_subu, do_xor, do_xori): New functions.  Move
 911         bodies of corresponding code from 32 bit insn to these.  Also used
 912         by MIPS16 versions of functions.
 913
 914         * sim-main.h (RAIDX, T8IDX, T8, SPIDX): Define.
 915         (IMEM16): Drop NR argument from macro.
 916
 917 start-sanitize-sky
 918 Mon Apr 13 16:28:52 1998  Frank Ch. Eigler  <fche@cygnus.com>
 919
 920         * interp.c (decode_coproc): Add proper 1000000 bit-string at top
 921         of VU lower instruction.
 922
 923 end-sanitize-sky
 924 start-sanitize-sky
 925 Thu Apr  9 16:38:23 1998  Frank Ch. Eigler  <fche@cygnus.com>
 926
 927         * r5900.igen (LQC,SQC): Adapted code to DOUBLEWORD accesses
 928         instead of QUADWORD.
 929
 930         * sim-main.h: Removed attempt at allowing 128-bit access.
 931
 932 end-sanitize-sky
 933 start-sanitize-sky
 934 Wed Apr  8 18:12:13 1998  Frank Ch. Eigler  <fche@cygnus.com>
 935
 936         * Makefile.in (SIM_SKY_OBJS): Added sky-vudis.o.
 937
 938         * interp.c (decode_coproc): Refer to VU CIA as a "special"
 939         register, not as a "misc" register.  Aha.  Add activity
 940         assertions after VCALLMS* instructions.
 941
 942 end-sanitize-sky
 943 start-sanitize-sky
 944 Tue Apr  7 18:32:49 1998  Frank Ch. Eigler  <fche@cygnus.com>
 945
 946         * interp.c (decode_coproc): Do not apply superfluous E (end) flag
 947         to upper code of generated VU instruction.
 948
 949 end-sanitize-sky
 950 start-sanitize-sky
 951 Mon Apr  6 19:55:56 1998  Frank Ch. Eigler  <fche@cygnus.com>
 952
 953         * interp.c (cop_[ls]q): Replaced stub with proper COP2 code.
 954
 955         * sim-main.h (LOADADDRMASK): Redefine to allow 128-bit accesses
 956         for TARGET_SKY.
 957
 958         * r5900.igen (SQC2): Thinko.
 959
 960 end-sanitize-sky
 961 start-sanitize-sky
 962 Sun Apr  5 12:05:44 1998  Frank Ch. Eigler  <fche@cygnus.com>
 963
 964         * interp.c (*): Adapt code to merged VU device & state structs.
 965         (decode_coproc): Execute COP2 each macroinstruction without
 966         pipelining, by stepping VU to completion state.  Adapted to
 967         read_vu_*_reg style of register access.
 968
 969         * mips.igen ([SL]QC2): Removed these COP2 instructions.
 970
 971         * r5900.igen ([SL]QC2): Transplanted these COP2 instructions here.
 972
 973         * sim-main.h (cop_[ls]q): Enclosed in TARGET_SKY guards.
 974
 975 end-sanitize-sky
 976 Sat Apr  4 22:39:50 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 977
 978         * Makefile.in (SIM_OBJS): Add sim-main.o.
 979
 980         * sim-main.h (address_translation, load_memory, store_memory,
 981         cache_op, sync_operation, prefetch, ifetch32, pending_tick): Mark
 982         as INLINE_SIM_MAIN.
 983         (pr_addr, pr_uword64): Declare.
 984         (sim-main.c): Include when H_REVEALS_MODULE_P.
 985
 986         * interp.c (address_translation, load_memory, store_memory,
 987         cache_op, sync_operation, prefetch, ifetch32, pending_tick): Move
 988         from here.
 989         * sim-main.c: To here. Fix compilation problems.
 990
 991         * configure.in: Enable inlining.
 992         * configure: Re-config.
 993
 994 Sat Apr  4 20:36:25 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 995
 996         * configure: Regenerated to track ../common/aclocal.m4 changes.
 997
 998 Fri Apr  3 04:32:35 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 999
1000         * mips.igen: Include tx.igen.
1001         * Makefile.in (IGEN_INCLUDE): Add tx.igen.
1002         * tx.igen: New file, contains MADD and MADDU.
1003
1004         * interp.c (load_memory): When shifting bytes, use LOADDRMASK not
1005         the hardwired constant `7'.
1006         (store_memory): Ditto.
1007         (LOADDRMASK): Move definition to sim-main.h.
1008
1009         mips.igen (MTC0): Enable for r3900.
1010         (ADDU): Add trace.
1011
1012         mips.igen (do_load_byte): Delete.
1013         (do_load, do_store, do_load_left, do_load_write, do_store_left,
1014         do_store_right): New functions.
1015         (SW*, LW*, SD*, LD*, SH, LH, SB, LB): Use.
1016
1017         configure.in: Let the tx39 use igen again.
1018         configure: Update.
1019
1020 Thu Apr  2 10:59:39 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1021
1022         * interp.c (sim_monitor): get_mem_info returns a 4 byte quantity,
1023         not an address sized quantity.  Return zero for cache sizes.
1024
1025 Wed Apr  1 23:47:53 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1026
1027         * mips.igen (r3900): r3900 does not support 64 bit integer
1028         operations.
1029
1030 start-sanitize-sky
1031 Wed Apr 1 08:20:31 1998  Frank Ch. Eigler  <fche@cygnus.com>
1032
1033         * mips.igen (SQC2/LQC2): Make bodies sky-target-only also.
1034
1035 end-sanitize-sky
1036 start-sanitize-sky
1037 Mon Mar 30 18:41:43 1998  Frank Ch. Eigler  <fche@cygnus.com>
1038
1039         * interp.c (decode_coproc): Continuing COP2 work.
1040         (cop_[ls]q): Make sky-target-only.
1041
1042         * sim-main.h (COP_[LS]Q): Make sky-target-only.
1043 end-sanitize-sky
1044 Mon Mar 30 14:46:05 1998  Gavin Koch  <gavin@cygnus.com>
1045
1046         * configure.in (mipstx39*-*-*): Use gencode simulator rather
1047         than igen one.
1048         * configure : Rebuild.
1049
1050 start-sanitize-sky
1051 Sun Mar 29 17:50:11       Frank Ch. Eigler  <fche@cygnus.com>
1052
1053         * interp.c (decode_coproc): Added a missing TARGET_SKY check
1054         around COP2 implementation skeleton.
1055
1056 end-sanitize-sky
1057 start-sanitize-sky
1058 Fri Mar 27 16:19:29 1998  Frank Ch. Eigler  <fche@cygnus.com>
1059
1060         * Makefile.in (SIM_SKY_OBJS): Replaced sky-vu[01].o with sky-vu.o.
1061
1062         * interp.c (sim_{load,store}_register): Use new vu[01]_device
1063         static to access VU registers.
1064         (decode_coproc): Added skeleton of sky COP2 (VU) instruction
1065         decoding.  Work in progress.
1066
1067         * mips.igen (LDCzz, SDCzz): Removed *5900 case for this
1068         overlapping/redundant bit pattern.
1069         (LQC2, SQC2): Added *5900 COP2 instruction skeleta.  Work in
1070         progress.
1071
1072         * sim-main.h (status_CU[012]): Added COP[n]-enabled flags for
1073         status register.
1074
1075         * interp.c (cop_lq, cop_sq): New functions for future 128-bit
1076         access to coprocessor registers.
1077
1078         * sim-main.h (COP_LQ, COP_SQ): New macro front-ends for above.
1079 end-sanitize-sky
1080 Fri Mar 27 16:15:52 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1081
1082         * configure: Regenerated to track ../common/aclocal.m4 changes.
1083
1084 Fri Mar 27 15:01:50 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1085
1086         * interp.c (mips_option_handler): Iterate over MAX_NR_PROCESSORS.
1087
1088 Wed Mar 25 16:44:27 1998  Ian Carmichael  <iancarm@cygnus.com>
1089
1090         * configure: Regenerated to track ../common/aclocal.m4 changes.
1091         * config.in: Regenerated to track ../common/aclocal.m4 changes.
1092
1093 Wed Mar 25 12:35:29 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1094
1095         * configure: Regenerated to track ../common/aclocal.m4 changes.
1096
1097 Wed Mar 25 10:05:46 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1098
1099         * interp.c (Max, Min): Comment out functions. Not yet used.
1100
1101 start-sanitize-vr4320
1102 Wed Mar 25 10:04:13 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1103
1104         * vr4320.igen (DCLZ): Pacify GCC, 64 bit arg, int format.
1105
1106 end-sanitize-vr4320
1107 Wed Mar 18 12:38:12 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1108
1109         * configure: Regenerated to track ../common/aclocal.m4 changes.
1110
1111 Tue Mar 17 19:05:20 1998  Frank Ch. Eigler  <fche@cygnus.com>
1112
1113         * Makefile.in (MIPS_EXTRA_LIBS, SIM_EXTRA_LIBS): Added
1114         configurable settings for stand-alone simulator.
1115
1116 start-sanitize-sky
1117         * configure.in: Added --with-sim-gpu2 option to specify path of
1118         sky GPU2 library.  Triggers -DSKY_GPU2 for sky-gpuif.c, and
1119         links/compiles stand-alone simulator with this library.
1120
1121         * interp.c (MEM_SIZE): Increased default sky memory size to 16MB.
1122 end-sanitize-sky
1123         * configure.in: Added X11 search, just in case.
1124
1125         * configure: Regenerated.
1126
1127 Wed Mar 11 14:09:10 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1128
1129         * interp.c (sim_write, sim_read, load_memory, store_memory):
1130         Replace sim_core_*_map with read_map, write_map, exec_map resp.
1131
1132 start-sanitize-vr4320
1133 Tue Mar 10 10:32:22 1998  Gavin Koch  <gavin@cygnus.com>
1134
1135         * vr4320.igen (clz,dclz) : Added.
1136         (dmac): Replaced 99, with LO.
1137
1138 end-sanitize-vr4320
1139 start-sanitize-cygnus
1140 Fri Mar  6 08:30:58 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1141
1142         * mdmx.igen (SHFL.REPA.fmt, SHFL.REPB.fmt): Fix bit fields.
1143
1144 end-sanitize-cygnus
1145 start-sanitize-vr4320
1146 Tue Mar  3 11:56:29 1998  Gavin Koch  <gavin@cygnus.com>
1147
1148         * vr4320.igen: New file.
1149         * Makefile.in (vr4320.igen) : Added.
1150         * configure.in (mips64vr4320-*-*): Added.
1151         * configure : Rebuilt.
1152         * mips.igen : Correct the bfd-names in the mips-ISA model entries.
1153         Add the vr4320 model entry and mark the vr4320 insn as necessary.
1154
1155 end-sanitize-vr4320
1156 Tue Mar  3 13:58:43 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1157
1158         * sim-main.h (GETFCC): Return an unsigned value.
1159
1160 start-sanitize-r5900
1161         * r5900.igen: Use an unsigned array index variable `i'.
1162         (QFSRV): Ditto for variable bytes.
1163
1164 end-sanitize-r5900
1165 Tue Mar  3 13:21:37 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1166
1167         * mips.igen (DIV): Fix check for -1 / MIN_INT.
1168         (DADD): Result destination is RD not RT.
1169
1170 start-sanitize-r5900
1171         * r5900.igen (DIV1): Fix check for -1 / MIN_INT.
1172         (DIVU1): Don't check for MIN_INT / -1 as performing unsigned
1173         divide.
1174
1175 end-sanitize-r5900
1176 Fri Feb 27 13:49:49 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1177
1178         * sim-main.h (HIACCESS, LOACCESS): Always define.
1179
1180         * mdmx.igen (Maxi, Mini): Rename Max, Min.
1181
1182         * interp.c (sim_info): Delete.
1183
1184 Fri Feb 27 18:41:01 1998  Doug Evans  <devans@canuck.cygnus.com>
1185
1186         * interp.c (DECLARE_OPTION_HANDLER): Use it.
1187         (mips_option_handler): New argument `cpu'.
1188         (sim_open): Update call to sim_add_option_table.
1189
1190 Wed Feb 25 18:56:22 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1191
1192         * mips.igen (CxC1): Add tracing.
1193
1194 start-sanitize-r5900
1195 Wed Feb 25 13:59:03 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1196
1197         * r5900.igen (StoreFP): Delete.
1198         (r59fp_store, r59fp_overflow, r59fp_op1, r59fp_op2, r59fp_op3):
1199         New functions.
1200         (rsqrt.s, sqrt.s): Implement.
1201         (r59cond): New function.
1202         (C.COND.S): Call r59cond in assembler line.
1203         (cvt.w.s, cvt.s.w): Implement.
1204
1205         * mips.igen (rsqrt.fmt, sqrt.fmt, cvt.*.*): Remove from r5900
1206         instruction set.
1207
1208         * sim-main.h: Define an enum of r5900 FCSR bit fields.
1209
1210 end-sanitize-r5900
1211 start-sanitize-r5900
1212 Tue Feb 24 14:44:18 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1213
1214         * r5900.igen: Add tracing to all p* instructions.
1215
1216 Tue Feb 24 02:47:33 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1217
1218         * interp.c (sim_store_register, sim_fetch_register): Pull swifty
1219         to get gdb talking to re-aranged sim_cpu register structure.
1220
1221 end-sanitize-r5900
1222 Fri Feb 20 17:43:21 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1223
1224         * sim-main.h (Max, Min): Declare.
1225
1226         * interp.c (Max, Min): New functions.
1227
1228         * mips.igen (BC1): Add tracing.
1229
1230 start-sanitize-cygnus
1231 Fri Feb 20 16:27:17 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1232
1233         * mdmx.igen: Tag all functions as requiring either with mdmx or
1234         vr5400 processor.
1235
1236 end-sanitize-cygnus
1237 start-sanitize-r5900
1238 Fri Feb 20 15:55:51 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1239
1240         * configure.in (SIM_AC_OPTION_FLOAT): For r5900, set FP bit size
1241         to 32.
1242         (SIM_AC_OPTION_BITSIZE): For r5900, set nr address bits to 32.
1243
1244         * mips.igen (C.cond.fmt, ..): Not part of r5900 insn set.
1245
1246         * r5900.igen: Rewrite.
1247
1248         * sim-main.h: Move r5900 registers to a separate _sim_r5900_cpu
1249         struct.
1250         (GPR_SB, GPR_SH, GPR_SW, GPR_SD, GPR_UB, GPR_UH, GPR_UW, GPR_UD):
1251         Define in terms of GPR/GPR1 instead of REGISTERS/REGISTERS.1
1252
1253 end-sanitize-r5900
1254 Thu Feb 19 14:50:00 1998  John Metzler  <jmetzler@cygnus.com>
1255
1256         * interp.c Added memory map for stack in vr4100
1257
1258 Thu Feb 19 10:21:21 1998  Gavin Koch  <gavin@cygnus.com>
1259
1260         * interp.c (load_memory): Add missing "break"'s.
1261
1262 Tue Feb 17 12:45:35 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1263
1264         * interp.c (sim_store_register, sim_fetch_register): Pass in
1265         length parameter.  Return -1.
1266
1267 Tue Feb 10 11:57:40 1998  Ian Carmichael  <iancarm@cygnus.com>
1268
1269         * interp.c: Added hardware init hook, fixed warnings.
1270
1271 Sat Feb  7 17:16:20 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1272
1273         * Makefile.in (itable.h itable.c): Depend on SIM_@sim_gen@_ALL.
1274
1275 Tue Feb  3 11:36:02 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1276
1277         * interp.c (ifetch16): New function.
1278
1279         * sim-main.h (IMEM32): Rename IMEM.
1280         (IMEM16_IMMED): Define.
1281         (IMEM16): Define.
1282         (DELAY_SLOT): Update.
1283
1284         * m16run.c (sim_engine_run): New file.
1285
1286         * m16.igen: All instructions except LB.
1287         (LB): Call do_load_byte.
1288         * mips.igen (do_load_byte): New function.
1289         (LB): Call do_load_byte.
1290
1291         * mips.igen: Move spec for insn bit size and high bit from here.
1292         * Makefile.in (tmp-igen, tmp-m16): To here.
1293
1294         * m16.dc: New file, decode mips16 instructions.
1295
1296         * Makefile.in (SIM_NO_ALL): Define.
1297         (tmp-m16): Generate both 16 bit and 32 bit simulator engines.
1298
1299 start-sanitize-tx19
1300         * m16.igen: Mark all mips16 insns as being part of the tx19 insn
1301         set.
1302
1303 end-sanitize-tx19
1304 Tue Feb  3 11:28:00 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1305
1306         * configure.in (mips_fpu_bitsize): For tx39, restrict floating
1307         point unit to 32 bit registers.
1308         * configure: Re-generate.
1309
1310 Sun Feb  1 15:47:14 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1311
1312         * configure.in (sim_use_gen): Make IGEN the default simulator
1313         generator for generic 32 and 64 bit mips targets.
1314         * configure: Re-generate.
1315
1316 Sun Feb  1 16:52:37 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1317
1318         * sim-main.h (SizeFGR): Determine from floating-point and not gpr
1319         bitsize.
1320
1321         * interp.c (sim_fetch_register, sim_store_register): Read/write
1322         FGR from correct location.
1323         (sim_open): Set size of FGR's according to
1324         WITH_TARGET_FLOATING_POINT_BITSIZE.
1325
1326         * sim-main.h (FGR): Store floating point registers in a separate
1327         array.
1328
1329 Sun Feb  1 16:47:51 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1330
1331         * configure: Regenerated to track ../common/aclocal.m4 changes.
1332
1333 start-sanitize-cygnus
1334         * mdmx.igen: Mark all instructions as 64bit/fp specific.
1335
1336 end-sanitize-cygnus
1337 Tue Feb  3 00:10:50 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1338
1339         * interp.c (ColdReset): Call PENDING_INVALIDATE.
1340
1341         * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Call PENDING_TICK.
1342
1343         * interp.c (pending_tick): New function.  Deliver pending writes.
1344
1345         * sim-main.h (PENDING_FILL, PENDING_TICK, PENDING_SCHED,
1346         PENDING_BIT, PENDING_INVALIDATE): Re-write pipeline code so that
1347         it can handle mixed sized quantites and single bits.
1348
1349 Mon Feb  2 17:43:15 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1350
1351         * interp.c (oengine.h): Do not include when building with IGEN.
1352         (sim_open): Replace GPRLEN by WITH_TARGET_WORD_BITSIZE.
1353         (sim_info): Ditto for PROCESSOR_64BIT.
1354         (sim_monitor): Replace ut_reg with unsigned_word.
1355         (*): Ditto for t_reg.
1356         (LOADDRMASK): Define.
1357         (sim_open): Remove defunct check that host FP is IEEE compliant,
1358         using software to emulate floating point.
1359         (value_fpr, ...): Always compile, was conditional on HASFPU.
1360
1361 Sun Feb  1 11:15:29 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1362
1363         * sim-main.h (sim_state): Make the cpu array MAX_NR_PROCESSORS in
1364         size.
1365
1366         * interp.c (SD, CPU): Define.
1367         (mips_option_handler): Set flags in each CPU.
1368         (interrupt_event): Assume CPU 0 is the one being iterrupted.
1369         (sim_close): Do not clear STATE, deleted anyway.
1370         (sim_write, sim_read): Assume CPU zero's vm should be used for
1371         data transfers.
1372         (sim_create_inferior): Set the PC for all processors.
1373         (sim_monitor, store_word, load_word, mips16_entry): Add cpu
1374         argument.
1375         (mips16_entry): Pass correct nr of args to store_word, load_word.
1376         (ColdReset): Cold reset all cpu's.
1377         (signal_exception): Pass cpu to sim_monitor & mips16_entry.
1378         (sim_monitor, load_memory, store_memory, signal_exception): Use
1379         `CPU' instead of STATE_CPU.
1380
1381
1382         * sim-main.h: Replace uses of STATE_CPU with CPU. Replace sd with
1383         SD or CPU_.
1384
1385         * sim-main.h (signal_exception): Add sim_cpu arg.
1386         (SignalException*): Pass both SD and CPU to signal_exception.
1387         * interp.c (signal_exception): Update.
1388
1389         * sim-main.h (value_fpr, store_fpr, dotrace, ifetch32), interp.c:
1390         Ditto
1391         (sync_operation, prefetch, cache_op, store_memory, load_memory,
1392         address_translation): Ditto
1393         (decode_coproc, cop_lw, cop_ld, cop_sw, cop_sd): Ditto.
1394
1395 start-sanitize-cygnus
1396         * mdmx.igen (get_scale): Pass CPU_ to semantic_illegal instead of
1397         `sd'.
1398         (ByteAlign): Use StoreFPR, pass args in correct order.
1399
1400 end-sanitize-cygnus
1401 start-sanitize-r5900
1402 Sun Feb  1 10:59:55 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1403
1404         * configure.in (sim_igen_filter): For r5900, configure as SMP.
1405
1406 end-sanitize-r5900
1407 Sat Jan 31 18:15:41 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1408
1409         * configure: Regenerated to track ../common/aclocal.m4 changes.
1410
1411 Sat Jan 31 14:49:24 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1412
1413 start-sanitize-r5900
1414         * configure.in (sim_igen_filter): For r5900, use igen.
1415         * configure: Re-generate.
1416
1417 end-sanitize-r5900
1418         * interp.c (sim_engine_run): Add `nr_cpus' argument.
1419
1420         * mips.igen (model): Map processor names onto BFD name.
1421
1422         * sim-main.h (CPU_CIA): Delete.
1423         (SET_CIA, GET_CIA): Define
1424
1425 Wed Jan 21 16:16:27 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1426
1427         * sim-main.h (GPR_SET): Define, used by igen when zeroing a
1428         regiser.
1429
1430         * configure.in (default_endian): Configure a big-endian simulator
1431         by default.
1432         * configure: Re-generate.
1433
1434 Mon Jan 19 22:26:29 1998  Doug Evans  <devans@seba>
1435
1436         * configure: Regenerated to track ../common/aclocal.m4 changes.
1437
1438 Mon Jan  5 20:38:54 1998  Mark Alexander  <marka@cygnus.com>
1439
1440         * interp.c (sim_monitor): Handle Densan monitor outbyte
1441         and inbyte functions.
1442
1443 1997-12-29  Felix Lee  <flee@cygnus.com>
1444
1445         * interp.c (sim_engine_run): msvc cpp barfs on #if (a==b!=c).
1446
1447 Wed Dec 17 14:48:20 1997  Jeffrey A Law  (law@cygnus.com)
1448
1449         * Makefile.in (tmp-igen): Arrange for $zero to always be
1450         reset to zero after every instruction.
1451
1452 Mon Dec 15 23:17:11 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1453
1454         * configure: Regenerated to track ../common/aclocal.m4 changes.
1455         * config.in: Ditto.
1456
1457 start-sanitize-cygnus
1458 Sat Dec 13 15:18:51 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1459
1460         * vr5400.igen (Low32Bits, High32Bits): Sign extend extracted 32
1461         bit values.
1462
1463 Fri Dec 12 12:26:07 1997  Jeffrey A Law  (law@cygnus.com)
1464
1465         * configure.in (sim_igen_filter): Multi-sim vr5000 - vr5000 or
1466         vr5400 with the vr5000 as the default.
1467
1468 end-sanitize-cygnus
1469 Wed Dec 10 17:10:45 1997  Jeffrey A Law  (law@cygnus.com)
1470
1471         * mips.igen (MSUB): Fix to work like MADD.
1472         * gencode.c (MSUB): Similarly.
1473
1474 start-sanitize-cygnus
1475 Tue Dec  9 12:02:12 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1476
1477         * configure.in (sim_igen_filter): Multi-sim vr5400 - vr5000 or
1478         vr5400.
1479
1480 end-sanitize-cygnus
1481 Thu Dec  4 09:21:05 1997  Doug Evans  <devans@canuck.cygnus.com>
1482
1483         * configure: Regenerated to track ../common/aclocal.m4 changes.
1484
1485 Wed Nov 26 11:00:23 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1486
1487         * mips.igen (LWC1): Correct assembler - lwc1 not swc1.
1488
1489 start-sanitize-cygnus
1490         * mdmx.igen (value_vr): Correct sim_io_eprintf format argument.
1491         (value_cc, store_cc): Implement.
1492
1493         * sim-main.h: Add 8*3*8 bit accumulator.
1494
1495         * vr5400.igen: Move mdmx instructins from here
1496         * mdmx.igen: To here - new file. Add/fix missing instructions.
1497         * mips.igen: Include mdmx.igen.
1498         * Makefile.in (IGEN_INCLUDE): Add mdmx.igen.
1499
1500 end-sanitize-cygnus
1501 Sun Nov 23 01:45:20 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1502
1503         * sim-main.h (sim-fpu.h): Include.
1504
1505         * interp.c (convert, SquareRoot, Recip, Divide, Multiply, Sub,
1506         Add, Negate, AbsoluteValue, Equal, Less, Infinity, NaN): Rewrite
1507         using host independant sim_fpu module.
1508
1509 Thu Nov 20 19:56:22 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1510
1511         * interp.c (signal_exception): Report internal errors with SIGABRT
1512         not SIGQUIT.
1513
1514         * sim-main.h (C0_CONFIG): New register.
1515         (signal.h): No longer include.
1516
1517         * interp.c (decode_coproc): Allow access C0_CONFIG to register.
1518
1519 Tue Nov 18 15:33:48 1997  Doug Evans  <devans@canuck.cygnus.com>
1520
1521         * Makefile.in (SIM_OBJS): Use $(SIM_NEW_COMMON_OBJS).
1522
1523 Fri Nov 14 11:56:48 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1524
1525         * mips.igen: Tag vr5000 instructions.
1526         (ANDI): Was missing mipsIV model, fix assembler syntax.
1527         (do_c_cond_fmt): New function.
1528         (C.cond.fmt): Handle mips I-III which do not support CC field
1529         separatly.
1530         (bc1): Handle mips IV which do not have a delaed FCC separatly.
1531         (SDR): Mask paddr when BigEndianMem, not the converse as specified
1532         in IV3.2 spec.
1533         (DMULT, DMULTU): Force use of hosts 64bit multiplication.  Handle
1534         vr5000 which saves LO in a GPR separatly.
1535
1536         * configure.in (enable-sim-igen): For vr5000, select vr5000
1537         specific instructions.
1538         * configure: Re-generate.
1539
1540 Wed Nov 12 14:42:52 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1541
1542         * Makefile.in (SIM_OBJS): Add sim-fpu module.
1543
1544         * interp.c (store_fpr), sim-main.h: Add separate fmt_uninterpreted_32 and
1545         fmt_uninterpreted_64 bit cases to switch.  Convert to
1546         fmt_formatted,
1547
1548         * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Define,
1549
1550         * mips.igen (SWR): Mask paddr when BigEndianMem, not the converse
1551         as specified in IV3.2 spec.
1552         (MTC1, DMTC1): Call StoreFPR to store the GPR in the FPR.
1553
1554 Tue Nov 11 12:38:23 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1555
1556         * mips.igen: Delay slot branches add OFFSET to NIA not CIA.
1557         (MFC0, MTC0, SWC1, LWC1, SDC1, LDC1): Implement.
1558         (start-sanitize-r5900):
1559         (LWXC1, SWXC1): Delete from r5900 instruction set.
1560         (end-sanitize-r5900):
1561         (MTC1, MFC1, DMTC1, DMFC1, CFC1, CTC1): Implement separate non
1562         PENDING_FILL versions of instructions.  Simplify.
1563         (X): New function.
1564         (MULT, MULTU): Implement separate RD==0 and RD!=0 versions of
1565         instructions.
1566         (BEQZ, ..., SLT, SLTI, TLT, TLE, TLI, ...): Explicitly cast GPR to
1567         a signed value.
1568         (MTHI, MFHI): Disable code checking HI-LO.
1569
1570         * sim-main.h (dotrace,tracefh), interp.c: Make dotrace & tracefh
1571         global.
1572         (NULLIFY_NEXT_INSTRUCTION): Call dotrace.
1573
1574 Thu Nov  6 16:36:35 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1575
1576         * gencode.c (build_mips16_operands): Replace IPC with cia.
1577
1578         * interp.c (sim_monitor, signal_exception, cache_op, store_fpr,
1579         value_fpr, cop_ld, cop_lw, cop_sw, cop_sd, decode_coproc): Replace
1580         IPC to `cia'.
1581         (UndefinedResult): Replace function with macro/function
1582         combination.
1583         (sim_engine_run): Don't save PC in IPC.
1584
1585         * sim-main.h (IPC): Delete.
1586
1587         start-sanitize-cygnus
1588         * vr5400.igen (vr): Add missing cia argument to value_fpr.
1589         (do_select): Rename function select.
1590         end-sanitize-cygnus
1591
1592         * interp.c (signal_exception, store_word, load_word,
1593         address_translation, load_memory, store_memory, cache_op,
1594         prefetch, sync_operation, ifetch, value_fpr, store_fpr, convert,
1595         cop_lw, cop_ld, cop_sw, cop_sd, decode_coproc, sim_monitor): Add
1596         current instruction address - cia - argument.
1597         (sim_read, sim_write): Call address_translation directly.
1598         (sim_engine_run): Rename variable vaddr to cia.
1599         (signal_exception): Pass cia to sim_monitor
1600
1601         * sim-main.h (SignalException, LoadWord, StoreWord, CacheOp,
1602         Prefetch, SyncOperation, ValueFPR, StoreFPR, Convert, COP_LW,
1603         COP_LD, COP_SW, COP_SD, DecodeCoproc): Update.
1604
1605         * sim-main.h (SignalExceptionSimulatorFault): Delete definition.
1606         * interp.c (sim_open): Replace SignalExceptionSimulatorFault with
1607         SIM_ASSERT.
1608
1609         * interp.c (signal_exception): Pass restart address to
1610         sim_engine_restart.
1611
1612         * Makefile.in (semantics.o, engine.o, support.o, itable.o,
1613         idecode.o): Add dependency.
1614
1615         * sim-main.h (SIM_ENGINE_HALT_HOOK, SIM_ENGINE_RESUME_HOOK):
1616         Delete definitions
1617         (DELAY_SLOT): Update NIA not PC with branch address.
1618         (NULLIFY_NEXT_INSTRUCTION): Set NIA to instruction after next.
1619
1620         * mips.igen: Use CIA not PC in branch calculations.
1621         (illegal): Call SignalException.
1622         (BEQ, ADDIU): Fix assembler.
1623
1624 Wed Nov  5 12:19:56 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1625
1626         * m16.igen (JALX): Was missing.
1627
1628         * configure.in (enable-sim-igen): New configuration option.
1629         * configure: Re-generate.
1630
1631         * sim-main.h (MAX_INSNS, INSN_NAME): Define.
1632
1633         * interp.c (load_memory, store_memory): Delete parameter RAW.
1634         (sim_read, sim_write): Use sim_core_{read,write}_buffer directly
1635         bypassing {load,store}_memory.
1636
1637         * sim-main.h (ByteSwapMem): Delete definition.
1638
1639         * Makefile.in (SIM_OBJS): Add sim-memopt module.
1640
1641         * interp.c (sim_do_command, sim_commands): Delete mips specific
1642         commands.  Handled by module sim-options.
1643
1644         * sim-main.h (SIM_HAVE_FLATMEM): Undefine, use sim-core.o module.
1645         (WITH_MODULO_MEMORY): Define.
1646
1647         * interp.c (sim_info): Delete code printing memory size.
1648
1649         * interp.c (mips_size): Nee sim_size, delete function.
1650         (power2): Delete.
1651         (monitor, monitor_base, monitor_size): Delete global variables.
1652         (sim_open, sim_close): Delete code creating monitor and other
1653         memory regions.  Use sim-memopts module, via sim_do_commandf, to
1654         manage memory regions.
1655         (load_memory, store_memory): Use sim-core for memory model.
1656
1657         * interp.c (address_translation): Delete all memory map code
1658         except line forcing 32 bit addresses.
1659
1660 Wed Nov  5 11:21:11 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1661
1662         * sim-main.h (WITH_TRACE): Delete definition.  Enables common
1663         trace options.
1664
1665         * interp.c (logfh, logfile): Delete globals.
1666         (sim_open, sim_close): Delete code opening & closing log file.
1667         (mips_option_handler): Delete -l and -n options.
1668         (OPTION mips_options): Ditto.
1669
1670         * interp.c (OPTION mips_options): Rename option trace to dinero.
1671         (mips_option_handler): Update.
1672
1673 Wed Nov  5 09:35:59 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1674
1675         * interp.c (fetch_str): New function.
1676         (sim_monitor): Rewrite using sim_read & sim_write.
1677         (sim_open): Check magic number.
1678         (sim_open): Write monitor vectors into memory using sim_write.
1679         (MONITOR_BASE, MONITOR_SIZE, MEM_SIZE): Define.
1680         (sim_read, sim_write): Simplify - transfer data one byte at a
1681         time.
1682         (load_memory, store_memory): Clarify meaning of parameter RAW.
1683
1684         * sim-main.h (isHOST): Defete definition.
1685         (isTARGET): Mark as depreciated.
1686         (address_translation): Delete parameter HOST.
1687
1688         * interp.c (address_translation): Delete parameter HOST.
1689
1690 start-sanitize-tx49
1691 Wed Oct 29 14:21:32 1997  Gavin Koch  <gavin@cygnus.com>
1692
1693         * gencode.c: Add tx49 configury and insns.
1694         * configure.in: Add tx49 configury.
1695         * configure: Update.
1696
1697 end-sanitize-tx49
1698 Wed Oct 29 11:13:56 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1699
1700         * mips.igen:
1701
1702         * Makefile.in (IGEN_INCLUDE): Files included by mips.igen.
1703         (tmp-igen, tmp-m16): Depend on IGEN_INCLUDE.
1704
1705 Tue Oct 28 11:06:47 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1706
1707         * mips.igen: Add model filter field to records.
1708
1709 Mon Oct 27 17:53:59 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1710
1711         * Makefile.in (SIM_NO_CFLAGS): Define.  Define WITH_IGEN=0.
1712
1713         interp.c (sim_engine_run): Do not compile function sim_engine_run
1714         when WITH_IGEN == 1.
1715
1716         * configure.in (sim_igen_flags, sim_m16_flags): Set according to
1717         target architecture.
1718
1719         Makefile.in (tmp-igen, tmp-m16): Drop -F and -M options to
1720         igen. Replace with configuration variables sim_igen_flags /
1721         sim_m16_flags.
1722
1723         start-sanitize-r5900
1724         * r5900.igen: New file. Copy r5900 insns here.
1725         end-sanitize-r5900
1726         start-sanitize-cygnus
1727         * vr5400.igen: New file.
1728         end-sanitize-cygnus
1729         * m16.igen: New file.  Copy mips16 insns here.
1730         * mips.igen: From here.
1731
1732 Mon Oct 27 13:53:59 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1733
1734         start-sanitize-cygnus
1735         * mips.igen: Tag all mipsIV instructions with vr5400 model.
1736
1737         * configure.in: Add mips64vr5400 target.
1738         * configure: Re-generate.
1739
1740         end-sanitize-cygnus
1741         * Makefile.in (SIM_NO_OBJ): Define, move SIM_M16_OBJ, SIM_IGEN_OBJ
1742         to top.
1743         (tmp-igen, tmp-m16): Pass -I srcdir to igen.
1744
1745 Sat Oct 25 16:51:40 1997  Gavin Koch  <gavin@cygnus.com>
1746
1747         * gencode.c (build_instruction): Follow sim_write's lead in using
1748         BigEndianMem instead of !ByteSwapMem.
1749
1750 Fri Oct 24 17:41:49 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1751
1752         * configure.in (sim_gen): Dependent on target, select type of
1753         generator.  Always select old style generator.
1754
1755         configure: Re-generate.
1756
1757         Makefile.in (tmp-igen, tmp-m16, clean-m16, clean-igen): New
1758         targets.
1759         (SIM_M16_CFLAGS, SIM_M16_ALL, SIM_M16_OBJ, BUILT_SRC_FROM_M16,
1760         SIM_IGEN_CFLAGS, SIM_IGEN_ALL, SIM_IGEN_OBJ, BUILT_SRC_FROM_IGEN,
1761         IGEN_TRACE, IGEN_INSN, IGEN_DC): Define
1762         (SIM_EXTRA_CFLAGS, SIM_EXTRA_ALL, SIM_OBJS): Add member
1763         SIM_@sim_gen@_*, set by autoconf.
1764
1765 Wed Oct 22 12:52:06 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1766
1767         * sim-main.h (NULLIFY_NEXT_INSTRUCTION, DELAY_SLOT): Define.
1768
1769         * interp.c (ColdReset): Remove #ifdef HASFPU, check
1770         CURRENT_FLOATING_POINT instead.
1771
1772         * interp.c (ifetch32): New function. Fetch 32 bit instruction.
1773         (address_translation): Raise exception InstructionFetch when
1774         translation fails and isINSTRUCTION.
1775
1776         * interp.c (sim_open, sim_write, sim_monitor, store_word,
1777         sim_engine_run): Change type of of vaddr and paddr to
1778         address_word.
1779         (address_translation, prefetch, load_memory, store_memory,
1780         cache_op): Change type of vAddr and pAddr to address_word.
1781
1782         * gencode.c (build_instruction): Change type of vaddr and paddr to
1783         address_word.
1784
1785 Mon Oct 20 15:29:04 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1786
1787         * sim-main.h (ALU64_END, ALU32_END): Use ALU*_OVERFLOW_RESULT
1788         macro to obtain result of ALU op.
1789
1790 Tue Oct 21 17:39:14 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1791
1792         * interp.c (sim_info): Call profile_print.
1793
1794 Mon Oct 20 13:31:20 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1795
1796         * Makefile.in (SIM_OBJS): Add sim-profile.o module.
1797
1798         * sim-main.h (WITH_PROFILE): Do not define, defined in
1799         common/sim-config.h.  Use sim-profile module.
1800         (simPROFILE): Delete defintion.
1801
1802         * interp.c (PROFILE): Delete definition.
1803         (mips_option_handler): Delete 'p', 'y' and 'x' profile options.
1804         (sim_close): Delete code writing profile histogram.
1805         (mips_set_profile, mips_set_profile_size, writeout16, writeout32):
1806         Delete.
1807         (sim_engine_run): Delete code profiling the PC.
1808
1809 Mon Oct 20 13:31:20 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1810
1811         * sim-main.h (SIGNEXTEND): Force type of result to unsigned_word.
1812
1813         * interp.c (sim_monitor): Make register pointers of type
1814         unsigned_word*.
1815
1816         * sim-main.h: Make registers of type unsigned_word not
1817         signed_word.
1818
1819 Thu Oct 16 10:31:39 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1820
1821 start-sanitize-r5900
1822         * sim-main.h (BYTES_IN_MMI_REGS, ..., SUB_REG_FETCH, ..., GPR_SB,
1823         ...): Move to sim-main.h
1824
1825 end-sanitize-r5900
1826         * interp.c (sync_operation): Rename from SyncOperation, make
1827         global, add SD argument.
1828         (prefetch): Rename from Prefetch, make global, add SD argument.
1829         (decode_coproc): Make global.
1830
1831         * sim-main.h (SyncOperation, DecodeCoproc, Pefetch): Define.
1832
1833         * gencode.c (build_instruction): Generate DecodeCoproc not
1834         decode_coproc calls.
1835
1836         * interp.c (SETFCC, GETFCC, PREVCOC1): Move to sim-main.h
1837         (SizeFGR): Move to sim-main.h
1838         (simHALTEX, simHALTIN, simTRACE, simPROFILE, simDELAYSLOT,
1839         simSIGINT, simJALDELAYSLOT): Move to sim-main.h
1840         (FP_FLAGS, FP_ENABLE, FP_CAUSE, IR, UF, OF, DZ, IO, UO): Move to
1841         sim-main.h.
1842         (FP_FS, FP_MASK_RM, FP_SH_RM, FP_RM_NEAREST, FP_RM_TOPINF,
1843         FP_RM_TOMINF, GETRM): Move to sim-main.h.
1844         (Uncached, CachedNoncoherent, CachedCoherent, Cached,
1845         isINSTRUCTION, ..., AccessLength_BYTE, ...): Move to sim-main.h.
1846         (UserMode, BigEndianMem, ByteSwapMem, ReverseEndian,
1847         BigEndianCPU, status_KSU_mask, ...). Moved to sim-main.h
1848
1849         * sim-main.h (ALU32_END, ALU64_END): Define. When overflow raise
1850         exception.
1851         (sim-alu.h): Include.
1852         (NULLIFY_NIA, NULL_CIA, CPU_CIA): Define.
1853         (sim_cia): Typedef to instruction_address.
1854
1855 Thu Oct 16 10:31:41 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1856
1857         * Makefile.in (interp.o): Rename generated file engine.c to
1858         oengine.c.
1859
1860         * interp.c: Update.
1861
1862 Thu Oct 16 10:31:40 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1863
1864         * gencode.c (build_instruction): Use FPR_STATE not fpr_state.
1865
1866 Thu Oct 16 10:31:39 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1867
1868         * gencode.c (build_instruction): For "FPSQRT", output correct
1869         number of arguments to Recip.
1870
1871 Tue Oct 14 17:38:18 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1872
1873         * Makefile.in (interp.o): Depends on sim-main.h
1874
1875         * interp.c (mips16_entry, ColdReset,dotrace): Add SD argument. Use GPR not registers.
1876
1877         * sim-main.h (sim_cpu): Add registers, register_widths, fpr_state,
1878         ipc, dspc, pending_*, hiaccess, loaccess, state, dsstate fields.
1879         (REGISTERS, REGISTER_WIDTHS, FPR_STATE, IPC, DSPC, PENDING_*,
1880         STATE, DSSTATE): Define
1881         (GPR, FGRIDX, ..): Define.
1882
1883         * interp.c (registers, register_widths, fpr_state, ipc, dspc,
1884         pending_*, hiaccess, loaccess, state, dsstate): Delete globals.
1885         (GPR, FGRIDX, ...): Delete macros.
1886
1887         * interp.c: Update names to match defines from sim-main.h
1888
1889 Tue Oct 14 15:11:45 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1890
1891         * interp.c (sim_monitor): Add SD argument.
1892         (sim_warning): Delete.  Replace calls with calls to
1893         sim_io_eprintf.
1894         (sim_error): Delete. Replace calls with sim_io_error.
1895         (open_trace, writeout32, writeout16, getnum): Add SD argument.
1896         (mips_set_profile): Rename from sim_set_profile. Add SD argument.
1897         (mips_set_profile_size): Rename from sim_set_profile_size. Add SD
1898         argument.
1899         (mips_size): Rename from sim_size. Add SD argument.
1900
1901         * interp.c (simulator): Delete global variable.
1902         (callback): Delete global variable.
1903         (mips_option_handler, sim_open, sim_write, sim_read,
1904         sim_store_register, sim_fetch_register, sim_info, sim_do_command,
1905         sim_size,sim_monitor): Use sim_io_* not callback->*.
1906         (sim_open): ZALLOC simulator struct.
1907         (PROFILE): Do not define.
1908
1909 Tue Oct 14 13:35:48 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1910
1911         * interp.c (sim_open), support.h: Replace CHECKSIM macro found in
1912         support.h with corresponding code.
1913
1914         * sim-main.h (word64, uword64), support.h: Move definition to
1915         sim-main.h.
1916         (WORD64LO, WORD64HI, SET64LO, SET64HI, WORD64, UWORD64): Ditto.
1917
1918         * support.h: Delete
1919         * Makefile.in: Update dependencies
1920         * interp.c: Do not include.
1921
1922 Tue Oct 14 13:35:48 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1923
1924         * interp.c (address_translation, load_memory, store_memory,
1925         cache_op): Rename to from AddressTranslation et.al., make global,
1926         add SD argument
1927
1928         * sim-main.h (AddressTranslation, LoadMemory, StoreMemory,
1929         CacheOp): Define.
1930
1931         * interp.c (SignalException): Rename to signal_exception, make
1932         global.
1933
1934         * interp.c (Interrupt, ...): Move definitions to sim-main.h.
1935
1936         * sim-main.h (SignalException, SignalExceptionInterrupt,
1937         SignalExceptionInstructionFetch, SignalExceptionAddressStore,
1938         SignalExceptionAddressLoad, SignalExceptionSimulatorFault,
1939         SignalExceptionIntegerOverflow, SignalExceptionCoProcessorUnusable):
1940         Define.
1941
1942         * interp.c, support.h: Use.
1943
1944 Tue Oct 14 13:19:20 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1945
1946         * interp.c (ValueFPR, StoreFPR), sim-main.h: Make global, rename
1947         to value_fpr / store_fpr. Add SD argument.
1948         (NaN, Infinity, Less, Equal, AbsoluteValue, Negate, Add, Sub,
1949         Multiply, Divide, Recip, SquareRoot, Convert): Make global.
1950
1951         * sim-main.h (ValueFPR, StoreFPR): Define.
1952
1953 Tue Oct 14 13:06:55 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1954
1955         * interp.c (sim_engine_run): Check consistency between configure
1956         WITH_TARGET_WORD_BITSIZE and WITH_FLOATING_POINT and gensim GPRLEN
1957         and HASFPU.
1958
1959         * configure.in (mips_bitsize): Configure WITH_TARGET_WORD_BITSIZE.
1960         (mips_fpu): Configure WITH_FLOATING_POINT.
1961         (mips_endian): Configure WITH_TARGET_ENDIAN.
1962         * configure: Update.
1963
1964 Fri Oct  3 09:28:00 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1965
1966         * configure: Regenerated to track ../common/aclocal.m4 changes.
1967
1968 start-sanitize-r5900
1969 Mon Aug 25 19:11:15 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1970
1971         * interp.c (MAX_REG): Allow up-to 128 registers.
1972         (LO1, HI1): Define value that matches REGISTER_NAMES in gdb.
1973         (REGISTER_SA): Ditto.
1974         (sim_open): Initialize register_widths for r5900 specific
1975         registers.
1976         (sim_fetch_register, sim_store_register): Check for request of
1977         r5900 specific SA register.  Check for request for hi 64 bits of
1978         r5900 specific registers.
1979
1980 end-sanitize-r5900
1981 Mon Sep 29 14:45:00 1997  Bob Manson  <manson@charmed.cygnus.com>
1982
1983         * configure: Regenerated.
1984
1985 Fri Sep 26 12:48:18 1997  Mark Alexander  <marka@cygnus.com>
1986
1987         * interp.c: Allow Debug, DEPC, and EPC registers to be examined in GDB.
1988
1989 Thu Sep 25 11:15:22 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1990
1991         * gencode.c (print_igen_insn_models): Assume certain architectures
1992         include all mips* instructions.
1993         (print_igen_insn_format): Use data_size==-1 as marker for MIPS16
1994         instruction.
1995
1996         * Makefile.in (tmp.igen): Add target. Generate igen input from
1997         gencode file.
1998
1999         * gencode.c (FEATURE_IGEN): Define.
2000         (main): Add --igen option.  Generate output in igen format.
2001         (process_instructions): Format output according to igen option.
2002         (print_igen_insn_format): New function.
2003         (print_igen_insn_models): New function.
2004         (process_instructions): Only issue warnings and ignore
2005         instructions when no FEATURE_IGEN.
2006
2007 Wed Sep 24 17:38:57 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2008
2009         * interp.c (COP_SD, COP_LD): Add UNUSED to pacify GCC for some
2010         MIPS targets.
2011
2012 Tue Sep 23 11:04:38 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2013
2014         * configure: Regenerated to track ../common/aclocal.m4 changes.
2015
2016 Tue Sep 23 10:19:51 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2017
2018         * Makefile.in (SIM_ALIGNMENT, SIM_ENDIAN, SIM_HOSTENDIAN,
2019         SIM_RESERVED_BITS): Delete, moved to common.
2020         (SIM_EXTRA_CFLAGS): Update.
2021
2022 Mon Sep 22 11:46:20 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2023
2024         * configure.in: Configure non-strict memory alignment.
2025         * configure: Regenerated to track ../common/aclocal.m4 changes.
2026
2027 Fri Sep 19 17:45:25 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2028
2029         * configure: Regenerated to track ../common/aclocal.m4 changes.
2030
2031 Sat Sep 20 14:07:28 1997  Gavin Koch  <gavin@cygnus.com>
2032
2033         * gencode.c (SDBBP,DERET): Added (3900) insns.
2034         (RFE): Turn on for 3900.
2035         * interp.c (DebugBreakPoint,DEPC,Debug,Debug_*): Added.
2036         (dsstate): Made global.
2037         (SUBTARGET_R3900): Added.
2038         (CANCELDELAYSLOT): New.
2039         (SignalException): Ignore SystemCall rather than ignore and
2040         terminate.  Add DebugBreakPoint handling.
2041         (decode_coproc): New insns RFE, DERET; and new registers Debug
2042         and DEPC protected by SUBTARGET_R3900.
2043         (sim_engine_run): Use CANCELDELAYSLOT rather than clearing
2044         bits explicitly.
2045         * Makefile.in,configure.in: Add mips subtarget option.
2046         * configure: Update.
2047
2048 Fri Sep 19 09:33:27 1997  Gavin Koch  <gavin@cygnus.com>
2049
2050         * gencode.c: Add r3900 (tx39).
2051
2052 start-sanitize-tx19
2053         * gencode.c: Fix some configuration problems by improving
2054         the relationship between tx19 and tx39.
2055 end-sanitize-tx19
2056
2057 Tue Sep 16 15:52:04 1997  Gavin Koch  <gavin@cygnus.com>
2058
2059         * gencode.c (build_instruction): Don't need to subtract 4 for
2060         JALR, just 2.
2061
2062 Tue Sep 16 11:32:28 1997  Gavin Koch  <gavin@cygnus.com>
2063
2064         * interp.c: Correct some HASFPU problems.
2065
2066 Mon Sep 15 17:36:15 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2067
2068         * configure: Regenerated to track ../common/aclocal.m4 changes.
2069
2070 Fri Sep 12 12:01:39 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2071
2072         * interp.c (mips_options): Fix samples option short form, should
2073         be `x'.
2074
2075 Thu Sep 11 09:35:29 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2076
2077         * interp.c (sim_info): Enable info code.  Was just returning.
2078
2079 Tue Sep  9 17:30:57 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2080
2081         * interp.c (decode_coproc): Clarify warning about unsuported MTC0,
2082         MFC0.
2083
2084 Tue Sep  9 16:28:28 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2085
2086         * gencode.c (build_instruction): Use SIGNED64 for 64 bit
2087         constants.
2088         (build_instruction): Ditto for LL.
2089
2090 start-sanitize-tx19
2091 Sun Sep  7 16:05:46 1997  Gavin Koch  <gavin@cygnus.com>
2092
2093         * mips/configure.in, mips/gencode: Add tx19/r1900.
2094
2095 end-sanitize-tx19
2096 Thu Sep  4 17:21:23 1997  Doug Evans  <dje@seba>
2097
2098         * configure: Regenerated to track ../common/aclocal.m4 changes.
2099
2100 start-sanitize-r5900
2101 Mon Sep  1 18:43:30 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2102
2103         * gencode.c (build_instruction): For "pabsw" and "pabsh", check
2104         for overflow due to ABS of MININT, set result to MAXINT.
2105         (build_instruction): For "psrlvw", signextend bit 31.
2106
2107 end-sanitize-r5900
2108 Wed Aug 27 18:13:22 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2109
2110         * configure: Regenerated to track ../common/aclocal.m4 changes.
2111         * config.in: Ditto.
2112
2113 Wed Aug 27 14:12:27 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2114
2115         * interp.c (sim_open): Add call to sim_analyze_program, update
2116         call to sim_config.
2117
2118 Tue Aug 26 10:40:07 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2119
2120         * interp.c (sim_kill): Delete.
2121         (sim_create_inferior): Add ABFD argument. Set PC from same.
2122         (sim_load): Move code initializing trap handlers from here.
2123         (sim_open): To here.
2124         (sim_load): Delete, use sim-hload.c.
2125
2126         * Makefile.in (SIM_OBJS): Add sim-hload.o module.
2127
2128 Mon Aug 25 17:50:22 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2129
2130         * configure: Regenerated to track ../common/aclocal.m4 changes.
2131         * config.in: Ditto.
2132
2133 Mon Aug 25 15:59:48 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2134
2135         * interp.c (sim_open): Add ABFD argument.
2136         (sim_load): Move call to sim_config from here.
2137         (sim_open): To here.  Check return status.
2138
2139 start-sanitize-r5900
2140         * gencode.c (build_instruction): Do not define x8000000000000000,
2141         x7FFFFFFFFFFFFFFF, or xFFFFFFFF80000000.
2142
2143 end-sanitize-r5900
2144 start-sanitize-r5900
2145 Mon Jul 28 19:49:29 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2146
2147         * gencode.c (build_instruction): For "pdivw", "pdivbw" and
2148         "pdivuw" check for overflow due to signed divide by -1.
2149
2150 end-sanitize-r5900
2151 Fri Jul 25 15:00:45 1997  Gavin Koch  <gavin@cygnus.com>
2152
2153         * gencode.c (build_instruction): Two arg MADD should
2154         not assign result to $0.
2155
2156 start-sanitize-r5900
2157 Thu Jul 10 11:58:48 1997  Andrew Cagney  <cagney@critters.cygnus.com>
2158
2159         * gencode.c (build_instruction): For "ppac5" use unsigned
2160         arrithmetic so that the sign bit doesn't smear when right shifted.
2161         (build_instruction): For "pdiv" perform sign extension when
2162         storing results in HI and LO.
2163         (build_instructions): For "pdiv" and "pdivbw" check for
2164         divide-by-zero.
2165         (build_instruction): For "pmfhl.slw" update hi part of dest
2166         register as well as low part.
2167         (build_instruction): For "pmfhl" portably handle long long values.
2168         (build_instruction): For "pmfhl.sh" correctly negative values.
2169         Store half words 2 and three in the correct place.
2170         (build_instruction): For "psllvw", sign extend value after shift.
2171
2172 end-sanitize-r5900
2173 Thu Jun 26 12:13:17 1997  Angela Marie Thomas (angela@cygnus.com)
2174
2175         * sim/mips/configure: Change default_sim_endian to 0 (bi-endian)
2176         * sim/mips/configure.in: Regenerate.
2177
2178 Wed Jul  9 10:29:21 1997  Andrew Cagney  <cagney@critters.cygnus.com>
2179
2180         * interp.c (SUB_REG_UW, SUB_REG_SW, SUB_REG_*): Use more explicit
2181         signed8, unsigned8 et.al. types.
2182
2183 start-sanitize-r5900
2184         * gencode.c (build_instruction): For PMULTU* do not sign extend
2185         registers.  Make generated code easier to debug.
2186
2187 end-sanitize-r5900
2188         * interp.c (SUB_REG_FETCH): Handle both little and big endian
2189         hosts when selecting subreg.
2190
2191 start-sanitize-r5900
2192 Tue Jul  8 18:07:20 1997  Andrew Cagney  <cagney@andros.cygnus.com>
2193
2194         * gencode.c (type_for_data_len): For 32bit operations concerned
2195         with overflow, perform op using 64bits.
2196         (build_instruction): For PADD, always compute operation using type
2197         returned by type_for_data_len.
2198         (build_instruction): For PSUBU, when overflow, saturate to zero as
2199         actually underflow.
2200
2201 end-sanitize-r5900
2202 Wed Jul  2 11:54:10 1997  Jeffrey A Law  (law@cygnus.com)
2203
2204 start-sanitize-r5900
2205         * gencode.c (build_instruction): Handle "pext5" according to
2206         version 1.95 of the r5900 ISA.
2207
2208         * gencode.c (build_instruction): Handle "ppac5" according to
2209         version 1.95 of the r5900 ISA.
2210
2211 end-sanitize-r5900
2212         * interp.c (sim_engine_run): Reset the ZERO register to zero
2213         regardless of FEATURE_WARN_ZERO.
2214         * gencode.c (FEATURE_WARNINGS): Remove FEATURE_WARN_ZERO.
2215
2216 Wed Jun  4 10:43:14 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2217
2218         * interp.c (decode_coproc): Implement MTC0 N, CAUSE.
2219         (SignalException): For BreakPoints ignore any mode bits and just
2220         save the PC.
2221         (SignalException): Always set the CAUSE register.
2222
2223 Tue Jun  3 05:00:33 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2224
2225         * interp.c (SignalException): Clear the simDELAYSLOT flag when an
2226         exception has been taken.
2227
2228         * interp.c: Implement the ERET and mt/f sr instructions.
2229
2230 start-sanitize-r5900
2231 Mon Jun  2 23:28:19 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2232
2233         * gencode.c (build_instruction): For paddu, extract unsigned
2234         sub-fields.
2235
2236         * gencode.c (build_instruction): Saturate padds instead of padd
2237         instructions.
2238
2239 end-sanitize-r5900
2240 Sat May 31 00:44:16 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2241
2242         * interp.c (SignalException): Don't bother restarting an
2243         interrupt.
2244
2245 Fri May 30 23:41:48 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2246
2247         * interp.c (SignalException): Really take an interrupt.
2248         (interrupt_event): Only deliver interrupts when enabled.
2249
2250 Tue May 27 20:08:06 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2251
2252         * interp.c (sim_info): Only print info when verbose.
2253         (sim_info) Use sim_io_printf for output.
2254
2255 Tue May 27 14:22:23 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2256
2257         * interp.c (CoProcPresent): Add UNUSED attribute - not used by all
2258         mips architectures.
2259
2260 Tue May 27 14:22:23 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2261
2262         * interp.c (sim_do_command): Check for common commands if a
2263         simulator specific command fails.
2264
2265 Thu May 22 09:32:03 1997  Gavin Koch  <gavin@cygnus.com>
2266
2267         * interp.c (sim_engine_run): ifdef out uses of simSTOP, simSTEP
2268         and simBE when DEBUG is defined.
2269
2270 Wed May 21 09:08:10 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2271
2272         * interp.c (interrupt_event): New function.  Pass exception event
2273         onto exception handler.
2274
2275         * configure.in: Check for stdlib.h.
2276         * configure: Regenerate.
2277
2278         * gencode.c (build_instruction): Add UNUSED attribute to tempS
2279         variable declaration.
2280         (build_instruction): Initialize memval1.
2281         (build_instruction): Add UNUSED attribute to byte, bigend,
2282         reverse.
2283         (build_operands): Ditto.
2284
2285         * interp.c: Fix GCC warnings.
2286         (sim_get_quit_code): Delete.
2287
2288         * configure.in: Add INLINE, ENDIAN, HOSTENDIAN and WARNINGS.
2289         * Makefile.in: Ditto.
2290         * configure: Re-generate.
2291
2292         * Makefile.in (SIM_OBJS): Add sim-watch.o module.
2293
2294 Tue May 20 15:08:56 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2295
2296         * interp.c (mips_option_handler): New function parse argumes using
2297         sim-options.
2298         (myname): Replace with STATE_MY_NAME.
2299         (sim_open): Delete check for host endianness - performed by
2300         sim_config.
2301         (simHOSTBE, simBE): Delete, replaced by sim-endian flags.
2302         (sim_open): Move much of the initialization from here.
2303         (sim_load): To here.  After the image has been loaded and
2304         endianness set.
2305         (sim_open): Move ColdReset from here.
2306         (sim_create_inferior): To here.
2307         (sim_open): Make FP check less dependant on host endianness.
2308
2309         * Makefile.in (SIM_RUN_OBJS): Set to nrun.o - use new version or
2310         run.
2311         * interp.c (sim_set_callbacks): Delete.
2312
2313         * interp.c (membank, membank_base, membank_size): Replace with
2314         STATE_MEMORY, STATE_MEM_SIZE, STATE_MEM_BASE.
2315         (sim_open): Remove call to callback->init. gdb/run do this.
2316
2317         * interp.c: Update
2318
2319         * sim-main.h (SIM_HAVE_FLATMEM): Define.
2320
2321         * interp.c (big_endian_p): Delete, replaced by
2322         current_target_byte_order.
2323
2324 Tue May 20 13:55:00 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2325
2326         * interp.c (host_read_long, host_read_word, host_swap_word,
2327         host_swap_long): Delete. Using common sim-endian.
2328         (sim_fetch_register, sim_store_register): Use H2T.
2329         (pipeline_ticks): Delete.  Handled by sim-events.
2330         (sim_info): Update.
2331         (sim_engine_run): Update.
2332
2333 Tue May 20 13:42:03 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2334
2335         * interp.c (sim_stop_reason): Move code determining simEXCEPTION
2336         reason from here.
2337         (SignalException): To here. Signal using sim_engine_halt.
2338         (sim_stop_reason): Delete, moved to common.
2339
2340 Tue May 20 10:19:48 1997  Andrew Cagney  <cagney@b2.cygnus.com>
2341
2342         * interp.c (sim_open): Add callback argument.
2343         (sim_set_callbacks): Delete SIM_DESC argument.
2344         (sim_size): Ditto.
2345
2346 Mon May 19 18:20:38 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2347
2348         * Makefile.in (SIM_OBJS): Add common modules.
2349
2350         * interp.c (sim_set_callbacks): Also set SD callback.
2351         (set_endianness, xfer_*, swap_*): Delete.
2352         (host_read_word, host_read_long, host_swap_word, host_swap_long):
2353         Change to functions using sim-endian macros.
2354         (control_c, sim_stop): Delete, use common version.
2355         (simulate): Convert into.
2356         (sim_engine_run): This function.
2357         (sim_resume): Delete.
2358
2359         * interp.c (simulation): New variable - the simulator object.
2360         (sim_kind): Delete global - merged into simulation.
2361         (sim_load): Cleanup.  Move PC assignment from here.
2362         (sim_create_inferior): To here.
2363
2364         * sim-main.h: New file.
2365         * interp.c (sim-main.h): Include.
2366
2367 Thu Apr 24 00:39:51 1997  Doug Evans  <dje@canuck.cygnus.com>
2368
2369         * configure: Regenerated to track ../common/aclocal.m4 changes.
2370
2371 Wed Apr 23 17:32:19 1997  Doug Evans  <dje@canuck.cygnus.com>
2372
2373         * tconfig.in (SIM_HAVE_BIENDIAN): Define.
2374
2375 Mon Apr 21 17:16:13 1997  Gavin Koch  <gavin@cygnus.com>
2376
2377         * gencode.c (build_instruction): DIV instructions: check
2378         for division by zero and integer overflow before using
2379         host's division operation.
2380
2381 Thu Apr 17 03:18:14 1997  Doug Evans  <dje@canuck.cygnus.com>
2382
2383         * Makefile.in (SIM_OBJS): Add sim-load.o.
2384         * interp.c: #include bfd.h.
2385         (target_byte_order): Delete.
2386         (sim_kind, myname, big_endian_p): New static locals.
2387         (sim_open): Set sim_kind, myname.  Move call to set_endianness to
2388         after argument parsing.  Recognize -E arg, set endianness accordingly.
2389         (sim_load): Return SIM_RC.  New arg abfd.  Call sim_load_file to
2390         load file into simulator.  Set PC from bfd.
2391         (sim_create_inferior): Return SIM_RC.  Delete arg start_address.
2392         (set_endianness): Use big_endian_p instead of target_byte_order.
2393
2394 Wed Apr 16 17:55:37 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2395
2396         * interp.c (sim_size): Delete prototype - conflicts with
2397         definition in remote-sim.h.  Correct definition.
2398
2399 Mon Apr  7 15:45:02 1997  Andrew Cagney  <cagney@kremvax.cygnus.com>
2400
2401         * configure: Regenerated to track ../common/aclocal.m4 changes.
2402         * config.in: Ditto.
2403
2404 Wed Apr  2 15:06:28 1997  Doug Evans  <dje@canuck.cygnus.com>
2405
2406         * interp.c (sim_open): New arg `kind'.
2407
2408         * configure: Regenerated to track ../common/aclocal.m4 changes.
2409
2410 Wed Apr  2 14:34:19 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
2411
2412         * configure: Regenerated to track ../common/aclocal.m4 changes.
2413
2414 Tue Mar 25 11:38:22 1997  Doug Evans  <dje@canuck.cygnus.com>
2415
2416         * interp.c (sim_open): Set optind to 0 before calling getopt.
2417
2418 Wed Mar 19 01:14:00 1997  Andrew Cagney  <cagney@kremvax.cygnus.com>
2419
2420         * configure: Regenerated to track ../common/aclocal.m4 changes.
2421
2422 Mon Mar 17 10:52:59 1997  Gavin Koch  <gavin@cetus.cygnus.com>
2423
2424         * interp.c : Replace uses of pr_addr with pr_uword64
2425         where the bit length is always 64 independent of SIM_ADDR.
2426         (pr_uword64) : added.
2427
2428 Mon Mar 17 15:10:07 1997  Andrew Cagney  <cagney@kremvax.cygnus.com>
2429
2430         * configure: Re-generate.
2431
2432 Fri Mar 14 10:34:11 1997  Michael Meissner  <meissner@cygnus.com>
2433
2434         * configure: Regenerate to track ../common/aclocal.m4 changes.
2435
2436 Thu Mar 13 12:51:36 1997  Doug Evans  <dje@canuck.cygnus.com>
2437
2438         * interp.c (sim_open): New SIM_DESC result.  Argument is now
2439         in argv form.
2440         (other sim_*): New SIM_DESC argument.
2441
2442 start-sanitize-r5900
2443 Wed Feb 26 18:32:21 1997  Gavin Koch  <gavin@cygnus.com>
2444
2445         * gencode.c (POP_AND,POP_OR,POP_NOR,POP_XOR):
2446         Change values to avoid overloading DOUBLEWORD which is tested
2447         for all insns.
2448         * gencode.c: reinstate "offending code".
2449
2450 end-sanitize-r5900
2451 Mon Feb 24 22:47:14 1997  Dawn Perchik  <dawn@cygnus.com>
2452
2453         * interp.c: Fix printing of addresses for non-64-bit targets.
2454         (pr_addr): Add function to print address based on size.
2455 start-sanitize-r5900
2456         * gencode.c: #ifdef out offending code until a permanent fix
2457         can be added.  Code is causing build errors for non-5900 mips targets.
2458 end-sanitize-r5900
2459
2460 start-sanitize-r5900
2461 Thu Feb 20 10:40:24 1997  Gavin Koch  <gavin@cetus.cygnus.com>
2462
2463         * gencode.c (process_instructions): Correct test for ISA dependent
2464         architecture bits in isa field of MIPS_DECODE.
2465
2466 end-sanitize-r5900
2467 Wed Feb 19 14:42:09 1997  Mark Alexander  <marka@cygnus.com>
2468
2469         * interp.c (simopen): Add support for LSI MiniRISC PMON vectors.
2470
2471 start-sanitize-r5900
2472 Tue Feb 18 17:03:47 1997  Gavin Koch  <gavin@cygnus.com>
2473
2474         * gencode.c (MIPS_DECODE): Correct instruction feature flags for
2475         PMADDUW.
2476
2477 end-sanitize-r5900
2478 Thu Feb 13 14:08:30 1997  Ian Lance Taylor  <ian@cygnus.com>
2479
2480         * gencode.c (build_mips16_operands): Correct computation of base
2481         address for extended PC relative instruction.
2482
2483 start-sanitize-r5900
2484 Fri Feb  7 11:12:44 1997  Gavin Koch  <gavin@cygnus.com>
2485
2486         * Makefile.in, configure, configure.in, gencode.c,
2487         interp.c, support.h: add r5900.
2488
2489 end-sanitize-r5900
2490 Thu Feb  6 17:16:15 1997  Ian Lance Taylor  <ian@cygnus.com>
2491
2492         * interp.c (mips16_entry): Add support for floating point cases.
2493         (SignalException): Pass floating point cases to mips16_entry.
2494         (ValueFPR): Don't restrict fmt_single and fmt_word to even
2495         registers.
2496         (StoreFPR): Likewise.  Also, don't clobber fpr + 1 for fmt_single
2497         or fmt_word.
2498         (COP_LW): Pass fmt_word rather than fmt_uninterpreted to StoreFPR,
2499         and then set the state to fmt_uninterpreted.
2500         (COP_SW): Temporarily set the state to fmt_word while calling
2501         ValueFPR.
2502
2503 Tue Feb  4 16:48:25 1997  Ian Lance Taylor  <ian@cygnus.com>
2504
2505         * gencode.c (build_instruction): The high order may be set in the
2506         comparison flags at any ISA level, not just ISA 4.
2507
2508 Tue Feb  4 13:33:30 1997  Doug Evans  <dje@canuck.cygnus.com>
2509
2510         * Makefile.in (@COMMON_MAKEFILE_FRAG): Use
2511         COMMON_{PRE,POST}_CONFIG_FRAG instead.
2512         * configure.in: sinclude ../common/aclocal.m4.
2513         * configure: Regenerated.
2514
2515 Fri Jan 31 11:11:45 1997  Ian Lance Taylor  <ian@cygnus.com>
2516
2517         * configure: Rebuild after change to aclocal.m4.
2518
2519 Thu Jan 23 11:46:23 1997  Stu Grossman  (grossman@critters.cygnus.com)
2520
2521         * configure configure.in Makefile.in:  Update to new configure
2522         scheme which is more compatible with WinGDB builds.
2523         * configure.in:  Improve comment on how to run autoconf.
2524         * configure:  Re-run autoconf to get new ../common/aclocal.m4.
2525         * Makefile.in:  Use autoconf substitution to install common
2526         makefile fragment.
2527
2528 Wed Jan  8 12:39:03 1997  Jim Wilson  <wilson@cygnus.com>
2529
2530         * gencode.c (build_instruction): Use BigEndianCPU instead of
2531         ByteSwapMem.
2532
2533 Thu Jan 02 22:23:04 1997  Mark Alexander  <marka@cygnus.com>
2534
2535         * interp.c (sim_monitor): Make output to stdout visible in
2536         wingdb's I/O log window.
2537
2538 Tue Dec 31 07:04:00 1996  Mark Alexander  <marka@cygnus.com>
2539
2540         * support.h: Undo previous change to SIGTRAP
2541         and SIGQUIT values.
2542
2543 Mon Dec 30 17:36:06 1996  Ian Lance Taylor  <ian@cygnus.com>
2544
2545         * interp.c (store_word, load_word): New static functions.
2546         (mips16_entry): New static function.
2547         (SignalException): Look for mips16 entry and exit instructions.
2548         (simulate): Use the correct index when setting fpr_state after
2549         doing a pending move.
2550
2551 Sun Dec 29 09:37:18 1996  Mark Alexander  <marka@cygnus.com>
2552
2553         * interp.c: Fix byte-swapping code throughout to work on
2554         both little- and big-endian hosts.
2555
2556 Sun Dec 29 09:18:32 1996  Mark Alexander  <marka@cygnus.com>
2557
2558         * support.h: Make definitions of SIGTRAP and SIGQUIT consistent
2559         with gdb/config/i386/xm-windows.h.
2560
2561 Fri Dec 27 22:48:51 1996  Mark Alexander  <marka@cygnus.com>
2562
2563         * gencode.c (build_instruction): Work around MSVC++ code gen bug
2564         that messes up arithmetic shifts.
2565
2566 Fri Dec 20 11:04:05 1996  Stu Grossman  (grossman@critters.cygnus.com)
2567
2568         * support.h:  Use _WIN32 instead of __WIN32__.  Also add defs for
2569         SIGTRAP and SIGQUIT for _WIN32.
2570
2571 Thu Dec 19 14:07:27 1996  Ian Lance Taylor  <ian@cygnus.com>
2572
2573         * gencode.c (build_instruction) [MUL]: Cast operands to word64, to
2574         force a 64 bit multiplication.
2575         (build_instruction) [OR]: In mips16 mode, don't do anything if the
2576         destination register is 0, since that is the default mips16 nop
2577         instruction.
2578
2579 Mon Dec 16 14:59:38 1996  Ian Lance Taylor  <ian@cygnus.com>
2580
2581         * gencode.c (MIPS16_DECODE): SWRASP is I8, not RI.
2582         (build_endian_shift): Don't check proc64.
2583         (build_instruction): Always set memval to uword64.  Cast op2 to
2584         uword64 when shifting it left in memory instructions.  Always use
2585         the same code for stores--don't special case proc64.
2586
2587         * gencode.c (build_mips16_operands): Fix base PC value for PC
2588         relative operands.
2589         (build_instruction): Call JALDELAYSLOT rather than DELAYSLOT for a
2590         jal instruction.
2591         * interp.c (simJALDELAYSLOT): Define.
2592         (JALDELAYSLOT): Define.
2593         (INDELAYSLOT, INJALDELAYSLOT): Define.
2594         (simulate): Clear simJALDELAYSLOT when simDELAYSLOT is cleared.
2595
2596 Tue Dec 24 22:11:20 1996  Angela Marie Thomas (angela@cygnus.com)
2597
2598         * interp.c (sim_open): add flush_cache as a PMON routine
2599         (sim_monitor): handle flush_cache by ignoring it
2600
2601 Wed Dec 11 13:53:51 1996  Jim Wilson  <wilson@cygnus.com>
2602
2603         * gencode.c (build_instruction): Use !ByteSwapMem instead of
2604         BigEndianMem.
2605         * interp.c (CONFIG, config_EP_{mask,shift,D,DxxDxx, config_BE): Delete.
2606         (BigEndianMem): Rename to ByteSwapMem and change sense.
2607         (BigEndianCPU, sim_write, LoadMemory, StoreMemory): Change
2608         BigEndianMem references to !ByteSwapMem.
2609         (set_endianness): New function, with prototype.
2610         (sim_open): Call set_endianness.
2611         (sim_info): Use simBE instead of BigEndianMem.
2612         (xfer_direct_word, xfer_direct_long, swap_direct_word,
2613         swap_direct_long, xfer_big_word, xfer_big_long, xfer_little_word,
2614         xfer_little_long, swap_word, swap_long): Delete unnecessary MSC_VER
2615         ifdefs, keeping the prototype declaration.
2616         (swap_word): Rewrite correctly.
2617         (ColdReset): Delete references to CONFIG.  Delete endianness related
2618         code; moved to set_endianness.
2619
2620 Tue Dec 10 11:32:04 1996  Jim Wilson  <wilson@cygnus.com>
2621
2622         * gencode.c (build_instruction, case JUMP): Truncate PC to 32 bits.
2623         * interp.c (CHECKHILO): Define away.
2624         (simSIGINT): New macro.
2625         (membank_size): Increase from 1MB to 2MB.
2626         (control_c): New function.
2627         (sim_resume): Rename parameter signal to signal_number.  Add local
2628         variable prev.  Call signal before and after simulate.
2629         (sim_stop_reason): Add simSIGINT support.
2630         (sim_warning, sim_error, dotrace, SignalException): Define as stdarg
2631         functions always.
2632         (sim_warning): Delete call to SignalException.  Do call printf_filtered
2633         if logfh is NULL.
2634         (AddressTranslation): Add #ifdef DEBUG around debugging message and
2635         a call to sim_warning.
2636
2637 Wed Nov 27 11:53:50 1996  Ian Lance Taylor  <ian@cygnus.com>
2638
2639         * gencode.c (process_instructions): If ! proc64, skip DOUBLEWORD
2640         16 bit instructions.
2641
2642 Tue Nov 26 11:53:12 1996  Ian Lance Taylor  <ian@cygnus.com>
2643
2644         Add support for mips16 (16 bit MIPS implementation):
2645         * gencode.c (inst_type): Add mips16 instruction encoding types.
2646         (GETDATASIZEINSN): Define.
2647         (MIPS_DECODE): Add REG flag to dsllv, dsrav, and dsrlv.  Add
2648         jalx.  Add LEFT flag to mfhi and mflo.  Add RIGHT flag to mthi and
2649         mtlo.
2650         (MIPS16_DECODE): New table, for mips16 instructions.
2651         (bitmap_val): New static function.
2652         (struct mips16_op): Define.
2653         (mips16_op_table): New table, for mips16 operands.
2654         (build_mips16_operands): New static function.
2655         (process_instructions): If PC is odd, decode a mips16
2656         instruction.  Break out instruction handling into new
2657         build_instruction function.
2658         (build_instruction): New static function, broken out of
2659         process_instructions.  Check modifiers rather than flags for SHIFT
2660         bit count and m[ft]{hi,lo} direction.
2661         (usage): Pass program name to fprintf.
2662         (main): Remove unused variable this_option_optind.  Change
2663         ``*loptarg++'' to ``loptarg++''.
2664         (my_strtoul): Parenthesize && within ||.
2665         * interp.c (LoadMemory): Accept a halfword pAddr if vAddr is odd.
2666         (simulate): If PC is odd, fetch a 16 bit instruction, and
2667         increment PC by 2 rather than 4.
2668         * configure.in: Add case for mips16*-*-*.
2669         * configure: Rebuild.
2670
2671 Fri Nov 22 08:49:36 1996  Mark Alexander  <marka@cygnus.com>
2672
2673         * interp.c: Allow -t to enable tracing in standalone simulator.
2674         Fix garbage output in trace file and error messages.
2675
2676 Wed Nov 20 01:54:37 1996  Doug Evans  <dje@canuck.cygnus.com>
2677
2678         * Makefile.in: Delete stuff moved to ../common/Make-common.in.
2679         (SIM_{OBJS,EXTRA_CFLAGS,EXTRA_CLEAN}): Define.
2680         * configure.in: Simplify using macros in ../common/aclocal.m4.
2681         * configure: Regenerated.
2682         * tconfig.in: New file.
2683
2684 Tue Nov 12 13:34:00 1996  Dawn Perchik  <dawn@cygnus.com>
2685
2686         * interp.c: Fix bugs in 64-bit port.
2687         Use ansi function declarations for msvc compiler.
2688         Initialize and test file pointer in trace code.
2689         Prevent duplicate definition of LAST_EMED_REGNUM.
2690
2691 Tue Oct 15 11:07:06 1996  Mark Alexander  <marka@cygnus.com>
2692
2693         * interp.c (xfer_big_long): Prevent unwanted sign extension.
2694
2695 Thu Sep 26 17:35:00 1996  James G. Smith  <jsmith@cygnus.co.uk>
2696
2697         * interp.c (SignalException): Check for explicit terminating
2698         breakpoint value.
2699         * gencode.c: Pass instruction value through SignalException()
2700         calls for Trap, Breakpoint and Syscall.
2701
2702 Thu Sep 26 11:35:17 1996  James G. Smith  <jsmith@cygnus.co.uk>
2703
2704         * interp.c (SquareRoot): Add HAVE_SQRT check to ensure sqrt() is
2705         only used on those hosts that provide it.
2706         * configure.in: Add sqrt() to list of functions to be checked for.
2707         * config.in: Re-generated.
2708         * configure: Re-generated.
2709
2710 Fri Sep 20 15:47:12 1996  Ian Lance Taylor  <ian@cygnus.com>
2711
2712         * gencode.c (process_instructions): Call build_endian_shift when
2713         expanding STORE RIGHT, to fix swr.
2714         * support.h (SIGNEXTEND): If the sign bit is not set, explicitly
2715         clear the high bits.
2716         * interp.c (Convert): Fix fmt_single to fmt_long to not truncate.
2717         Fix float to int conversions to produce signed values.
2718
2719 Thu Sep 19 15:34:17 1996  Ian Lance Taylor  <ian@cygnus.com>
2720
2721         * gencode.c (MIPS_DECODE): Set UNSIGNED for multu instruction.
2722         (process_instructions): Correct handling of nor instruction.
2723         Correct shift count for 32 bit shift instructions. Correct sign
2724         extension for arithmetic shifts to not shift the number of bits in
2725         the type.  Fix 64 bit multiply high word calculation.  Fix 32 bit
2726         unsigned multiply.  Fix ldxc1 and friends to use coprocessor 1.
2727         Fix madd.
2728         * interp.c (CHECKHILO): Don't set HIACCESS, LOACCESS, or HLPC.
2729         It's OK to have a mult follow a mult.  What's not OK is to have a
2730         mult follow an mfhi.
2731         (Convert): Comment out incorrect rounding code.
2732
2733 Mon Sep 16 11:38:16 1996  James G. Smith  <jsmith@cygnus.co.uk>
2734
2735         * interp.c (sim_monitor): Improved monitor printf
2736         simulation. Tidied up simulator warnings, and added "--log" option
2737         for directing warning message output.
2738         * gencode.c: Use sim_warning() rather than WARNING macro.
2739
2740 Thu Aug 22 15:03:12 1996  Ian Lance Taylor  <ian@cygnus.com>
2741
2742         * Makefile.in (gencode): Depend upon gencode.o, getopt.o, and
2743         getopt1.o, rather than on gencode.c.  Link objects together.
2744         Don't link against -liberty.
2745         (gencode.o, getopt.o, getopt1.o): New targets.
2746         * gencode.c: Include <ctype.h> and "ansidecl.h".
2747         (AND): Undefine after including "ansidecl.h".
2748         (ULONG_MAX): Define if not defined.
2749         (OP_*): Don't define macros; now defined in opcode/mips.h.
2750         (main): Call my_strtoul rather than strtoul.
2751         (my_strtoul): New static function.
2752
2753 Wed Jul 17 18:12:38 1996  Stu Grossman  (grossman@critters.cygnus.com)
2754
2755         * gencode.c (process_instructions):  Generate word64 and uword64
2756         instead of `long long' and `unsigned long long' data types.
2757         * interp.c:  #include sysdep.h to get signals, and define default
2758         for SIGBUS.
2759         * (Convert):  Work around for Visual-C++ compiler bug with type
2760         conversion.
2761         * support.h:  Make things compile under Visual-C++ by using
2762         __int64 instead of `long long'.  Change many refs to long long
2763         into word64/uword64 typedefs.
2764
2765 Wed Jun 26 12:24:55 1996  Jason Molenda  (crash@godzilla.cygnus.co.jp)
2766
2767         * Makefile.in (bindir, libdir, datadir, mandir, infodir, includedir,
2768         INSTALL_PROGRAM, INSTALL_DATA): Use autoconf-set values.
2769         (docdir): Removed.
2770         * configure.in (AC_PREREQ): autoconf 2.5 or higher.
2771         (AC_PROG_INSTALL): Added.
2772         (AC_PROG_CC): Moved to before configure.host call.
2773         * configure: Rebuilt.
2774
2775 Wed Jun  5 08:28:13 1996  James G. Smith  <jsmith@cygnus.co.uk>
2776
2777         * configure.in: Define @SIMCONF@ depending on mips target.
2778         * configure: Rebuild.
2779         * Makefile.in (run): Add @SIMCONF@ to control simulator
2780         construction.
2781         * gencode.c: Change LOADDRMASK to 64bit memory model only.
2782         * interp.c: Remove some debugging, provide more detailed error
2783         messages, update memory accesses to use LOADDRMASK.
2784
2785 Mon Jun  3 11:55:03 1996  Ian Lance Taylor  <ian@cygnus.com>
2786
2787         * configure.in: Add calls to AC_CONFIG_HEADER, AC_CHECK_HEADERS,
2788         AC_CHECK_LIB, and AC_CHECK_FUNCS.  Change AC_OUTPUT to set
2789         stamp-h.
2790         * configure: Rebuild.
2791         * config.in: New file, generated by autoheader.
2792         * interp.c: Include "config.h".  Include <stdlib.h>, <string.h>,
2793         and <strings.h> if they exist.  Replace #ifdef sun with #ifdef
2794         HAVE_ANINT and HAVE_AINT, as appropriate.
2795         * Makefile.in (run): Use @LIBS@ rather than -lm.
2796         (interp.o): Depend upon config.h.
2797         (Makefile): Just rebuild Makefile.
2798         (clean): Remove stamp-h.
2799         (mostlyclean): Make the same as clean, not as distclean.
2800         (config.h, stamp-h): New targets.
2801
2802 Fri May 10 00:41:17 1996  James G. Smith  <jsmith@cygnus.co.uk>
2803
2804         * interp.c (ColdReset): Fix boolean test. Make all simulator
2805         globals static.
2806
2807 Wed May  8 15:12:58 1996  James G. Smith  <jsmith@cygnus.co.uk>
2808
2809         * interp.c (xfer_direct_word, xfer_direct_long,
2810         swap_direct_word, swap_direct_long, xfer_big_word,
2811         xfer_big_long, xfer_little_word, xfer_little_long,
2812         swap_word,swap_long): Added.
2813         * interp.c (ColdReset): Provide function indirection to
2814         host<->simulated_target transfer routines.
2815         * interp.c (sim_store_register, sim_fetch_register): Updated to
2816         make use of indirected transfer routines.
2817
2818 Fri Apr 19 15:48:24 1996  James G. Smith  <jsmith@cygnus.co.uk>
2819
2820         * gencode.c (process_instructions): Ensure FP ABS instruction
2821         recognised.
2822         * interp.c (AbsoluteValue): Add routine. Also provide simple PMON
2823         system call support.
2824
2825 Wed Apr 10 09:51:38 1996  James G. Smith  <jsmith@cygnus.co.uk>
2826
2827         * interp.c (sim_do_command): Complain if callback structure not
2828         initialised.
2829
2830 Thu Mar 28 13:50:51 1996  James G. Smith  <jsmith@cygnus.co.uk>
2831
2832         * interp.c (Convert): Provide round-to-nearest and round-to-zero
2833         support for Sun hosts.
2834         * Makefile.in (gencode): Ensure the host compiler and libraries
2835         used for cross-hosted build.
2836
2837 Wed Mar 27 14:42:12 1996  James G. Smith  <jsmith@cygnus.co.uk>
2838
2839         * interp.c, gencode.c: Some more (TODO) tidying.
2840
2841 Thu Mar  7 11:19:33 1996  James G. Smith  <jsmith@cygnus.co.uk>
2842
2843         * gencode.c, interp.c: Replaced explicit long long references with
2844         WORD64HI, WORD64LO, SET64HI and SET64LO macro calls.
2845         * support.h (SET64LO, SET64HI): Macros added.
2846
2847 Wed Feb 21 12:16:21 1996  Ian Lance Taylor  <ian@cygnus.com>
2848
2849         * configure: Regenerate with autoconf 2.7.
2850
2851 Tue Jan 30 08:48:18 1996  Fred Fish  <fnf@cygnus.com>
2852
2853         * interp.c (LoadMemory): Enclose text following #endif in /* */.
2854         * support.h: Remove superfluous "1" from #if.
2855         * support.h (CHECKSIM): Remove stray 'a' at end of line.
2856
2857 Mon Dec  4 11:44:40 1995  Jamie Smith  <jsmith@cygnus.com>
2858
2859         * interp.c (StoreFPR): Control UndefinedResult() call on
2860         WARN_RESULT manifest.
2861
2862 Fri Dec  1 16:37:19 1995  James G. Smith  <jsmith@cygnus.co.uk>
2863
2864         * gencode.c: Tidied instruction decoding, and added FP instruction
2865         support.
2866
2867         * interp.c: Added dineroIII, and BSD profiling support. Also
2868         run-time FP handling.
2869
2870 Sun Oct 22 00:57:18 1995  James G. Smith  <jsmith@pasanda.cygnus.co.uk>
2871
2872         * Changelog, Makefile.in, README.Cygnus, configure, configure.in,
2873         gencode.c, interp.c, support.h: created.