sim/mips/ChangeLog

   1 2003-01-04  Richard Sandiford  <rsandifo@redhat.com>
   2             Andrew Cagney  <ac131313@redhat.com>
   3             Gavin Romig-Koch  <gavin@redhat.com>
   4             Graydon Hoare  <graydon@redhat.com>
   5             Aldy Hernandez  <aldyh@redhat.com>
   6             Dave Brolley  <brolley@redhat.com>
   7             Chris Demetriou  <cgd@broadcom.com>
   8
   9         * configure.in (mips64vr*): Define TARGET_ENABLE_FR to 1.
  10         (sim_mach_default): New variable.
  11         (mips64vr-*-*, mips64vrel-*-*): New configurations.
  12         Add a new simulator generator, MULTI.
  13         * configure: Regenerate.
  14         * Makefile.in (SIM_MULTI_OBJ, SIM_EXTRA_DISTCLEAN): New variables.
  15         (multi-run.o): New dependency.
  16         (SIM_MULTI_ALL, SIM_MULTI_IGEN_CONFIGS): New variables.
  17         (tmp-mach-multi, tmp-itable-multi, tmp-run-multi): New rules.
  18         (tmp-multi): Combine them.
  19         (BUILT_SRC_FROM_MULTI): New variable.  Depend on tmp-multi.
  20         (clean-extra): Remove sources in BUILT_SRC_FROM_MULTI.
  21         (distclean-extra): New rule.
  22         * sim-main.h: Include bfd.h.
  23         (MIPS_MACH): New macro.
  24         * mips.igen (vr4120, vr5400, vr5500): New models.
  25         (clo, clz, dclo, dclz, madd, maddu, msub, msub, mul): Add *vr5500.
  26         * vr.igen: Replace with new version.
  27
  28 2003-01-04  Chris Demetriou  <cgd@broadcom.com>
  29
  30         * configure.in: Use SIM_AC_OPTION_RESERVED_BITS(1).
  31         * configure: Regenerate.
  32
  33 2002-12-31  Chris Demetriou  <cgd@broadcom.com>
  34
  35         * sim-main.h (check_branch_bug, mark_branch_bug): Remove.
  36         * mips.igen: Remove all invocations of check_branch_bug and
  37         mark_branch_bug.
  38
  39 2002-12-16  Chris Demetriou  <cgd@broadcom.com>
  40
  41         * tconfig.in: Include "gdb/callback.h" and "gdb/remote-sim.h".
  42
  43 2002-07-30  Chris Demetriou  <cgd@broadcom.com>
  44
  45         * mips.igen (do_load_double, do_store_double): New functions.
  46         (LDC1, SDC1): Rename to...
  47         (LDC1b, SDC1b): respectively.
  48         (LDC1a, SDC1a): New instructions for MIPS II and MIPS32 support.
  49
  50 2002-07-29  Michael Snyder  <msnyder@redhat.com>
  51
  52         * cp1.c (fp_recip2): Modify initialization expression so that
  53         GCC will recognize it as constant.
  54
  55 2002-06-18  Chris Demetriou  <cgd@broadcom.com>
  56
  57         * mdmx.c (SD_): Delete.
  58         (Unpredictable): Re-define, for now, to directly invoke
  59         unpredictable_action().
  60         (mdmx_acc_op): Fix error in .ob immediate handling.
  61
  62 2002-06-18  Andrew Cagney  <cagney@redhat.com>
  63
  64         * interp.c (sim_firmware_command): Initialize `address'.
  65
  66 2002-06-16  Andrew Cagney  <ac131313@redhat.com>
  67
  68         * configure: Regenerated to track ../common/aclocal.m4 changes.
  69
  70 2002-06-14  Chris Demetriou  <cgd@broadcom.com>
  71             Ed Satterthwaite  <ehs@broadcom.com>
  72
  73         * mips3d.igen: New file which contains MIPS-3D ASE instructions.
  74         * Makefile.in (IGEN_INCLUDE): Add mips3d.igen.
  75         * mips.igen: Include mips3d.igen.
  76         (mips3d): New model name for MIPS-3D ASE instructions.
  77         (CVT.W.fmt): Don't use this instruction for word (source) format
  78         instructions.
  79         * cp1.c (fp_binary_r, fp_add_r, fp_mul_r, fpu_inv1, fpu_inv1_32)
  80         (fpu_inv1_64, fp_recip1, fp_recip2, fpu_inv_sqrt1, fpu_inv_sqrt1_32)
  81         (fpu_inv_sqrt1_64, fp_rsqrt1, fp_rsqrt2): New functions.
  82         (NR_FRAC_GUARD, IMPLICIT_1): New macros.
  83         * sim-main.h (fmt_pw, CompareAbs, AddR, MultiplyR, Recip1, Recip2)
  84         (RSquareRoot1, RSquareRoot2): New macros.
  85         (fp_add_r, fp_mul_r, fp_recip1, fp_recip2, fp_rsqrt1)
  86         (fp_rsqrt2): New functions.
  87         * configure.in: Add MIPS-3D support to mipsisa64 simulator.
  88         * configure: Regenerate.
  89
  90 2002-06-13  Chris Demetriou  <cgd@broadcom.com>
  91             Ed Satterthwaite  <ehs@broadcom.com>
  92
  93         * cp1.c (FP_PS_upper, FP_PS_lower, FP_PS_cat, FPQNaN_PS): New macros.
  94         (value_fpr, store_fpr, fp_cmp, fp_unary, fp_binary, fp_mac)
  95         (fp_inv_sqrt, fpu_format_name): Add paired-single support.
  96         (convert): Note that this function is not used for paired-single
  97         format conversions.
  98         (ps_lower, ps_upper, pack_ps, convert_ps): New functions.
  99         * mips.igen (FMT, MOVtf.fmt): Add paired-single support.
 100         (check_fmt_p): Enable paired-single support.
 101         (ALNV.PS, CVT.PS.S, CVT.S.PL, CVT.S.PU, PLL.PS, PLU.PS, PUL.PS)
 102         (PUU.PS): New instructions.
 103         (CVT.S.fmt): Don't use this instruction for paired-single format
 104         destinations.
 105         * sim-main.h (FP_formats): New value 'fmt_ps.'
 106         (ps_lower, ps_upper, pack_ps, convert_ps): New prototypes.
 107         (PSLower, PSUpper, PackPS, ConvertPS): New macros.
 108
 109 2002-06-12  Chris Demetriou  <cgd@broadcom.com>
 110
 111         * mips.igen: Fix formatting of function calls in
 112         many FP operations.
 113
 114 2002-06-12  Chris Demetriou  <cgd@broadcom.com>
 115
 116         * mips.igen (MOVN, MOVZ): Trace result.
 117         (TNEI): Print "tnei" as the opcode name in traces.
 118         (CEIL.W): Add disassembly string for traces.
 119         (RSQRT.fmt): Make location of disassembly string consistent
 120         with other instructions.
 121
 122 2002-06-12  Chris Demetriou  <cgd@broadcom.com>
 123
 124         * mips.igen (X): Delete unused function.
 125
 126 2002-06-08  Andrew Cagney  <cagney@redhat.com>
 127
 128         * interp.c: Include "gdb/callback.h" and "gdb/remote-sim.h".
 129
 130 2002-06-07  Chris Demetriou  <cgd@broadcom.com>
 131             Ed Satterthwaite  <ehs@broadcom.com>
 132
 133         * cp1.c (inner_mac, fp_mac, inner_rsqrt, fp_inv_sqrt)
 134         (fp_rsqrt, fp_madd, fp_msub, fp_nmadd, fp_nmsub): New functions.
 135         * sim-main.h (fp_rsqrt, fp_madd, fp_msub, fp_nmadd)
 136         (fp_nmsub): New prototypes.
 137         (RSquareRoot, MultiplyAdd, MultiplySub, NegMultiplyAdd)
 138         (NegMultiplySub): New defines.
 139         * mips.igen (RSQRT.fmt): Use RSquareRoot().
 140         (MADD.D, MADD.S): Replace with...
 141         (MADD.fmt): New instruction.
 142         (MSUB.D, MSUB.S): Replace with...
 143         (MSUB.fmt): New instruction.
 144         (NMADD.D, NMADD.S): Replace with...
 145         (NMADD.fmt): New instruction.
 146         (NMSUB.D, MSUB.S): Replace with...
 147         (NMSUB.fmt): New instruction.
 148
 149 2002-06-07  Chris Demetriou  <cgd@broadcom.com>
 150             Ed Satterthwaite  <ehs@broadcom.com>
 151
 152         * cp1.c: Fix more comment spelling and formatting.
 153         (value_fcr, store_fcr): Use fenr_FS rather than hard-coding value.
 154         (denorm_mode): New function.
 155         (fpu_unary, fpu_binary): Round results after operation, collect
 156         status from rounding operations, and update the FCSR.
 157         (convert): Collect status from integer conversions and rounding
 158         operations, and update the FCSR.  Adjust NaN values that result
 159         from conversions.  Convert to use sim_io_eprintf rather than
 160         fprintf, and remove some debugging code.
 161         * cp1.h (fenr_FS): New define.
 162
 163 2002-06-07  Chris Demetriou  <cgd@broadcom.com>
 164
 165         * cp1.c (convert): Remove unusable debugging code, and move MIPS
 166         rounding mode to sim FP rounding mode flag conversion code into...
 167         (rounding_mode): New function.
 168
 169 2002-06-07  Chris Demetriou  <cgd@broadcom.com>
 170
 171         * cp1.c: Clean up formatting of a few comments.
 172         (value_fpr): Reformat switch statement.
 173
 174 2002-06-06  Chris Demetriou  <cgd@broadcom.com>
 175             Ed Satterthwaite  <ehs@broadcom.com>
 176
 177         * cp1.h: New file.
 178         * sim-main.h: Include cp1.h.
 179         (SETFCC, GETFCC, IR, UF, OF, DX, IO, UO, FP_FLAGS, FP_ENABLE)
 180         (FP_CAUSE, GETFS, FP_RM_NEAREST, FP_RM_TOZERO, FP_RM_TOPINF)
 181         (FP_RM_TOMINF, GETRM): Remove.  Moved to cp1.h.
 182         (FP_FS, FP_MASK_RM, FP_SH_RM, Nan, Less, Equal): Remove.
 183         (value_fcr, store_fcr, test_fcsr, fp_cmp): New prototypes.
 184         (ValueFCR, StoreFCR, TestFCSR, Compare): New macros.
 185         * cp1.c: Don't include sim-fpu.h; already included by
 186         sim-main.h.  Clean up formatting of some comments.
 187         (NaN, Equal, Less): Remove.
 188         (test_fcsr, value_fcr, store_fcr, update_fcsr, fp_test)
 189         (fp_cmp): New functions.
 190         * mips.igen (do_c_cond_fmt): Remove.
 191         (C.cond.fmta, C.cond.fmtb): Replace uses of do_c_cond_fmt_a with
 192         Compare.  Add result tracing.
 193         (CxC1): Remove, replace with...
 194         (CFC1a, CFC1b, CFC1c, CTC1a, CTC1b, CTC1c): New instructions.
 195         (DMxC1): Remove, replace with...
 196         (DMFC1a, DMFC1b, DMTC1a, DMTC1b): New instructions.
 197         (MxC1): Remove, replace with...
 198         (MFC1a, MFC1b, MTC1a, MTC1b): New instructions.
 199
 200 2002-06-04  Chris Demetriou  <cgd@broadcom.com>
 201
 202         * sim-main.h (FGRIDX): Remove, replace all uses with...
 203         (FGR_BASE): New macro.
 204         (FP0_REGNUM, FCRCS_REGNUM, FCRIR_REGNUM): New macros.
 205         (_sim_cpu): Move 'fgr' member to be right before 'fpr_state' member.
 206         (NR_FGR, FGR): Likewise.
 207         * interp.c: Replace all uses of FGRIDX with FGR_BASE.
 208         * mips.igen: Likewise.
 209
 210 2002-06-04  Chris Demetriou  <cgd@broadcom.com>
 211
 212         * cp1.c: Add an FSF Copyright notice to this file.
 213
 214 2002-06-04  Chris Demetriou  <cgd@broadcom.com>
 215             Ed Satterthwaite  <ehs@broadcom.com>
 216
 217         * cp1.c (Infinity): Remove.
 218         * sim-main.h (Infinity): Likewise.
 219
 220         * cp1.c (fp_unary, fp_binary): New functions.
 221         (fp_abs, fp_neg, fp_add, fp_sub, fp_mul, fp_div, fp_recip)
 222         (fp_sqrt): New functions, implemented in terms of the above.
 223         (AbsoluteValue, Negate, Add, Sub, Multiply, Divide)
 224         (Recip, SquareRoot): Remove (replaced by functions above).
 225         * sim-main.h (fp_abs, fp_neg, fp_add, fp_sub, fp_mul, fp_div)
 226         (fp_recip, fp_sqrt): New prototypes.
 227         (AbsoluteValue, Negate, Add, Sub, Multiply, Divide)
 228         (Recip, SquareRoot): Replace prototypes with #defines which
 229         invoke the functions above.
 230
 231 2002-06-03  Chris Demetriou  <cgd@broadcom.com>
 232
 233         * sim-main.h (Nan, Infinity, Less, Equal, AbsoluteValue, Negate)
 234         (Add, Sub, Multiply, Divide, Recip, SquareRoot): Move lower in
 235         file, remove PARAMS from prototypes.
 236         (value_fpr, store_fpr, convert): Likewise.  Use SIM_STATE to provide
 237         simulator state arguments.
 238         (ValueFPR, StoreFPR, Convert): Move lower in file.  Use SIM_ARGS to
 239         pass simulator state arguments.
 240         * cp1.c (SD): Redefine as CPU_STATE(cpu).
 241         (store_fpr, convert): Remove 'sd' argument.
 242         (value_fpr): Likewise.  Convert to use 'SD' instead.
 243
 244 2002-06-03  Chris Demetriou  <cgd@broadcom.com>
 245
 246         * cp1.c (Min, Max): Remove #if 0'd functions.
 247         * sim-main.h (Min, Max): Remove.
 248
 249 2002-06-03  Chris Demetriou  <cgd@broadcom.com>
 250
 251         * cp1.c: fix formatting of switch case and default labels.
 252         * interp.c: Likewise.
 253         * sim-main.c: Likewise.
 254
 255 2002-06-03  Chris Demetriou  <cgd@broadcom.com>
 256
 257         * cp1.c: Clean up comments which describe FP formats.
 258          (FPQNaN_DOUBLE, FPQNaN_LONG): Generate using UNSIGNED64.
 259
 260 2002-06-03  Chris Demetriou  <cgd@broadcom.com>
 261             Ed Satterthwaite  <ehs@broadcom.com>
 262
 263         * configure.in (mipsisa64sb1*-*-*): New target for supporting
 264         Broadcom SiByte SB-1 processor configurations.
 265         * configure: Regenerate.
 266         * sb1.igen: New file.
 267         * mips.igen: Include sb1.igen.
 268         (sb1): New model.
 269         * Makefile.in (IGEN_INCLUDE): Add sb1.igen.
 270         * mdmx.igen: Add "sb1" model to all appropriate functions and
 271         instructions.
 272         * mdmx.c (AbsDiffOB, AvgOB, AccAbsDiffOB): New functions.
 273         (ob_func, ob_acc): Reference the above.
 274         (qh_acc): Adjust to keep the same size as ob_acc.
 275         * sim-main.h (status_SBX, MX_VECT_ABSD, MX_VECT_AVG, MX_AbsDiff)
 276         (MX_Avg, MX_VECT_ABSDA, MX_AbsDiffC): New macros.
 277
 278 2002-06-03  Chris Demetriou  <cgd@broadcom.com>
 279
 280         * Makefile.in (IGEN_INCLUDE): Add mdmx.igen.
 281
 282 2002-06-02  Chris Demetriou  <cgd@broadcom.com>
 283             Ed Satterthwaite  <ehs@broadcom.com>
 284
 285         * mips.igen (mdmx): New (pseudo-)model.
 286         * mdmx.c, mdmx.igen: New files.
 287         * Makefile.in (SIM_OBJS): Add mdmx.o.
 288         * sim-main.h (MDMX_accumulator, MX_fmtsel, signed24, signed48):
 289         New typedefs.
 290         (ACC, MX_Add, MX_AddA, MX_AddL, MX_And, MX_C_EQ, MX_C_LT, MX_Comp)
 291         (MX_FMT_OB, MX_FMT_QH, MX_Max, MX_Min, MX_Msgn, MX_Mul, MX_MulA)
 292         (MX_MulL, MX_MulS, MX_MulSL, MX_Nor, MX_Or, MX_Pick, MX_RAC)
 293         (MX_RAC_H, MX_RAC_L, MX_RAC_M, MX_RNAS, MX_RNAU, MX_RND_AS)
 294         (MX_RND_AU, MX_RND_ES, MX_RND_EU, MX_RND_ZS, MX_RND_ZU, MX_RNES)
 295         (MX_RNEU, MX_RZS, MX_RZU, MX_SHFL, MX_ShiftLeftLogical)
 296         (MX_ShiftRightArith, MX_ShiftRightLogical, MX_Sub, MX_SubA, MX_SubL)
 297         (MX_VECT_ADD, MX_VECT_ADDA, MX_VECT_ADDL, MX_VECT_AND)
 298         (MX_VECT_MAX, MX_VECT_MIN, MX_VECT_MSGN, MX_VECT_MUL, MX_VECT_MULA)
 299         (MX_VECT_MULL, MX_VECT_MULS, MX_VECT_MULSL, MX_VECT_NOR)
 300         (MX_VECT_OR, MX_VECT_SLL, MX_VECT_SRA, MX_VECT_SRL, MX_VECT_SUB)
 301         (MX_VECT_SUBA, MX_VECT_SUBL, MX_VECT_XOR, MX_WACH, MX_WACL, MX_Xor)
 302         (SIM_ARGS, SIM_STATE, UnpredictableResult, fmt_mdmx, ob_fmtsel)
 303         (qh_fmtsel): New macros.
 304         (_sim_cpu): New member "acc".
 305         (mdmx_acc_op, mdmx_cc_op, mdmx_cpr_op, mdmx_pick_op, mdmx_rac_op)
 306         (mdmx_round_op, mdmx_shuffle, mdmx_wach, mdmx_wacl): New functions.
 307
 308 2002-05-01  Chris Demetriou  <cgd@broadcom.com>
 309
 310         * interp.c: Use 'deprecated' rather than 'depreciated.'
 311         * sim-main.h: Likewise.
 312
 313 2002-05-01  Chris Demetriou  <cgd@broadcom.com>
 314
 315         * cp1.c (store_fpr): Remove #ifdef'd out call to UndefinedResult
 316         which wouldn't compile anyway.
 317         * sim-main.h (unpredictable_action): New function prototype.
 318         (Unpredictable): Define to call igen function unpredictable().
 319         (NotWordValue): New macro to call igen function not_word_value().
 320         (UndefinedResult): Remove.
 321         * interp.c (undefined_result): Remove.
 322         (unpredictable_action): New function.
 323         * mips.igen (not_word_value, unpredictable): New functions.
 324         (ADD, ADDI, do_addiu, do_addu, BGEZAL, BGEZALL, BLTZAL, BLTZALL)
 325         (CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, do_mult, do_multu)
 326         (do_sra, do_srav, do_srl, do_srlv, SUB, do_subu): Invoke
 327         NotWordValue() to check for unpredictable inputs, then
 328         Unpredictable() to handle them.
 329
 330 2002-02-24  Chris Demetriou  <cgd@broadcom.com>
 331
 332         * mips.igen: Fix formatting of calls to Unpredictable().
 333
 334 2002-04-20  Andrew Cagney  <ac131313@redhat.com>
 335
 336         * interp.c (sim_open): Revert previous change.
 337
 338 2002-04-18  Alexandre Oliva  <aoliva@redhat.com>
 339
 340         * interp.c (sim_open): Disable chunk of code that wrote code in
 341         vector table entries.
 342
 343 2002-03-19  Chris Demetriou  <cgd@broadcom.com>
 344
 345         * cp1.c (FP_S_s, FP_D_s, FP_S_be, FP_D_be, FP_S_e, FP_D_e, FP_S_f)
 346         (FP_D_f, FP_S_fb, FP_D_fb, FPINF_SINGLE, FPINF_DOUBLE): Remove
 347         unused definitions.
 348
 349 2002-03-19  Chris Demetriou  <cgd@broadcom.com>
 350
 351         * cp1.c: Fix many formatting issues.
 352
 353 2002-03-19  Chris G. Demetriou  <cgd@broadcom.com>
 354
 355         * cp1.c (fpu_format_name): New function to replace...
 356         (DOFMT): This.  Delete, and update all callers.
 357         (fpu_rounding_mode_name): New function to replace...
 358         (RMMODE): This.  Delete, and update all callers.
 359
 360 2002-03-19  Chris G. Demetriou  <cgd@broadcom.com>
 361
 362         * interp.c: Move FPU support routines from here to...
 363         * cp1.c: Here.  New file.
 364         * Makefile.in (SIM_OBJS): Add cp1.o to object list.
 365         (cp1.o): New target.
 366
 367 2002-03-12  Chris Demetriou  <cgd@broadcom.com>
 368
 369         * configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
 370         * mips.igen (mips32, mips64): New models, add to all instructions
 371         and functions as appropriate.
 372         (loadstore_ea, check_u64): New variant for model mips64.
 373         (check_fmt_p): New variant for models mipsV and mips64, remove
 374         mipsV model marking fro other variant.
 375         (SLL) Rename to...
 376         (SLLa) this.
 377         (CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
 378         for mips32 and mips64.
 379         (DCLO, DCLZ): New instructions for mips64.
 380
 381 2002-03-07  Chris Demetriou  <cgd@broadcom.com>
 382
 383         * mips.igen (BREAK, LUI, ORI, SYSCALL, XORI): Print
 384         immediate or code as a hex value with the "%#lx" format.
 385         (ANDI): Likewise, and fix printed instruction name.
 386
 387 2002-03-05  Chris Demetriou  <cgd@broadcom.com>
 388
 389         * sim-main.h (UndefinedResult, Unpredictable): New macros
 390         which currently do nothing.
 391
 392 2002-03-05  Chris Demetriou  <cgd@broadcom.com>
 393
 394         * sim-main.h (status_UX, status_SX, status_KX, status_TS)
 395         (status_PX, status_MX, status_CU0, status_CU1, status_CU2)
 396         (status_CU3): New definitions.
 397
 398         * sim-main.h (ExceptionCause): Add new values for MIPS32
 399         and MIPS64: MDMX, MCheck, CacheErr.  Update comments
 400         for DebugBreakPoint and NMIReset to note their status in
 401         MIPS32 and MIPS64.
 402         (SignalExceptionMDMX, SignalExceptionWatch, SignalExceptionMCheck)
 403         (SignalExceptionCacheErr): New exception macros.
 404
 405 2002-03-05  Chris Demetriou  <cgd@broadcom.com>
 406
 407         * mips.igen (check_fpu): Enable check for coprocessor 1 usability.
 408         * sim-main.h (COP_Usable): Define, but for now coprocessor 1
 409         is always enabled.
 410         (SignalExceptionCoProcessorUnusable): Take as argument the
 411         unusable coprocessor number.
 412
 413 2002-03-05  Chris Demetriou  <cgd@broadcom.com>
 414
 415         * mips.igen: Fix formatting of all SignalException calls.
 416
 417 2002-03-05  Chris Demetriou  <cgd@broadcom.com>
 418
 419         * sim-main.h (SIGNEXTEND): Remove.
 420
 421 2002-03-04  Chris Demetriou  <cgd@broadcom.com>
 422
 423         * mips.igen: Remove gencode comment from top of file, fix
 424         spelling in another comment.
 425
 426 2002-03-04  Chris Demetriou  <cgd@broadcom.com>
 427
 428         * mips.igen (check_fmt, check_fmt_p): New functions to check
 429         whether specific floating point formats are usable.
 430         (ABS.fmt, ADD.fmt, CEIL.L.fmt, CEIL.W, DIV.fmt, FLOOR.L.fmt)
 431         (FLOOR.W.fmt, MOV.fmt, MUL.fmt, NEG.fmt, RECIP.fmt, ROUND.L.fmt)
 432         (ROUND.W.fmt, RSQRT.fmt, SQRT.fmt, SUB.fmt, TRUNC.L.fmt, TRUNC.W):
 433         Use the new functions.
 434         (do_c_cond_fmt): Remove format checks...
 435         (C.cond.fmta, C.cond.fmtb): And move them into all callers.
 436
 437 2002-03-03  Chris Demetriou  <cgd@broadcom.com>
 438
 439         * mips.igen: Fix formatting of check_fpu calls.
 440
 441 2002-03-03  Chris Demetriou  <cgd@broadcom.com>
 442
 443         * mips.igen (FLOOR.L.fmt): Store correct destination register.
 444
 445 2002-03-03  Chris Demetriou  <cgd@broadcom.com>
 446
 447         * mips.igen: Remove whitespace at end of lines.
 448
 449 2002-03-02  Chris Demetriou  <cgd@broadcom.com>
 450
 451         * mips.igen (loadstore_ea): New function to do effective
 452         address calculations.
 453         (do_load, do_load_left, do_load_right, LL, LDD, PREF, do_store,
 454         do_store_left, do_store_right, SC, SCD, PREFX, SWC1, SWXC1,
 455         CACHE): Use loadstore_ea to do effective address computations.
 456
 457 2002-03-02  Chris Demetriou  <cgd@broadcom.com>
 458
 459         * interp.c (load_word): Use EXTEND32 rather than SIGNEXTEND.
 460         * mips.igen (LL, CxC1, MxC1): Likewise.
 461
 462 2002-03-02  Chris Demetriou  <cgd@broadcom.com>
 463
 464         * mips.igen (LL, LLD, PREF, SC, SCD, ABS.fmt, ADD.fmt, CEIL.L.fmt,
 465         CEIL.W, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt, CVT.W.fmt, DIV.fmt,
 466         FLOOR.L.fmt, FLOOR.W.fmt, MADD.D, MADD.S, MOV.fmt, MOVtf.fmt,
 467         MSUB.D, MSUB.S, MUL.fmt, NEG.fmt, NMADD.D, NMADD.S, NMSUB.D,
 468         NMSUB.S, PREFX, RECIP.fmt, ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt,
 469         SQRT.fmt, SUB.fmt, SWC1, SWXC1, TRUNC.L.fmt, TRUNC.W, CACHE):
 470         Don't split opcode fields by hand, use the opcode field values
 471         provided by igen.
 472
 473 2002-03-01  Chris Demetriou  <cgd@broadcom.com>
 474
 475         * mips.igen (do_divu): Fix spacing.
 476
 477         * mips.igen (do_dsllv): Move to be right before DSLLV,
 478         to match the rest of the do_<shift> functions.
 479
 480 2002-03-01  Chris Demetriou  <cgd@broadcom.com>
 481
 482         * mips.igen (do_dsll, do_dsllv, DSLL32, do_dsra, DSRA32, do_dsrl,
 483         DSRL32, do_dsrlv): Trace inputs and results.
 484
 485 2002-03-01  Chris Demetriou  <cgd@broadcom.com>
 486
 487         * mips.igen (CACHE): Provide instruction-printing string.
 488
 489         * interp.c (signal_exception): Comment tokens after #endif.
 490
 491 2002-02-28  Chris Demetriou  <cgd@broadcom.com>
 492
 493         * mips.igen (LWXC1): Mark with filter "64,f", rather than just "32".
 494         (MOVtf, MxC1, MxC1, DMxC1, DMxC1, CxC1, CxC1, SQRT.fmt, MOV.fmt,
 495         NEG.fmt, ROUND.L.fmt, TRUNC.L.fmt, CEIL.L.fmt, FLOOR.L.fmt,
 496         ROUND.W.fmt, TRUNC.W, CEIL.W, FLOOR.W.fmt, RECIP.fmt, RSQRT.fmt,
 497         CVT.S.fmt, CVT.D.fmt, CVT.W.fmt, CVT.L.fmt, MOVtf.fmt, C.cond.fmta,
 498         C.cond.fmtb, SUB.fmt, MUL.fmt, DIV.fmt, MOVZ.fmt, MOVN.fmt, LDXC1,
 499         SWXC1, SDXC1, MSUB.D, MSUB.S, NMADD.S, NMADD.D, NMSUB.S, NMSUB.D,
 500         LWC1, SWC1): Add "f" to filter, since these are FP instructions.
 501
 502 2002-02-28  Chris Demetriou  <cgd@broadcom.com>
 503
 504         * mips.igen (DSRA32, DSRAV): Fix order of arguments in
 505         instruction-printing string.
 506         (LWU): Use '64' as the filter flag.
 507
 508 2002-02-28  Chris Demetriou  <cgd@broadcom.com>
 509
 510         * mips.igen (SDXC1): Fix instruction-printing string.
 511
 512 2002-02-28  Chris Demetriou  <cgd@broadcom.com>
 513
 514         * mips.igen (LDC1, SDC1): Remove mipsI model, and mark with
 515         filter flags "32,f".
 516
 517 2002-02-27  Chris Demetriou  <cgd@broadcom.com>
 518
 519         * mips.igen (PREFX): This is a 64-bit instruction, use '64'
 520         as the filter flag.
 521
 522 2002-02-27  Chris Demetriou  <cgd@broadcom.com>
 523
 524         * mips.igen (PREFX): Tweak instruction opcode fields (i.e.,
 525         add a comma) so that it more closely match the MIPS ISA
 526         documentation opcode partitioning.
 527         (PREF): Put useful names on opcode fields, and include
 528         instruction-printing string.
 529
 530 2002-02-27  Chris Demetriou  <cgd@broadcom.com>
 531
 532         * mips.igen (check_u64): New function which in the future will
 533         check whether 64-bit instructions are usable and signal an
 534         exception if not.  Currently a no-op.
 535         (DADD, DADDI, DADDIU, DADDU, DDIV, DDIVU, DMULT, DMULTU, DSLL,
 536         DSLL32, DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB,
 537         DSUBU, LD, LDL, LDR, LLD, LWU, SCD, SD, SDL, SDR, DMxC1, LDXC1,
 538         LWXC1, SDXC1, SWXC1, DMFC0, DMTC0): Use check_u64.
 539
 540         * mips.igen (check_fpu): New function which in the future will
 541         check whether FPU instructions are usable and signal an exception
 542         if not.  Currently a no-op.
 543         (ABS.fmt, ADD.fmt, BC1a, BC1b, C.cond.fmta, C.cond.fmtb,
 544         CEIL.L.fmt, CEIL.W, CxC1, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt,
 545         CVT.W.fmt, DIV.fmt, DMxC1, DMxC1, FLOOR.L.fmt, FLOOR.W.fmt, LDC1,
 546         LDXC1, LWC1, LWXC1, MADD.D, MADD.S, MxC1, MOV.fmt, MOVtf,
 547         MOVtf.fmt, MOVN.fmt, MOVZ.fmt, MSUB.D, MSUB.S, MUL.fmt, NEG.fmt,
 548         NMADD.D, NMADD.S, NMSUB.D, NMSUB.S, RECIP.fmt, ROUND.L.fmt,
 549         ROUND.W.fmt, RSQRT.fmt, SDC1, SDXC1, SQRT.fmt, SUB.fmt, SWC1,
 550         SWXC1, TRUNC.L.fmt, TRUNC.W): Use check_fpu.
 551
 552 2002-02-27  Chris Demetriou  <cgd@broadcom.com>
 553
 554         * mips.igen (do_load_left, do_load_right): Move to be immediately
 555         following do_load.
 556         (do_store_left, do_store_right): Move to be immediately following
 557         do_store.
 558
 559 2002-02-27  Chris Demetriou  <cgd@broadcom.com>
 560
 561         * mips.igen (mipsV): New model name.  Also, add it to
 562         all instructions and functions where it is appropriate.
 563
 564 2002-02-18  Chris Demetriou  <cgd@broadcom.com>
 565
 566         * mips.igen: For all functions and instructions, list model
 567         names that support that instruction one per line.
 568
 569 2002-02-11  Chris Demetriou  <cgd@broadcom.com>
 570
 571         * mips.igen: Add some additional comments about supported
 572         models, and about which instructions go where.
 573         (BC1b, MFC0, MTC0, RFE): Sort supported models in the same
 574         order as is used in the rest of the file.
 575
 576 2002-02-11  Chris Demetriou  <cgd@broadcom.com>
 577
 578         * mips.igen (ADD, ADDI, DADDI, DSUB, SUB): Add comment
 579         indicating that ALU32_END or ALU64_END are there to check
 580         for overflow.
 581         (DADD): Likewise, but also remove previous comment about
 582         overflow checking.
 583
 584 2002-02-10  Chris Demetriou  <cgd@broadcom.com>
 585
 586         * mips.igen (DDIV, DIV, DIVU, DMULT, DMULTU, DSLL, DSLL32,
 587         DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB, DSUBU,
 588         JALR, JR, MOVN, MOVZ, MTLO, MULT, MULTU, SLL, SLLV, SLT, SLTU,
 589         SRAV, SRLV, SUB, SUBU, SYNC, XOR, MOVtf, DI, DMFC0, DMTC0, EI,
 590         ERET, RFE, TLBP, TLBR, TLBWI, TLBWR): Tweak instruction opcode
 591         fields (i.e., add and move commas) so that they more closely
 592         match the MIPS ISA documentation opcode partitioning.
 593
 594 2002-02-10  Chris Demetriou  <cgd@broadcom.com>
 595
 596         * mips.igen (ADDI): Print immediate value.
 597         (BREAK): Print code.
 598         (DADDIU, DSRAV, DSRLV): Print correct instruction name.
 599         (SLL): Print "nop" specially, and don't run the code
 600         that does the shift for the "nop" case.
 601
 602 2001-11-17  Fred Fish  <fnf@redhat.com>
 603
 604         * sim-main.h (float_operation): Move enum declaration outside
 605         of _sim_cpu struct declaration.
 606
 607 2001-04-12  Jim Blandy  <jimb@redhat.com>
 608
 609         * mips.igen (CFC1, CTC1): Pass the correct register numbers to
 610         PENDING_FILL.  Use PENDING_SCHED directly to handle the pending
 611         set of the FCSR.
 612         * sim-main.h (COCIDX): Remove definition; this isn't supported by
 613         PENDING_FILL, and you can get the intended effect gracefully by
 614         calling PENDING_SCHED directly.
 615
 616 2001-02-23  Ben Elliston  <bje@redhat.com>
 617
 618         * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Only define if not
 619         already defined elsewhere.
 620
 621 2001-02-19  Ben Elliston  <bje@redhat.com>
 622
 623         * sim-main.h (sim_monitor): Return an int.
 624         * interp.c (sim_monitor): Add return values.
 625         (signal_exception): Handle error conditions from sim_monitor.
 626
 627 2001-02-08  Ben Elliston  <bje@redhat.com>
 628
 629         * sim-main.c (load_memory): Pass cia to sim_core_read* functions.
 630         (store_memory): Likewise, pass cia to sim_core_write*.
 631
 632 2000-10-19  Frank Ch. Eigler  <fche@redhat.com>
 633
 634         On advice from Chris G. Demetriou <cgd@sibyte.com>:
 635         * sim-main.h (GPR_CLEAR): Remove unused alternative macro.
 636
 637 Thu Jul 27 22:02:05 2000  Andrew Cagney  <cagney@b1.cygnus.com>
 638
 639         From Maciej W. Rozycki <macro@ds2.pg.gda.pl>:
 640         * Makefile.in: Don't delete *.igen when cleaning directory.
 641
 642 Wed Jul 19 18:50:51 2000  Andrew Cagney  <cagney@b1.cygnus.com>
 643
 644         * m16.igen (break): Call SignalException not sim_engine_halt.
 645
 646 Mon Jul  3 11:13:20 2000  Andrew Cagney  <cagney@b1.cygnus.com>
 647
 648         From Jason Eckhardt:
 649         * mips.igen (MOVZ.fmt, MOVN.fmt): Move conditional on GPR[RT].
 650
 651 Tue Jun 13 20:52:07 2000  Andrew Cagney  <cagney@b1.cygnus.com>
 652
 653         * mips.igen (MxC1, DMxC1): Fix printf formatting.
 654
 655 2000-05-24  Michael Hayes  <mhayes@cygnus.com>
 656
 657         * mips.igen (do_dmultx): Fix typo.
 658
 659 Tue May 23 21:39:23 2000  Andrew Cagney  <cagney@b1.cygnus.com>
 660
 661         * configure: Regenerated to track ../common/aclocal.m4 changes.
 662
 663 Fri Apr 28 20:48:36 2000  Andrew Cagney  <cagney@b1.cygnus.com>
 664
 665         * mips.igen (DMxC1): Fix format arguments for sim_io_eprintf call.
 666
 667 2000-04-12  Frank Ch. Eigler  <fche@redhat.com>
 668
 669         * sim-main.h (GPR_CLEAR): Define macro.
 670
 671 Mon Apr 10 00:07:09 2000  Andrew Cagney  <cagney@b1.cygnus.com>
 672
 673         * interp.c (decode_coproc): Output long using %lx and not %s.
 674
 675 2000-03-21  Frank Ch. Eigler  <fche@redhat.com>
 676
 677         * interp.c (sim_open): Sort & extend dummy memory regions for
 678         --board=jmr3904 for eCos.
 679
 680 2000-03-02  Frank Ch. Eigler  <fche@redhat.com>
 681
 682         * configure: Regenerated.
 683
 684 Tue Feb  8 18:35:01 2000  Donald Lindsay  <dlindsay@hound.cygnus.com>
 685
 686         * interp.c, mips.igen: all 5 DEADC0DE situations now have sim_io_eprintf
 687         calls, conditional on the simulator being in verbose mode.
 688
 689 Fri Feb  4 09:45:15 2000  Donald Lindsay  <dlindsay@cygnus.com>
 690
 691         * sim-main.c (cache_op): Added case arm so that CACHE ops to a secondary
 692         cache don't get ReservedInstruction traps.
 693
 694 1999-11-29  Mark Salter  <msalter@cygnus.com>
 695
 696         * dv-tx3904sio.c (tx3904sio_io_write_buffer): Use write value as a mask
 697         to clear status bits in sdisr register. This is how the hardware works.
 698
 699         * interp.c (sim_open): Added more memory aliases for jmr3904 hardware
 700         being used by cygmon.
 701
 702 1999-11-11  Andrew Haley  <aph@cygnus.com>
 703
 704         * interp.c (decode_coproc): Correctly handle DMFC0 and DMTC0
 705         instructions.
 706
 707 Thu Sep  9 15:12:08 1999  Geoffrey Keating  <geoffk@cygnus.com>
 708
 709         * mips.igen (MULT): Correct previous mis-applied patch.
 710
 711 Tue Sep  7 13:34:54 1999  Geoffrey Keating  <geoffk@cygnus.com>
 712
 713         * mips.igen (delayslot32): Handle sequence like
 714         mtc1 $at,$f12 ; jal fp_add ; mov.s $f13,$f12
 715         correctly by calling ENGINE_ISSUE_PREFIX_HOOK() before issue.
 716         (MULT): Actually pass the third register...
 717
 718 1999-09-03  Mark Salter  <msalter@cygnus.com>
 719
 720         * interp.c (sim_open): Added more memory aliases for additional
 721         hardware being touched by cygmon on jmr3904 board.
 722
 723 Thu Sep  2 18:15:53 1999  Andrew Cagney  <cagney@b1.cygnus.com>
 724
 725         * configure: Regenerated to track ../common/aclocal.m4 changes.
 726
 727 Tue Jul 27 16:36:51 1999  Andrew Cagney  <cagney@amy.cygnus.com>
 728
 729         * interp.c (sim_store_register): Handle case where client - GDB -
 730         specifies that a 4 byte register is 8 bytes in size.
 731         (sim_fetch_register): Ditto.
 732
 733 1999-07-14  Frank Ch. Eigler  <fche@cygnus.com>
 734
 735         Implement "sim firmware" option, inspired by jimb's version of 1998-01.
 736         * interp.c (firmware_option_p): New global flag: "sim firmware" given.
 737         (idt_monitor_base): Base address for IDT monitor traps.
 738         (pmon_monitor_base): Ditto for PMON.
 739         (lsipmon_monitor_base): Ditto for LSI PMON.
 740         (MONITOR_BASE, MONITOR_SIZE): Removed macros.
 741         (mips_option): Add "firmware" option with new OPTION_FIRMWARE key.
 742         (sim_firmware_command): New function.
 743         (mips_option_handler): Call it for OPTION_FIRMWARE.
 744         (sim_open): Allocate memory for idt_monitor region.  If "--board"
 745         option was given, add no monitor by default.  Add BREAK hooks only if
 746         monitors are also there.
 747
 748 Mon Jul 12 00:02:27 1999  Andrew Cagney  <cagney@amy.cygnus.com>
 749
 750         * interp.c (sim_monitor): Flush output before reading input.
 751
 752 Sun Jul 11 19:28:11 1999  Andrew Cagney  <cagney@b1.cygnus.com>
 753
 754         * tconfig.in (SIM_HANDLES_LMA): Always define.
 755
 756 Thu Jul  8 16:06:59 1999  Andrew Cagney  <cagney@b1.cygnus.com>
 757
 758         From Mark Salter <msalter@cygnus.com>:
 759         * interp.c (BOARD_BSP): Define.  Add to list of possible boards.
 760         (sim_open): Add setup for BSP board.
 761
 762 Wed Jul  7 12:45:58 1999  Andrew Cagney  <cagney@b1.cygnus.com>
 763
 764         * mips.igen (MULT, MULTU): Add syntax for two operand version.
 765         (DMFC0, DMTC0): Recognize.  Call DecodeCoproc which will report
 766         them as unimplemented.
 767
 768 1999-05-08  Felix Lee  <flee@cygnus.com>
 769
 770         * configure: Regenerated to track ../common/aclocal.m4 changes.
 771
 772 1999-04-21  Frank Ch. Eigler  <fche@cygnus.com>
 773
 774         * mips.igen (bc0f): For the TX39 only, decode this as a no-op stub.
 775
 776 Thu Apr 15 14:15:17 1999  Andrew Cagney  <cagney@amy.cygnus.com>
 777
 778         * configure.in: Any mips64vr5*-*-* target should have
 779         -DTARGET_ENABLE_FR=1.
 780         (default_endian): Any mips64vr*el-*-* target should default to
 781         LITTLE_ENDIAN.
 782         * configure: Re-generate.
 783
 784 1999-02-19  Gavin Romig-Koch  <gavin@cygnus.com>
 785
 786         * mips.igen (ldl): Extend from _16_, not 32.
 787
 788 Wed Jan 27 18:51:38 1999  Andrew Cagney  <cagney@chook.cygnus.com>
 789
 790         * interp.c (sim_store_register): Force registers written to by GDB
 791         into an un-interpreted state.
 792
 793 1999-02-05  Frank Ch. Eigler  <fche@cygnus.com>
 794
 795         * dv-tx3904sio.c (tx3904sio_tickle): After a polled I/O from the
 796         CPU, start periodic background I/O polls.
 797         (tx3904sio_poll): New function: periodic I/O poller.
 798
 799 1998-12-30  Frank Ch. Eigler  <fche@cygnus.com>
 800
 801         * mips.igen (BREAK): Call signal_exception instead of sim_engine_halt.
 802
 803 Tue Dec 29 16:03:53 1998  Rainer Orth  <ro@TechFak.Uni-Bielefeld.DE>
 804
 805         * configure.in, configure (mips64vr5*-*-*): Added missing ;; in
 806         case statement.
 807
 808 1998-12-29  Frank Ch. Eigler  <fche@cygnus.com>
 809
 810         * interp.c (sim_open): Allocate jm3904 memory in smaller chunks.
 811         (load_word): Call SIM_CORE_SIGNAL hook on error.
 812         (signal_exception): Call SIM_CPU_EXCEPTION_TRIGGER hook before
 813         starting.  For exception dispatching, pass PC instead of NULL_CIA.
 814         (decode_coproc): Use COP0_BADVADDR to store faulting address.
 815         * sim-main.h (COP0_BADVADDR): Define.
 816         (SIM_CORE_SIGNAL): Define hook to call mips_core_signal.
 817         (SIM_CPU_EXCEPTION*): Define hooks to call mips_cpu_exception*().
 818         (_sim_cpu): Add exc_* fields to store register value snapshots.
 819         * mips.igen (*): Replace memory-related SignalException* calls
 820         with references to SIM_CORE_SIGNAL hook.
 821
 822         * dv-tx3904irc.c (tx3904irc_port_event): printf format warning
 823         fix.
 824         * sim-main.c (*): Minor warning cleanups.
 825
 826 1998-12-24  Gavin Romig-Koch  <gavin@cygnus.com>
 827
 828         * m16.igen (DADDIU5): Correct type-o.
 829
 830 Mon Dec 21 10:34:48 1998  Andrew Cagney  <cagney@chook>
 831
 832         * mips.igen (do_ddiv, do_ddivu): Pacify GCC. Update hi/lo via tmp
 833         variables.
 834
 835 Wed Dec 16 18:20:28 1998  Andrew Cagney  <cagney@chook>
 836
 837         * Makefile.in (SIM_EXTRA_CFLAGS): No longer need to add .../newlib
 838         to include path.
 839         (interp.o): Add dependency on itable.h
 840         (oengine.c, gencode): Delete remaining references.
 841         (BUILT_SRC_FROM_GEN): Clean up.
 842
 843 1998-12-16  Gavin Romig-Koch  <gavin@cygnus.com>
 844
 845         * vr4run.c: New.
 846         * Makefile.in (SIM_HACK_OBJ,HACK_OBJS,HACK_GEN_SRCS,libhack.a,
 847         tmp-hack,tmp-m32-hack,tmp-m16-hack,tmp-itable-hack,
 848         tmp-run-hack) : New.
 849         * m16.igen (LD,DADDIU,DADDUI5,DADJSP,DADDIUSP,DADDI,DADDU,DSUBU,
 850         DSLL,DSRL,DSRA,DSLLV,DSRAV,DMULT,DMULTU,DDIV,DDIVU,JALX32,JALX):
 851         Drop the "64" qualifier to get the HACK generator working.
 852         Use IMMEDIATE rather than IMMED.  Use SHAMT rather than SHIFT.
 853         * mips.igen (do_daddiu,do_ddiv,do_divu): Remove the 64-only
 854         qualifier to get the hack generator working.
 855         (do_dsll,do_dsllv,do_dsra,do_dsrl,do_dsrlv): New.
 856         (DSLL): Use do_dsll.
 857         (DSLLV): Use do_dsllv.
 858         (DSRA): Use do_dsra.
 859         (DSRL): Use do_dsrl.
 860         (DSRLV): Use do_dsrlv.
 861         (BC1): Move *vr4100 to get the HACK generator working.
 862         (CxC1, DMxC1, MxC1,MACCU,MACCHI,MACCHIU): Rename to
 863         get the HACK generator working.
 864         (MACC) Rename to get the HACK generator working.
 865         (DMACC,MACCS,DMACCS): Add the 64.
 866
 867 1998-12-12  Gavin Romig-Koch  <gavin@cygnus.com>
 868
 869         * mips.igen (BC1): Renamed to BC1a and BC1b to avoid conflicts.
 870         * sim-main.h (SizeFGR): Handle TARGET_ENABLE_FR.
 871
 872 1998-12-11  Gavin Romig-Koch  <gavin@cygnus.com>
 873
 874     * mips/interp.c (DEBUG): Cleanups.
 875
 876 1998-12-10  Frank Ch. Eigler  <fche@cygnus.com>
 877
 878         * dv-tx3904sio.c (tx3904sio_io_read_buffer): Endianness fixes.
 879         (tx3904sio_tickle): fflush after a stdout character output.
 880
 881 1998-12-03  Frank Ch. Eigler  <fche@cygnus.com>
 882
 883         * interp.c (sim_close): Uninstall modules.
 884
 885 Wed Nov 25 13:41:03 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 886
 887         * sim-main.h, interp.c (sim_monitor): Change to global
 888         function.
 889
 890 Wed Nov 25 17:33:24 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 891
 892         * configure.in (vr4100): Only include vr4100 instructions in
 893         simulator.
 894         * configure: Re-generate.
 895         * m16.igen (*): Tag all mips16 instructions as also being vr4100.
 896
 897 Mon Nov 23 18:20:36 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 898
 899         * Makefile.in (SIM_CFLAGS): Do not define WITH_IGEN.
 900         * sim-main.h, sim-main.c, interp.c: Delete #if WITH_IGEN keeping
 901         true alternative.
 902
 903         * configure.in (sim_default_gen, sim_use_gen): Replace with
 904         sim_gen.
 905         (--enable-sim-igen): Delete config option. Always using IGEN.
 906         * configure: Re-generate.
 907
 908         * Makefile.in (gencode): Kill, kill, kill.
 909         * gencode.c: Ditto.
 910
 911 Mon Nov 23 18:07:36 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 912
 913         * configure.in: Configure mips64vr4100-elf nee mips64vr41* as a 64
 914         bit mips16 igen simulator.
 915         * configure: Re-generate.
 916
 917         * mips.igen (check_div_hilo, check_mult_hilo, check_mf_hilo): Mark
 918         as part of vr4100 ISA.
 919         * vr.igen: Mark all instructions as 64 bit only.
 920
 921 Mon Nov 23 17:07:37 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 922
 923         * interp.c (get_cell, sim_monitor, fetch_str, CoProcPresent):
 924         Pacify GCC.
 925
 926 Mon Nov 23 13:23:40 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 927
 928         * configure.in: Configure mips-lsi-elf nee mips*lsi* as a
 929         mipsIII/mips16 igen simulator.  Fix sim_gen VS sim_igen typos.
 930         * configure: Re-generate.
 931
 932         * m16.igen (BREAK): Define breakpoint instruction.
 933         (JALX32): Mark instruction as mips16 and not r3900.
 934         * mips.igen (C.cond.fmt): Fix typo in instruction format.
 935
 936         * sim-main.h (PENDING_FILL): Wrap C statements in do/while.
 937
 938 Sat Nov  7 09:54:38 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 939
 940         * gencode.c (build_instruction - BREAK): For MIPS16, handle BREAK
 941         insn as a debug breakpoint.
 942
 943         * sim-main.h (PENDING_SLOT_BIT): Fix, was incorrectly defined as
 944         pending.slot_size.
 945         (PENDING_SCHED): Clean up trace statement.
 946         (PENDING_SCHED): Increment PENDING_IN and PENDING_TOTAL.
 947         (PENDING_FILL): Delay write by only one cycle.
 948         (PENDING_FILL): For FSRs, write fmt_uninterpreted to FPR_STATE.
 949
 950         * sim-main.c (pending_tick): Clean up trace statements. Add trace
 951         of pending writes.
 952         (pending_tick): Fix sizes in switch statements, 4 & 8 instead of
 953         32 & 64.
 954         (pending_tick): Move incrementing of index to FOR statement.
 955         (pending_tick): Only update PENDING_OUT after a write has occured.
 956
 957         * configure.in: Add explicit mips-lsi-* target.  Use gencode to
 958         build simulator.
 959         * configure: Re-generate.
 960
 961         * interp.c (sim_engine_run OLD): Delete explicit call to
 962         PENDING_TICK. Now called via ENGINE_ISSUE_PREFIX_HOOK.
 963
 964 Sat Oct 30 09:49:10 1998  Frank Ch. Eigler  <fche@cygnus.com>
 965
 966         * dv-tx3904cpu.c (deliver_tx3904cpu_interrupt): Add dummy
 967         interrupt level number to match changed SignalExceptionInterrupt
 968         macro.
 969
 970 Fri Oct  9 18:02:25 1998  Doug Evans  <devans@canuck.cygnus.com>
 971
 972         * interp.c: #include "itable.h" if WITH_IGEN.
 973         (get_insn_name): New function.
 974         (sim_open): Initialize CPU_INSN_NAME,CPU_MAX_INSNS.
 975         * sim-main.h (MAX_INSNS,INSN_NAME): Delete.
 976
 977 Mon Sep 14 12:36:44 1998  Frank Ch. Eigler  <fche@cygnus.com>
 978
 979         * configure: Rebuilt to inhale new common/aclocal.m4.
 980
 981 Tue Sep  1 15:39:18 1998  Frank Ch. Eigler  <fche@cygnus.com>
 982
 983         * dv-tx3904sio.c: Include sim-assert.h.
 984
 985 Tue Aug 25 12:49:46 1998  Frank Ch. Eigler  <fche@cygnus.com>
 986
 987         * dv-tx3904sio.c: New file: tx3904 serial I/O module.
 988         * configure.in: Add dv-tx3904sio, dv-sockser for tx39 target.
 989         Reorganize target-specific sim-hardware checks.
 990         * configure: rebuilt.
 991         * interp.c (sim_open): For tx39 target boards, set
 992         OPERATING_ENVIRONMENT, add tx3904sio devices.
 993         * tconfig.in: For tx39 target, set SIM_HANDLES_LMA for loading
 994         ROM executables.  Install dv-sockser into sim-modules list.
 995
 996         * dv-tx3904irc.c: Compiler warning clean-up.
 997         * dv-tx3904tmr.c: Compiler warning clean-up.  Remove particularly
 998         frequent hw-trace messages.
 999
1000 Fri Jul 31 18:14:16 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1001
1002         * vr.igen (MulAcc): Identify as a vr4100 specific function.
1003
1004 Sat Jul 25 16:03:14 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1005
1006         * Makefile.in (IGEN_INCLUDE): Add vr.igen.
1007
1008         * vr.igen: New file.
1009         (MAC/MADD16, DMAC/DMADD16): Implement using code from gencode.c.
1010         * mips.igen: Define vr4100 model. Include vr.igen.
1011 Mon Jun 29 09:21:07 1998  Gavin Koch  <gavin@cygnus.com>
1012
1013         * mips.igen (check_mf_hilo): Correct check.
1014
1015 Wed Jun 17 12:20:49 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1016
1017         * sim-main.h (interrupt_event): Add prototype.
1018
1019         * dv-tx3904tmr.c (tx3904tmr_io_write_buffer): Delete unused
1020         register_ptr, register_value.
1021         (deliver_tx3904tmr_tick): Fix types passed to printf fmt.
1022
1023         * sim-main.h (tracefh): Make extern.
1024
1025 Tue Jun 16 14:39:00 1998  Frank Ch. Eigler  <fche@cygnus.com>
1026
1027         * dv-tx3904tmr.c: Deschedule timer event after dispatching.
1028         Reduce unnecessarily high timer event frequency.
1029         * dv-tx3904cpu.c: Ditto for interrupt event.
1030
1031 Wed Jun 10 13:22:32 1998  Frank Ch. Eigler  <fche@cygnus.com>
1032
1033         * interp.c (decode_coproc): For TX39, add stub COP0 register #7,
1034         to allay warnings.
1035         (interrupt_event): Made non-static.
1036
1037         * dv-tx3904tmr.c (deliver_tx3904tmr_tick): Correct accidental
1038         interchange of configuration values for external vs. internal
1039         clock dividers.
1040
1041 Tue Jun  9 12:46:24 1998  Ian Carmichael  <iancarm@cygnus.com>
1042
1043         * mips.igen (BREAK): Moved code to here for
1044         simulator-reserved break instructions.
1045         * gencode.c (build_instruction): Ditto.
1046         * interp.c (signal_exception): Code moved from here.  Non-
1047         reserved instructions now use exception vector, rather
1048         than halting sim.
1049         * sim-main.h: Moved magic constants to here.
1050
1051 Tue Jun  9 12:29:50 1998  Frank Ch. Eigler  <fche@cygnus.com>
1052
1053         * dv-tx3904cpu.c (deliver_*_interrupt,*_port_event): Set the CAUSE
1054         register upon non-zero interrupt event level, clear upon zero
1055         event value.
1056         * dv-tx3904irc.c (*_port_event): Handle deactivated interrupt signal
1057         by passing zero event value.
1058         (*_io_{read,write}_buffer): Endianness fixes.
1059         * dv-tx3904tmr.c (*_io_{read,write}_buffer): Endianness fixes.
1060         (deliver_*_tick): Reduce sim event interval to 75% of count interval.
1061
1062         * interp.c (sim_open): Added jmr3904pal board type that adds PAL-based
1063         serial I/O and timer module at base address 0xFFFF0000.
1064
1065 Tue Jun  9 11:52:29 1998  Gavin Koch  <gavin@cygnus.com>
1066
1067         * mips.igen (SWC1) : Correct the handling of ReverseEndian
1068         and BigEndianCPU.
1069
1070 Tue Jun  9 11:40:57 1998  Gavin Koch  <gavin@cygnus.com>
1071
1072         * configure.in (mips_fpu_bitsize) : Set this correctly for 32-bit mips
1073         parts.
1074         * configure: Update.
1075
1076 Thu Jun  4 15:37:33 1998  Frank Ch. Eigler  <fche@cygnus.com>
1077
1078         * dv-tx3904tmr.c: New file - implements tx3904 timer.
1079         * dv-tx3904{irc,cpu}.c: Mild reformatting.
1080         * configure.in: Include tx3904tmr in hw_device list.
1081         * configure: Rebuilt.
1082         * interp.c (sim_open): Instantiate three timer instances.
1083         Fix address typo of tx3904irc instance.
1084
1085 Tue Jun  2 15:48:02 1998  Ian Carmichael  <iancarm@cygnus.com>
1086
1087         * interp.c (signal_exception): SystemCall exception now uses
1088         the exception vector.
1089
1090 Mon Jun  1 18:18:26 1998  Frank Ch. Eigler  <fche@cygnus.com>
1091
1092         * interp.c (decode_coproc): For TX39, add stub COP0 register #3,
1093         to allay warnings.
1094
1095 Fri May 29 11:40:39 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1096
1097         * configure.in (sim_igen_filter): Match mips*tx39 not mipst*tx39.
1098
1099 Mon May 25 20:47:45 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1100
1101         * dv-tx3904cpu.c, dv-tx3904irc.c: Rename *_callback to *_method.
1102
1103         * dv-tx3904cpu.c, dv-tx3904irc.c: Include hw-main.h and
1104         sim-main.h. Declare a struct hw_descriptor instead of struct
1105         hw_device_descriptor.
1106
1107 Mon May 25 12:41:38 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1108
1109         * mips.igen (do_store_left, do_load_left): Compute nr of left and
1110         right bits and then re-align left hand bytes to correct byte
1111         lanes.  Fix incorrect computation in do_store_left when loading
1112         bytes from second word.
1113
1114 Fri May 22 13:34:20 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1115
1116         * configure.in (SIM_AC_OPTION_HARDWARE): Only enable when tx3904.
1117         * interp.c (sim_open): Only create a device tree when HW is
1118         enabled.
1119
1120         * dv-tx3904irc.c (tx3904irc_finish): Pacify GCC.
1121         * interp.c (signal_exception): Ditto.
1122
1123 Thu May 21 14:24:11 1998  Gavin Koch  <gavin@cygnus.com>
1124
1125         * gencode.c: Mark BEGEZALL as LIKELY.
1126
1127 Thu May 21 18:57:19 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1128
1129         * sim-main.h (ALU32_END): Sign extend 32 bit results.
1130         * mips.igen (ADD, SUB, ADDI, DADD, DSUB): Trace.
1131
1132 Mon May 18 18:22:42 1998  Frank Ch. Eigler  <fche@cygnus.com>
1133
1134         * configure.in (SIM_AC_OPTION_HARDWARE): Added common hardware
1135         modules.  Recognize TX39 target with "mips*tx39" pattern.
1136         * configure: Rebuilt.
1137         * sim-main.h (*): Added many macros defining bits in
1138         TX39 control registers.
1139         (SignalInterrupt): Send actual PC instead of NULL.
1140         (SignalNMIReset): New exception type.
1141         * interp.c (board): New variable for future use to identify
1142         a particular board being simulated.
1143         (mips_option_handler,mips_options): Added "--board" option.
1144         (interrupt_event): Send actual PC.
1145         (sim_open): Make memory layout conditional on board setting.
1146         (signal_exception): Initial implementation of hardware interrupt
1147         handling.  Accept another break instruction variant for simulator
1148         exit.
1149         (decode_coproc): Implement RFE instruction for TX39.
1150         (mips.igen): Decode RFE instruction as such.
1151         * configure.in (tx3904cpu,tx3904irc): Added devices for tx3904.
1152         * interp.c: Define "jmr3904" and "jmr3904debug" board types and
1153         bbegin to implement memory map.
1154         * dv-tx3904cpu.c: New file.
1155         * dv-tx3904irc.c: New file.
1156
1157 Wed May 13 14:40:11 1998  Gavin Koch  <gavin@cygnus.com>
1158
1159         * mips.igen (check_mt_hilo): Create a separate r3900 version.
1160
1161 Wed May 13 14:11:46 1998  Gavin Koch  <gavin@cygnus.com>
1162
1163         * tx.igen (madd,maddu):  Replace calls to check_op_hilo
1164         with calls to check_div_hilo.
1165
1166 Wed May 13 09:59:27 1998  Gavin Koch  <gavin@cygnus.com>
1167
1168         * mips/mips.igen (check_op_hilo,check_mult_hilo,check_div_hilo):
1169         Replace check_op_hilo with check_mult_hilo and check_div_hilo.
1170         Add special r3900 version of do_mult_hilo.
1171         (do_dmultx,do_mult,do_multu): Replace calls to check_op_hilo
1172         with calls to check_mult_hilo.
1173         (do_ddiv,do_ddivu,do_div,do_divu): Replace calls to check_op_hilo
1174         with calls to check_div_hilo.
1175
1176 Tue May 12 15:22:11 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1177
1178         * configure.in (SUBTARGET_R3900): Define for mipstx39 target.
1179         Document a replacement.
1180
1181 Fri May  8 17:48:19 1998  Ian Carmichael  <iancarm@cygnus.com>
1182
1183         * interp.c (sim_monitor): Make mon_printf work.
1184
1185 Wed May  6 19:42:19 1998  Doug Evans  <devans@canuck.cygnus.com>
1186
1187         * sim-main.h (INSN_NAME): New arg `cpu'.
1188
1189 Tue Apr 28 18:33:31 1998  Geoffrey Noer  <noer@cygnus.com>
1190
1191         * configure: Regenerated to track ../common/aclocal.m4 changes.
1192
1193 Sun Apr 26 15:31:55 1998  Tom Tromey  <tromey@creche>
1194
1195         * configure: Regenerated to track ../common/aclocal.m4 changes.
1196         * config.in: Ditto.
1197
1198 Sun Apr 26 15:20:01 1998  Tom Tromey  <tromey@cygnus.com>
1199
1200         * acconfig.h: New file.
1201         * configure.in: Reverted change of Apr 24; use sinclude again.
1202
1203 Fri Apr 24 14:16:40 1998  Tom Tromey  <tromey@creche>
1204
1205         * configure: Regenerated to track ../common/aclocal.m4 changes.
1206         * config.in: Ditto.
1207
1208 Fri Apr 24 11:19:20 1998  Tom Tromey  <tromey@cygnus.com>
1209
1210         * configure.in: Don't call sinclude.
1211
1212 Fri Apr 24 11:35:01 1998  Andrew Cagney  <cagney@chook.cygnus.com>
1213
1214         * mips.igen (do_store_left): Pass 0 not NULL to store_memory.
1215
1216 Tue Apr 21 11:59:50 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1217
1218         * mips.igen (ERET): Implement.
1219
1220         * interp.c (decode_coproc): Return sign-extended EPC.
1221
1222         * mips.igen (ANDI, LUI, MFC0): Add tracing code.
1223
1224         * interp.c (signal_exception): Do not ignore Trap.
1225         (signal_exception): On TRAP, restart at exception address.
1226         (HALT_INSTRUCTION, HALT_INSTRUCTION_MASK): Define.
1227         (signal_exception): Update.
1228         (sim_open): Patch V_COMMON interrupt vector with an abort sequence
1229         so that TRAP instructions are caught.
1230
1231 Mon Apr 20 11:26:55 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1232
1233         * sim-main.h (struct hilo_access, struct hilo_history): Define,
1234         contains HI/LO access history.
1235         (struct _sim_cpu): Make hiaccess and loaccess of type hilo_access.
1236         (HIACCESS, LOACCESS): Delete, replace with
1237         (HIHISTORY, LOHISTORY): New macros.
1238         (CHECKHILO): Delete all, moved to mips.igen
1239
1240         * gencode.c (build_instruction): Do not generate checks for
1241         correct HI/LO register usage.
1242
1243         * interp.c (old_engine_run): Delete checks for correct HI/LO
1244         register usage.
1245
1246         * mips.igen (check_mt_hilo, check_mf_hilo, check_op_hilo,
1247         check_mf_cycles): New functions.
1248         (do_mfhi, do_mflo, "mthi", "mtlo", do_ddiv, do_ddivu, do_div,
1249         do_divu, domultx, do_mult, do_multu): Use.
1250
1251         * tx.igen ("madd", "maddu"): Use.
1252
1253 Wed Apr 15 18:31:54 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1254
1255         * mips.igen (DSRAV): Use function do_dsrav.
1256         (SRAV): Use new function do_srav.
1257
1258         * m16.igen (BEQZ, BNEZ): Compare GPR[TRX] not GPR[RX].
1259         (B): Sign extend 11 bit immediate.
1260         (EXT-B*): Shift 16 bit immediate left by 1.
1261         (ADDIU*): Don't sign extend immediate value.
1262
1263 Wed Apr 15 10:32:15 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1264
1265         * m16run.c (sim_engine_run): Restore CIA after handling an event.
1266
1267         * sim-main.h (DELAY_SLOT, NULLIFY_NEXT_INSTRUCTION): For IGEN, use
1268         functions.
1269
1270         * mips.igen (delayslot32, nullify_next_insn): New functions.
1271         (m16.igen): Always include.
1272         (do_*): Add more tracing.
1273
1274         * m16.igen (delayslot16): Add NIA argument, could be called by a
1275         32 bit MIPS16 instruction.
1276
1277         * interp.c (ifetch16): Move function from here.
1278         * sim-main.c (ifetch16): To here.
1279
1280         * sim-main.c (ifetch16, ifetch32): Update to match current
1281         implementations of LH, LW.
1282         (signal_exception): Don't print out incorrect hex value of illegal
1283         instruction.
1284
1285 Wed Apr 15 00:17:25 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1286
1287         * m16run.c (sim_engine_run): Use IMEM16 and IMEM32 to fetch an
1288         instruction.
1289
1290         * m16.igen: Implement MIPS16 instructions.
1291
1292         * mips.igen (do_addiu, do_addu, do_and, do_daddiu, do_daddu,
1293         do_ddiv, do_ddivu, do_div, do_divu, do_dmultx, do_dmultu, do_srav,
1294         do_dsubu, do_mfhi, do_mflo, do_mult, do_multu, do_nor, do_or,
1295         do_sll, do_sllv, do_slt, do_slti, do_sltiu, do_sltu, do_sra,
1296         do_srl, do_srlv, do_subu, do_xor, do_xori): New functions.  Move
1297         bodies of corresponding code from 32 bit insn to these.  Also used
1298         by MIPS16 versions of functions.
1299
1300         * sim-main.h (RAIDX, T8IDX, T8, SPIDX): Define.
1301         (IMEM16): Drop NR argument from macro.
1302
1303 Sat Apr  4 22:39:50 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1304
1305         * Makefile.in (SIM_OBJS): Add sim-main.o.
1306
1307         * sim-main.h (address_translation, load_memory, store_memory,
1308         cache_op, sync_operation, prefetch, ifetch32, pending_tick): Mark
1309         as INLINE_SIM_MAIN.
1310         (pr_addr, pr_uword64): Declare.
1311         (sim-main.c): Include when H_REVEALS_MODULE_P.
1312
1313         * interp.c (address_translation, load_memory, store_memory,
1314         cache_op, sync_operation, prefetch, ifetch32, pending_tick): Move
1315         from here.
1316         * sim-main.c: To here. Fix compilation problems.
1317
1318         * configure.in: Enable inlining.
1319         * configure: Re-config.
1320
1321 Sat Apr  4 20:36:25 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1322
1323         * configure: Regenerated to track ../common/aclocal.m4 changes.
1324
1325 Fri Apr  3 04:32:35 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1326
1327         * mips.igen: Include tx.igen.
1328         * Makefile.in (IGEN_INCLUDE): Add tx.igen.
1329         * tx.igen: New file, contains MADD and MADDU.
1330
1331         * interp.c (load_memory): When shifting bytes, use LOADDRMASK not
1332         the hardwired constant `7'.
1333         (store_memory): Ditto.
1334         (LOADDRMASK): Move definition to sim-main.h.
1335
1336         mips.igen (MTC0): Enable for r3900.
1337         (ADDU): Add trace.
1338
1339         mips.igen (do_load_byte): Delete.
1340         (do_load, do_store, do_load_left, do_load_write, do_store_left,
1341         do_store_right): New functions.
1342         (SW*, LW*, SD*, LD*, SH, LH, SB, LB): Use.
1343
1344         configure.in: Let the tx39 use igen again.
1345         configure: Update.
1346
1347 Thu Apr  2 10:59:39 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1348
1349         * interp.c (sim_monitor): get_mem_info returns a 4 byte quantity,
1350         not an address sized quantity.  Return zero for cache sizes.
1351
1352 Wed Apr  1 23:47:53 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1353
1354         * mips.igen (r3900): r3900 does not support 64 bit integer
1355         operations.
1356
1357 Mon Mar 30 14:46:05 1998  Gavin Koch  <gavin@cygnus.com>
1358
1359         * configure.in (mipstx39*-*-*): Use gencode simulator rather
1360         than igen one.
1361         * configure : Rebuild.
1362
1363 Fri Mar 27 16:15:52 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1364
1365         * configure: Regenerated to track ../common/aclocal.m4 changes.
1366
1367 Fri Mar 27 15:01:50 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1368
1369         * interp.c (mips_option_handler): Iterate over MAX_NR_PROCESSORS.
1370
1371 Wed Mar 25 16:44:27 1998  Ian Carmichael  <iancarm@cygnus.com>
1372
1373         * configure: Regenerated to track ../common/aclocal.m4 changes.
1374         * config.in: Regenerated to track ../common/aclocal.m4 changes.
1375
1376 Wed Mar 25 12:35:29 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1377
1378         * configure: Regenerated to track ../common/aclocal.m4 changes.
1379
1380 Wed Mar 25 10:05:46 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1381
1382         * interp.c (Max, Min): Comment out functions. Not yet used.
1383
1384 Wed Mar 18 12:38:12 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1385
1386         * configure: Regenerated to track ../common/aclocal.m4 changes.
1387
1388 Tue Mar 17 19:05:20 1998  Frank Ch. Eigler  <fche@cygnus.com>
1389
1390         * Makefile.in (MIPS_EXTRA_LIBS, SIM_EXTRA_LIBS): Added
1391         configurable settings for stand-alone simulator.
1392
1393         * configure.in: Added X11 search, just in case.
1394
1395         * configure: Regenerated.
1396
1397 Wed Mar 11 14:09:10 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1398
1399         * interp.c (sim_write, sim_read, load_memory, store_memory):
1400         Replace sim_core_*_map with read_map, write_map, exec_map resp.
1401
1402 Tue Mar  3 13:58:43 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1403
1404         * sim-main.h (GETFCC): Return an unsigned value.
1405
1406 Tue Mar  3 13:21:37 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1407
1408         * mips.igen (DIV): Fix check for -1 / MIN_INT.
1409         (DADD): Result destination is RD not RT.
1410
1411 Fri Feb 27 13:49:49 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1412
1413         * sim-main.h (HIACCESS, LOACCESS): Always define.
1414
1415         * mdmx.igen (Maxi, Mini): Rename Max, Min.
1416
1417         * interp.c (sim_info): Delete.
1418
1419 Fri Feb 27 18:41:01 1998  Doug Evans  <devans@canuck.cygnus.com>
1420
1421         * interp.c (DECLARE_OPTION_HANDLER): Use it.
1422         (mips_option_handler): New argument `cpu'.
1423         (sim_open): Update call to sim_add_option_table.
1424
1425 Wed Feb 25 18:56:22 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1426
1427         * mips.igen (CxC1): Add tracing.
1428
1429 Fri Feb 20 17:43:21 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1430
1431         * sim-main.h (Max, Min): Declare.
1432
1433         * interp.c (Max, Min): New functions.
1434
1435         * mips.igen (BC1): Add tracing.
1436
1437 Thu Feb 19 14:50:00 1998  John Metzler  <jmetzler@cygnus.com>
1438
1439         * interp.c Added memory map for stack in vr4100
1440
1441 Thu Feb 19 10:21:21 1998  Gavin Koch  <gavin@cygnus.com>
1442
1443         * interp.c (load_memory): Add missing "break"'s.
1444
1445 Tue Feb 17 12:45:35 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1446
1447         * interp.c (sim_store_register, sim_fetch_register): Pass in
1448         length parameter.  Return -1.
1449
1450 Tue Feb 10 11:57:40 1998  Ian Carmichael  <iancarm@cygnus.com>
1451
1452         * interp.c: Added hardware init hook, fixed warnings.
1453
1454 Sat Feb  7 17:16:20 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1455
1456         * Makefile.in (itable.h itable.c): Depend on SIM_@sim_gen@_ALL.
1457
1458 Tue Feb  3 11:36:02 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1459
1460         * interp.c (ifetch16): New function.
1461
1462         * sim-main.h (IMEM32): Rename IMEM.
1463         (IMEM16_IMMED): Define.
1464         (IMEM16): Define.
1465         (DELAY_SLOT): Update.
1466
1467         * m16run.c (sim_engine_run): New file.
1468
1469         * m16.igen: All instructions except LB.
1470         (LB): Call do_load_byte.
1471         * mips.igen (do_load_byte): New function.
1472         (LB): Call do_load_byte.
1473
1474         * mips.igen: Move spec for insn bit size and high bit from here.
1475         * Makefile.in (tmp-igen, tmp-m16): To here.
1476
1477         * m16.dc: New file, decode mips16 instructions.
1478
1479         * Makefile.in (SIM_NO_ALL): Define.
1480         (tmp-m16): Generate both 16 bit and 32 bit simulator engines.
1481
1482 Tue Feb  3 11:28:00 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1483
1484         * configure.in (mips_fpu_bitsize): For tx39, restrict floating
1485         point unit to 32 bit registers.
1486         * configure: Re-generate.
1487
1488 Sun Feb  1 15:47:14 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1489
1490         * configure.in (sim_use_gen): Make IGEN the default simulator
1491         generator for generic 32 and 64 bit mips targets.
1492         * configure: Re-generate.
1493
1494 Sun Feb  1 16:52:37 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1495
1496         * sim-main.h (SizeFGR): Determine from floating-point and not gpr
1497         bitsize.
1498
1499         * interp.c (sim_fetch_register, sim_store_register): Read/write
1500         FGR from correct location.
1501         (sim_open): Set size of FGR's according to
1502         WITH_TARGET_FLOATING_POINT_BITSIZE.
1503
1504         * sim-main.h (FGR): Store floating point registers in a separate
1505         array.
1506
1507 Sun Feb  1 16:47:51 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1508
1509         * configure: Regenerated to track ../common/aclocal.m4 changes.
1510
1511 Tue Feb  3 00:10:50 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1512
1513         * interp.c (ColdReset): Call PENDING_INVALIDATE.
1514
1515         * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Call PENDING_TICK.
1516
1517         * interp.c (pending_tick): New function.  Deliver pending writes.
1518
1519         * sim-main.h (PENDING_FILL, PENDING_TICK, PENDING_SCHED,
1520         PENDING_BIT, PENDING_INVALIDATE): Re-write pipeline code so that
1521         it can handle mixed sized quantites and single bits.
1522
1523 Mon Feb  2 17:43:15 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1524
1525         * interp.c (oengine.h): Do not include when building with IGEN.
1526         (sim_open): Replace GPRLEN by WITH_TARGET_WORD_BITSIZE.
1527         (sim_info): Ditto for PROCESSOR_64BIT.
1528         (sim_monitor): Replace ut_reg with unsigned_word.
1529         (*): Ditto for t_reg.
1530         (LOADDRMASK): Define.
1531         (sim_open): Remove defunct check that host FP is IEEE compliant,
1532         using software to emulate floating point.
1533         (value_fpr, ...): Always compile, was conditional on HASFPU.
1534
1535 Sun Feb  1 11:15:29 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1536
1537         * sim-main.h (sim_state): Make the cpu array MAX_NR_PROCESSORS in
1538         size.
1539
1540         * interp.c (SD, CPU): Define.
1541         (mips_option_handler): Set flags in each CPU.
1542         (interrupt_event): Assume CPU 0 is the one being iterrupted.
1543         (sim_close): Do not clear STATE, deleted anyway.
1544         (sim_write, sim_read): Assume CPU zero's vm should be used for
1545         data transfers.
1546         (sim_create_inferior): Set the PC for all processors.
1547         (sim_monitor, store_word, load_word, mips16_entry): Add cpu
1548         argument.
1549         (mips16_entry): Pass correct nr of args to store_word, load_word.
1550         (ColdReset): Cold reset all cpu's.
1551         (signal_exception): Pass cpu to sim_monitor & mips16_entry.
1552         (sim_monitor, load_memory, store_memory, signal_exception): Use
1553         `CPU' instead of STATE_CPU.
1554
1555
1556         * sim-main.h: Replace uses of STATE_CPU with CPU. Replace sd with
1557         SD or CPU_.
1558
1559         * sim-main.h (signal_exception): Add sim_cpu arg.
1560         (SignalException*): Pass both SD and CPU to signal_exception.
1561         * interp.c (signal_exception): Update.
1562
1563         * sim-main.h (value_fpr, store_fpr, dotrace, ifetch32), interp.c:
1564         Ditto
1565         (sync_operation, prefetch, cache_op, store_memory, load_memory,
1566         address_translation): Ditto
1567         (decode_coproc, cop_lw, cop_ld, cop_sw, cop_sd): Ditto.
1568
1569 Sat Jan 31 18:15:41 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1570
1571         * configure: Regenerated to track ../common/aclocal.m4 changes.
1572
1573 Sat Jan 31 14:49:24 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1574
1575         * interp.c (sim_engine_run): Add `nr_cpus' argument.
1576
1577         * mips.igen (model): Map processor names onto BFD name.
1578
1579         * sim-main.h (CPU_CIA): Delete.
1580         (SET_CIA, GET_CIA): Define
1581
1582 Wed Jan 21 16:16:27 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1583
1584         * sim-main.h (GPR_SET): Define, used by igen when zeroing a
1585         regiser.
1586
1587         * configure.in (default_endian): Configure a big-endian simulator
1588         by default.
1589         * configure: Re-generate.
1590
1591 Mon Jan 19 22:26:29 1998  Doug Evans  <devans@seba>
1592
1593         * configure: Regenerated to track ../common/aclocal.m4 changes.
1594
1595 Mon Jan  5 20:38:54 1998  Mark Alexander  <marka@cygnus.com>
1596
1597         * interp.c (sim_monitor): Handle Densan monitor outbyte
1598         and inbyte functions.
1599
1600 1997-12-29  Felix Lee  <flee@cygnus.com>
1601
1602         * interp.c (sim_engine_run): msvc cpp barfs on #if (a==b!=c).
1603
1604 Wed Dec 17 14:48:20 1997  Jeffrey A Law  (law@cygnus.com)
1605
1606         * Makefile.in (tmp-igen): Arrange for $zero to always be
1607         reset to zero after every instruction.
1608
1609 Mon Dec 15 23:17:11 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1610
1611         * configure: Regenerated to track ../common/aclocal.m4 changes.
1612         * config.in: Ditto.
1613
1614 Wed Dec 10 17:10:45 1997  Jeffrey A Law  (law@cygnus.com)
1615
1616         * mips.igen (MSUB): Fix to work like MADD.
1617         * gencode.c (MSUB): Similarly.
1618
1619 Thu Dec  4 09:21:05 1997  Doug Evans  <devans@canuck.cygnus.com>
1620
1621         * configure: Regenerated to track ../common/aclocal.m4 changes.
1622
1623 Wed Nov 26 11:00:23 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1624
1625         * mips.igen (LWC1): Correct assembler - lwc1 not swc1.
1626
1627 Sun Nov 23 01:45:20 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1628
1629         * sim-main.h (sim-fpu.h): Include.
1630
1631         * interp.c (convert, SquareRoot, Recip, Divide, Multiply, Sub,
1632         Add, Negate, AbsoluteValue, Equal, Less, Infinity, NaN): Rewrite
1633         using host independant sim_fpu module.
1634
1635 Thu Nov 20 19:56:22 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1636
1637         * interp.c (signal_exception): Report internal errors with SIGABRT
1638         not SIGQUIT.
1639
1640         * sim-main.h (C0_CONFIG): New register.
1641         (signal.h): No longer include.
1642
1643         * interp.c (decode_coproc): Allow access C0_CONFIG to register.
1644
1645 Tue Nov 18 15:33:48 1997  Doug Evans  <devans@canuck.cygnus.com>
1646
1647         * Makefile.in (SIM_OBJS): Use $(SIM_NEW_COMMON_OBJS).
1648
1649 Fri Nov 14 11:56:48 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1650
1651         * mips.igen: Tag vr5000 instructions.
1652         (ANDI): Was missing mipsIV model, fix assembler syntax.
1653         (do_c_cond_fmt): New function.
1654         (C.cond.fmt): Handle mips I-III which do not support CC field
1655         separatly.
1656         (bc1): Handle mips IV which do not have a delaed FCC separatly.
1657         (SDR): Mask paddr when BigEndianMem, not the converse as specified
1658         in IV3.2 spec.
1659         (DMULT, DMULTU): Force use of hosts 64bit multiplication.  Handle
1660         vr5000 which saves LO in a GPR separatly.
1661
1662         * configure.in (enable-sim-igen): For vr5000, select vr5000
1663         specific instructions.
1664         * configure: Re-generate.
1665
1666 Wed Nov 12 14:42:52 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1667
1668         * Makefile.in (SIM_OBJS): Add sim-fpu module.
1669
1670         * interp.c (store_fpr), sim-main.h: Add separate fmt_uninterpreted_32 and
1671         fmt_uninterpreted_64 bit cases to switch.  Convert to
1672         fmt_formatted,
1673
1674         * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Define,
1675
1676         * mips.igen (SWR): Mask paddr when BigEndianMem, not the converse
1677         as specified in IV3.2 spec.
1678         (MTC1, DMTC1): Call StoreFPR to store the GPR in the FPR.
1679
1680 Tue Nov 11 12:38:23 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1681
1682         * mips.igen: Delay slot branches add OFFSET to NIA not CIA.
1683         (MFC0, MTC0, SWC1, LWC1, SDC1, LDC1): Implement.
1684         (MTC1, MFC1, DMTC1, DMFC1, CFC1, CTC1): Implement separate non
1685         PENDING_FILL versions of instructions.  Simplify.
1686         (X): New function.
1687         (MULT, MULTU): Implement separate RD==0 and RD!=0 versions of
1688         instructions.
1689         (BEQZ, ..., SLT, SLTI, TLT, TLE, TLI, ...): Explicitly cast GPR to
1690         a signed value.
1691         (MTHI, MFHI): Disable code checking HI-LO.
1692
1693         * sim-main.h (dotrace,tracefh), interp.c: Make dotrace & tracefh
1694         global.
1695         (NULLIFY_NEXT_INSTRUCTION): Call dotrace.
1696
1697 Thu Nov  6 16:36:35 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1698
1699         * gencode.c (build_mips16_operands): Replace IPC with cia.
1700
1701         * interp.c (sim_monitor, signal_exception, cache_op, store_fpr,
1702         value_fpr, cop_ld, cop_lw, cop_sw, cop_sd, decode_coproc): Replace
1703         IPC to `cia'.
1704         (UndefinedResult): Replace function with macro/function
1705         combination.
1706         (sim_engine_run): Don't save PC in IPC.
1707
1708         * sim-main.h (IPC): Delete.
1709
1710
1711         * interp.c (signal_exception, store_word, load_word,
1712         address_translation, load_memory, store_memory, cache_op,
1713         prefetch, sync_operation, ifetch, value_fpr, store_fpr, convert,
1714         cop_lw, cop_ld, cop_sw, cop_sd, decode_coproc, sim_monitor): Add
1715         current instruction address - cia - argument.
1716         (sim_read, sim_write): Call address_translation directly.
1717         (sim_engine_run): Rename variable vaddr to cia.
1718         (signal_exception): Pass cia to sim_monitor
1719
1720         * sim-main.h (SignalException, LoadWord, StoreWord, CacheOp,
1721         Prefetch, SyncOperation, ValueFPR, StoreFPR, Convert, COP_LW,
1722         COP_LD, COP_SW, COP_SD, DecodeCoproc): Update.
1723
1724         * sim-main.h (SignalExceptionSimulatorFault): Delete definition.
1725         * interp.c (sim_open): Replace SignalExceptionSimulatorFault with
1726         SIM_ASSERT.
1727
1728         * interp.c (signal_exception): Pass restart address to
1729         sim_engine_restart.
1730
1731         * Makefile.in (semantics.o, engine.o, support.o, itable.o,
1732         idecode.o): Add dependency.
1733
1734         * sim-main.h (SIM_ENGINE_HALT_HOOK, SIM_ENGINE_RESUME_HOOK):
1735         Delete definitions
1736         (DELAY_SLOT): Update NIA not PC with branch address.
1737         (NULLIFY_NEXT_INSTRUCTION): Set NIA to instruction after next.
1738
1739         * mips.igen: Use CIA not PC in branch calculations.
1740         (illegal): Call SignalException.
1741         (BEQ, ADDIU): Fix assembler.
1742
1743 Wed Nov  5 12:19:56 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1744
1745         * m16.igen (JALX): Was missing.
1746
1747         * configure.in (enable-sim-igen): New configuration option.
1748         * configure: Re-generate.
1749
1750         * sim-main.h (MAX_INSNS, INSN_NAME): Define.
1751
1752         * interp.c (load_memory, store_memory): Delete parameter RAW.
1753         (sim_read, sim_write): Use sim_core_{read,write}_buffer directly
1754         bypassing {load,store}_memory.
1755
1756         * sim-main.h (ByteSwapMem): Delete definition.
1757
1758         * Makefile.in (SIM_OBJS): Add sim-memopt module.
1759
1760         * interp.c (sim_do_command, sim_commands): Delete mips specific
1761         commands.  Handled by module sim-options.
1762
1763         * sim-main.h (SIM_HAVE_FLATMEM): Undefine, use sim-core.o module.
1764         (WITH_MODULO_MEMORY): Define.
1765
1766         * interp.c (sim_info): Delete code printing memory size.
1767
1768         * interp.c (mips_size): Nee sim_size, delete function.
1769         (power2): Delete.
1770         (monitor, monitor_base, monitor_size): Delete global variables.
1771         (sim_open, sim_close): Delete code creating monitor and other
1772         memory regions.  Use sim-memopts module, via sim_do_commandf, to
1773         manage memory regions.
1774         (load_memory, store_memory): Use sim-core for memory model.
1775
1776         * interp.c (address_translation): Delete all memory map code
1777         except line forcing 32 bit addresses.
1778
1779 Wed Nov  5 11:21:11 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1780
1781         * sim-main.h (WITH_TRACE): Delete definition.  Enables common
1782         trace options.
1783
1784         * interp.c (logfh, logfile): Delete globals.
1785         (sim_open, sim_close): Delete code opening & closing log file.
1786         (mips_option_handler): Delete -l and -n options.
1787         (OPTION mips_options): Ditto.
1788
1789         * interp.c (OPTION mips_options): Rename option trace to dinero.
1790         (mips_option_handler): Update.
1791
1792 Wed Nov  5 09:35:59 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1793
1794         * interp.c (fetch_str): New function.
1795         (sim_monitor): Rewrite using sim_read & sim_write.
1796         (sim_open): Check magic number.
1797         (sim_open): Write monitor vectors into memory using sim_write.
1798         (MONITOR_BASE, MONITOR_SIZE, MEM_SIZE): Define.
1799         (sim_read, sim_write): Simplify - transfer data one byte at a
1800         time.
1801         (load_memory, store_memory): Clarify meaning of parameter RAW.
1802
1803         * sim-main.h (isHOST): Defete definition.
1804         (isTARGET): Mark as depreciated.
1805         (address_translation): Delete parameter HOST.
1806
1807         * interp.c (address_translation): Delete parameter HOST.
1808
1809 Wed Oct 29 11:13:56 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1810
1811         * mips.igen:
1812
1813         * Makefile.in (IGEN_INCLUDE): Files included by mips.igen.
1814         (tmp-igen, tmp-m16): Depend on IGEN_INCLUDE.
1815
1816 Tue Oct 28 11:06:47 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1817
1818         * mips.igen: Add model filter field to records.
1819
1820 Mon Oct 27 17:53:59 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1821
1822         * Makefile.in (SIM_NO_CFLAGS): Define.  Define WITH_IGEN=0.
1823
1824         interp.c (sim_engine_run): Do not compile function sim_engine_run
1825         when WITH_IGEN == 1.
1826
1827         * configure.in (sim_igen_flags, sim_m16_flags): Set according to
1828         target architecture.
1829
1830         Makefile.in (tmp-igen, tmp-m16): Drop -F and -M options to
1831         igen. Replace with configuration variables sim_igen_flags /
1832         sim_m16_flags.
1833
1834         * m16.igen: New file.  Copy mips16 insns here.
1835         * mips.igen: From here.
1836
1837 Mon Oct 27 13:53:59 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1838
1839         * Makefile.in (SIM_NO_OBJ): Define, move SIM_M16_OBJ, SIM_IGEN_OBJ
1840         to top.
1841         (tmp-igen, tmp-m16): Pass -I srcdir to igen.
1842
1843 Sat Oct 25 16:51:40 1997  Gavin Koch  <gavin@cygnus.com>
1844
1845         * gencode.c (build_instruction): Follow sim_write's lead in using
1846         BigEndianMem instead of !ByteSwapMem.
1847
1848 Fri Oct 24 17:41:49 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1849
1850         * configure.in (sim_gen): Dependent on target, select type of
1851         generator.  Always select old style generator.
1852
1853         configure: Re-generate.
1854
1855         Makefile.in (tmp-igen, tmp-m16, clean-m16, clean-igen): New
1856         targets.
1857         (SIM_M16_CFLAGS, SIM_M16_ALL, SIM_M16_OBJ, BUILT_SRC_FROM_M16,
1858         SIM_IGEN_CFLAGS, SIM_IGEN_ALL, SIM_IGEN_OBJ, BUILT_SRC_FROM_IGEN,
1859         IGEN_TRACE, IGEN_INSN, IGEN_DC): Define
1860         (SIM_EXTRA_CFLAGS, SIM_EXTRA_ALL, SIM_OBJS): Add member
1861         SIM_@sim_gen@_*, set by autoconf.
1862
1863 Wed Oct 22 12:52:06 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1864
1865         * sim-main.h (NULLIFY_NEXT_INSTRUCTION, DELAY_SLOT): Define.
1866
1867         * interp.c (ColdReset): Remove #ifdef HASFPU, check
1868         CURRENT_FLOATING_POINT instead.
1869
1870         * interp.c (ifetch32): New function. Fetch 32 bit instruction.
1871         (address_translation): Raise exception InstructionFetch when
1872         translation fails and isINSTRUCTION.
1873
1874         * interp.c (sim_open, sim_write, sim_monitor, store_word,
1875         sim_engine_run): Change type of of vaddr and paddr to
1876         address_word.
1877         (address_translation, prefetch, load_memory, store_memory,
1878         cache_op): Change type of vAddr and pAddr to address_word.
1879
1880         * gencode.c (build_instruction): Change type of vaddr and paddr to
1881         address_word.
1882
1883 Mon Oct 20 15:29:04 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1884
1885         * sim-main.h (ALU64_END, ALU32_END): Use ALU*_OVERFLOW_RESULT
1886         macro to obtain result of ALU op.
1887
1888 Tue Oct 21 17:39:14 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1889
1890         * interp.c (sim_info): Call profile_print.
1891
1892 Mon Oct 20 13:31:20 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1893
1894         * Makefile.in (SIM_OBJS): Add sim-profile.o module.
1895
1896         * sim-main.h (WITH_PROFILE): Do not define, defined in
1897         common/sim-config.h.  Use sim-profile module.
1898         (simPROFILE): Delete defintion.
1899
1900         * interp.c (PROFILE): Delete definition.
1901         (mips_option_handler): Delete 'p', 'y' and 'x' profile options.
1902         (sim_close): Delete code writing profile histogram.
1903         (mips_set_profile, mips_set_profile_size, writeout16, writeout32):
1904         Delete.
1905         (sim_engine_run): Delete code profiling the PC.
1906
1907 Mon Oct 20 13:31:20 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1908
1909         * sim-main.h (SIGNEXTEND): Force type of result to unsigned_word.
1910
1911         * interp.c (sim_monitor): Make register pointers of type
1912         unsigned_word*.
1913
1914         * sim-main.h: Make registers of type unsigned_word not
1915         signed_word.
1916
1917 Thu Oct 16 10:31:39 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1918
1919         * interp.c (sync_operation): Rename from SyncOperation, make
1920         global, add SD argument.
1921         (prefetch): Rename from Prefetch, make global, add SD argument.
1922         (decode_coproc): Make global.
1923
1924         * sim-main.h (SyncOperation, DecodeCoproc, Pefetch): Define.
1925
1926         * gencode.c (build_instruction): Generate DecodeCoproc not
1927         decode_coproc calls.
1928
1929         * interp.c (SETFCC, GETFCC, PREVCOC1): Move to sim-main.h
1930         (SizeFGR): Move to sim-main.h
1931         (simHALTEX, simHALTIN, simTRACE, simPROFILE, simDELAYSLOT,
1932         simSIGINT, simJALDELAYSLOT): Move to sim-main.h
1933         (FP_FLAGS, FP_ENABLE, FP_CAUSE, IR, UF, OF, DZ, IO, UO): Move to
1934         sim-main.h.
1935         (FP_FS, FP_MASK_RM, FP_SH_RM, FP_RM_NEAREST, FP_RM_TOPINF,
1936         FP_RM_TOMINF, GETRM): Move to sim-main.h.
1937         (Uncached, CachedNoncoherent, CachedCoherent, Cached,
1938         isINSTRUCTION, ..., AccessLength_BYTE, ...): Move to sim-main.h.
1939         (UserMode, BigEndianMem, ByteSwapMem, ReverseEndian,
1940         BigEndianCPU, status_KSU_mask, ...). Moved to sim-main.h
1941
1942         * sim-main.h (ALU32_END, ALU64_END): Define. When overflow raise
1943         exception.
1944         (sim-alu.h): Include.
1945         (NULLIFY_NIA, NULL_CIA, CPU_CIA): Define.
1946         (sim_cia): Typedef to instruction_address.
1947
1948 Thu Oct 16 10:31:41 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1949
1950         * Makefile.in (interp.o): Rename generated file engine.c to
1951         oengine.c.
1952
1953         * interp.c: Update.
1954
1955 Thu Oct 16 10:31:40 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1956
1957         * gencode.c (build_instruction): Use FPR_STATE not fpr_state.
1958
1959 Thu Oct 16 10:31:39 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1960
1961         * gencode.c (build_instruction): For "FPSQRT", output correct
1962         number of arguments to Recip.
1963
1964 Tue Oct 14 17:38:18 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1965
1966         * Makefile.in (interp.o): Depends on sim-main.h
1967
1968         * interp.c (mips16_entry, ColdReset,dotrace): Add SD argument. Use GPR not registers.
1969
1970         * sim-main.h (sim_cpu): Add registers, register_widths, fpr_state,
1971         ipc, dspc, pending_*, hiaccess, loaccess, state, dsstate fields.
1972         (REGISTERS, REGISTER_WIDTHS, FPR_STATE, IPC, DSPC, PENDING_*,
1973         STATE, DSSTATE): Define
1974         (GPR, FGRIDX, ..): Define.
1975
1976         * interp.c (registers, register_widths, fpr_state, ipc, dspc,
1977         pending_*, hiaccess, loaccess, state, dsstate): Delete globals.
1978         (GPR, FGRIDX, ...): Delete macros.
1979
1980         * interp.c: Update names to match defines from sim-main.h
1981
1982 Tue Oct 14 15:11:45 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1983
1984         * interp.c (sim_monitor): Add SD argument.
1985         (sim_warning): Delete.  Replace calls with calls to
1986         sim_io_eprintf.
1987         (sim_error): Delete. Replace calls with sim_io_error.
1988         (open_trace, writeout32, writeout16, getnum): Add SD argument.
1989         (mips_set_profile): Rename from sim_set_profile. Add SD argument.
1990         (mips_set_profile_size): Rename from sim_set_profile_size. Add SD
1991         argument.
1992         (mips_size): Rename from sim_size. Add SD argument.
1993
1994         * interp.c (simulator): Delete global variable.
1995         (callback): Delete global variable.
1996         (mips_option_handler, sim_open, sim_write, sim_read,
1997         sim_store_register, sim_fetch_register, sim_info, sim_do_command,
1998         sim_size,sim_monitor): Use sim_io_* not callback->*.
1999         (sim_open): ZALLOC simulator struct.
2000         (PROFILE): Do not define.
2001
2002 Tue Oct 14 13:35:48 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2003
2004         * interp.c (sim_open), support.h: Replace CHECKSIM macro found in
2005         support.h with corresponding code.
2006
2007         * sim-main.h (word64, uword64), support.h: Move definition to
2008         sim-main.h.
2009         (WORD64LO, WORD64HI, SET64LO, SET64HI, WORD64, UWORD64): Ditto.
2010
2011         * support.h: Delete
2012         * Makefile.in: Update dependencies
2013         * interp.c: Do not include.
2014
2015 Tue Oct 14 13:35:48 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2016
2017         * interp.c (address_translation, load_memory, store_memory,
2018         cache_op): Rename to from AddressTranslation et.al., make global,
2019         add SD argument
2020
2021         * sim-main.h (AddressTranslation, LoadMemory, StoreMemory,
2022         CacheOp): Define.
2023
2024         * interp.c (SignalException): Rename to signal_exception, make
2025         global.
2026
2027         * interp.c (Interrupt, ...): Move definitions to sim-main.h.
2028
2029         * sim-main.h (SignalException, SignalExceptionInterrupt,
2030         SignalExceptionInstructionFetch, SignalExceptionAddressStore,
2031         SignalExceptionAddressLoad, SignalExceptionSimulatorFault,
2032         SignalExceptionIntegerOverflow, SignalExceptionCoProcessorUnusable):
2033         Define.
2034
2035         * interp.c, support.h: Use.
2036
2037 Tue Oct 14 13:19:20 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2038
2039         * interp.c (ValueFPR, StoreFPR), sim-main.h: Make global, rename
2040         to value_fpr / store_fpr. Add SD argument.
2041         (NaN, Infinity, Less, Equal, AbsoluteValue, Negate, Add, Sub,
2042         Multiply, Divide, Recip, SquareRoot, Convert): Make global.
2043
2044         * sim-main.h (ValueFPR, StoreFPR): Define.
2045
2046 Tue Oct 14 13:06:55 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2047
2048         * interp.c (sim_engine_run): Check consistency between configure
2049         WITH_TARGET_WORD_BITSIZE and WITH_FLOATING_POINT and gensim GPRLEN
2050         and HASFPU.
2051
2052         * configure.in (mips_bitsize): Configure WITH_TARGET_WORD_BITSIZE.
2053         (mips_fpu): Configure WITH_FLOATING_POINT.
2054         (mips_endian): Configure WITH_TARGET_ENDIAN.
2055         * configure: Update.
2056
2057 Fri Oct  3 09:28:00 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2058
2059         * configure: Regenerated to track ../common/aclocal.m4 changes.
2060
2061 Mon Sep 29 14:45:00 1997  Bob Manson  <manson@charmed.cygnus.com>
2062
2063         * configure: Regenerated.
2064
2065 Fri Sep 26 12:48:18 1997  Mark Alexander  <marka@cygnus.com>
2066
2067         * interp.c: Allow Debug, DEPC, and EPC registers to be examined in GDB.
2068
2069 Thu Sep 25 11:15:22 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2070
2071         * gencode.c (print_igen_insn_models): Assume certain architectures
2072         include all mips* instructions.
2073         (print_igen_insn_format): Use data_size==-1 as marker for MIPS16
2074         instruction.
2075
2076         * Makefile.in (tmp.igen): Add target. Generate igen input from
2077         gencode file.
2078
2079         * gencode.c (FEATURE_IGEN): Define.
2080         (main): Add --igen option.  Generate output in igen format.
2081         (process_instructions): Format output according to igen option.
2082         (print_igen_insn_format): New function.
2083         (print_igen_insn_models): New function.
2084         (process_instructions): Only issue warnings and ignore
2085         instructions when no FEATURE_IGEN.
2086
2087 Wed Sep 24 17:38:57 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2088
2089         * interp.c (COP_SD, COP_LD): Add UNUSED to pacify GCC for some
2090         MIPS targets.
2091
2092 Tue Sep 23 11:04:38 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2093
2094         * configure: Regenerated to track ../common/aclocal.m4 changes.
2095
2096 Tue Sep 23 10:19:51 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2097
2098         * Makefile.in (SIM_ALIGNMENT, SIM_ENDIAN, SIM_HOSTENDIAN,
2099         SIM_RESERVED_BITS): Delete, moved to common.
2100         (SIM_EXTRA_CFLAGS): Update.
2101
2102 Mon Sep 22 11:46:20 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2103
2104         * configure.in: Configure non-strict memory alignment.
2105         * configure: Regenerated to track ../common/aclocal.m4 changes.
2106
2107 Fri Sep 19 17:45:25 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2108
2109         * configure: Regenerated to track ../common/aclocal.m4 changes.
2110
2111 Sat Sep 20 14:07:28 1997  Gavin Koch  <gavin@cygnus.com>
2112
2113         * gencode.c (SDBBP,DERET): Added (3900) insns.
2114         (RFE): Turn on for 3900.
2115         * interp.c (DebugBreakPoint,DEPC,Debug,Debug_*): Added.
2116         (dsstate): Made global.
2117         (SUBTARGET_R3900): Added.
2118         (CANCELDELAYSLOT): New.
2119         (SignalException): Ignore SystemCall rather than ignore and
2120         terminate.  Add DebugBreakPoint handling.
2121         (decode_coproc): New insns RFE, DERET; and new registers Debug
2122         and DEPC protected by SUBTARGET_R3900.
2123         (sim_engine_run): Use CANCELDELAYSLOT rather than clearing
2124         bits explicitly.
2125         * Makefile.in,configure.in: Add mips subtarget option.
2126         * configure: Update.
2127
2128 Fri Sep 19 09:33:27 1997  Gavin Koch  <gavin@cygnus.com>
2129
2130         * gencode.c: Add r3900 (tx39).
2131
2132
2133 Tue Sep 16 15:52:04 1997  Gavin Koch  <gavin@cygnus.com>
2134
2135         * gencode.c (build_instruction): Don't need to subtract 4 for
2136         JALR, just 2.
2137
2138 Tue Sep 16 11:32:28 1997  Gavin Koch  <gavin@cygnus.com>
2139
2140         * interp.c: Correct some HASFPU problems.
2141
2142 Mon Sep 15 17:36:15 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2143
2144         * configure: Regenerated to track ../common/aclocal.m4 changes.
2145
2146 Fri Sep 12 12:01:39 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2147
2148         * interp.c (mips_options): Fix samples option short form, should
2149         be `x'.
2150
2151 Thu Sep 11 09:35:29 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2152
2153         * interp.c (sim_info): Enable info code.  Was just returning.
2154
2155 Tue Sep  9 17:30:57 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2156
2157         * interp.c (decode_coproc): Clarify warning about unsuported MTC0,
2158         MFC0.
2159
2160 Tue Sep  9 16:28:28 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2161
2162         * gencode.c (build_instruction): Use SIGNED64 for 64 bit
2163         constants.
2164         (build_instruction): Ditto for LL.
2165
2166 Thu Sep  4 17:21:23 1997  Doug Evans  <dje@seba>
2167
2168         * configure: Regenerated to track ../common/aclocal.m4 changes.
2169
2170 Wed Aug 27 18:13:22 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2171
2172         * configure: Regenerated to track ../common/aclocal.m4 changes.
2173         * config.in: Ditto.
2174
2175 Wed Aug 27 14:12:27 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2176
2177         * interp.c (sim_open): Add call to sim_analyze_program, update
2178         call to sim_config.
2179
2180 Tue Aug 26 10:40:07 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2181
2182         * interp.c (sim_kill): Delete.
2183         (sim_create_inferior): Add ABFD argument. Set PC from same.
2184         (sim_load): Move code initializing trap handlers from here.
2185         (sim_open): To here.
2186         (sim_load): Delete, use sim-hload.c.
2187
2188         * Makefile.in (SIM_OBJS): Add sim-hload.o module.
2189
2190 Mon Aug 25 17:50:22 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2191
2192         * configure: Regenerated to track ../common/aclocal.m4 changes.
2193         * config.in: Ditto.
2194
2195 Mon Aug 25 15:59:48 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2196
2197         * interp.c (sim_open): Add ABFD argument.
2198         (sim_load): Move call to sim_config from here.
2199         (sim_open): To here.  Check return status.
2200
2201 Fri Jul 25 15:00:45 1997  Gavin Koch  <gavin@cygnus.com>
2202
2203         * gencode.c (build_instruction): Two arg MADD should
2204         not assign result to $0.
2205
2206 Thu Jun 26 12:13:17 1997  Angela Marie Thomas (angela@cygnus.com)
2207
2208         * sim/mips/configure: Change default_sim_endian to 0 (bi-endian)
2209         * sim/mips/configure.in: Regenerate.
2210
2211 Wed Jul  9 10:29:21 1997  Andrew Cagney  <cagney@critters.cygnus.com>
2212
2213         * interp.c (SUB_REG_UW, SUB_REG_SW, SUB_REG_*): Use more explicit
2214         signed8, unsigned8 et.al. types.
2215
2216         * interp.c (SUB_REG_FETCH): Handle both little and big endian
2217         hosts when selecting subreg.
2218
2219 Wed Jul  2 11:54:10 1997  Jeffrey A Law  (law@cygnus.com)
2220
2221         * interp.c (sim_engine_run): Reset the ZERO register to zero
2222         regardless of FEATURE_WARN_ZERO.
2223         * gencode.c (FEATURE_WARNINGS): Remove FEATURE_WARN_ZERO.
2224
2225 Wed Jun  4 10:43:14 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2226
2227         * interp.c (decode_coproc): Implement MTC0 N, CAUSE.
2228         (SignalException): For BreakPoints ignore any mode bits and just
2229         save the PC.
2230         (SignalException): Always set the CAUSE register.
2231
2232 Tue Jun  3 05:00:33 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2233
2234         * interp.c (SignalException): Clear the simDELAYSLOT flag when an
2235         exception has been taken.
2236
2237         * interp.c: Implement the ERET and mt/f sr instructions.
2238
2239 Sat May 31 00:44:16 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2240
2241         * interp.c (SignalException): Don't bother restarting an
2242         interrupt.
2243
2244 Fri May 30 23:41:48 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2245
2246         * interp.c (SignalException): Really take an interrupt.
2247         (interrupt_event): Only deliver interrupts when enabled.
2248
2249 Tue May 27 20:08:06 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2250
2251         * interp.c (sim_info): Only print info when verbose.
2252         (sim_info) Use sim_io_printf for output.
2253
2254 Tue May 27 14:22:23 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2255
2256         * interp.c (CoProcPresent): Add UNUSED attribute - not used by all
2257         mips architectures.
2258
2259 Tue May 27 14:22:23 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2260
2261         * interp.c (sim_do_command): Check for common commands if a
2262         simulator specific command fails.
2263
2264 Thu May 22 09:32:03 1997  Gavin Koch  <gavin@cygnus.com>
2265
2266         * interp.c (sim_engine_run): ifdef out uses of simSTOP, simSTEP
2267         and simBE when DEBUG is defined.
2268
2269 Wed May 21 09:08:10 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2270
2271         * interp.c (interrupt_event): New function.  Pass exception event
2272         onto exception handler.
2273
2274         * configure.in: Check for stdlib.h.
2275         * configure: Regenerate.
2276
2277         * gencode.c (build_instruction): Add UNUSED attribute to tempS
2278         variable declaration.
2279         (build_instruction): Initialize memval1.
2280         (build_instruction): Add UNUSED attribute to byte, bigend,
2281         reverse.
2282         (build_operands): Ditto.
2283
2284         * interp.c: Fix GCC warnings.
2285         (sim_get_quit_code): Delete.
2286
2287         * configure.in: Add INLINE, ENDIAN, HOSTENDIAN and WARNINGS.
2288         * Makefile.in: Ditto.
2289         * configure: Re-generate.
2290
2291         * Makefile.in (SIM_OBJS): Add sim-watch.o module.
2292
2293 Tue May 20 15:08:56 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2294
2295         * interp.c (mips_option_handler): New function parse argumes using
2296         sim-options.
2297         (myname): Replace with STATE_MY_NAME.
2298         (sim_open): Delete check for host endianness - performed by
2299         sim_config.
2300         (simHOSTBE, simBE): Delete, replaced by sim-endian flags.
2301         (sim_open): Move much of the initialization from here.
2302         (sim_load): To here.  After the image has been loaded and
2303         endianness set.
2304         (sim_open): Move ColdReset from here.
2305         (sim_create_inferior): To here.
2306         (sim_open): Make FP check less dependant on host endianness.
2307
2308         * Makefile.in (SIM_RUN_OBJS): Set to nrun.o - use new version or
2309         run.
2310         * interp.c (sim_set_callbacks): Delete.
2311
2312         * interp.c (membank, membank_base, membank_size): Replace with
2313         STATE_MEMORY, STATE_MEM_SIZE, STATE_MEM_BASE.
2314         (sim_open): Remove call to callback->init. gdb/run do this.
2315
2316         * interp.c: Update
2317
2318         * sim-main.h (SIM_HAVE_FLATMEM): Define.
2319
2320         * interp.c (big_endian_p): Delete, replaced by
2321         current_target_byte_order.
2322
2323 Tue May 20 13:55:00 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2324
2325         * interp.c (host_read_long, host_read_word, host_swap_word,
2326         host_swap_long): Delete. Using common sim-endian.
2327         (sim_fetch_register, sim_store_register): Use H2T.
2328         (pipeline_ticks): Delete.  Handled by sim-events.
2329         (sim_info): Update.
2330         (sim_engine_run): Update.
2331
2332 Tue May 20 13:42:03 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2333
2334         * interp.c (sim_stop_reason): Move code determining simEXCEPTION
2335         reason from here.
2336         (SignalException): To here. Signal using sim_engine_halt.
2337         (sim_stop_reason): Delete, moved to common.
2338
2339 Tue May 20 10:19:48 1997  Andrew Cagney  <cagney@b2.cygnus.com>
2340
2341         * interp.c (sim_open): Add callback argument.
2342         (sim_set_callbacks): Delete SIM_DESC argument.
2343         (sim_size): Ditto.
2344
2345 Mon May 19 18:20:38 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2346
2347         * Makefile.in (SIM_OBJS): Add common modules.
2348
2349         * interp.c (sim_set_callbacks): Also set SD callback.
2350         (set_endianness, xfer_*, swap_*): Delete.
2351         (host_read_word, host_read_long, host_swap_word, host_swap_long):
2352         Change to functions using sim-endian macros.
2353         (control_c, sim_stop): Delete, use common version.
2354         (simulate): Convert into.
2355         (sim_engine_run): This function.
2356         (sim_resume): Delete.
2357
2358         * interp.c (simulation): New variable - the simulator object.
2359         (sim_kind): Delete global - merged into simulation.
2360         (sim_load): Cleanup.  Move PC assignment from here.
2361         (sim_create_inferior): To here.
2362
2363         * sim-main.h: New file.
2364         * interp.c (sim-main.h): Include.
2365
2366 Thu Apr 24 00:39:51 1997  Doug Evans  <dje@canuck.cygnus.com>
2367
2368         * configure: Regenerated to track ../common/aclocal.m4 changes.
2369
2370 Wed Apr 23 17:32:19 1997  Doug Evans  <dje@canuck.cygnus.com>
2371
2372         * tconfig.in (SIM_HAVE_BIENDIAN): Define.
2373
2374 Mon Apr 21 17:16:13 1997  Gavin Koch  <gavin@cygnus.com>
2375
2376         * gencode.c (build_instruction): DIV instructions: check
2377         for division by zero and integer overflow before using
2378         host's division operation.
2379
2380 Thu Apr 17 03:18:14 1997  Doug Evans  <dje@canuck.cygnus.com>
2381
2382         * Makefile.in (SIM_OBJS): Add sim-load.o.
2383         * interp.c: #include bfd.h.
2384         (target_byte_order): Delete.
2385         (sim_kind, myname, big_endian_p): New static locals.
2386         (sim_open): Set sim_kind, myname.  Move call to set_endianness to
2387         after argument parsing.  Recognize -E arg, set endianness accordingly.
2388         (sim_load): Return SIM_RC.  New arg abfd.  Call sim_load_file to
2389         load file into simulator.  Set PC from bfd.
2390         (sim_create_inferior): Return SIM_RC.  Delete arg start_address.
2391         (set_endianness): Use big_endian_p instead of target_byte_order.
2392
2393 Wed Apr 16 17:55:37 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2394
2395         * interp.c (sim_size): Delete prototype - conflicts with
2396         definition in remote-sim.h.  Correct definition.
2397
2398 Mon Apr  7 15:45:02 1997  Andrew Cagney  <cagney@kremvax.cygnus.com>
2399
2400         * configure: Regenerated to track ../common/aclocal.m4 changes.
2401         * config.in: Ditto.
2402
2403 Wed Apr  2 15:06:28 1997  Doug Evans  <dje@canuck.cygnus.com>
2404
2405         * interp.c (sim_open): New arg `kind'.
2406
2407         * configure: Regenerated to track ../common/aclocal.m4 changes.
2408
2409 Wed Apr  2 14:34:19 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
2410
2411         * configure: Regenerated to track ../common/aclocal.m4 changes.
2412
2413 Tue Mar 25 11:38:22 1997  Doug Evans  <dje@canuck.cygnus.com>
2414
2415         * interp.c (sim_open): Set optind to 0 before calling getopt.
2416
2417 Wed Mar 19 01:14:00 1997  Andrew Cagney  <cagney@kremvax.cygnus.com>
2418
2419         * configure: Regenerated to track ../common/aclocal.m4 changes.
2420
2421 Mon Mar 17 10:52:59 1997  Gavin Koch  <gavin@cetus.cygnus.com>
2422
2423         * interp.c : Replace uses of pr_addr with pr_uword64
2424         where the bit length is always 64 independent of SIM_ADDR.
2425         (pr_uword64) : added.
2426
2427 Mon Mar 17 15:10:07 1997  Andrew Cagney  <cagney@kremvax.cygnus.com>
2428
2429         * configure: Re-generate.
2430
2431 Fri Mar 14 10:34:11 1997  Michael Meissner  <meissner@cygnus.com>
2432
2433         * configure: Regenerate to track ../common/aclocal.m4 changes.
2434
2435 Thu Mar 13 12:51:36 1997  Doug Evans  <dje@canuck.cygnus.com>
2436
2437         * interp.c (sim_open): New SIM_DESC result.  Argument is now
2438         in argv form.
2439         (other sim_*): New SIM_DESC argument.
2440
2441 Mon Feb 24 22:47:14 1997  Dawn Perchik  <dawn@cygnus.com>
2442
2443         * interp.c: Fix printing of addresses for non-64-bit targets.
2444         (pr_addr): Add function to print address based on size.
2445
2446 Wed Feb 19 14:42:09 1997  Mark Alexander  <marka@cygnus.com>
2447
2448         * interp.c (simopen): Add support for LSI MiniRISC PMON vectors.
2449
2450 Thu Feb 13 14:08:30 1997  Ian Lance Taylor  <ian@cygnus.com>
2451
2452         * gencode.c (build_mips16_operands): Correct computation of base
2453         address for extended PC relative instruction.
2454
2455 Thu Feb  6 17:16:15 1997  Ian Lance Taylor  <ian@cygnus.com>
2456
2457         * interp.c (mips16_entry): Add support for floating point cases.
2458         (SignalException): Pass floating point cases to mips16_entry.
2459         (ValueFPR): Don't restrict fmt_single and fmt_word to even
2460         registers.
2461         (StoreFPR): Likewise.  Also, don't clobber fpr + 1 for fmt_single
2462         or fmt_word.
2463         (COP_LW): Pass fmt_word rather than fmt_uninterpreted to StoreFPR,
2464         and then set the state to fmt_uninterpreted.
2465         (COP_SW): Temporarily set the state to fmt_word while calling
2466         ValueFPR.
2467
2468 Tue Feb  4 16:48:25 1997  Ian Lance Taylor  <ian@cygnus.com>
2469
2470         * gencode.c (build_instruction): The high order may be set in the
2471         comparison flags at any ISA level, not just ISA 4.
2472
2473 Tue Feb  4 13:33:30 1997  Doug Evans  <dje@canuck.cygnus.com>
2474
2475         * Makefile.in (@COMMON_MAKEFILE_FRAG): Use
2476         COMMON_{PRE,POST}_CONFIG_FRAG instead.
2477         * configure.in: sinclude ../common/aclocal.m4.
2478         * configure: Regenerated.
2479
2480 Fri Jan 31 11:11:45 1997  Ian Lance Taylor  <ian@cygnus.com>
2481
2482         * configure: Rebuild after change to aclocal.m4.
2483
2484 Thu Jan 23 11:46:23 1997  Stu Grossman  (grossman@critters.cygnus.com)
2485
2486         * configure configure.in Makefile.in:  Update to new configure
2487         scheme which is more compatible with WinGDB builds.
2488         * configure.in:  Improve comment on how to run autoconf.
2489         * configure:  Re-run autoconf to get new ../common/aclocal.m4.
2490         * Makefile.in:  Use autoconf substitution to install common
2491         makefile fragment.
2492
2493 Wed Jan  8 12:39:03 1997  Jim Wilson  <wilson@cygnus.com>
2494
2495         * gencode.c (build_instruction): Use BigEndianCPU instead of
2496         ByteSwapMem.
2497
2498 Thu Jan 02 22:23:04 1997  Mark Alexander  <marka@cygnus.com>
2499
2500         * interp.c (sim_monitor): Make output to stdout visible in
2501         wingdb's I/O log window.
2502
2503 Tue Dec 31 07:04:00 1996  Mark Alexander  <marka@cygnus.com>
2504
2505         * support.h: Undo previous change to SIGTRAP
2506         and SIGQUIT values.
2507
2508 Mon Dec 30 17:36:06 1996  Ian Lance Taylor  <ian@cygnus.com>
2509
2510         * interp.c (store_word, load_word): New static functions.
2511         (mips16_entry): New static function.
2512         (SignalException): Look for mips16 entry and exit instructions.
2513         (simulate): Use the correct index when setting fpr_state after
2514         doing a pending move.
2515
2516 Sun Dec 29 09:37:18 1996  Mark Alexander  <marka@cygnus.com>
2517
2518         * interp.c: Fix byte-swapping code throughout to work on
2519         both little- and big-endian hosts.
2520
2521 Sun Dec 29 09:18:32 1996  Mark Alexander  <marka@cygnus.com>
2522
2523         * support.h: Make definitions of SIGTRAP and SIGQUIT consistent
2524         with gdb/config/i386/xm-windows.h.
2525
2526 Fri Dec 27 22:48:51 1996  Mark Alexander  <marka@cygnus.com>
2527
2528         * gencode.c (build_instruction): Work around MSVC++ code gen bug
2529         that messes up arithmetic shifts.
2530
2531 Fri Dec 20 11:04:05 1996  Stu Grossman  (grossman@critters.cygnus.com)
2532
2533         * support.h:  Use _WIN32 instead of __WIN32__.  Also add defs for
2534         SIGTRAP and SIGQUIT for _WIN32.
2535
2536 Thu Dec 19 14:07:27 1996  Ian Lance Taylor  <ian@cygnus.com>
2537
2538         * gencode.c (build_instruction) [MUL]: Cast operands to word64, to
2539         force a 64 bit multiplication.
2540         (build_instruction) [OR]: In mips16 mode, don't do anything if the
2541         destination register is 0, since that is the default mips16 nop
2542         instruction.
2543
2544 Mon Dec 16 14:59:38 1996  Ian Lance Taylor  <ian@cygnus.com>
2545
2546         * gencode.c (MIPS16_DECODE): SWRASP is I8, not RI.
2547         (build_endian_shift): Don't check proc64.
2548         (build_instruction): Always set memval to uword64.  Cast op2 to
2549         uword64 when shifting it left in memory instructions.  Always use
2550         the same code for stores--don't special case proc64.
2551
2552         * gencode.c (build_mips16_operands): Fix base PC value for PC
2553         relative operands.
2554         (build_instruction): Call JALDELAYSLOT rather than DELAYSLOT for a
2555         jal instruction.
2556         * interp.c (simJALDELAYSLOT): Define.
2557         (JALDELAYSLOT): Define.
2558         (INDELAYSLOT, INJALDELAYSLOT): Define.
2559         (simulate): Clear simJALDELAYSLOT when simDELAYSLOT is cleared.
2560
2561 Tue Dec 24 22:11:20 1996  Angela Marie Thomas (angela@cygnus.com)
2562
2563         * interp.c (sim_open): add flush_cache as a PMON routine
2564         (sim_monitor): handle flush_cache by ignoring it
2565
2566 Wed Dec 11 13:53:51 1996  Jim Wilson  <wilson@cygnus.com>
2567
2568         * gencode.c (build_instruction): Use !ByteSwapMem instead of
2569         BigEndianMem.
2570         * interp.c (CONFIG, config_EP_{mask,shift,D,DxxDxx, config_BE): Delete.
2571         (BigEndianMem): Rename to ByteSwapMem and change sense.
2572         (BigEndianCPU, sim_write, LoadMemory, StoreMemory): Change
2573         BigEndianMem references to !ByteSwapMem.
2574         (set_endianness): New function, with prototype.
2575         (sim_open): Call set_endianness.
2576         (sim_info): Use simBE instead of BigEndianMem.
2577         (xfer_direct_word, xfer_direct_long, swap_direct_word,
2578         swap_direct_long, xfer_big_word, xfer_big_long, xfer_little_word,
2579         xfer_little_long, swap_word, swap_long): Delete unnecessary MSC_VER
2580         ifdefs, keeping the prototype declaration.
2581         (swap_word): Rewrite correctly.
2582         (ColdReset): Delete references to CONFIG.  Delete endianness related
2583         code; moved to set_endianness.
2584
2585 Tue Dec 10 11:32:04 1996  Jim Wilson  <wilson@cygnus.com>
2586
2587         * gencode.c (build_instruction, case JUMP): Truncate PC to 32 bits.
2588         * interp.c (CHECKHILO): Define away.
2589         (simSIGINT): New macro.
2590         (membank_size): Increase from 1MB to 2MB.
2591         (control_c): New function.
2592         (sim_resume): Rename parameter signal to signal_number.  Add local
2593         variable prev.  Call signal before and after simulate.
2594         (sim_stop_reason): Add simSIGINT support.
2595         (sim_warning, sim_error, dotrace, SignalException): Define as stdarg
2596         functions always.
2597         (sim_warning): Delete call to SignalException.  Do call printf_filtered
2598         if logfh is NULL.
2599         (AddressTranslation): Add #ifdef DEBUG around debugging message and
2600         a call to sim_warning.
2601
2602 Wed Nov 27 11:53:50 1996  Ian Lance Taylor  <ian@cygnus.com>
2603
2604         * gencode.c (process_instructions): If ! proc64, skip DOUBLEWORD
2605         16 bit instructions.
2606
2607 Tue Nov 26 11:53:12 1996  Ian Lance Taylor  <ian@cygnus.com>
2608
2609         Add support for mips16 (16 bit MIPS implementation):
2610         * gencode.c (inst_type): Add mips16 instruction encoding types.
2611         (GETDATASIZEINSN): Define.
2612         (MIPS_DECODE): Add REG flag to dsllv, dsrav, and dsrlv.  Add
2613         jalx.  Add LEFT flag to mfhi and mflo.  Add RIGHT flag to mthi and
2614         mtlo.
2615         (MIPS16_DECODE): New table, for mips16 instructions.
2616         (bitmap_val): New static function.
2617         (struct mips16_op): Define.
2618         (mips16_op_table): New table, for mips16 operands.
2619         (build_mips16_operands): New static function.
2620         (process_instructions): If PC is odd, decode a mips16
2621         instruction.  Break out instruction handling into new
2622         build_instruction function.
2623         (build_instruction): New static function, broken out of
2624         process_instructions.  Check modifiers rather than flags for SHIFT
2625         bit count and m[ft]{hi,lo} direction.
2626         (usage): Pass program name to fprintf.
2627         (main): Remove unused variable this_option_optind.  Change
2628         ``*loptarg++'' to ``loptarg++''.
2629         (my_strtoul): Parenthesize && within ||.
2630         * interp.c (LoadMemory): Accept a halfword pAddr if vAddr is odd.
2631         (simulate): If PC is odd, fetch a 16 bit instruction, and
2632         increment PC by 2 rather than 4.
2633         * configure.in: Add case for mips16*-*-*.
2634         * configure: Rebuild.
2635
2636 Fri Nov 22 08:49:36 1996  Mark Alexander  <marka@cygnus.com>
2637
2638         * interp.c: Allow -t to enable tracing in standalone simulator.
2639         Fix garbage output in trace file and error messages.
2640
2641 Wed Nov 20 01:54:37 1996  Doug Evans  <dje@canuck.cygnus.com>
2642
2643         * Makefile.in: Delete stuff moved to ../common/Make-common.in.
2644         (SIM_{OBJS,EXTRA_CFLAGS,EXTRA_CLEAN}): Define.
2645         * configure.in: Simplify using macros in ../common/aclocal.m4.
2646         * configure: Regenerated.
2647         * tconfig.in: New file.
2648
2649 Tue Nov 12 13:34:00 1996  Dawn Perchik  <dawn@cygnus.com>
2650
2651         * interp.c: Fix bugs in 64-bit port.
2652         Use ansi function declarations for msvc compiler.
2653         Initialize and test file pointer in trace code.
2654         Prevent duplicate definition of LAST_EMED_REGNUM.
2655
2656 Tue Oct 15 11:07:06 1996  Mark Alexander  <marka@cygnus.com>
2657
2658         * interp.c (xfer_big_long): Prevent unwanted sign extension.
2659
2660 Thu Sep 26 17:35:00 1996  James G. Smith  <jsmith@cygnus.co.uk>
2661
2662         * interp.c (SignalException): Check for explicit terminating
2663         breakpoint value.
2664         * gencode.c: Pass instruction value through SignalException()
2665         calls for Trap, Breakpoint and Syscall.
2666
2667 Thu Sep 26 11:35:17 1996  James G. Smith  <jsmith@cygnus.co.uk>
2668
2669         * interp.c (SquareRoot): Add HAVE_SQRT check to ensure sqrt() is
2670         only used on those hosts that provide it.
2671         * configure.in: Add sqrt() to list of functions to be checked for.
2672         * config.in: Re-generated.
2673         * configure: Re-generated.
2674
2675 Fri Sep 20 15:47:12 1996  Ian Lance Taylor  <ian@cygnus.com>
2676
2677         * gencode.c (process_instructions): Call build_endian_shift when
2678         expanding STORE RIGHT, to fix swr.
2679         * support.h (SIGNEXTEND): If the sign bit is not set, explicitly
2680         clear the high bits.
2681         * interp.c (Convert): Fix fmt_single to fmt_long to not truncate.
2682         Fix float to int conversions to produce signed values.
2683
2684 Thu Sep 19 15:34:17 1996  Ian Lance Taylor  <ian@cygnus.com>
2685
2686         * gencode.c (MIPS_DECODE): Set UNSIGNED for multu instruction.
2687         (process_instructions): Correct handling of nor instruction.
2688         Correct shift count for 32 bit shift instructions. Correct sign
2689         extension for arithmetic shifts to not shift the number of bits in
2690         the type.  Fix 64 bit multiply high word calculation.  Fix 32 bit
2691         unsigned multiply.  Fix ldxc1 and friends to use coprocessor 1.
2692         Fix madd.
2693         * interp.c (CHECKHILO): Don't set HIACCESS, LOACCESS, or HLPC.
2694         It's OK to have a mult follow a mult.  What's not OK is to have a
2695         mult follow an mfhi.
2696         (Convert): Comment out incorrect rounding code.
2697
2698 Mon Sep 16 11:38:16 1996  James G. Smith  <jsmith@cygnus.co.uk>
2699
2700         * interp.c (sim_monitor): Improved monitor printf
2701         simulation. Tidied up simulator warnings, and added "--log" option
2702         for directing warning message output.
2703         * gencode.c: Use sim_warning() rather than WARNING macro.
2704
2705 Thu Aug 22 15:03:12 1996  Ian Lance Taylor  <ian@cygnus.com>
2706
2707         * Makefile.in (gencode): Depend upon gencode.o, getopt.o, and
2708         getopt1.o, rather than on gencode.c.  Link objects together.
2709         Don't link against -liberty.
2710         (gencode.o, getopt.o, getopt1.o): New targets.
2711         * gencode.c: Include <ctype.h> and "ansidecl.h".
2712         (AND): Undefine after including "ansidecl.h".
2713         (ULONG_MAX): Define if not defined.
2714         (OP_*): Don't define macros; now defined in opcode/mips.h.
2715         (main): Call my_strtoul rather than strtoul.
2716         (my_strtoul): New static function.
2717
2718 Wed Jul 17 18:12:38 1996  Stu Grossman  (grossman@critters.cygnus.com)
2719
2720         * gencode.c (process_instructions):  Generate word64 and uword64
2721         instead of `long long' and `unsigned long long' data types.
2722         * interp.c:  #include sysdep.h to get signals, and define default
2723         for SIGBUS.
2724         * (Convert):  Work around for Visual-C++ compiler bug with type
2725         conversion.
2726         * support.h:  Make things compile under Visual-C++ by using
2727         __int64 instead of `long long'.  Change many refs to long long
2728         into word64/uword64 typedefs.
2729
2730 Wed Jun 26 12:24:55 1996  Jason Molenda  (crash@godzilla.cygnus.co.jp)
2731
2732         * Makefile.in (bindir, libdir, datadir, mandir, infodir, includedir,
2733         INSTALL_PROGRAM, INSTALL_DATA): Use autoconf-set values.
2734         (docdir): Removed.
2735         * configure.in (AC_PREREQ): autoconf 2.5 or higher.
2736         (AC_PROG_INSTALL): Added.
2737         (AC_PROG_CC): Moved to before configure.host call.
2738         * configure: Rebuilt.
2739
2740 Wed Jun  5 08:28:13 1996  James G. Smith  <jsmith@cygnus.co.uk>
2741
2742         * configure.in: Define @SIMCONF@ depending on mips target.
2743         * configure: Rebuild.
2744         * Makefile.in (run): Add @SIMCONF@ to control simulator
2745         construction.
2746         * gencode.c: Change LOADDRMASK to 64bit memory model only.
2747         * interp.c: Remove some debugging, provide more detailed error
2748         messages, update memory accesses to use LOADDRMASK.
2749
2750 Mon Jun  3 11:55:03 1996  Ian Lance Taylor  <ian@cygnus.com>
2751
2752         * configure.in: Add calls to AC_CONFIG_HEADER, AC_CHECK_HEADERS,
2753         AC_CHECK_LIB, and AC_CHECK_FUNCS.  Change AC_OUTPUT to set
2754         stamp-h.
2755         * configure: Rebuild.
2756         * config.in: New file, generated by autoheader.
2757         * interp.c: Include "config.h".  Include <stdlib.h>, <string.h>,
2758         and <strings.h> if they exist.  Replace #ifdef sun with #ifdef
2759         HAVE_ANINT and HAVE_AINT, as appropriate.
2760         * Makefile.in (run): Use @LIBS@ rather than -lm.
2761         (interp.o): Depend upon config.h.
2762         (Makefile): Just rebuild Makefile.
2763         (clean): Remove stamp-h.
2764         (mostlyclean): Make the same as clean, not as distclean.
2765         (config.h, stamp-h): New targets.
2766
2767 Fri May 10 00:41:17 1996  James G. Smith  <jsmith@cygnus.co.uk>
2768
2769         * interp.c (ColdReset): Fix boolean test. Make all simulator
2770         globals static.
2771
2772 Wed May  8 15:12:58 1996  James G. Smith  <jsmith@cygnus.co.uk>
2773
2774         * interp.c (xfer_direct_word, xfer_direct_long,
2775         swap_direct_word, swap_direct_long, xfer_big_word,
2776         xfer_big_long, xfer_little_word, xfer_little_long,
2777         swap_word,swap_long): Added.
2778         * interp.c (ColdReset): Provide function indirection to
2779         host<->simulated_target transfer routines.
2780         * interp.c (sim_store_register, sim_fetch_register): Updated to
2781         make use of indirected transfer routines.
2782
2783 Fri Apr 19 15:48:24 1996  James G. Smith  <jsmith@cygnus.co.uk>
2784
2785         * gencode.c (process_instructions): Ensure FP ABS instruction
2786         recognised.
2787         * interp.c (AbsoluteValue): Add routine. Also provide simple PMON
2788         system call support.
2789
2790 Wed Apr 10 09:51:38 1996  James G. Smith  <jsmith@cygnus.co.uk>
2791
2792         * interp.c (sim_do_command): Complain if callback structure not
2793         initialised.
2794
2795 Thu Mar 28 13:50:51 1996  James G. Smith  <jsmith@cygnus.co.uk>
2796
2797         * interp.c (Convert): Provide round-to-nearest and round-to-zero
2798         support for Sun hosts.
2799         * Makefile.in (gencode): Ensure the host compiler and libraries
2800         used for cross-hosted build.
2801
2802 Wed Mar 27 14:42:12 1996  James G. Smith  <jsmith@cygnus.co.uk>
2803
2804         * interp.c, gencode.c: Some more (TODO) tidying.
2805
2806 Thu Mar  7 11:19:33 1996  James G. Smith  <jsmith@cygnus.co.uk>
2807
2808         * gencode.c, interp.c: Replaced explicit long long references with
2809         WORD64HI, WORD64LO, SET64HI and SET64LO macro calls.
2810         * support.h (SET64LO, SET64HI): Macros added.
2811
2812 Wed Feb 21 12:16:21 1996  Ian Lance Taylor  <ian@cygnus.com>
2813
2814         * configure: Regenerate with autoconf 2.7.
2815
2816 Tue Jan 30 08:48:18 1996  Fred Fish  <fnf@cygnus.com>
2817
2818         * interp.c (LoadMemory): Enclose text following #endif in /* */.
2819         * support.h: Remove superfluous "1" from #if.
2820         * support.h (CHECKSIM): Remove stray 'a' at end of line.
2821
2822 Mon Dec  4 11:44:40 1995  Jamie Smith  <jsmith@cygnus.com>
2823
2824         * interp.c (StoreFPR): Control UndefinedResult() call on
2825         WARN_RESULT manifest.
2826
2827 Fri Dec  1 16:37:19 1995  James G. Smith  <jsmith@cygnus.co.uk>
2828
2829         * gencode.c: Tidied instruction decoding, and added FP instruction
2830         support.
2831
2832         * interp.c: Added dineroIII, and BSD profiling support. Also
2833         run-time FP handling.
2834
2835 Sun Oct 22 00:57:18 1995  James G. Smith  <jsmith@pasanda.cygnus.co.uk>
2836
2837         * Changelog, Makefile.in, README.Cygnus, configure, configure.in,
2838         gencode.c, interp.c, support.h: created.