sim/mips/ChangeLog

   1 2002-06-12  Chris Demetriou  <cgd@broadcom.com>
   2
   3         * mips.igen: Fix formatting of function calls in
   4         many FP operations.
   5
   6 2002-06-12  Chris Demetriou  <cgd@broadcom.com>
   7
   8         * mips.igen (MOVN, MOVZ): Trace result.
   9         (TNEI): Print "tnei" as the opcode name in traces.
  10         (CEIL.W): Add disassembly string for traces.
  11         (RSQRT.fmt): Make location of disassembly string consistent
  12         with other instructions.
  13
  14 2002-06-12  Chris Demetriou  <cgd@broadcom.com>
  15
  16         * mips.igen (X): Delete unused function.
  17
  18 2002-06-08  Andrew Cagney  <cagney@redhat.com>
  19
  20         * interp.c: Include "gdb/callback.h" and "gdb/remote-sim.h".
  21
  22 2002-06-07  Chris Demetriou  <cgd@broadcom.com>
  23             Ed Satterthwaite  <ehs@broadcom.com>
  24
  25         * cp1.c (inner_mac, fp_mac, inner_rsqrt, fp_inv_sqrt)
  26         (fp_rsqrt, fp_madd, fp_msub, fp_nmadd, fp_nmsub): New functions.
  27         * sim-main.h (fp_rsqrt, fp_madd, fp_msub, fp_nmadd)
  28         (fp_nmsub): New prototypes.
  29         (RSquareRoot, MultiplyAdd, MultiplySub, NegMultiplyAdd)
  30         (NegMultiplySub): New defines.
  31         * mips.igen (RSQRT.fmt): Use RSquareRoot().
  32         (MADD.D, MADD.S): Replace with...
  33         (MADD.fmt): New instruction.
  34         (MSUB.D, MSUB.S): Replace with...
  35         (MSUB.fmt): New instruction.
  36         (NMADD.D, NMADD.S): Replace with...
  37         (NMADD.fmt): New instruction.
  38         (NMSUB.D, MSUB.S): Replace with...
  39         (NMSUB.fmt): New instruction.
  40
  41 2002-06-07  Chris Demetriou  <cgd@broadcom.com>
  42             Ed Satterthwaite  <ehs@broadcom.com>
  43
  44         * cp1.c: Fix more comment spelling and formatting.
  45         (value_fcr, store_fcr): Use fenr_FS rather than hard-coding value.
  46         (denorm_mode): New function.
  47         (fpu_unary, fpu_binary): Round results after operation, collect
  48         status from rounding operations, and update the FCSR.
  49         (convert): Collect status from integer conversions and rounding
  50         operations, and update the FCSR.  Adjust NaN values that result
  51         from conversions.  Convert to use sim_io_eprintf rather than
  52         fprintf, and remove some debugging code.
  53         * cp1.h (fenr_FS): New define.
  54
  55 2002-06-07  Chris Demetriou  <cgd@broadcom.com>
  56
  57         * cp1.c (convert): Remove unusable debugging code, and move MIPS
  58         rounding mode to sim FP rounding mode flag conversion code into...
  59         (rounding_mode): New function.
  60
  61 2002-06-07  Chris Demetriou  <cgd@broadcom.com>
  62
  63         * cp1.c: Clean up formatting of a few comments.
  64         (value_fpr): Reformat switch statement.
  65
  66 2002-06-06  Chris Demetriou  <cgd@broadcom.com>
  67             Ed Satterthwaite  <ehs@broadcom.com>
  68
  69         * cp1.h: New file.
  70         * sim-main.h: Include cp1.h.
  71         (SETFCC, GETFCC, IR, UF, OF, DX, IO, UO, FP_FLAGS, FP_ENABLE)
  72         (FP_CAUSE, GETFS, FP_RM_NEAREST, FP_RM_TOZERO, FP_RM_TOPINF)
  73         (FP_RM_TOMINF, GETRM): Remove.  Moved to cp1.h.
  74         (FP_FS, FP_MASK_RM, FP_SH_RM, Nan, Less, Equal): Remove.
  75         (value_fcr, store_fcr, test_fcsr, fp_cmp): New prototypes.
  76         (ValueFCR, StoreFCR, TestFCSR, Compare): New macros.
  77         * cp1.c: Don't include sim-fpu.h; already included by
  78         sim-main.h.  Clean up formatting of some comments.
  79         (NaN, Equal, Less): Remove.
  80         (test_fcsr, value_fcr, store_fcr, update_fcsr, fp_test)
  81         (fp_cmp): New functions.
  82         * mips.igen (do_c_cond_fmt): Remove.
  83         (C.cond.fmta, C.cond.fmtb): Replace uses of do_c_cond_fmt_a with
  84         Compare.  Add result tracing.
  85         (CxC1): Remove, replace with...
  86         (CFC1a, CFC1b, CFC1c, CTC1a, CTC1b, CTC1c): New instructions.
  87         (DMxC1): Remove, replace with...
  88         (DMFC1a, DMFC1b, DMTC1a, DMTC1b): New instructions.
  89         (MxC1): Remove, replace with...
  90         (MFC1a, MFC1b, MTC1a, MTC1b): New instructions.
  91
  92 2002-06-04  Chris Demetriou  <cgd@broadcom.com>
  93
  94         * sim-main.h (FGRIDX): Remove, replace all uses with...
  95         (FGR_BASE): New macro.
  96         (FP0_REGNUM, FCRCS_REGNUM, FCRIR_REGNUM): New macros.
  97         (_sim_cpu): Move 'fgr' member to be right before 'fpr_state' member.
  98         (NR_FGR, FGR): Likewise.
  99         * interp.c: Replace all uses of FGRIDX with FGR_BASE.
 100         * mips.igen: Likewise.
 101
 102 2002-06-04  Chris Demetriou  <cgd@broadcom.com>
 103
 104         * cp1.c: Add an FSF Copyright notice to this file.
 105
 106 2002-06-04  Chris Demetriou  <cgd@broadcom.com>
 107             Ed Satterthwaite  <ehs@broadcom.com>
 108
 109         * cp1.c (Infinity): Remove.
 110         * sim-main.h (Infinity): Likewise.
 111
 112         * cp1.c (fp_unary, fp_binary): New functions.
 113         (fp_abs, fp_neg, fp_add, fp_sub, fp_mul, fp_div, fp_recip)
 114         (fp_sqrt): New functions, implemented in terms of the above.
 115         (AbsoluteValue, Negate, Add, Sub, Multiply, Divide)
 116         (Recip, SquareRoot): Remove (replaced by functions above).
 117         * sim-main.h (fp_abs, fp_neg, fp_add, fp_sub, fp_mul, fp_div)
 118         (fp_recip, fp_sqrt): New prototypes.
 119         (AbsoluteValue, Negate, Add, Sub, Multiply, Divide)
 120         (Recip, SquareRoot): Replace prototypes with #defines which
 121         invoke the functions above.
 122
 123 2002-06-03  Chris Demetriou  <cgd@broadcom.com>
 124
 125         * sim-main.h (Nan, Infinity, Less, Equal, AbsoluteValue, Negate)
 126         (Add, Sub, Multiply, Divide, Recip, SquareRoot): Move lower in
 127         file, remove PARAMS from prototypes.
 128         (value_fpr, store_fpr, convert): Likewise.  Use SIM_STATE to provide
 129         simulator state arguments.
 130         (ValueFPR, StoreFPR, Convert): Move lower in file.  Use SIM_ARGS to
 131         pass simulator state arguments.
 132         * cp1.c (SD): Redefine as CPU_STATE(cpu).
 133         (store_fpr, convert): Remove 'sd' argument.
 134         (value_fpr): Likewise.  Convert to use 'SD' instead.
 135
 136 2002-06-03  Chris Demetriou  <cgd@broadcom.com>
 137
 138         * cp1.c (Min, Max): Remove #if 0'd functions.
 139         * sim-main.h (Min, Max): Remove.
 140
 141 2002-06-03  Chris Demetriou  <cgd@broadcom.com>
 142
 143         * cp1.c: fix formatting of switch case and default labels.
 144         * interp.c: Likewise.
 145         * sim-main.c: Likewise.
 146
 147 2002-06-03  Chris Demetriou  <cgd@broadcom.com>
 148
 149         * cp1.c: Clean up comments which describe FP formats.
 150          (FPQNaN_DOUBLE, FPQNaN_LONG): Generate using UNSIGNED64.
 151
 152 2002-06-03  Chris Demetriou  <cgd@broadcom.com>
 153             Ed Satterthwaite  <ehs@broadcom.com>
 154
 155         * configure.in (mipsisa64sb1*-*-*): New target for supporting
 156         Broadcom SiByte SB-1 processor configurations.
 157         * configure: Regenerate.
 158         * sb1.igen: New file.
 159         * mips.igen: Include sb1.igen.
 160         (sb1): New model.
 161         * Makefile.in (IGEN_INCLUDE): Add sb1.igen.
 162         * mdmx.igen: Add "sb1" model to all appropriate functions and
 163         instructions.
 164         * mdmx.c (AbsDiffOB, AvgOB, AccAbsDiffOB): New functions.
 165         (ob_func, ob_acc): Reference the above.
 166         (qh_acc): Adjust to keep the same size as ob_acc.
 167         * sim-main.h (status_SBX, MX_VECT_ABSD, MX_VECT_AVG, MX_AbsDiff)
 168         (MX_Avg, MX_VECT_ABSDA, MX_AbsDiffC): New macros.
 169
 170 2002-06-03  Chris Demetriou  <cgd@broadcom.com>
 171
 172         * Makefile.in (IGEN_INCLUDE): Add mdmx.igen.
 173
 174 2002-06-02  Chris Demetriou  <cgd@broadcom.com>
 175             Ed Satterthwaite  <ehs@broadcom.com>
 176
 177         * mips.igen (mdmx): New (pseudo-)model.
 178         * mdmx.c, mdmx.igen: New files.
 179         * Makefile.in (SIM_OBJS): Add mdmx.o.
 180         * sim-main.h (MDMX_accumulator, MX_fmtsel, signed24, signed48):
 181         New typedefs.
 182         (ACC, MX_Add, MX_AddA, MX_AddL, MX_And, MX_C_EQ, MX_C_LT, MX_Comp)
 183         (MX_FMT_OB, MX_FMT_QH, MX_Max, MX_Min, MX_Msgn, MX_Mul, MX_MulA)
 184         (MX_MulL, MX_MulS, MX_MulSL, MX_Nor, MX_Or, MX_Pick, MX_RAC)
 185         (MX_RAC_H, MX_RAC_L, MX_RAC_M, MX_RNAS, MX_RNAU, MX_RND_AS)
 186         (MX_RND_AU, MX_RND_ES, MX_RND_EU, MX_RND_ZS, MX_RND_ZU, MX_RNES)
 187         (MX_RNEU, MX_RZS, MX_RZU, MX_SHFL, MX_ShiftLeftLogical)
 188         (MX_ShiftRightArith, MX_ShiftRightLogical, MX_Sub, MX_SubA, MX_SubL)
 189         (MX_VECT_ADD, MX_VECT_ADDA, MX_VECT_ADDL, MX_VECT_AND)
 190         (MX_VECT_MAX, MX_VECT_MIN, MX_VECT_MSGN, MX_VECT_MUL, MX_VECT_MULA)
 191         (MX_VECT_MULL, MX_VECT_MULS, MX_VECT_MULSL, MX_VECT_NOR)
 192         (MX_VECT_OR, MX_VECT_SLL, MX_VECT_SRA, MX_VECT_SRL, MX_VECT_SUB)
 193         (MX_VECT_SUBA, MX_VECT_SUBL, MX_VECT_XOR, MX_WACH, MX_WACL, MX_Xor)
 194         (SIM_ARGS, SIM_STATE, UnpredictableResult, fmt_mdmx, ob_fmtsel)
 195         (qh_fmtsel): New macros.
 196         (_sim_cpu): New member "acc".
 197         (mdmx_acc_op, mdmx_cc_op, mdmx_cpr_op, mdmx_pick_op, mdmx_rac_op)
 198         (mdmx_round_op, mdmx_shuffle, mdmx_wach, mdmx_wacl): New functions.
 199
 200 2002-05-01  Chris Demetriou  <cgd@broadcom.com>
 201
 202         * interp.c: Use 'deprecated' rather than 'depreciated.'
 203         * sim-main.h: Likewise.
 204
 205 2002-05-01  Chris Demetriou  <cgd@broadcom.com>
 206
 207         * cp1.c (store_fpr): Remove #ifdef'd out call to UndefinedResult
 208         which wouldn't compile anyway.
 209         * sim-main.h (unpredictable_action): New function prototype.
 210         (Unpredictable): Define to call igen function unpredictable().
 211         (NotWordValue): New macro to call igen function not_word_value().
 212         (UndefinedResult): Remove.
 213         * interp.c (undefined_result): Remove.
 214         (unpredictable_action): New function.
 215         * mips.igen (not_word_value, unpredictable): New functions.
 216         (ADD, ADDI, do_addiu, do_addu, BGEZAL, BGEZALL, BLTZAL, BLTZALL)
 217         (CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, do_mult, do_multu)
 218         (do_sra, do_srav, do_srl, do_srlv, SUB, do_subu): Invoke
 219         NotWordValue() to check for unpredictable inputs, then
 220         Unpredictable() to handle them.
 221
 222 2002-02-24  Chris Demetriou  <cgd@broadcom.com>
 223
 224         * mips.igen: Fix formatting of calls to Unpredictable().
 225
 226 2002-04-20  Andrew Cagney  <ac131313@redhat.com>
 227
 228         * interp.c (sim_open): Revert previous change.
 229
 230 2002-04-18  Alexandre Oliva  <aoliva@redhat.com>
 231
 232         * interp.c (sim_open): Disable chunk of code that wrote code in
 233         vector table entries.
 234
 235 2002-03-19  Chris Demetriou  <cgd@broadcom.com>
 236
 237         * cp1.c (FP_S_s, FP_D_s, FP_S_be, FP_D_be, FP_S_e, FP_D_e, FP_S_f)
 238         (FP_D_f, FP_S_fb, FP_D_fb, FPINF_SINGLE, FPINF_DOUBLE): Remove
 239         unused definitions.
 240
 241 2002-03-19  Chris Demetriou  <cgd@broadcom.com>
 242
 243         * cp1.c: Fix many formatting issues.
 244
 245 2002-03-19  Chris G. Demetriou  <cgd@broadcom.com>
 246
 247         * cp1.c (fpu_format_name): New function to replace...
 248         (DOFMT): This.  Delete, and update all callers.
 249         (fpu_rounding_mode_name): New function to replace...
 250         (RMMODE): This.  Delete, and update all callers.
 251
 252 2002-03-19  Chris G. Demetriou  <cgd@broadcom.com>
 253
 254         * interp.c: Move FPU support routines from here to...
 255         * cp1.c: Here.  New file.
 256         * Makefile.in (SIM_OBJS): Add cp1.o to object list.
 257         (cp1.o): New target.
 258
 259 2002-03-12  Chris Demetriou  <cgd@broadcom.com>
 260
 261         * configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
 262         * mips.igen (mips32, mips64): New models, add to all instructions
 263         and functions as appropriate.
 264         (loadstore_ea, check_u64): New variant for model mips64.
 265         (check_fmt_p): New variant for models mipsV and mips64, remove
 266         mipsV model marking fro other variant.
 267         (SLL) Rename to...
 268         (SLLa) this.
 269         (CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
 270         for mips32 and mips64.
 271         (DCLO, DCLZ): New instructions for mips64.
 272
 273 2002-03-07  Chris Demetriou  <cgd@broadcom.com>
 274
 275         * mips.igen (BREAK, LUI, ORI, SYSCALL, XORI): Print
 276         immediate or code as a hex value with the "%#lx" format.
 277         (ANDI): Likewise, and fix printed instruction name.
 278
 279 2002-03-05  Chris Demetriou  <cgd@broadcom.com>
 280
 281         * sim-main.h (UndefinedResult, Unpredictable): New macros
 282         which currently do nothing.
 283
 284 2002-03-05  Chris Demetriou  <cgd@broadcom.com>
 285
 286         * sim-main.h (status_UX, status_SX, status_KX, status_TS)
 287         (status_PX, status_MX, status_CU0, status_CU1, status_CU2)
 288         (status_CU3): New definitions.
 289
 290         * sim-main.h (ExceptionCause): Add new values for MIPS32
 291         and MIPS64: MDMX, MCheck, CacheErr.  Update comments
 292         for DebugBreakPoint and NMIReset to note their status in
 293         MIPS32 and MIPS64.
 294         (SignalExceptionMDMX, SignalExceptionWatch, SignalExceptionMCheck)
 295         (SignalExceptionCacheErr): New exception macros.
 296
 297 2002-03-05  Chris Demetriou  <cgd@broadcom.com>
 298
 299         * mips.igen (check_fpu): Enable check for coprocessor 1 usability.
 300         * sim-main.h (COP_Usable): Define, but for now coprocessor 1
 301         is always enabled.
 302         (SignalExceptionCoProcessorUnusable): Take as argument the
 303         unusable coprocessor number.
 304
 305 2002-03-05  Chris Demetriou  <cgd@broadcom.com>
 306
 307         * mips.igen: Fix formatting of all SignalException calls.
 308
 309 2002-03-05  Chris Demetriou  <cgd@broadcom.com>
 310
 311         * sim-main.h (SIGNEXTEND): Remove.
 312
 313 2002-03-04  Chris Demetriou  <cgd@broadcom.com>
 314
 315         * mips.igen: Remove gencode comment from top of file, fix
 316         spelling in another comment.
 317
 318 2002-03-04  Chris Demetriou  <cgd@broadcom.com>
 319
 320         * mips.igen (check_fmt, check_fmt_p): New functions to check
 321         whether specific floating point formats are usable.
 322         (ABS.fmt, ADD.fmt, CEIL.L.fmt, CEIL.W, DIV.fmt, FLOOR.L.fmt)
 323         (FLOOR.W.fmt, MOV.fmt, MUL.fmt, NEG.fmt, RECIP.fmt, ROUND.L.fmt)
 324         (ROUND.W.fmt, RSQRT.fmt, SQRT.fmt, SUB.fmt, TRUNC.L.fmt, TRUNC.W):
 325         Use the new functions.
 326         (do_c_cond_fmt): Remove format checks...
 327         (C.cond.fmta, C.cond.fmtb): And move them into all callers.
 328
 329 2002-03-03  Chris Demetriou  <cgd@broadcom.com>
 330
 331         * mips.igen: Fix formatting of check_fpu calls.
 332
 333 2002-03-03  Chris Demetriou  <cgd@broadcom.com>
 334
 335         * mips.igen (FLOOR.L.fmt): Store correct destination register.
 336
 337 2002-03-03  Chris Demetriou  <cgd@broadcom.com>
 338
 339         * mips.igen: Remove whitespace at end of lines.
 340
 341 2002-03-02  Chris Demetriou  <cgd@broadcom.com>
 342
 343         * mips.igen (loadstore_ea): New function to do effective
 344         address calculations.
 345         (do_load, do_load_left, do_load_right, LL, LDD, PREF, do_store,
 346         do_store_left, do_store_right, SC, SCD, PREFX, SWC1, SWXC1,
 347         CACHE): Use loadstore_ea to do effective address computations.
 348
 349 2002-03-02  Chris Demetriou  <cgd@broadcom.com>
 350
 351         * interp.c (load_word): Use EXTEND32 rather than SIGNEXTEND.
 352         * mips.igen (LL, CxC1, MxC1): Likewise.
 353
 354 2002-03-02  Chris Demetriou  <cgd@broadcom.com>
 355
 356         * mips.igen (LL, LLD, PREF, SC, SCD, ABS.fmt, ADD.fmt, CEIL.L.fmt,
 357         CEIL.W, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt, CVT.W.fmt, DIV.fmt,
 358         FLOOR.L.fmt, FLOOR.W.fmt, MADD.D, MADD.S, MOV.fmt, MOVtf.fmt,
 359         MSUB.D, MSUB.S, MUL.fmt, NEG.fmt, NMADD.D, NMADD.S, NMSUB.D,
 360         NMSUB.S, PREFX, RECIP.fmt, ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt,
 361         SQRT.fmt, SUB.fmt, SWC1, SWXC1, TRUNC.L.fmt, TRUNC.W, CACHE):
 362         Don't split opcode fields by hand, use the opcode field values
 363         provided by igen.
 364
 365 2002-03-01  Chris Demetriou  <cgd@broadcom.com>
 366
 367         * mips.igen (do_divu): Fix spacing.
 368
 369         * mips.igen (do_dsllv): Move to be right before DSLLV,
 370         to match the rest of the do_<shift> functions.
 371
 372 2002-03-01  Chris Demetriou  <cgd@broadcom.com>
 373
 374         * mips.igen (do_dsll, do_dsllv, DSLL32, do_dsra, DSRA32, do_dsrl,
 375         DSRL32, do_dsrlv): Trace inputs and results.
 376
 377 2002-03-01  Chris Demetriou  <cgd@broadcom.com>
 378
 379         * mips.igen (CACHE): Provide instruction-printing string.
 380
 381         * interp.c (signal_exception): Comment tokens after #endif.
 382
 383 2002-02-28  Chris Demetriou  <cgd@broadcom.com>
 384
 385         * mips.igen (LWXC1): Mark with filter "64,f", rather than just "32".
 386         (MOVtf, MxC1, MxC1, DMxC1, DMxC1, CxC1, CxC1, SQRT.fmt, MOV.fmt,
 387         NEG.fmt, ROUND.L.fmt, TRUNC.L.fmt, CEIL.L.fmt, FLOOR.L.fmt,
 388         ROUND.W.fmt, TRUNC.W, CEIL.W, FLOOR.W.fmt, RECIP.fmt, RSQRT.fmt,
 389         CVT.S.fmt, CVT.D.fmt, CVT.W.fmt, CVT.L.fmt, MOVtf.fmt, C.cond.fmta,
 390         C.cond.fmtb, SUB.fmt, MUL.fmt, DIV.fmt, MOVZ.fmt, MOVN.fmt, LDXC1,
 391         SWXC1, SDXC1, MSUB.D, MSUB.S, NMADD.S, NMADD.D, NMSUB.S, NMSUB.D,
 392         LWC1, SWC1): Add "f" to filter, since these are FP instructions.
 393
 394 2002-02-28  Chris Demetriou  <cgd@broadcom.com>
 395
 396         * mips.igen (DSRA32, DSRAV): Fix order of arguments in
 397         instruction-printing string.
 398         (LWU): Use '64' as the filter flag.
 399
 400 2002-02-28  Chris Demetriou  <cgd@broadcom.com>
 401
 402         * mips.igen (SDXC1): Fix instruction-printing string.
 403
 404 2002-02-28  Chris Demetriou  <cgd@broadcom.com>
 405
 406         * mips.igen (LDC1, SDC1): Remove mipsI model, and mark with
 407         filter flags "32,f".
 408
 409 2002-02-27  Chris Demetriou  <cgd@broadcom.com>
 410
 411         * mips.igen (PREFX): This is a 64-bit instruction, use '64'
 412         as the filter flag.
 413
 414 2002-02-27  Chris Demetriou  <cgd@broadcom.com>
 415
 416         * mips.igen (PREFX): Tweak instruction opcode fields (i.e.,
 417         add a comma) so that it more closely match the MIPS ISA
 418         documentation opcode partitioning.
 419         (PREF): Put useful names on opcode fields, and include
 420         instruction-printing string.
 421
 422 2002-02-27  Chris Demetriou  <cgd@broadcom.com>
 423
 424         * mips.igen (check_u64): New function which in the future will
 425         check whether 64-bit instructions are usable and signal an
 426         exception if not.  Currently a no-op.
 427         (DADD, DADDI, DADDIU, DADDU, DDIV, DDIVU, DMULT, DMULTU, DSLL,
 428         DSLL32, DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB,
 429         DSUBU, LD, LDL, LDR, LLD, LWU, SCD, SD, SDL, SDR, DMxC1, LDXC1,
 430         LWXC1, SDXC1, SWXC1, DMFC0, DMTC0): Use check_u64.
 431
 432         * mips.igen (check_fpu): New function which in the future will
 433         check whether FPU instructions are usable and signal an exception
 434         if not.  Currently a no-op.
 435         (ABS.fmt, ADD.fmt, BC1a, BC1b, C.cond.fmta, C.cond.fmtb,
 436         CEIL.L.fmt, CEIL.W, CxC1, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt,
 437         CVT.W.fmt, DIV.fmt, DMxC1, DMxC1, FLOOR.L.fmt, FLOOR.W.fmt, LDC1,
 438         LDXC1, LWC1, LWXC1, MADD.D, MADD.S, MxC1, MOV.fmt, MOVtf,
 439         MOVtf.fmt, MOVN.fmt, MOVZ.fmt, MSUB.D, MSUB.S, MUL.fmt, NEG.fmt,
 440         NMADD.D, NMADD.S, NMSUB.D, NMSUB.S, RECIP.fmt, ROUND.L.fmt,
 441         ROUND.W.fmt, RSQRT.fmt, SDC1, SDXC1, SQRT.fmt, SUB.fmt, SWC1,
 442         SWXC1, TRUNC.L.fmt, TRUNC.W): Use check_fpu.
 443
 444 2002-02-27  Chris Demetriou  <cgd@broadcom.com>
 445
 446         * mips.igen (do_load_left, do_load_right): Move to be immediately
 447         following do_load.
 448         (do_store_left, do_store_right): Move to be immediately following
 449         do_store.
 450
 451 2002-02-27  Chris Demetriou  <cgd@broadcom.com>
 452
 453         * mips.igen (mipsV): New model name.  Also, add it to
 454         all instructions and functions where it is appropriate.
 455
 456 2002-02-18  Chris Demetriou  <cgd@broadcom.com>
 457
 458         * mips.igen: For all functions and instructions, list model
 459         names that support that instruction one per line.
 460
 461 2002-02-11  Chris Demetriou  <cgd@broadcom.com>
 462
 463         * mips.igen: Add some additional comments about supported
 464         models, and about which instructions go where.
 465         (BC1b, MFC0, MTC0, RFE): Sort supported models in the same
 466         order as is used in the rest of the file.
 467
 468 2002-02-11  Chris Demetriou  <cgd@broadcom.com>
 469
 470         * mips.igen (ADD, ADDI, DADDI, DSUB, SUB): Add comment
 471         indicating that ALU32_END or ALU64_END are there to check
 472         for overflow.
 473         (DADD): Likewise, but also remove previous comment about
 474         overflow checking.
 475
 476 2002-02-10  Chris Demetriou  <cgd@broadcom.com>
 477
 478         * mips.igen (DDIV, DIV, DIVU, DMULT, DMULTU, DSLL, DSLL32,
 479         DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB, DSUBU,
 480         JALR, JR, MOVN, MOVZ, MTLO, MULT, MULTU, SLL, SLLV, SLT, SLTU,
 481         SRAV, SRLV, SUB, SUBU, SYNC, XOR, MOVtf, DI, DMFC0, DMTC0, EI,
 482         ERET, RFE, TLBP, TLBR, TLBWI, TLBWR): Tweak instruction opcode
 483         fields (i.e., add and move commas) so that they more closely
 484         match the MIPS ISA documentation opcode partitioning.
 485
 486 2002-02-10  Chris Demetriou  <cgd@broadcom.com>
 487
 488         * mips.igen (ADDI): Print immediate value.
 489         (BREAK): Print code.
 490         (DADDIU, DSRAV, DSRLV): Print correct instruction name.
 491         (SLL): Print "nop" specially, and don't run the code
 492         that does the shift for the "nop" case.
 493
 494 2001-11-17  Fred Fish  <fnf@redhat.com>
 495
 496         * sim-main.h (float_operation): Move enum declaration outside
 497         of _sim_cpu struct declaration.
 498
 499 2001-04-12  Jim Blandy  <jimb@redhat.com>
 500
 501         * mips.igen (CFC1, CTC1): Pass the correct register numbers to
 502         PENDING_FILL.  Use PENDING_SCHED directly to handle the pending
 503         set of the FCSR.
 504         * sim-main.h (COCIDX): Remove definition; this isn't supported by
 505         PENDING_FILL, and you can get the intended effect gracefully by
 506         calling PENDING_SCHED directly.
 507
 508 2001-02-23  Ben Elliston  <bje@redhat.com>
 509
 510         * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Only define if not
 511         already defined elsewhere.
 512
 513 2001-02-19  Ben Elliston  <bje@redhat.com>
 514
 515         * sim-main.h (sim_monitor): Return an int.
 516         * interp.c (sim_monitor): Add return values.
 517         (signal_exception): Handle error conditions from sim_monitor.
 518
 519 2001-02-08  Ben Elliston  <bje@redhat.com>
 520
 521         * sim-main.c (load_memory): Pass cia to sim_core_read* functions.
 522         (store_memory): Likewise, pass cia to sim_core_write*.
 523
 524 2000-10-19  Frank Ch. Eigler  <fche@redhat.com>
 525
 526         On advice from Chris G. Demetriou <cgd@sibyte.com>:
 527         * sim-main.h (GPR_CLEAR): Remove unused alternative macro.
 528
 529 Thu Jul 27 22:02:05 2000  Andrew Cagney  <cagney@b1.cygnus.com>
 530
 531         From Maciej W. Rozycki <macro@ds2.pg.gda.pl>:
 532         * Makefile.in: Don't delete *.igen when cleaning directory.
 533
 534 Wed Jul 19 18:50:51 2000  Andrew Cagney  <cagney@b1.cygnus.com>
 535
 536         * m16.igen (break): Call SignalException not sim_engine_halt.
 537
 538 Mon Jul  3 11:13:20 2000  Andrew Cagney  <cagney@b1.cygnus.com>
 539
 540         From Jason Eckhardt:
 541         * mips.igen (MOVZ.fmt, MOVN.fmt): Move conditional on GPR[RT].
 542
 543 Tue Jun 13 20:52:07 2000  Andrew Cagney  <cagney@b1.cygnus.com>
 544
 545         * mips.igen (MxC1, DMxC1): Fix printf formatting.
 546
 547 2000-05-24  Michael Hayes  <mhayes@cygnus.com>
 548
 549         * mips.igen (do_dmultx): Fix typo.
 550
 551 Tue May 23 21:39:23 2000  Andrew Cagney  <cagney@b1.cygnus.com>
 552
 553         * configure: Regenerated to track ../common/aclocal.m4 changes.
 554
 555 Fri Apr 28 20:48:36 2000  Andrew Cagney  <cagney@b1.cygnus.com>
 556
 557         * mips.igen (DMxC1): Fix format arguments for sim_io_eprintf call.
 558
 559 2000-04-12  Frank Ch. Eigler  <fche@redhat.com>
 560
 561         * sim-main.h (GPR_CLEAR): Define macro.
 562
 563 Mon Apr 10 00:07:09 2000  Andrew Cagney  <cagney@b1.cygnus.com>
 564
 565         * interp.c (decode_coproc): Output long using %lx and not %s.
 566
 567 2000-03-21  Frank Ch. Eigler  <fche@redhat.com>
 568
 569         * interp.c (sim_open): Sort & extend dummy memory regions for
 570         --board=jmr3904 for eCos.
 571
 572 2000-03-02  Frank Ch. Eigler  <fche@redhat.com>
 573
 574         * configure: Regenerated.
 575
 576 Tue Feb  8 18:35:01 2000  Donald Lindsay  <dlindsay@hound.cygnus.com>
 577
 578         * interp.c, mips.igen: all 5 DEADC0DE situations now have sim_io_eprintf
 579         calls, conditional on the simulator being in verbose mode.
 580
 581 Fri Feb  4 09:45:15 2000  Donald Lindsay  <dlindsay@cygnus.com>
 582
 583         * sim-main.c (cache_op): Added case arm so that CACHE ops to a secondary
 584         cache don't get ReservedInstruction traps.
 585
 586 1999-11-29  Mark Salter  <msalter@cygnus.com>
 587
 588         * dv-tx3904sio.c (tx3904sio_io_write_buffer): Use write value as a mask
 589         to clear status bits in sdisr register. This is how the hardware works.
 590
 591         * interp.c (sim_open): Added more memory aliases for jmr3904 hardware
 592         being used by cygmon.
 593
 594 1999-11-11  Andrew Haley  <aph@cygnus.com>
 595
 596         * interp.c (decode_coproc): Correctly handle DMFC0 and DMTC0
 597         instructions.
 598
 599 Thu Sep  9 15:12:08 1999  Geoffrey Keating  <geoffk@cygnus.com>
 600
 601         * mips.igen (MULT): Correct previous mis-applied patch.
 602
 603 Tue Sep  7 13:34:54 1999  Geoffrey Keating  <geoffk@cygnus.com>
 604
 605         * mips.igen (delayslot32): Handle sequence like
 606         mtc1 $at,$f12 ; jal fp_add ; mov.s $f13,$f12
 607         correctly by calling ENGINE_ISSUE_PREFIX_HOOK() before issue.
 608         (MULT): Actually pass the third register...
 609
 610 1999-09-03  Mark Salter  <msalter@cygnus.com>
 611
 612         * interp.c (sim_open): Added more memory aliases for additional
 613         hardware being touched by cygmon on jmr3904 board.
 614
 615 Thu Sep  2 18:15:53 1999  Andrew Cagney  <cagney@b1.cygnus.com>
 616
 617         * configure: Regenerated to track ../common/aclocal.m4 changes.
 618
 619 Tue Jul 27 16:36:51 1999  Andrew Cagney  <cagney@amy.cygnus.com>
 620
 621         * interp.c (sim_store_register): Handle case where client - GDB -
 622         specifies that a 4 byte register is 8 bytes in size.
 623         (sim_fetch_register): Ditto.
 624
 625 1999-07-14  Frank Ch. Eigler  <fche@cygnus.com>
 626
 627         Implement "sim firmware" option, inspired by jimb's version of 1998-01.
 628         * interp.c (firmware_option_p): New global flag: "sim firmware" given.
 629         (idt_monitor_base): Base address for IDT monitor traps.
 630         (pmon_monitor_base): Ditto for PMON.
 631         (lsipmon_monitor_base): Ditto for LSI PMON.
 632         (MONITOR_BASE, MONITOR_SIZE): Removed macros.
 633         (mips_option): Add "firmware" option with new OPTION_FIRMWARE key.
 634         (sim_firmware_command): New function.
 635         (mips_option_handler): Call it for OPTION_FIRMWARE.
 636         (sim_open): Allocate memory for idt_monitor region.  If "--board"
 637         option was given, add no monitor by default.  Add BREAK hooks only if
 638         monitors are also there.
 639
 640 Mon Jul 12 00:02:27 1999  Andrew Cagney  <cagney@amy.cygnus.com>
 641
 642         * interp.c (sim_monitor): Flush output before reading input.
 643
 644 Sun Jul 11 19:28:11 1999  Andrew Cagney  <cagney@b1.cygnus.com>
 645
 646         * tconfig.in (SIM_HANDLES_LMA): Always define.
 647
 648 Thu Jul  8 16:06:59 1999  Andrew Cagney  <cagney@b1.cygnus.com>
 649
 650         From Mark Salter <msalter@cygnus.com>:
 651         * interp.c (BOARD_BSP): Define.  Add to list of possible boards.
 652         (sim_open): Add setup for BSP board.
 653
 654 Wed Jul  7 12:45:58 1999  Andrew Cagney  <cagney@b1.cygnus.com>
 655
 656         * mips.igen (MULT, MULTU): Add syntax for two operand version.
 657         (DMFC0, DMTC0): Recognize.  Call DecodeCoproc which will report
 658         them as unimplemented.
 659
 660 1999-05-08  Felix Lee  <flee@cygnus.com>
 661
 662         * configure: Regenerated to track ../common/aclocal.m4 changes.
 663
 664 1999-04-21  Frank Ch. Eigler  <fche@cygnus.com>
 665
 666         * mips.igen (bc0f): For the TX39 only, decode this as a no-op stub.
 667
 668 Thu Apr 15 14:15:17 1999  Andrew Cagney  <cagney@amy.cygnus.com>
 669
 670         * configure.in: Any mips64vr5*-*-* target should have
 671         -DTARGET_ENABLE_FR=1.
 672         (default_endian): Any mips64vr*el-*-* target should default to
 673         LITTLE_ENDIAN.
 674         * configure: Re-generate.
 675
 676 1999-02-19  Gavin Romig-Koch  <gavin@cygnus.com>
 677
 678         * mips.igen (ldl): Extend from _16_, not 32.
 679
 680 Wed Jan 27 18:51:38 1999  Andrew Cagney  <cagney@chook.cygnus.com>
 681
 682         * interp.c (sim_store_register): Force registers written to by GDB
 683         into an un-interpreted state.
 684
 685 1999-02-05  Frank Ch. Eigler  <fche@cygnus.com>
 686
 687         * dv-tx3904sio.c (tx3904sio_tickle): After a polled I/O from the
 688         CPU, start periodic background I/O polls.
 689         (tx3904sio_poll): New function: periodic I/O poller.
 690
 691 1998-12-30  Frank Ch. Eigler  <fche@cygnus.com>
 692
 693         * mips.igen (BREAK): Call signal_exception instead of sim_engine_halt.
 694
 695 Tue Dec 29 16:03:53 1998  Rainer Orth  <ro@TechFak.Uni-Bielefeld.DE>
 696
 697         * configure.in, configure (mips64vr5*-*-*): Added missing ;; in
 698         case statement.
 699
 700 1998-12-29  Frank Ch. Eigler  <fche@cygnus.com>
 701
 702         * interp.c (sim_open): Allocate jm3904 memory in smaller chunks.
 703         (load_word): Call SIM_CORE_SIGNAL hook on error.
 704         (signal_exception): Call SIM_CPU_EXCEPTION_TRIGGER hook before
 705         starting.  For exception dispatching, pass PC instead of NULL_CIA.
 706         (decode_coproc): Use COP0_BADVADDR to store faulting address.
 707         * sim-main.h (COP0_BADVADDR): Define.
 708         (SIM_CORE_SIGNAL): Define hook to call mips_core_signal.
 709         (SIM_CPU_EXCEPTION*): Define hooks to call mips_cpu_exception*().
 710         (_sim_cpu): Add exc_* fields to store register value snapshots.
 711         * mips.igen (*): Replace memory-related SignalException* calls
 712         with references to SIM_CORE_SIGNAL hook.
 713
 714         * dv-tx3904irc.c (tx3904irc_port_event): printf format warning
 715         fix.
 716         * sim-main.c (*): Minor warning cleanups.
 717
 718 1998-12-24  Gavin Romig-Koch  <gavin@cygnus.com>
 719
 720         * m16.igen (DADDIU5): Correct type-o.
 721
 722 Mon Dec 21 10:34:48 1998  Andrew Cagney  <cagney@chook>
 723
 724         * mips.igen (do_ddiv, do_ddivu): Pacify GCC. Update hi/lo via tmp
 725         variables.
 726
 727 Wed Dec 16 18:20:28 1998  Andrew Cagney  <cagney@chook>
 728
 729         * Makefile.in (SIM_EXTRA_CFLAGS): No longer need to add .../newlib
 730         to include path.
 731         (interp.o): Add dependency on itable.h
 732         (oengine.c, gencode): Delete remaining references.
 733         (BUILT_SRC_FROM_GEN): Clean up.
 734
 735 1998-12-16  Gavin Romig-Koch  <gavin@cygnus.com>
 736
 737         * vr4run.c: New.
 738         * Makefile.in (SIM_HACK_OBJ,HACK_OBJS,HACK_GEN_SRCS,libhack.a,
 739         tmp-hack,tmp-m32-hack,tmp-m16-hack,tmp-itable-hack,
 740         tmp-run-hack) : New.
 741         * m16.igen (LD,DADDIU,DADDUI5,DADJSP,DADDIUSP,DADDI,DADDU,DSUBU,
 742         DSLL,DSRL,DSRA,DSLLV,DSRAV,DMULT,DMULTU,DDIV,DDIVU,JALX32,JALX):
 743         Drop the "64" qualifier to get the HACK generator working.
 744         Use IMMEDIATE rather than IMMED.  Use SHAMT rather than SHIFT.
 745         * mips.igen (do_daddiu,do_ddiv,do_divu): Remove the 64-only
 746         qualifier to get the hack generator working.
 747         (do_dsll,do_dsllv,do_dsra,do_dsrl,do_dsrlv): New.
 748         (DSLL): Use do_dsll.
 749         (DSLLV): Use do_dsllv.
 750         (DSRA): Use do_dsra.
 751         (DSRL): Use do_dsrl.
 752         (DSRLV): Use do_dsrlv.
 753         (BC1): Move *vr4100 to get the HACK generator working.
 754         (CxC1, DMxC1, MxC1,MACCU,MACCHI,MACCHIU): Rename to
 755         get the HACK generator working.
 756         (MACC) Rename to get the HACK generator working.
 757         (DMACC,MACCS,DMACCS): Add the 64.
 758
 759 1998-12-12  Gavin Romig-Koch  <gavin@cygnus.com>
 760
 761         * mips.igen (BC1): Renamed to BC1a and BC1b to avoid conflicts.
 762         * sim-main.h (SizeFGR): Handle TARGET_ENABLE_FR.
 763
 764 1998-12-11  Gavin Romig-Koch  <gavin@cygnus.com>
 765
 766     * mips/interp.c (DEBUG): Cleanups.
 767
 768 1998-12-10  Frank Ch. Eigler  <fche@cygnus.com>
 769
 770         * dv-tx3904sio.c (tx3904sio_io_read_buffer): Endianness fixes.
 771         (tx3904sio_tickle): fflush after a stdout character output.
 772
 773 1998-12-03  Frank Ch. Eigler  <fche@cygnus.com>
 774
 775         * interp.c (sim_close): Uninstall modules.
 776
 777 Wed Nov 25 13:41:03 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 778
 779         * sim-main.h, interp.c (sim_monitor): Change to global
 780         function.
 781
 782 Wed Nov 25 17:33:24 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 783
 784         * configure.in (vr4100): Only include vr4100 instructions in
 785         simulator.
 786         * configure: Re-generate.
 787         * m16.igen (*): Tag all mips16 instructions as also being vr4100.
 788
 789 Mon Nov 23 18:20:36 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 790
 791         * Makefile.in (SIM_CFLAGS): Do not define WITH_IGEN.
 792         * sim-main.h, sim-main.c, interp.c: Delete #if WITH_IGEN keeping
 793         true alternative.
 794
 795         * configure.in (sim_default_gen, sim_use_gen): Replace with
 796         sim_gen.
 797         (--enable-sim-igen): Delete config option. Always using IGEN.
 798         * configure: Re-generate.
 799
 800         * Makefile.in (gencode): Kill, kill, kill.
 801         * gencode.c: Ditto.
 802
 803 Mon Nov 23 18:07:36 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 804
 805         * configure.in: Configure mips64vr4100-elf nee mips64vr41* as a 64
 806         bit mips16 igen simulator.
 807         * configure: Re-generate.
 808
 809         * mips.igen (check_div_hilo, check_mult_hilo, check_mf_hilo): Mark
 810         as part of vr4100 ISA.
 811         * vr.igen: Mark all instructions as 64 bit only.
 812
 813 Mon Nov 23 17:07:37 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 814
 815         * interp.c (get_cell, sim_monitor, fetch_str, CoProcPresent):
 816         Pacify GCC.
 817
 818 Mon Nov 23 13:23:40 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 819
 820         * configure.in: Configure mips-lsi-elf nee mips*lsi* as a
 821         mipsIII/mips16 igen simulator.  Fix sim_gen VS sim_igen typos.
 822         * configure: Re-generate.
 823
 824         * m16.igen (BREAK): Define breakpoint instruction.
 825         (JALX32): Mark instruction as mips16 and not r3900.
 826         * mips.igen (C.cond.fmt): Fix typo in instruction format.
 827
 828         * sim-main.h (PENDING_FILL): Wrap C statements in do/while.
 829
 830 Sat Nov  7 09:54:38 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 831
 832         * gencode.c (build_instruction - BREAK): For MIPS16, handle BREAK
 833         insn as a debug breakpoint.
 834
 835         * sim-main.h (PENDING_SLOT_BIT): Fix, was incorrectly defined as
 836         pending.slot_size.
 837         (PENDING_SCHED): Clean up trace statement.
 838         (PENDING_SCHED): Increment PENDING_IN and PENDING_TOTAL.
 839         (PENDING_FILL): Delay write by only one cycle.
 840         (PENDING_FILL): For FSRs, write fmt_uninterpreted to FPR_STATE.
 841
 842         * sim-main.c (pending_tick): Clean up trace statements. Add trace
 843         of pending writes.
 844         (pending_tick): Fix sizes in switch statements, 4 & 8 instead of
 845         32 & 64.
 846         (pending_tick): Move incrementing of index to FOR statement.
 847         (pending_tick): Only update PENDING_OUT after a write has occured.
 848
 849         * configure.in: Add explicit mips-lsi-* target.  Use gencode to
 850         build simulator.
 851         * configure: Re-generate.
 852
 853         * interp.c (sim_engine_run OLD): Delete explicit call to
 854         PENDING_TICK. Now called via ENGINE_ISSUE_PREFIX_HOOK.
 855
 856 Sat Oct 30 09:49:10 1998  Frank Ch. Eigler  <fche@cygnus.com>
 857
 858         * dv-tx3904cpu.c (deliver_tx3904cpu_interrupt): Add dummy
 859         interrupt level number to match changed SignalExceptionInterrupt
 860         macro.
 861
 862 Fri Oct  9 18:02:25 1998  Doug Evans  <devans@canuck.cygnus.com>
 863
 864         * interp.c: #include "itable.h" if WITH_IGEN.
 865         (get_insn_name): New function.
 866         (sim_open): Initialize CPU_INSN_NAME,CPU_MAX_INSNS.
 867         * sim-main.h (MAX_INSNS,INSN_NAME): Delete.
 868
 869 Mon Sep 14 12:36:44 1998  Frank Ch. Eigler  <fche@cygnus.com>
 870
 871         * configure: Rebuilt to inhale new common/aclocal.m4.
 872
 873 Tue Sep  1 15:39:18 1998  Frank Ch. Eigler  <fche@cygnus.com>
 874
 875         * dv-tx3904sio.c: Include sim-assert.h.
 876
 877 Tue Aug 25 12:49:46 1998  Frank Ch. Eigler  <fche@cygnus.com>
 878
 879         * dv-tx3904sio.c: New file: tx3904 serial I/O module.
 880         * configure.in: Add dv-tx3904sio, dv-sockser for tx39 target.
 881         Reorganize target-specific sim-hardware checks.
 882         * configure: rebuilt.
 883         * interp.c (sim_open): For tx39 target boards, set
 884         OPERATING_ENVIRONMENT, add tx3904sio devices.
 885         * tconfig.in: For tx39 target, set SIM_HANDLES_LMA for loading
 886         ROM executables.  Install dv-sockser into sim-modules list.
 887
 888         * dv-tx3904irc.c: Compiler warning clean-up.
 889         * dv-tx3904tmr.c: Compiler warning clean-up.  Remove particularly
 890         frequent hw-trace messages.
 891
 892 Fri Jul 31 18:14:16 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 893
 894         * vr.igen (MulAcc): Identify as a vr4100 specific function.
 895
 896 Sat Jul 25 16:03:14 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 897
 898         * Makefile.in (IGEN_INCLUDE): Add vr.igen.
 899
 900         * vr.igen: New file.
 901         (MAC/MADD16, DMAC/DMADD16): Implement using code from gencode.c.
 902         * mips.igen: Define vr4100 model. Include vr.igen.
 903 Mon Jun 29 09:21:07 1998  Gavin Koch  <gavin@cygnus.com>
 904
 905         * mips.igen (check_mf_hilo): Correct check.
 906
 907 Wed Jun 17 12:20:49 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 908
 909         * sim-main.h (interrupt_event): Add prototype.
 910
 911         * dv-tx3904tmr.c (tx3904tmr_io_write_buffer): Delete unused
 912         register_ptr, register_value.
 913         (deliver_tx3904tmr_tick): Fix types passed to printf fmt.
 914
 915         * sim-main.h (tracefh): Make extern.
 916
 917 Tue Jun 16 14:39:00 1998  Frank Ch. Eigler  <fche@cygnus.com>
 918
 919         * dv-tx3904tmr.c: Deschedule timer event after dispatching.
 920         Reduce unnecessarily high timer event frequency.
 921         * dv-tx3904cpu.c: Ditto for interrupt event.
 922
 923 Wed Jun 10 13:22:32 1998  Frank Ch. Eigler  <fche@cygnus.com>
 924
 925         * interp.c (decode_coproc): For TX39, add stub COP0 register #7,
 926         to allay warnings.
 927         (interrupt_event): Made non-static.
 928
 929         * dv-tx3904tmr.c (deliver_tx3904tmr_tick): Correct accidental
 930         interchange of configuration values for external vs. internal
 931         clock dividers.
 932
 933 Tue Jun  9 12:46:24 1998  Ian Carmichael  <iancarm@cygnus.com>
 934
 935         * mips.igen (BREAK): Moved code to here for
 936         simulator-reserved break instructions.
 937         * gencode.c (build_instruction): Ditto.
 938         * interp.c (signal_exception): Code moved from here.  Non-
 939         reserved instructions now use exception vector, rather
 940         than halting sim.
 941         * sim-main.h: Moved magic constants to here.
 942
 943 Tue Jun  9 12:29:50 1998  Frank Ch. Eigler  <fche@cygnus.com>
 944
 945         * dv-tx3904cpu.c (deliver_*_interrupt,*_port_event): Set the CAUSE
 946         register upon non-zero interrupt event level, clear upon zero
 947         event value.
 948         * dv-tx3904irc.c (*_port_event): Handle deactivated interrupt signal
 949         by passing zero event value.
 950         (*_io_{read,write}_buffer): Endianness fixes.
 951         * dv-tx3904tmr.c (*_io_{read,write}_buffer): Endianness fixes.
 952         (deliver_*_tick): Reduce sim event interval to 75% of count interval.
 953
 954         * interp.c (sim_open): Added jmr3904pal board type that adds PAL-based
 955         serial I/O and timer module at base address 0xFFFF0000.
 956
 957 Tue Jun  9 11:52:29 1998  Gavin Koch  <gavin@cygnus.com>
 958
 959         * mips.igen (SWC1) : Correct the handling of ReverseEndian
 960         and BigEndianCPU.
 961
 962 Tue Jun  9 11:40:57 1998  Gavin Koch  <gavin@cygnus.com>
 963
 964         * configure.in (mips_fpu_bitsize) : Set this correctly for 32-bit mips
 965         parts.
 966         * configure: Update.
 967
 968 Thu Jun  4 15:37:33 1998  Frank Ch. Eigler  <fche@cygnus.com>
 969
 970         * dv-tx3904tmr.c: New file - implements tx3904 timer.
 971         * dv-tx3904{irc,cpu}.c: Mild reformatting.
 972         * configure.in: Include tx3904tmr in hw_device list.
 973         * configure: Rebuilt.
 974         * interp.c (sim_open): Instantiate three timer instances.
 975         Fix address typo of tx3904irc instance.
 976
 977 Tue Jun  2 15:48:02 1998  Ian Carmichael  <iancarm@cygnus.com>
 978
 979         * interp.c (signal_exception): SystemCall exception now uses
 980         the exception vector.
 981
 982 Mon Jun  1 18:18:26 1998  Frank Ch. Eigler  <fche@cygnus.com>
 983
 984         * interp.c (decode_coproc): For TX39, add stub COP0 register #3,
 985         to allay warnings.
 986
 987 Fri May 29 11:40:39 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 988
 989         * configure.in (sim_igen_filter): Match mips*tx39 not mipst*tx39.
 990
 991 Mon May 25 20:47:45 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 992
 993         * dv-tx3904cpu.c, dv-tx3904irc.c: Rename *_callback to *_method.
 994
 995         * dv-tx3904cpu.c, dv-tx3904irc.c: Include hw-main.h and
 996         sim-main.h. Declare a struct hw_descriptor instead of struct
 997         hw_device_descriptor.
 998
 999 Mon May 25 12:41:38 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1000
1001         * mips.igen (do_store_left, do_load_left): Compute nr of left and
1002         right bits and then re-align left hand bytes to correct byte
1003         lanes.  Fix incorrect computation in do_store_left when loading
1004         bytes from second word.
1005
1006 Fri May 22 13:34:20 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1007
1008         * configure.in (SIM_AC_OPTION_HARDWARE): Only enable when tx3904.
1009         * interp.c (sim_open): Only create a device tree when HW is
1010         enabled.
1011
1012         * dv-tx3904irc.c (tx3904irc_finish): Pacify GCC.
1013         * interp.c (signal_exception): Ditto.
1014
1015 Thu May 21 14:24:11 1998  Gavin Koch  <gavin@cygnus.com>
1016
1017         * gencode.c: Mark BEGEZALL as LIKELY.
1018
1019 Thu May 21 18:57:19 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1020
1021         * sim-main.h (ALU32_END): Sign extend 32 bit results.
1022         * mips.igen (ADD, SUB, ADDI, DADD, DSUB): Trace.
1023
1024 Mon May 18 18:22:42 1998  Frank Ch. Eigler  <fche@cygnus.com>
1025
1026         * configure.in (SIM_AC_OPTION_HARDWARE): Added common hardware
1027         modules.  Recognize TX39 target with "mips*tx39" pattern.
1028         * configure: Rebuilt.
1029         * sim-main.h (*): Added many macros defining bits in
1030         TX39 control registers.
1031         (SignalInterrupt): Send actual PC instead of NULL.
1032         (SignalNMIReset): New exception type.
1033         * interp.c (board): New variable for future use to identify
1034         a particular board being simulated.
1035         (mips_option_handler,mips_options): Added "--board" option.
1036         (interrupt_event): Send actual PC.
1037         (sim_open): Make memory layout conditional on board setting.
1038         (signal_exception): Initial implementation of hardware interrupt
1039         handling.  Accept another break instruction variant for simulator
1040         exit.
1041         (decode_coproc): Implement RFE instruction for TX39.
1042         (mips.igen): Decode RFE instruction as such.
1043         * configure.in (tx3904cpu,tx3904irc): Added devices for tx3904.
1044         * interp.c: Define "jmr3904" and "jmr3904debug" board types and
1045         bbegin to implement memory map.
1046         * dv-tx3904cpu.c: New file.
1047         * dv-tx3904irc.c: New file.
1048
1049 Wed May 13 14:40:11 1998  Gavin Koch  <gavin@cygnus.com>
1050
1051         * mips.igen (check_mt_hilo): Create a separate r3900 version.
1052
1053 Wed May 13 14:11:46 1998  Gavin Koch  <gavin@cygnus.com>
1054
1055         * tx.igen (madd,maddu):  Replace calls to check_op_hilo
1056         with calls to check_div_hilo.
1057
1058 Wed May 13 09:59:27 1998  Gavin Koch  <gavin@cygnus.com>
1059
1060         * mips/mips.igen (check_op_hilo,check_mult_hilo,check_div_hilo):
1061         Replace check_op_hilo with check_mult_hilo and check_div_hilo.
1062         Add special r3900 version of do_mult_hilo.
1063         (do_dmultx,do_mult,do_multu): Replace calls to check_op_hilo
1064         with calls to check_mult_hilo.
1065         (do_ddiv,do_ddivu,do_div,do_divu): Replace calls to check_op_hilo
1066         with calls to check_div_hilo.
1067
1068 Tue May 12 15:22:11 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1069
1070         * configure.in (SUBTARGET_R3900): Define for mipstx39 target.
1071         Document a replacement.
1072
1073 Fri May  8 17:48:19 1998  Ian Carmichael  <iancarm@cygnus.com>
1074
1075         * interp.c (sim_monitor): Make mon_printf work.
1076
1077 Wed May  6 19:42:19 1998  Doug Evans  <devans@canuck.cygnus.com>
1078
1079         * sim-main.h (INSN_NAME): New arg `cpu'.
1080
1081 Tue Apr 28 18:33:31 1998  Geoffrey Noer  <noer@cygnus.com>
1082
1083         * configure: Regenerated to track ../common/aclocal.m4 changes.
1084
1085 Sun Apr 26 15:31:55 1998  Tom Tromey  <tromey@creche>
1086
1087         * configure: Regenerated to track ../common/aclocal.m4 changes.
1088         * config.in: Ditto.
1089
1090 Sun Apr 26 15:20:01 1998  Tom Tromey  <tromey@cygnus.com>
1091
1092         * acconfig.h: New file.
1093         * configure.in: Reverted change of Apr 24; use sinclude again.
1094
1095 Fri Apr 24 14:16:40 1998  Tom Tromey  <tromey@creche>
1096
1097         * configure: Regenerated to track ../common/aclocal.m4 changes.
1098         * config.in: Ditto.
1099
1100 Fri Apr 24 11:19:20 1998  Tom Tromey  <tromey@cygnus.com>
1101
1102         * configure.in: Don't call sinclude.
1103
1104 Fri Apr 24 11:35:01 1998  Andrew Cagney  <cagney@chook.cygnus.com>
1105
1106         * mips.igen (do_store_left): Pass 0 not NULL to store_memory.
1107
1108 Tue Apr 21 11:59:50 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1109
1110         * mips.igen (ERET): Implement.
1111
1112         * interp.c (decode_coproc): Return sign-extended EPC.
1113
1114         * mips.igen (ANDI, LUI, MFC0): Add tracing code.
1115
1116         * interp.c (signal_exception): Do not ignore Trap.
1117         (signal_exception): On TRAP, restart at exception address.
1118         (HALT_INSTRUCTION, HALT_INSTRUCTION_MASK): Define.
1119         (signal_exception): Update.
1120         (sim_open): Patch V_COMMON interrupt vector with an abort sequence
1121         so that TRAP instructions are caught.
1122
1123 Mon Apr 20 11:26:55 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1124
1125         * sim-main.h (struct hilo_access, struct hilo_history): Define,
1126         contains HI/LO access history.
1127         (struct _sim_cpu): Make hiaccess and loaccess of type hilo_access.
1128         (HIACCESS, LOACCESS): Delete, replace with
1129         (HIHISTORY, LOHISTORY): New macros.
1130         (CHECKHILO): Delete all, moved to mips.igen
1131
1132         * gencode.c (build_instruction): Do not generate checks for
1133         correct HI/LO register usage.
1134
1135         * interp.c (old_engine_run): Delete checks for correct HI/LO
1136         register usage.
1137
1138         * mips.igen (check_mt_hilo, check_mf_hilo, check_op_hilo,
1139         check_mf_cycles): New functions.
1140         (do_mfhi, do_mflo, "mthi", "mtlo", do_ddiv, do_ddivu, do_div,
1141         do_divu, domultx, do_mult, do_multu): Use.
1142
1143         * tx.igen ("madd", "maddu"): Use.
1144
1145 Wed Apr 15 18:31:54 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1146
1147         * mips.igen (DSRAV): Use function do_dsrav.
1148         (SRAV): Use new function do_srav.
1149
1150         * m16.igen (BEQZ, BNEZ): Compare GPR[TRX] not GPR[RX].
1151         (B): Sign extend 11 bit immediate.
1152         (EXT-B*): Shift 16 bit immediate left by 1.
1153         (ADDIU*): Don't sign extend immediate value.
1154
1155 Wed Apr 15 10:32:15 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1156
1157         * m16run.c (sim_engine_run): Restore CIA after handling an event.
1158
1159         * sim-main.h (DELAY_SLOT, NULLIFY_NEXT_INSTRUCTION): For IGEN, use
1160         functions.
1161
1162         * mips.igen (delayslot32, nullify_next_insn): New functions.
1163         (m16.igen): Always include.
1164         (do_*): Add more tracing.
1165
1166         * m16.igen (delayslot16): Add NIA argument, could be called by a
1167         32 bit MIPS16 instruction.
1168
1169         * interp.c (ifetch16): Move function from here.
1170         * sim-main.c (ifetch16): To here.
1171
1172         * sim-main.c (ifetch16, ifetch32): Update to match current
1173         implementations of LH, LW.
1174         (signal_exception): Don't print out incorrect hex value of illegal
1175         instruction.
1176
1177 Wed Apr 15 00:17:25 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1178
1179         * m16run.c (sim_engine_run): Use IMEM16 and IMEM32 to fetch an
1180         instruction.
1181
1182         * m16.igen: Implement MIPS16 instructions.
1183
1184         * mips.igen (do_addiu, do_addu, do_and, do_daddiu, do_daddu,
1185         do_ddiv, do_ddivu, do_div, do_divu, do_dmultx, do_dmultu, do_srav,
1186         do_dsubu, do_mfhi, do_mflo, do_mult, do_multu, do_nor, do_or,
1187         do_sll, do_sllv, do_slt, do_slti, do_sltiu, do_sltu, do_sra,
1188         do_srl, do_srlv, do_subu, do_xor, do_xori): New functions.  Move
1189         bodies of corresponding code from 32 bit insn to these.  Also used
1190         by MIPS16 versions of functions.
1191
1192         * sim-main.h (RAIDX, T8IDX, T8, SPIDX): Define.
1193         (IMEM16): Drop NR argument from macro.
1194
1195 Sat Apr  4 22:39:50 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1196
1197         * Makefile.in (SIM_OBJS): Add sim-main.o.
1198
1199         * sim-main.h (address_translation, load_memory, store_memory,
1200         cache_op, sync_operation, prefetch, ifetch32, pending_tick): Mark
1201         as INLINE_SIM_MAIN.
1202         (pr_addr, pr_uword64): Declare.
1203         (sim-main.c): Include when H_REVEALS_MODULE_P.
1204
1205         * interp.c (address_translation, load_memory, store_memory,
1206         cache_op, sync_operation, prefetch, ifetch32, pending_tick): Move
1207         from here.
1208         * sim-main.c: To here. Fix compilation problems.
1209
1210         * configure.in: Enable inlining.
1211         * configure: Re-config.
1212
1213 Sat Apr  4 20:36:25 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1214
1215         * configure: Regenerated to track ../common/aclocal.m4 changes.
1216
1217 Fri Apr  3 04:32:35 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1218
1219         * mips.igen: Include tx.igen.
1220         * Makefile.in (IGEN_INCLUDE): Add tx.igen.
1221         * tx.igen: New file, contains MADD and MADDU.
1222
1223         * interp.c (load_memory): When shifting bytes, use LOADDRMASK not
1224         the hardwired constant `7'.
1225         (store_memory): Ditto.
1226         (LOADDRMASK): Move definition to sim-main.h.
1227
1228         mips.igen (MTC0): Enable for r3900.
1229         (ADDU): Add trace.
1230
1231         mips.igen (do_load_byte): Delete.
1232         (do_load, do_store, do_load_left, do_load_write, do_store_left,
1233         do_store_right): New functions.
1234         (SW*, LW*, SD*, LD*, SH, LH, SB, LB): Use.
1235
1236         configure.in: Let the tx39 use igen again.
1237         configure: Update.
1238
1239 Thu Apr  2 10:59:39 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1240
1241         * interp.c (sim_monitor): get_mem_info returns a 4 byte quantity,
1242         not an address sized quantity.  Return zero for cache sizes.
1243
1244 Wed Apr  1 23:47:53 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1245
1246         * mips.igen (r3900): r3900 does not support 64 bit integer
1247         operations.
1248
1249 Mon Mar 30 14:46:05 1998  Gavin Koch  <gavin@cygnus.com>
1250
1251         * configure.in (mipstx39*-*-*): Use gencode simulator rather
1252         than igen one.
1253         * configure : Rebuild.
1254
1255 Fri Mar 27 16:15:52 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1256
1257         * configure: Regenerated to track ../common/aclocal.m4 changes.
1258
1259 Fri Mar 27 15:01:50 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1260
1261         * interp.c (mips_option_handler): Iterate over MAX_NR_PROCESSORS.
1262
1263 Wed Mar 25 16:44:27 1998  Ian Carmichael  <iancarm@cygnus.com>
1264
1265         * configure: Regenerated to track ../common/aclocal.m4 changes.
1266         * config.in: Regenerated to track ../common/aclocal.m4 changes.
1267
1268 Wed Mar 25 12:35:29 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1269
1270         * configure: Regenerated to track ../common/aclocal.m4 changes.
1271
1272 Wed Mar 25 10:05:46 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1273
1274         * interp.c (Max, Min): Comment out functions. Not yet used.
1275
1276 Wed Mar 18 12:38:12 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1277
1278         * configure: Regenerated to track ../common/aclocal.m4 changes.
1279
1280 Tue Mar 17 19:05:20 1998  Frank Ch. Eigler  <fche@cygnus.com>
1281
1282         * Makefile.in (MIPS_EXTRA_LIBS, SIM_EXTRA_LIBS): Added
1283         configurable settings for stand-alone simulator.
1284
1285         * configure.in: Added X11 search, just in case.
1286
1287         * configure: Regenerated.
1288
1289 Wed Mar 11 14:09:10 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1290
1291         * interp.c (sim_write, sim_read, load_memory, store_memory):
1292         Replace sim_core_*_map with read_map, write_map, exec_map resp.
1293
1294 Tue Mar  3 13:58:43 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1295
1296         * sim-main.h (GETFCC): Return an unsigned value.
1297
1298 Tue Mar  3 13:21:37 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1299
1300         * mips.igen (DIV): Fix check for -1 / MIN_INT.
1301         (DADD): Result destination is RD not RT.
1302
1303 Fri Feb 27 13:49:49 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1304
1305         * sim-main.h (HIACCESS, LOACCESS): Always define.
1306
1307         * mdmx.igen (Maxi, Mini): Rename Max, Min.
1308
1309         * interp.c (sim_info): Delete.
1310
1311 Fri Feb 27 18:41:01 1998  Doug Evans  <devans@canuck.cygnus.com>
1312
1313         * interp.c (DECLARE_OPTION_HANDLER): Use it.
1314         (mips_option_handler): New argument `cpu'.
1315         (sim_open): Update call to sim_add_option_table.
1316
1317 Wed Feb 25 18:56:22 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1318
1319         * mips.igen (CxC1): Add tracing.
1320
1321 Fri Feb 20 17:43:21 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1322
1323         * sim-main.h (Max, Min): Declare.
1324
1325         * interp.c (Max, Min): New functions.
1326
1327         * mips.igen (BC1): Add tracing.
1328
1329 Thu Feb 19 14:50:00 1998  John Metzler  <jmetzler@cygnus.com>
1330
1331         * interp.c Added memory map for stack in vr4100
1332
1333 Thu Feb 19 10:21:21 1998  Gavin Koch  <gavin@cygnus.com>
1334
1335         * interp.c (load_memory): Add missing "break"'s.
1336
1337 Tue Feb 17 12:45:35 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1338
1339         * interp.c (sim_store_register, sim_fetch_register): Pass in
1340         length parameter.  Return -1.
1341
1342 Tue Feb 10 11:57:40 1998  Ian Carmichael  <iancarm@cygnus.com>
1343
1344         * interp.c: Added hardware init hook, fixed warnings.
1345
1346 Sat Feb  7 17:16:20 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1347
1348         * Makefile.in (itable.h itable.c): Depend on SIM_@sim_gen@_ALL.
1349
1350 Tue Feb  3 11:36:02 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1351
1352         * interp.c (ifetch16): New function.
1353
1354         * sim-main.h (IMEM32): Rename IMEM.
1355         (IMEM16_IMMED): Define.
1356         (IMEM16): Define.
1357         (DELAY_SLOT): Update.
1358
1359         * m16run.c (sim_engine_run): New file.
1360
1361         * m16.igen: All instructions except LB.
1362         (LB): Call do_load_byte.
1363         * mips.igen (do_load_byte): New function.
1364         (LB): Call do_load_byte.
1365
1366         * mips.igen: Move spec for insn bit size and high bit from here.
1367         * Makefile.in (tmp-igen, tmp-m16): To here.
1368
1369         * m16.dc: New file, decode mips16 instructions.
1370
1371         * Makefile.in (SIM_NO_ALL): Define.
1372         (tmp-m16): Generate both 16 bit and 32 bit simulator engines.
1373
1374 Tue Feb  3 11:28:00 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1375
1376         * configure.in (mips_fpu_bitsize): For tx39, restrict floating
1377         point unit to 32 bit registers.
1378         * configure: Re-generate.
1379
1380 Sun Feb  1 15:47:14 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1381
1382         * configure.in (sim_use_gen): Make IGEN the default simulator
1383         generator for generic 32 and 64 bit mips targets.
1384         * configure: Re-generate.
1385
1386 Sun Feb  1 16:52:37 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1387
1388         * sim-main.h (SizeFGR): Determine from floating-point and not gpr
1389         bitsize.
1390
1391         * interp.c (sim_fetch_register, sim_store_register): Read/write
1392         FGR from correct location.
1393         (sim_open): Set size of FGR's according to
1394         WITH_TARGET_FLOATING_POINT_BITSIZE.
1395
1396         * sim-main.h (FGR): Store floating point registers in a separate
1397         array.
1398
1399 Sun Feb  1 16:47:51 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1400
1401         * configure: Regenerated to track ../common/aclocal.m4 changes.
1402
1403 Tue Feb  3 00:10:50 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1404
1405         * interp.c (ColdReset): Call PENDING_INVALIDATE.
1406
1407         * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Call PENDING_TICK.
1408
1409         * interp.c (pending_tick): New function.  Deliver pending writes.
1410
1411         * sim-main.h (PENDING_FILL, PENDING_TICK, PENDING_SCHED,
1412         PENDING_BIT, PENDING_INVALIDATE): Re-write pipeline code so that
1413         it can handle mixed sized quantites and single bits.
1414
1415 Mon Feb  2 17:43:15 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1416
1417         * interp.c (oengine.h): Do not include when building with IGEN.
1418         (sim_open): Replace GPRLEN by WITH_TARGET_WORD_BITSIZE.
1419         (sim_info): Ditto for PROCESSOR_64BIT.
1420         (sim_monitor): Replace ut_reg with unsigned_word.
1421         (*): Ditto for t_reg.
1422         (LOADDRMASK): Define.
1423         (sim_open): Remove defunct check that host FP is IEEE compliant,
1424         using software to emulate floating point.
1425         (value_fpr, ...): Always compile, was conditional on HASFPU.
1426
1427 Sun Feb  1 11:15:29 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1428
1429         * sim-main.h (sim_state): Make the cpu array MAX_NR_PROCESSORS in
1430         size.
1431
1432         * interp.c (SD, CPU): Define.
1433         (mips_option_handler): Set flags in each CPU.
1434         (interrupt_event): Assume CPU 0 is the one being iterrupted.
1435         (sim_close): Do not clear STATE, deleted anyway.
1436         (sim_write, sim_read): Assume CPU zero's vm should be used for
1437         data transfers.
1438         (sim_create_inferior): Set the PC for all processors.
1439         (sim_monitor, store_word, load_word, mips16_entry): Add cpu
1440         argument.
1441         (mips16_entry): Pass correct nr of args to store_word, load_word.
1442         (ColdReset): Cold reset all cpu's.
1443         (signal_exception): Pass cpu to sim_monitor & mips16_entry.
1444         (sim_monitor, load_memory, store_memory, signal_exception): Use
1445         `CPU' instead of STATE_CPU.
1446
1447
1448         * sim-main.h: Replace uses of STATE_CPU with CPU. Replace sd with
1449         SD or CPU_.
1450
1451         * sim-main.h (signal_exception): Add sim_cpu arg.
1452         (SignalException*): Pass both SD and CPU to signal_exception.
1453         * interp.c (signal_exception): Update.
1454
1455         * sim-main.h (value_fpr, store_fpr, dotrace, ifetch32), interp.c:
1456         Ditto
1457         (sync_operation, prefetch, cache_op, store_memory, load_memory,
1458         address_translation): Ditto
1459         (decode_coproc, cop_lw, cop_ld, cop_sw, cop_sd): Ditto.
1460
1461 Sat Jan 31 18:15:41 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1462
1463         * configure: Regenerated to track ../common/aclocal.m4 changes.
1464
1465 Sat Jan 31 14:49:24 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1466
1467         * interp.c (sim_engine_run): Add `nr_cpus' argument.
1468
1469         * mips.igen (model): Map processor names onto BFD name.
1470
1471         * sim-main.h (CPU_CIA): Delete.
1472         (SET_CIA, GET_CIA): Define
1473
1474 Wed Jan 21 16:16:27 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1475
1476         * sim-main.h (GPR_SET): Define, used by igen when zeroing a
1477         regiser.
1478
1479         * configure.in (default_endian): Configure a big-endian simulator
1480         by default.
1481         * configure: Re-generate.
1482
1483 Mon Jan 19 22:26:29 1998  Doug Evans  <devans@seba>
1484
1485         * configure: Regenerated to track ../common/aclocal.m4 changes.
1486
1487 Mon Jan  5 20:38:54 1998  Mark Alexander  <marka@cygnus.com>
1488
1489         * interp.c (sim_monitor): Handle Densan monitor outbyte
1490         and inbyte functions.
1491
1492 1997-12-29  Felix Lee  <flee@cygnus.com>
1493
1494         * interp.c (sim_engine_run): msvc cpp barfs on #if (a==b!=c).
1495
1496 Wed Dec 17 14:48:20 1997  Jeffrey A Law  (law@cygnus.com)
1497
1498         * Makefile.in (tmp-igen): Arrange for $zero to always be
1499         reset to zero after every instruction.
1500
1501 Mon Dec 15 23:17:11 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1502
1503         * configure: Regenerated to track ../common/aclocal.m4 changes.
1504         * config.in: Ditto.
1505
1506 Wed Dec 10 17:10:45 1997  Jeffrey A Law  (law@cygnus.com)
1507
1508         * mips.igen (MSUB): Fix to work like MADD.
1509         * gencode.c (MSUB): Similarly.
1510
1511 Thu Dec  4 09:21:05 1997  Doug Evans  <devans@canuck.cygnus.com>
1512
1513         * configure: Regenerated to track ../common/aclocal.m4 changes.
1514
1515 Wed Nov 26 11:00:23 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1516
1517         * mips.igen (LWC1): Correct assembler - lwc1 not swc1.
1518
1519 Sun Nov 23 01:45:20 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1520
1521         * sim-main.h (sim-fpu.h): Include.
1522
1523         * interp.c (convert, SquareRoot, Recip, Divide, Multiply, Sub,
1524         Add, Negate, AbsoluteValue, Equal, Less, Infinity, NaN): Rewrite
1525         using host independant sim_fpu module.
1526
1527 Thu Nov 20 19:56:22 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1528
1529         * interp.c (signal_exception): Report internal errors with SIGABRT
1530         not SIGQUIT.
1531
1532         * sim-main.h (C0_CONFIG): New register.
1533         (signal.h): No longer include.
1534
1535         * interp.c (decode_coproc): Allow access C0_CONFIG to register.
1536
1537 Tue Nov 18 15:33:48 1997  Doug Evans  <devans@canuck.cygnus.com>
1538
1539         * Makefile.in (SIM_OBJS): Use $(SIM_NEW_COMMON_OBJS).
1540
1541 Fri Nov 14 11:56:48 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1542
1543         * mips.igen: Tag vr5000 instructions.
1544         (ANDI): Was missing mipsIV model, fix assembler syntax.
1545         (do_c_cond_fmt): New function.
1546         (C.cond.fmt): Handle mips I-III which do not support CC field
1547         separatly.
1548         (bc1): Handle mips IV which do not have a delaed FCC separatly.
1549         (SDR): Mask paddr when BigEndianMem, not the converse as specified
1550         in IV3.2 spec.
1551         (DMULT, DMULTU): Force use of hosts 64bit multiplication.  Handle
1552         vr5000 which saves LO in a GPR separatly.
1553
1554         * configure.in (enable-sim-igen): For vr5000, select vr5000
1555         specific instructions.
1556         * configure: Re-generate.
1557
1558 Wed Nov 12 14:42:52 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1559
1560         * Makefile.in (SIM_OBJS): Add sim-fpu module.
1561
1562         * interp.c (store_fpr), sim-main.h: Add separate fmt_uninterpreted_32 and
1563         fmt_uninterpreted_64 bit cases to switch.  Convert to
1564         fmt_formatted,
1565
1566         * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Define,
1567
1568         * mips.igen (SWR): Mask paddr when BigEndianMem, not the converse
1569         as specified in IV3.2 spec.
1570         (MTC1, DMTC1): Call StoreFPR to store the GPR in the FPR.
1571
1572 Tue Nov 11 12:38:23 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1573
1574         * mips.igen: Delay slot branches add OFFSET to NIA not CIA.
1575         (MFC0, MTC0, SWC1, LWC1, SDC1, LDC1): Implement.
1576         (MTC1, MFC1, DMTC1, DMFC1, CFC1, CTC1): Implement separate non
1577         PENDING_FILL versions of instructions.  Simplify.
1578         (X): New function.
1579         (MULT, MULTU): Implement separate RD==0 and RD!=0 versions of
1580         instructions.
1581         (BEQZ, ..., SLT, SLTI, TLT, TLE, TLI, ...): Explicitly cast GPR to
1582         a signed value.
1583         (MTHI, MFHI): Disable code checking HI-LO.
1584
1585         * sim-main.h (dotrace,tracefh), interp.c: Make dotrace & tracefh
1586         global.
1587         (NULLIFY_NEXT_INSTRUCTION): Call dotrace.
1588
1589 Thu Nov  6 16:36:35 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1590
1591         * gencode.c (build_mips16_operands): Replace IPC with cia.
1592
1593         * interp.c (sim_monitor, signal_exception, cache_op, store_fpr,
1594         value_fpr, cop_ld, cop_lw, cop_sw, cop_sd, decode_coproc): Replace
1595         IPC to `cia'.
1596         (UndefinedResult): Replace function with macro/function
1597         combination.
1598         (sim_engine_run): Don't save PC in IPC.
1599
1600         * sim-main.h (IPC): Delete.
1601
1602
1603         * interp.c (signal_exception, store_word, load_word,
1604         address_translation, load_memory, store_memory, cache_op,
1605         prefetch, sync_operation, ifetch, value_fpr, store_fpr, convert,
1606         cop_lw, cop_ld, cop_sw, cop_sd, decode_coproc, sim_monitor): Add
1607         current instruction address - cia - argument.
1608         (sim_read, sim_write): Call address_translation directly.
1609         (sim_engine_run): Rename variable vaddr to cia.
1610         (signal_exception): Pass cia to sim_monitor
1611
1612         * sim-main.h (SignalException, LoadWord, StoreWord, CacheOp,
1613         Prefetch, SyncOperation, ValueFPR, StoreFPR, Convert, COP_LW,
1614         COP_LD, COP_SW, COP_SD, DecodeCoproc): Update.
1615
1616         * sim-main.h (SignalExceptionSimulatorFault): Delete definition.
1617         * interp.c (sim_open): Replace SignalExceptionSimulatorFault with
1618         SIM_ASSERT.
1619
1620         * interp.c (signal_exception): Pass restart address to
1621         sim_engine_restart.
1622
1623         * Makefile.in (semantics.o, engine.o, support.o, itable.o,
1624         idecode.o): Add dependency.
1625
1626         * sim-main.h (SIM_ENGINE_HALT_HOOK, SIM_ENGINE_RESUME_HOOK):
1627         Delete definitions
1628         (DELAY_SLOT): Update NIA not PC with branch address.
1629         (NULLIFY_NEXT_INSTRUCTION): Set NIA to instruction after next.
1630
1631         * mips.igen: Use CIA not PC in branch calculations.
1632         (illegal): Call SignalException.
1633         (BEQ, ADDIU): Fix assembler.
1634
1635 Wed Nov  5 12:19:56 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1636
1637         * m16.igen (JALX): Was missing.
1638
1639         * configure.in (enable-sim-igen): New configuration option.
1640         * configure: Re-generate.
1641
1642         * sim-main.h (MAX_INSNS, INSN_NAME): Define.
1643
1644         * interp.c (load_memory, store_memory): Delete parameter RAW.
1645         (sim_read, sim_write): Use sim_core_{read,write}_buffer directly
1646         bypassing {load,store}_memory.
1647
1648         * sim-main.h (ByteSwapMem): Delete definition.
1649
1650         * Makefile.in (SIM_OBJS): Add sim-memopt module.
1651
1652         * interp.c (sim_do_command, sim_commands): Delete mips specific
1653         commands.  Handled by module sim-options.
1654
1655         * sim-main.h (SIM_HAVE_FLATMEM): Undefine, use sim-core.o module.
1656         (WITH_MODULO_MEMORY): Define.
1657
1658         * interp.c (sim_info): Delete code printing memory size.
1659
1660         * interp.c (mips_size): Nee sim_size, delete function.
1661         (power2): Delete.
1662         (monitor, monitor_base, monitor_size): Delete global variables.
1663         (sim_open, sim_close): Delete code creating monitor and other
1664         memory regions.  Use sim-memopts module, via sim_do_commandf, to
1665         manage memory regions.
1666         (load_memory, store_memory): Use sim-core for memory model.
1667
1668         * interp.c (address_translation): Delete all memory map code
1669         except line forcing 32 bit addresses.
1670
1671 Wed Nov  5 11:21:11 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1672
1673         * sim-main.h (WITH_TRACE): Delete definition.  Enables common
1674         trace options.
1675
1676         * interp.c (logfh, logfile): Delete globals.
1677         (sim_open, sim_close): Delete code opening & closing log file.
1678         (mips_option_handler): Delete -l and -n options.
1679         (OPTION mips_options): Ditto.
1680
1681         * interp.c (OPTION mips_options): Rename option trace to dinero.
1682         (mips_option_handler): Update.
1683
1684 Wed Nov  5 09:35:59 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1685
1686         * interp.c (fetch_str): New function.
1687         (sim_monitor): Rewrite using sim_read & sim_write.
1688         (sim_open): Check magic number.
1689         (sim_open): Write monitor vectors into memory using sim_write.
1690         (MONITOR_BASE, MONITOR_SIZE, MEM_SIZE): Define.
1691         (sim_read, sim_write): Simplify - transfer data one byte at a
1692         time.
1693         (load_memory, store_memory): Clarify meaning of parameter RAW.
1694
1695         * sim-main.h (isHOST): Defete definition.
1696         (isTARGET): Mark as depreciated.
1697         (address_translation): Delete parameter HOST.
1698
1699         * interp.c (address_translation): Delete parameter HOST.
1700
1701 Wed Oct 29 11:13:56 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1702
1703         * mips.igen:
1704
1705         * Makefile.in (IGEN_INCLUDE): Files included by mips.igen.
1706         (tmp-igen, tmp-m16): Depend on IGEN_INCLUDE.
1707
1708 Tue Oct 28 11:06:47 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1709
1710         * mips.igen: Add model filter field to records.
1711
1712 Mon Oct 27 17:53:59 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1713
1714         * Makefile.in (SIM_NO_CFLAGS): Define.  Define WITH_IGEN=0.
1715
1716         interp.c (sim_engine_run): Do not compile function sim_engine_run
1717         when WITH_IGEN == 1.
1718
1719         * configure.in (sim_igen_flags, sim_m16_flags): Set according to
1720         target architecture.
1721
1722         Makefile.in (tmp-igen, tmp-m16): Drop -F and -M options to
1723         igen. Replace with configuration variables sim_igen_flags /
1724         sim_m16_flags.
1725
1726         * m16.igen: New file.  Copy mips16 insns here.
1727         * mips.igen: From here.
1728
1729 Mon Oct 27 13:53:59 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1730
1731         * Makefile.in (SIM_NO_OBJ): Define, move SIM_M16_OBJ, SIM_IGEN_OBJ
1732         to top.
1733         (tmp-igen, tmp-m16): Pass -I srcdir to igen.
1734
1735 Sat Oct 25 16:51:40 1997  Gavin Koch  <gavin@cygnus.com>
1736
1737         * gencode.c (build_instruction): Follow sim_write's lead in using
1738         BigEndianMem instead of !ByteSwapMem.
1739
1740 Fri Oct 24 17:41:49 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1741
1742         * configure.in (sim_gen): Dependent on target, select type of
1743         generator.  Always select old style generator.
1744
1745         configure: Re-generate.
1746
1747         Makefile.in (tmp-igen, tmp-m16, clean-m16, clean-igen): New
1748         targets.
1749         (SIM_M16_CFLAGS, SIM_M16_ALL, SIM_M16_OBJ, BUILT_SRC_FROM_M16,
1750         SIM_IGEN_CFLAGS, SIM_IGEN_ALL, SIM_IGEN_OBJ, BUILT_SRC_FROM_IGEN,
1751         IGEN_TRACE, IGEN_INSN, IGEN_DC): Define
1752         (SIM_EXTRA_CFLAGS, SIM_EXTRA_ALL, SIM_OBJS): Add member
1753         SIM_@sim_gen@_*, set by autoconf.
1754
1755 Wed Oct 22 12:52:06 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1756
1757         * sim-main.h (NULLIFY_NEXT_INSTRUCTION, DELAY_SLOT): Define.
1758
1759         * interp.c (ColdReset): Remove #ifdef HASFPU, check
1760         CURRENT_FLOATING_POINT instead.
1761
1762         * interp.c (ifetch32): New function. Fetch 32 bit instruction.
1763         (address_translation): Raise exception InstructionFetch when
1764         translation fails and isINSTRUCTION.
1765
1766         * interp.c (sim_open, sim_write, sim_monitor, store_word,
1767         sim_engine_run): Change type of of vaddr and paddr to
1768         address_word.
1769         (address_translation, prefetch, load_memory, store_memory,
1770         cache_op): Change type of vAddr and pAddr to address_word.
1771
1772         * gencode.c (build_instruction): Change type of vaddr and paddr to
1773         address_word.
1774
1775 Mon Oct 20 15:29:04 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1776
1777         * sim-main.h (ALU64_END, ALU32_END): Use ALU*_OVERFLOW_RESULT
1778         macro to obtain result of ALU op.
1779
1780 Tue Oct 21 17:39:14 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1781
1782         * interp.c (sim_info): Call profile_print.
1783
1784 Mon Oct 20 13:31:20 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1785
1786         * Makefile.in (SIM_OBJS): Add sim-profile.o module.
1787
1788         * sim-main.h (WITH_PROFILE): Do not define, defined in
1789         common/sim-config.h.  Use sim-profile module.
1790         (simPROFILE): Delete defintion.
1791
1792         * interp.c (PROFILE): Delete definition.
1793         (mips_option_handler): Delete 'p', 'y' and 'x' profile options.
1794         (sim_close): Delete code writing profile histogram.
1795         (mips_set_profile, mips_set_profile_size, writeout16, writeout32):
1796         Delete.
1797         (sim_engine_run): Delete code profiling the PC.
1798
1799 Mon Oct 20 13:31:20 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1800
1801         * sim-main.h (SIGNEXTEND): Force type of result to unsigned_word.
1802
1803         * interp.c (sim_monitor): Make register pointers of type
1804         unsigned_word*.
1805
1806         * sim-main.h: Make registers of type unsigned_word not
1807         signed_word.
1808
1809 Thu Oct 16 10:31:39 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1810
1811         * interp.c (sync_operation): Rename from SyncOperation, make
1812         global, add SD argument.
1813         (prefetch): Rename from Prefetch, make global, add SD argument.
1814         (decode_coproc): Make global.
1815
1816         * sim-main.h (SyncOperation, DecodeCoproc, Pefetch): Define.
1817
1818         * gencode.c (build_instruction): Generate DecodeCoproc not
1819         decode_coproc calls.
1820
1821         * interp.c (SETFCC, GETFCC, PREVCOC1): Move to sim-main.h
1822         (SizeFGR): Move to sim-main.h
1823         (simHALTEX, simHALTIN, simTRACE, simPROFILE, simDELAYSLOT,
1824         simSIGINT, simJALDELAYSLOT): Move to sim-main.h
1825         (FP_FLAGS, FP_ENABLE, FP_CAUSE, IR, UF, OF, DZ, IO, UO): Move to
1826         sim-main.h.
1827         (FP_FS, FP_MASK_RM, FP_SH_RM, FP_RM_NEAREST, FP_RM_TOPINF,
1828         FP_RM_TOMINF, GETRM): Move to sim-main.h.
1829         (Uncached, CachedNoncoherent, CachedCoherent, Cached,
1830         isINSTRUCTION, ..., AccessLength_BYTE, ...): Move to sim-main.h.
1831         (UserMode, BigEndianMem, ByteSwapMem, ReverseEndian,
1832         BigEndianCPU, status_KSU_mask, ...). Moved to sim-main.h
1833
1834         * sim-main.h (ALU32_END, ALU64_END): Define. When overflow raise
1835         exception.
1836         (sim-alu.h): Include.
1837         (NULLIFY_NIA, NULL_CIA, CPU_CIA): Define.
1838         (sim_cia): Typedef to instruction_address.
1839
1840 Thu Oct 16 10:31:41 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1841
1842         * Makefile.in (interp.o): Rename generated file engine.c to
1843         oengine.c.
1844
1845         * interp.c: Update.
1846
1847 Thu Oct 16 10:31:40 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1848
1849         * gencode.c (build_instruction): Use FPR_STATE not fpr_state.
1850
1851 Thu Oct 16 10:31:39 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1852
1853         * gencode.c (build_instruction): For "FPSQRT", output correct
1854         number of arguments to Recip.
1855
1856 Tue Oct 14 17:38:18 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1857
1858         * Makefile.in (interp.o): Depends on sim-main.h
1859
1860         * interp.c (mips16_entry, ColdReset,dotrace): Add SD argument. Use GPR not registers.
1861
1862         * sim-main.h (sim_cpu): Add registers, register_widths, fpr_state,
1863         ipc, dspc, pending_*, hiaccess, loaccess, state, dsstate fields.
1864         (REGISTERS, REGISTER_WIDTHS, FPR_STATE, IPC, DSPC, PENDING_*,
1865         STATE, DSSTATE): Define
1866         (GPR, FGRIDX, ..): Define.
1867
1868         * interp.c (registers, register_widths, fpr_state, ipc, dspc,
1869         pending_*, hiaccess, loaccess, state, dsstate): Delete globals.
1870         (GPR, FGRIDX, ...): Delete macros.
1871
1872         * interp.c: Update names to match defines from sim-main.h
1873
1874 Tue Oct 14 15:11:45 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1875
1876         * interp.c (sim_monitor): Add SD argument.
1877         (sim_warning): Delete.  Replace calls with calls to
1878         sim_io_eprintf.
1879         (sim_error): Delete. Replace calls with sim_io_error.
1880         (open_trace, writeout32, writeout16, getnum): Add SD argument.
1881         (mips_set_profile): Rename from sim_set_profile. Add SD argument.
1882         (mips_set_profile_size): Rename from sim_set_profile_size. Add SD
1883         argument.
1884         (mips_size): Rename from sim_size. Add SD argument.
1885
1886         * interp.c (simulator): Delete global variable.
1887         (callback): Delete global variable.
1888         (mips_option_handler, sim_open, sim_write, sim_read,
1889         sim_store_register, sim_fetch_register, sim_info, sim_do_command,
1890         sim_size,sim_monitor): Use sim_io_* not callback->*.
1891         (sim_open): ZALLOC simulator struct.
1892         (PROFILE): Do not define.
1893
1894 Tue Oct 14 13:35:48 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1895
1896         * interp.c (sim_open), support.h: Replace CHECKSIM macro found in
1897         support.h with corresponding code.
1898
1899         * sim-main.h (word64, uword64), support.h: Move definition to
1900         sim-main.h.
1901         (WORD64LO, WORD64HI, SET64LO, SET64HI, WORD64, UWORD64): Ditto.
1902
1903         * support.h: Delete
1904         * Makefile.in: Update dependencies
1905         * interp.c: Do not include.
1906
1907 Tue Oct 14 13:35:48 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1908
1909         * interp.c (address_translation, load_memory, store_memory,
1910         cache_op): Rename to from AddressTranslation et.al., make global,
1911         add SD argument
1912
1913         * sim-main.h (AddressTranslation, LoadMemory, StoreMemory,
1914         CacheOp): Define.
1915
1916         * interp.c (SignalException): Rename to signal_exception, make
1917         global.
1918
1919         * interp.c (Interrupt, ...): Move definitions to sim-main.h.
1920
1921         * sim-main.h (SignalException, SignalExceptionInterrupt,
1922         SignalExceptionInstructionFetch, SignalExceptionAddressStore,
1923         SignalExceptionAddressLoad, SignalExceptionSimulatorFault,
1924         SignalExceptionIntegerOverflow, SignalExceptionCoProcessorUnusable):
1925         Define.
1926
1927         * interp.c, support.h: Use.
1928
1929 Tue Oct 14 13:19:20 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1930
1931         * interp.c (ValueFPR, StoreFPR), sim-main.h: Make global, rename
1932         to value_fpr / store_fpr. Add SD argument.
1933         (NaN, Infinity, Less, Equal, AbsoluteValue, Negate, Add, Sub,
1934         Multiply, Divide, Recip, SquareRoot, Convert): Make global.
1935
1936         * sim-main.h (ValueFPR, StoreFPR): Define.
1937
1938 Tue Oct 14 13:06:55 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1939
1940         * interp.c (sim_engine_run): Check consistency between configure
1941         WITH_TARGET_WORD_BITSIZE and WITH_FLOATING_POINT and gensim GPRLEN
1942         and HASFPU.
1943
1944         * configure.in (mips_bitsize): Configure WITH_TARGET_WORD_BITSIZE.
1945         (mips_fpu): Configure WITH_FLOATING_POINT.
1946         (mips_endian): Configure WITH_TARGET_ENDIAN.
1947         * configure: Update.
1948
1949 Fri Oct  3 09:28:00 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1950
1951         * configure: Regenerated to track ../common/aclocal.m4 changes.
1952
1953 Mon Sep 29 14:45:00 1997  Bob Manson  <manson@charmed.cygnus.com>
1954
1955         * configure: Regenerated.
1956
1957 Fri Sep 26 12:48:18 1997  Mark Alexander  <marka@cygnus.com>
1958
1959         * interp.c: Allow Debug, DEPC, and EPC registers to be examined in GDB.
1960
1961 Thu Sep 25 11:15:22 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1962
1963         * gencode.c (print_igen_insn_models): Assume certain architectures
1964         include all mips* instructions.
1965         (print_igen_insn_format): Use data_size==-1 as marker for MIPS16
1966         instruction.
1967
1968         * Makefile.in (tmp.igen): Add target. Generate igen input from
1969         gencode file.
1970
1971         * gencode.c (FEATURE_IGEN): Define.
1972         (main): Add --igen option.  Generate output in igen format.
1973         (process_instructions): Format output according to igen option.
1974         (print_igen_insn_format): New function.
1975         (print_igen_insn_models): New function.
1976         (process_instructions): Only issue warnings and ignore
1977         instructions when no FEATURE_IGEN.
1978
1979 Wed Sep 24 17:38:57 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1980
1981         * interp.c (COP_SD, COP_LD): Add UNUSED to pacify GCC for some
1982         MIPS targets.
1983
1984 Tue Sep 23 11:04:38 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1985
1986         * configure: Regenerated to track ../common/aclocal.m4 changes.
1987
1988 Tue Sep 23 10:19:51 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1989
1990         * Makefile.in (SIM_ALIGNMENT, SIM_ENDIAN, SIM_HOSTENDIAN,
1991         SIM_RESERVED_BITS): Delete, moved to common.
1992         (SIM_EXTRA_CFLAGS): Update.
1993
1994 Mon Sep 22 11:46:20 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1995
1996         * configure.in: Configure non-strict memory alignment.
1997         * configure: Regenerated to track ../common/aclocal.m4 changes.
1998
1999 Fri Sep 19 17:45:25 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2000
2001         * configure: Regenerated to track ../common/aclocal.m4 changes.
2002
2003 Sat Sep 20 14:07:28 1997  Gavin Koch  <gavin@cygnus.com>
2004
2005         * gencode.c (SDBBP,DERET): Added (3900) insns.
2006         (RFE): Turn on for 3900.
2007         * interp.c (DebugBreakPoint,DEPC,Debug,Debug_*): Added.
2008         (dsstate): Made global.
2009         (SUBTARGET_R3900): Added.
2010         (CANCELDELAYSLOT): New.
2011         (SignalException): Ignore SystemCall rather than ignore and
2012         terminate.  Add DebugBreakPoint handling.
2013         (decode_coproc): New insns RFE, DERET; and new registers Debug
2014         and DEPC protected by SUBTARGET_R3900.
2015         (sim_engine_run): Use CANCELDELAYSLOT rather than clearing
2016         bits explicitly.
2017         * Makefile.in,configure.in: Add mips subtarget option.
2018         * configure: Update.
2019
2020 Fri Sep 19 09:33:27 1997  Gavin Koch  <gavin@cygnus.com>
2021
2022         * gencode.c: Add r3900 (tx39).
2023
2024
2025 Tue Sep 16 15:52:04 1997  Gavin Koch  <gavin@cygnus.com>
2026
2027         * gencode.c (build_instruction): Don't need to subtract 4 for
2028         JALR, just 2.
2029
2030 Tue Sep 16 11:32:28 1997  Gavin Koch  <gavin@cygnus.com>
2031
2032         * interp.c: Correct some HASFPU problems.
2033
2034 Mon Sep 15 17:36:15 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2035
2036         * configure: Regenerated to track ../common/aclocal.m4 changes.
2037
2038 Fri Sep 12 12:01:39 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2039
2040         * interp.c (mips_options): Fix samples option short form, should
2041         be `x'.
2042
2043 Thu Sep 11 09:35:29 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2044
2045         * interp.c (sim_info): Enable info code.  Was just returning.
2046
2047 Tue Sep  9 17:30:57 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2048
2049         * interp.c (decode_coproc): Clarify warning about unsuported MTC0,
2050         MFC0.
2051
2052 Tue Sep  9 16:28:28 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2053
2054         * gencode.c (build_instruction): Use SIGNED64 for 64 bit
2055         constants.
2056         (build_instruction): Ditto for LL.
2057
2058 Thu Sep  4 17:21:23 1997  Doug Evans  <dje@seba>
2059
2060         * configure: Regenerated to track ../common/aclocal.m4 changes.
2061
2062 Wed Aug 27 18:13:22 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2063
2064         * configure: Regenerated to track ../common/aclocal.m4 changes.
2065         * config.in: Ditto.
2066
2067 Wed Aug 27 14:12:27 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2068
2069         * interp.c (sim_open): Add call to sim_analyze_program, update
2070         call to sim_config.
2071
2072 Tue Aug 26 10:40:07 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2073
2074         * interp.c (sim_kill): Delete.
2075         (sim_create_inferior): Add ABFD argument. Set PC from same.
2076         (sim_load): Move code initializing trap handlers from here.
2077         (sim_open): To here.
2078         (sim_load): Delete, use sim-hload.c.
2079
2080         * Makefile.in (SIM_OBJS): Add sim-hload.o module.
2081
2082 Mon Aug 25 17:50:22 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2083
2084         * configure: Regenerated to track ../common/aclocal.m4 changes.
2085         * config.in: Ditto.
2086
2087 Mon Aug 25 15:59:48 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2088
2089         * interp.c (sim_open): Add ABFD argument.
2090         (sim_load): Move call to sim_config from here.
2091         (sim_open): To here.  Check return status.
2092
2093 Fri Jul 25 15:00:45 1997  Gavin Koch  <gavin@cygnus.com>
2094
2095         * gencode.c (build_instruction): Two arg MADD should
2096         not assign result to $0.
2097
2098 Thu Jun 26 12:13:17 1997  Angela Marie Thomas (angela@cygnus.com)
2099
2100         * sim/mips/configure: Change default_sim_endian to 0 (bi-endian)
2101         * sim/mips/configure.in: Regenerate.
2102
2103 Wed Jul  9 10:29:21 1997  Andrew Cagney  <cagney@critters.cygnus.com>
2104
2105         * interp.c (SUB_REG_UW, SUB_REG_SW, SUB_REG_*): Use more explicit
2106         signed8, unsigned8 et.al. types.
2107
2108         * interp.c (SUB_REG_FETCH): Handle both little and big endian
2109         hosts when selecting subreg.
2110
2111 Wed Jul  2 11:54:10 1997  Jeffrey A Law  (law@cygnus.com)
2112
2113         * interp.c (sim_engine_run): Reset the ZERO register to zero
2114         regardless of FEATURE_WARN_ZERO.
2115         * gencode.c (FEATURE_WARNINGS): Remove FEATURE_WARN_ZERO.
2116
2117 Wed Jun  4 10:43:14 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2118
2119         * interp.c (decode_coproc): Implement MTC0 N, CAUSE.
2120         (SignalException): For BreakPoints ignore any mode bits and just
2121         save the PC.
2122         (SignalException): Always set the CAUSE register.
2123
2124 Tue Jun  3 05:00:33 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2125
2126         * interp.c (SignalException): Clear the simDELAYSLOT flag when an
2127         exception has been taken.
2128
2129         * interp.c: Implement the ERET and mt/f sr instructions.
2130
2131 Sat May 31 00:44:16 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2132
2133         * interp.c (SignalException): Don't bother restarting an
2134         interrupt.
2135
2136 Fri May 30 23:41:48 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2137
2138         * interp.c (SignalException): Really take an interrupt.
2139         (interrupt_event): Only deliver interrupts when enabled.
2140
2141 Tue May 27 20:08:06 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2142
2143         * interp.c (sim_info): Only print info when verbose.
2144         (sim_info) Use sim_io_printf for output.
2145
2146 Tue May 27 14:22:23 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2147
2148         * interp.c (CoProcPresent): Add UNUSED attribute - not used by all
2149         mips architectures.
2150
2151 Tue May 27 14:22:23 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2152
2153         * interp.c (sim_do_command): Check for common commands if a
2154         simulator specific command fails.
2155
2156 Thu May 22 09:32:03 1997  Gavin Koch  <gavin@cygnus.com>
2157
2158         * interp.c (sim_engine_run): ifdef out uses of simSTOP, simSTEP
2159         and simBE when DEBUG is defined.
2160
2161 Wed May 21 09:08:10 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2162
2163         * interp.c (interrupt_event): New function.  Pass exception event
2164         onto exception handler.
2165
2166         * configure.in: Check for stdlib.h.
2167         * configure: Regenerate.
2168
2169         * gencode.c (build_instruction): Add UNUSED attribute to tempS
2170         variable declaration.
2171         (build_instruction): Initialize memval1.
2172         (build_instruction): Add UNUSED attribute to byte, bigend,
2173         reverse.
2174         (build_operands): Ditto.
2175
2176         * interp.c: Fix GCC warnings.
2177         (sim_get_quit_code): Delete.
2178
2179         * configure.in: Add INLINE, ENDIAN, HOSTENDIAN and WARNINGS.
2180         * Makefile.in: Ditto.
2181         * configure: Re-generate.
2182
2183         * Makefile.in (SIM_OBJS): Add sim-watch.o module.
2184
2185 Tue May 20 15:08:56 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2186
2187         * interp.c (mips_option_handler): New function parse argumes using
2188         sim-options.
2189         (myname): Replace with STATE_MY_NAME.
2190         (sim_open): Delete check for host endianness - performed by
2191         sim_config.
2192         (simHOSTBE, simBE): Delete, replaced by sim-endian flags.
2193         (sim_open): Move much of the initialization from here.
2194         (sim_load): To here.  After the image has been loaded and
2195         endianness set.
2196         (sim_open): Move ColdReset from here.
2197         (sim_create_inferior): To here.
2198         (sim_open): Make FP check less dependant on host endianness.
2199
2200         * Makefile.in (SIM_RUN_OBJS): Set to nrun.o - use new version or
2201         run.
2202         * interp.c (sim_set_callbacks): Delete.
2203
2204         * interp.c (membank, membank_base, membank_size): Replace with
2205         STATE_MEMORY, STATE_MEM_SIZE, STATE_MEM_BASE.
2206         (sim_open): Remove call to callback->init. gdb/run do this.
2207
2208         * interp.c: Update
2209
2210         * sim-main.h (SIM_HAVE_FLATMEM): Define.
2211
2212         * interp.c (big_endian_p): Delete, replaced by
2213         current_target_byte_order.
2214
2215 Tue May 20 13:55:00 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2216
2217         * interp.c (host_read_long, host_read_word, host_swap_word,
2218         host_swap_long): Delete. Using common sim-endian.
2219         (sim_fetch_register, sim_store_register): Use H2T.
2220         (pipeline_ticks): Delete.  Handled by sim-events.
2221         (sim_info): Update.
2222         (sim_engine_run): Update.
2223
2224 Tue May 20 13:42:03 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2225
2226         * interp.c (sim_stop_reason): Move code determining simEXCEPTION
2227         reason from here.
2228         (SignalException): To here. Signal using sim_engine_halt.
2229         (sim_stop_reason): Delete, moved to common.
2230
2231 Tue May 20 10:19:48 1997  Andrew Cagney  <cagney@b2.cygnus.com>
2232
2233         * interp.c (sim_open): Add callback argument.
2234         (sim_set_callbacks): Delete SIM_DESC argument.
2235         (sim_size): Ditto.
2236
2237 Mon May 19 18:20:38 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2238
2239         * Makefile.in (SIM_OBJS): Add common modules.
2240
2241         * interp.c (sim_set_callbacks): Also set SD callback.
2242         (set_endianness, xfer_*, swap_*): Delete.
2243         (host_read_word, host_read_long, host_swap_word, host_swap_long):
2244         Change to functions using sim-endian macros.
2245         (control_c, sim_stop): Delete, use common version.
2246         (simulate): Convert into.
2247         (sim_engine_run): This function.
2248         (sim_resume): Delete.
2249
2250         * interp.c (simulation): New variable - the simulator object.
2251         (sim_kind): Delete global - merged into simulation.
2252         (sim_load): Cleanup.  Move PC assignment from here.
2253         (sim_create_inferior): To here.
2254
2255         * sim-main.h: New file.
2256         * interp.c (sim-main.h): Include.
2257
2258 Thu Apr 24 00:39:51 1997  Doug Evans  <dje@canuck.cygnus.com>
2259
2260         * configure: Regenerated to track ../common/aclocal.m4 changes.
2261
2262 Wed Apr 23 17:32:19 1997  Doug Evans  <dje@canuck.cygnus.com>
2263
2264         * tconfig.in (SIM_HAVE_BIENDIAN): Define.
2265
2266 Mon Apr 21 17:16:13 1997  Gavin Koch  <gavin@cygnus.com>
2267
2268         * gencode.c (build_instruction): DIV instructions: check
2269         for division by zero and integer overflow before using
2270         host's division operation.
2271
2272 Thu Apr 17 03:18:14 1997  Doug Evans  <dje@canuck.cygnus.com>
2273
2274         * Makefile.in (SIM_OBJS): Add sim-load.o.
2275         * interp.c: #include bfd.h.
2276         (target_byte_order): Delete.
2277         (sim_kind, myname, big_endian_p): New static locals.
2278         (sim_open): Set sim_kind, myname.  Move call to set_endianness to
2279         after argument parsing.  Recognize -E arg, set endianness accordingly.
2280         (sim_load): Return SIM_RC.  New arg abfd.  Call sim_load_file to
2281         load file into simulator.  Set PC from bfd.
2282         (sim_create_inferior): Return SIM_RC.  Delete arg start_address.
2283         (set_endianness): Use big_endian_p instead of target_byte_order.
2284
2285 Wed Apr 16 17:55:37 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2286
2287         * interp.c (sim_size): Delete prototype - conflicts with
2288         definition in remote-sim.h.  Correct definition.
2289
2290 Mon Apr  7 15:45:02 1997  Andrew Cagney  <cagney@kremvax.cygnus.com>
2291
2292         * configure: Regenerated to track ../common/aclocal.m4 changes.
2293         * config.in: Ditto.
2294
2295 Wed Apr  2 15:06:28 1997  Doug Evans  <dje@canuck.cygnus.com>
2296
2297         * interp.c (sim_open): New arg `kind'.
2298
2299         * configure: Regenerated to track ../common/aclocal.m4 changes.
2300
2301 Wed Apr  2 14:34:19 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
2302
2303         * configure: Regenerated to track ../common/aclocal.m4 changes.
2304
2305 Tue Mar 25 11:38:22 1997  Doug Evans  <dje@canuck.cygnus.com>
2306
2307         * interp.c (sim_open): Set optind to 0 before calling getopt.
2308
2309 Wed Mar 19 01:14:00 1997  Andrew Cagney  <cagney@kremvax.cygnus.com>
2310
2311         * configure: Regenerated to track ../common/aclocal.m4 changes.
2312
2313 Mon Mar 17 10:52:59 1997  Gavin Koch  <gavin@cetus.cygnus.com>
2314
2315         * interp.c : Replace uses of pr_addr with pr_uword64
2316         where the bit length is always 64 independent of SIM_ADDR.
2317         (pr_uword64) : added.
2318
2319 Mon Mar 17 15:10:07 1997  Andrew Cagney  <cagney@kremvax.cygnus.com>
2320
2321         * configure: Re-generate.
2322
2323 Fri Mar 14 10:34:11 1997  Michael Meissner  <meissner@cygnus.com>
2324
2325         * configure: Regenerate to track ../common/aclocal.m4 changes.
2326
2327 Thu Mar 13 12:51:36 1997  Doug Evans  <dje@canuck.cygnus.com>
2328
2329         * interp.c (sim_open): New SIM_DESC result.  Argument is now
2330         in argv form.
2331         (other sim_*): New SIM_DESC argument.
2332
2333 Mon Feb 24 22:47:14 1997  Dawn Perchik  <dawn@cygnus.com>
2334
2335         * interp.c: Fix printing of addresses for non-64-bit targets.
2336         (pr_addr): Add function to print address based on size.
2337
2338 Wed Feb 19 14:42:09 1997  Mark Alexander  <marka@cygnus.com>
2339
2340         * interp.c (simopen): Add support for LSI MiniRISC PMON vectors.
2341
2342 Thu Feb 13 14:08:30 1997  Ian Lance Taylor  <ian@cygnus.com>
2343
2344         * gencode.c (build_mips16_operands): Correct computation of base
2345         address for extended PC relative instruction.
2346
2347 Thu Feb  6 17:16:15 1997  Ian Lance Taylor  <ian@cygnus.com>
2348
2349         * interp.c (mips16_entry): Add support for floating point cases.
2350         (SignalException): Pass floating point cases to mips16_entry.
2351         (ValueFPR): Don't restrict fmt_single and fmt_word to even
2352         registers.
2353         (StoreFPR): Likewise.  Also, don't clobber fpr + 1 for fmt_single
2354         or fmt_word.
2355         (COP_LW): Pass fmt_word rather than fmt_uninterpreted to StoreFPR,
2356         and then set the state to fmt_uninterpreted.
2357         (COP_SW): Temporarily set the state to fmt_word while calling
2358         ValueFPR.
2359
2360 Tue Feb  4 16:48:25 1997  Ian Lance Taylor  <ian@cygnus.com>
2361
2362         * gencode.c (build_instruction): The high order may be set in the
2363         comparison flags at any ISA level, not just ISA 4.
2364
2365 Tue Feb  4 13:33:30 1997  Doug Evans  <dje@canuck.cygnus.com>
2366
2367         * Makefile.in (@COMMON_MAKEFILE_FRAG): Use
2368         COMMON_{PRE,POST}_CONFIG_FRAG instead.
2369         * configure.in: sinclude ../common/aclocal.m4.
2370         * configure: Regenerated.
2371
2372 Fri Jan 31 11:11:45 1997  Ian Lance Taylor  <ian@cygnus.com>
2373
2374         * configure: Rebuild after change to aclocal.m4.
2375
2376 Thu Jan 23 11:46:23 1997  Stu Grossman  (grossman@critters.cygnus.com)
2377
2378         * configure configure.in Makefile.in:  Update to new configure
2379         scheme which is more compatible with WinGDB builds.
2380         * configure.in:  Improve comment on how to run autoconf.
2381         * configure:  Re-run autoconf to get new ../common/aclocal.m4.
2382         * Makefile.in:  Use autoconf substitution to install common
2383         makefile fragment.
2384
2385 Wed Jan  8 12:39:03 1997  Jim Wilson  <wilson@cygnus.com>
2386
2387         * gencode.c (build_instruction): Use BigEndianCPU instead of
2388         ByteSwapMem.
2389
2390 Thu Jan 02 22:23:04 1997  Mark Alexander  <marka@cygnus.com>
2391
2392         * interp.c (sim_monitor): Make output to stdout visible in
2393         wingdb's I/O log window.
2394
2395 Tue Dec 31 07:04:00 1996  Mark Alexander  <marka@cygnus.com>
2396
2397         * support.h: Undo previous change to SIGTRAP
2398         and SIGQUIT values.
2399
2400 Mon Dec 30 17:36:06 1996  Ian Lance Taylor  <ian@cygnus.com>
2401
2402         * interp.c (store_word, load_word): New static functions.
2403         (mips16_entry): New static function.
2404         (SignalException): Look for mips16 entry and exit instructions.
2405         (simulate): Use the correct index when setting fpr_state after
2406         doing a pending move.
2407
2408 Sun Dec 29 09:37:18 1996  Mark Alexander  <marka@cygnus.com>
2409
2410         * interp.c: Fix byte-swapping code throughout to work on
2411         both little- and big-endian hosts.
2412
2413 Sun Dec 29 09:18:32 1996  Mark Alexander  <marka@cygnus.com>
2414
2415         * support.h: Make definitions of SIGTRAP and SIGQUIT consistent
2416         with gdb/config/i386/xm-windows.h.
2417
2418 Fri Dec 27 22:48:51 1996  Mark Alexander  <marka@cygnus.com>
2419
2420         * gencode.c (build_instruction): Work around MSVC++ code gen bug
2421         that messes up arithmetic shifts.
2422
2423 Fri Dec 20 11:04:05 1996  Stu Grossman  (grossman@critters.cygnus.com)
2424
2425         * support.h:  Use _WIN32 instead of __WIN32__.  Also add defs for
2426         SIGTRAP and SIGQUIT for _WIN32.
2427
2428 Thu Dec 19 14:07:27 1996  Ian Lance Taylor  <ian@cygnus.com>
2429
2430         * gencode.c (build_instruction) [MUL]: Cast operands to word64, to
2431         force a 64 bit multiplication.
2432         (build_instruction) [OR]: In mips16 mode, don't do anything if the
2433         destination register is 0, since that is the default mips16 nop
2434         instruction.
2435
2436 Mon Dec 16 14:59:38 1996  Ian Lance Taylor  <ian@cygnus.com>
2437
2438         * gencode.c (MIPS16_DECODE): SWRASP is I8, not RI.
2439         (build_endian_shift): Don't check proc64.
2440         (build_instruction): Always set memval to uword64.  Cast op2 to
2441         uword64 when shifting it left in memory instructions.  Always use
2442         the same code for stores--don't special case proc64.
2443
2444         * gencode.c (build_mips16_operands): Fix base PC value for PC
2445         relative operands.
2446         (build_instruction): Call JALDELAYSLOT rather than DELAYSLOT for a
2447         jal instruction.
2448         * interp.c (simJALDELAYSLOT): Define.
2449         (JALDELAYSLOT): Define.
2450         (INDELAYSLOT, INJALDELAYSLOT): Define.
2451         (simulate): Clear simJALDELAYSLOT when simDELAYSLOT is cleared.
2452
2453 Tue Dec 24 22:11:20 1996  Angela Marie Thomas (angela@cygnus.com)
2454
2455         * interp.c (sim_open): add flush_cache as a PMON routine
2456         (sim_monitor): handle flush_cache by ignoring it
2457
2458 Wed Dec 11 13:53:51 1996  Jim Wilson  <wilson@cygnus.com>
2459
2460         * gencode.c (build_instruction): Use !ByteSwapMem instead of
2461         BigEndianMem.
2462         * interp.c (CONFIG, config_EP_{mask,shift,D,DxxDxx, config_BE): Delete.
2463         (BigEndianMem): Rename to ByteSwapMem and change sense.
2464         (BigEndianCPU, sim_write, LoadMemory, StoreMemory): Change
2465         BigEndianMem references to !ByteSwapMem.
2466         (set_endianness): New function, with prototype.
2467         (sim_open): Call set_endianness.
2468         (sim_info): Use simBE instead of BigEndianMem.
2469         (xfer_direct_word, xfer_direct_long, swap_direct_word,
2470         swap_direct_long, xfer_big_word, xfer_big_long, xfer_little_word,
2471         xfer_little_long, swap_word, swap_long): Delete unnecessary MSC_VER
2472         ifdefs, keeping the prototype declaration.
2473         (swap_word): Rewrite correctly.
2474         (ColdReset): Delete references to CONFIG.  Delete endianness related
2475         code; moved to set_endianness.
2476
2477 Tue Dec 10 11:32:04 1996  Jim Wilson  <wilson@cygnus.com>
2478
2479         * gencode.c (build_instruction, case JUMP): Truncate PC to 32 bits.
2480         * interp.c (CHECKHILO): Define away.
2481         (simSIGINT): New macro.
2482         (membank_size): Increase from 1MB to 2MB.
2483         (control_c): New function.
2484         (sim_resume): Rename parameter signal to signal_number.  Add local
2485         variable prev.  Call signal before and after simulate.
2486         (sim_stop_reason): Add simSIGINT support.
2487         (sim_warning, sim_error, dotrace, SignalException): Define as stdarg
2488         functions always.
2489         (sim_warning): Delete call to SignalException.  Do call printf_filtered
2490         if logfh is NULL.
2491         (AddressTranslation): Add #ifdef DEBUG around debugging message and
2492         a call to sim_warning.
2493
2494 Wed Nov 27 11:53:50 1996  Ian Lance Taylor  <ian@cygnus.com>
2495
2496         * gencode.c (process_instructions): If ! proc64, skip DOUBLEWORD
2497         16 bit instructions.
2498
2499 Tue Nov 26 11:53:12 1996  Ian Lance Taylor  <ian@cygnus.com>
2500
2501         Add support for mips16 (16 bit MIPS implementation):
2502         * gencode.c (inst_type): Add mips16 instruction encoding types.
2503         (GETDATASIZEINSN): Define.
2504         (MIPS_DECODE): Add REG flag to dsllv, dsrav, and dsrlv.  Add
2505         jalx.  Add LEFT flag to mfhi and mflo.  Add RIGHT flag to mthi and
2506         mtlo.
2507         (MIPS16_DECODE): New table, for mips16 instructions.
2508         (bitmap_val): New static function.
2509         (struct mips16_op): Define.
2510         (mips16_op_table): New table, for mips16 operands.
2511         (build_mips16_operands): New static function.
2512         (process_instructions): If PC is odd, decode a mips16
2513         instruction.  Break out instruction handling into new
2514         build_instruction function.
2515         (build_instruction): New static function, broken out of
2516         process_instructions.  Check modifiers rather than flags for SHIFT
2517         bit count and m[ft]{hi,lo} direction.
2518         (usage): Pass program name to fprintf.
2519         (main): Remove unused variable this_option_optind.  Change
2520         ``*loptarg++'' to ``loptarg++''.
2521         (my_strtoul): Parenthesize && within ||.
2522         * interp.c (LoadMemory): Accept a halfword pAddr if vAddr is odd.
2523         (simulate): If PC is odd, fetch a 16 bit instruction, and
2524         increment PC by 2 rather than 4.
2525         * configure.in: Add case for mips16*-*-*.
2526         * configure: Rebuild.
2527
2528 Fri Nov 22 08:49:36 1996  Mark Alexander  <marka@cygnus.com>
2529
2530         * interp.c: Allow -t to enable tracing in standalone simulator.
2531         Fix garbage output in trace file and error messages.
2532
2533 Wed Nov 20 01:54:37 1996  Doug Evans  <dje@canuck.cygnus.com>
2534
2535         * Makefile.in: Delete stuff moved to ../common/Make-common.in.
2536         (SIM_{OBJS,EXTRA_CFLAGS,EXTRA_CLEAN}): Define.
2537         * configure.in: Simplify using macros in ../common/aclocal.m4.
2538         * configure: Regenerated.
2539         * tconfig.in: New file.
2540
2541 Tue Nov 12 13:34:00 1996  Dawn Perchik  <dawn@cygnus.com>
2542
2543         * interp.c: Fix bugs in 64-bit port.
2544         Use ansi function declarations for msvc compiler.
2545         Initialize and test file pointer in trace code.
2546         Prevent duplicate definition of LAST_EMED_REGNUM.
2547
2548 Tue Oct 15 11:07:06 1996  Mark Alexander  <marka@cygnus.com>
2549
2550         * interp.c (xfer_big_long): Prevent unwanted sign extension.
2551
2552 Thu Sep 26 17:35:00 1996  James G. Smith  <jsmith@cygnus.co.uk>
2553
2554         * interp.c (SignalException): Check for explicit terminating
2555         breakpoint value.
2556         * gencode.c: Pass instruction value through SignalException()
2557         calls for Trap, Breakpoint and Syscall.
2558
2559 Thu Sep 26 11:35:17 1996  James G. Smith  <jsmith@cygnus.co.uk>
2560
2561         * interp.c (SquareRoot): Add HAVE_SQRT check to ensure sqrt() is
2562         only used on those hosts that provide it.
2563         * configure.in: Add sqrt() to list of functions to be checked for.
2564         * config.in: Re-generated.
2565         * configure: Re-generated.
2566
2567 Fri Sep 20 15:47:12 1996  Ian Lance Taylor  <ian@cygnus.com>
2568
2569         * gencode.c (process_instructions): Call build_endian_shift when
2570         expanding STORE RIGHT, to fix swr.
2571         * support.h (SIGNEXTEND): If the sign bit is not set, explicitly
2572         clear the high bits.
2573         * interp.c (Convert): Fix fmt_single to fmt_long to not truncate.
2574         Fix float to int conversions to produce signed values.
2575
2576 Thu Sep 19 15:34:17 1996  Ian Lance Taylor  <ian@cygnus.com>
2577
2578         * gencode.c (MIPS_DECODE): Set UNSIGNED for multu instruction.
2579         (process_instructions): Correct handling of nor instruction.
2580         Correct shift count for 32 bit shift instructions. Correct sign
2581         extension for arithmetic shifts to not shift the number of bits in
2582         the type.  Fix 64 bit multiply high word calculation.  Fix 32 bit
2583         unsigned multiply.  Fix ldxc1 and friends to use coprocessor 1.
2584         Fix madd.
2585         * interp.c (CHECKHILO): Don't set HIACCESS, LOACCESS, or HLPC.
2586         It's OK to have a mult follow a mult.  What's not OK is to have a
2587         mult follow an mfhi.
2588         (Convert): Comment out incorrect rounding code.
2589
2590 Mon Sep 16 11:38:16 1996  James G. Smith  <jsmith@cygnus.co.uk>
2591
2592         * interp.c (sim_monitor): Improved monitor printf
2593         simulation. Tidied up simulator warnings, and added "--log" option
2594         for directing warning message output.
2595         * gencode.c: Use sim_warning() rather than WARNING macro.
2596
2597 Thu Aug 22 15:03:12 1996  Ian Lance Taylor  <ian@cygnus.com>
2598
2599         * Makefile.in (gencode): Depend upon gencode.o, getopt.o, and
2600         getopt1.o, rather than on gencode.c.  Link objects together.
2601         Don't link against -liberty.
2602         (gencode.o, getopt.o, getopt1.o): New targets.
2603         * gencode.c: Include <ctype.h> and "ansidecl.h".
2604         (AND): Undefine after including "ansidecl.h".
2605         (ULONG_MAX): Define if not defined.
2606         (OP_*): Don't define macros; now defined in opcode/mips.h.
2607         (main): Call my_strtoul rather than strtoul.
2608         (my_strtoul): New static function.
2609
2610 Wed Jul 17 18:12:38 1996  Stu Grossman  (grossman@critters.cygnus.com)
2611
2612         * gencode.c (process_instructions):  Generate word64 and uword64
2613         instead of `long long' and `unsigned long long' data types.
2614         * interp.c:  #include sysdep.h to get signals, and define default
2615         for SIGBUS.
2616         * (Convert):  Work around for Visual-C++ compiler bug with type
2617         conversion.
2618         * support.h:  Make things compile under Visual-C++ by using
2619         __int64 instead of `long long'.  Change many refs to long long
2620         into word64/uword64 typedefs.
2621
2622 Wed Jun 26 12:24:55 1996  Jason Molenda  (crash@godzilla.cygnus.co.jp)
2623
2624         * Makefile.in (bindir, libdir, datadir, mandir, infodir, includedir,
2625         INSTALL_PROGRAM, INSTALL_DATA): Use autoconf-set values.
2626         (docdir): Removed.
2627         * configure.in (AC_PREREQ): autoconf 2.5 or higher.
2628         (AC_PROG_INSTALL): Added.
2629         (AC_PROG_CC): Moved to before configure.host call.
2630         * configure: Rebuilt.
2631
2632 Wed Jun  5 08:28:13 1996  James G. Smith  <jsmith@cygnus.co.uk>
2633
2634         * configure.in: Define @SIMCONF@ depending on mips target.
2635         * configure: Rebuild.
2636         * Makefile.in (run): Add @SIMCONF@ to control simulator
2637         construction.
2638         * gencode.c: Change LOADDRMASK to 64bit memory model only.
2639         * interp.c: Remove some debugging, provide more detailed error
2640         messages, update memory accesses to use LOADDRMASK.
2641
2642 Mon Jun  3 11:55:03 1996  Ian Lance Taylor  <ian@cygnus.com>
2643
2644         * configure.in: Add calls to AC_CONFIG_HEADER, AC_CHECK_HEADERS,
2645         AC_CHECK_LIB, and AC_CHECK_FUNCS.  Change AC_OUTPUT to set
2646         stamp-h.
2647         * configure: Rebuild.
2648         * config.in: New file, generated by autoheader.
2649         * interp.c: Include "config.h".  Include <stdlib.h>, <string.h>,
2650         and <strings.h> if they exist.  Replace #ifdef sun with #ifdef
2651         HAVE_ANINT and HAVE_AINT, as appropriate.
2652         * Makefile.in (run): Use @LIBS@ rather than -lm.
2653         (interp.o): Depend upon config.h.
2654         (Makefile): Just rebuild Makefile.
2655         (clean): Remove stamp-h.
2656         (mostlyclean): Make the same as clean, not as distclean.
2657         (config.h, stamp-h): New targets.
2658
2659 Fri May 10 00:41:17 1996  James G. Smith  <jsmith@cygnus.co.uk>
2660
2661         * interp.c (ColdReset): Fix boolean test. Make all simulator
2662         globals static.
2663
2664 Wed May  8 15:12:58 1996  James G. Smith  <jsmith@cygnus.co.uk>
2665
2666         * interp.c (xfer_direct_word, xfer_direct_long,
2667         swap_direct_word, swap_direct_long, xfer_big_word,
2668         xfer_big_long, xfer_little_word, xfer_little_long,
2669         swap_word,swap_long): Added.
2670         * interp.c (ColdReset): Provide function indirection to
2671         host<->simulated_target transfer routines.
2672         * interp.c (sim_store_register, sim_fetch_register): Updated to
2673         make use of indirected transfer routines.
2674
2675 Fri Apr 19 15:48:24 1996  James G. Smith  <jsmith@cygnus.co.uk>
2676
2677         * gencode.c (process_instructions): Ensure FP ABS instruction
2678         recognised.
2679         * interp.c (AbsoluteValue): Add routine. Also provide simple PMON
2680         system call support.
2681
2682 Wed Apr 10 09:51:38 1996  James G. Smith  <jsmith@cygnus.co.uk>
2683
2684         * interp.c (sim_do_command): Complain if callback structure not
2685         initialised.
2686
2687 Thu Mar 28 13:50:51 1996  James G. Smith  <jsmith@cygnus.co.uk>
2688
2689         * interp.c (Convert): Provide round-to-nearest and round-to-zero
2690         support for Sun hosts.
2691         * Makefile.in (gencode): Ensure the host compiler and libraries
2692         used for cross-hosted build.
2693
2694 Wed Mar 27 14:42:12 1996  James G. Smith  <jsmith@cygnus.co.uk>
2695
2696         * interp.c, gencode.c: Some more (TODO) tidying.
2697
2698 Thu Mar  7 11:19:33 1996  James G. Smith  <jsmith@cygnus.co.uk>
2699
2700         * gencode.c, interp.c: Replaced explicit long long references with
2701         WORD64HI, WORD64LO, SET64HI and SET64LO macro calls.
2702         * support.h (SET64LO, SET64HI): Macros added.
2703
2704 Wed Feb 21 12:16:21 1996  Ian Lance Taylor  <ian@cygnus.com>
2705
2706         * configure: Regenerate with autoconf 2.7.
2707
2708 Tue Jan 30 08:48:18 1996  Fred Fish  <fnf@cygnus.com>
2709
2710         * interp.c (LoadMemory): Enclose text following #endif in /* */.
2711         * support.h: Remove superfluous "1" from #if.
2712         * support.h (CHECKSIM): Remove stray 'a' at end of line.
2713
2714 Mon Dec  4 11:44:40 1995  Jamie Smith  <jsmith@cygnus.com>
2715
2716         * interp.c (StoreFPR): Control UndefinedResult() call on
2717         WARN_RESULT manifest.
2718
2719 Fri Dec  1 16:37:19 1995  James G. Smith  <jsmith@cygnus.co.uk>
2720
2721         * gencode.c: Tidied instruction decoding, and added FP instruction
2722         support.
2723
2724         * interp.c: Added dineroIII, and BSD profiling support. Also
2725         run-time FP handling.
2726
2727 Sun Oct 22 00:57:18 1995  James G. Smith  <jsmith@pasanda.cygnus.co.uk>
2728
2729         * Changelog, Makefile.in, README.Cygnus, configure, configure.in,
2730         gencode.c, interp.c, support.h: created.