sim/mips/cp1.h

   1 /*> cp1.h <*/
   2 /* MIPS Simulator FPU (CoProcessor 1) definitions.
   3    Copyright (C) 1997, 1998, 2002, 2007, 2008, 2009, 2010
   4    Free Software Foundation, Inc.
   5    Derived from sim-main.h contributed by Cygnus Solutions,
   6    modified substantially by Ed Satterthwaite of Broadcom Corporation
   7    (SiByte).
   8
   9 This file is part of GDB, the GNU debugger.
  10
  11 This program is free software; you can redistribute it and/or modify
  12 it under the terms of the GNU General Public License as published by
  13 the Free Software Foundation; either version 3 of the License, or
  14 (at your option) any later version.
  15
  16 This program is distributed in the hope that it will be useful,
  17 but WITHOUT ANY WARRANTY; without even the implied warranty of
  18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  19 GNU General Public License for more details.
  20
  21 You should have received a copy of the GNU General Public License
  22 along with this program.  If not, see <http://www.gnu.org/licenses/>.  */
  23
  24 #ifndef CP1_H
  25 #define CP1_H
  26
  27 /* See sim-main.h for allocation of registers FCR0 and FCR31 (FCSR)
  28    in CPU state (struct sim_cpu), and for FPU functions.  */
  29
  30 #define fcsr_FCC_mask      (0xFE800000)
  31 #define fcsr_FCC_shift     (23)
  32 #define fcsr_FCC_bit(cc)   ((cc) == 0 ? 23 : (24 + (cc)))
  33 #define fcsr_FS            (1 << 24) /* MIPS III onwards : Flush to Zero */
  34 #define fcsr_ZERO_mask     (0x007C0000)
  35 #define fcsr_CAUSE_mask    (0x0003F000)
  36 #define fcsr_CAUSE_shift   (12)
  37 #define fcsr_ENABLES_mask  (0x00000F80)
  38 #define fcsr_ENABLES_shift (7)
  39 #define fcsr_FLAGS_mask    (0x0000007C)
  40 #define fcsr_FLAGS_shift   (2)
  41 #define fcsr_RM_mask       (0x00000003)
  42 #define fcsr_RM_shift      (0)
  43
  44 #define fenr_FS            (0x00000004)
  45
  46 /* Macros to update and retrieve the FCSR condition-code bits.  This
  47    is complicated by the fact that there is a hole in the index range
  48    of the bits within the FCSR register.  (Note that the number of bits
  49    visible depends on the ISA in use, but that is handled elsewhere.)  */
  50 #define SETFCC(cc,v) \
  51   do { \
  52     (FCSR = ((FCSR & ~(1 << fcsr_FCC_bit(cc))) | ((v) << fcsr_FCC_bit(cc)))); \
  53   } while (0)
  54 #define GETFCC(cc) ((FCSR & (1 << fcsr_FCC_bit(cc))) != 0 ? 1 : 0)
  55
  56
  57 /* Read flush-to-zero bit (not right-justified).  */
  58 #define GETFS()            ((int)(FCSR & fcsr_FS))
  59
  60
  61 /* FCSR flag bits definitions and access macros.  */
  62 #define IR            0   /* I: Inexact Result */
  63 #define UF            1   /* U: UnderFlow */
  64 #define OF            2   /* O: OverFlow */
  65 #define DZ            3   /* Z: Division by Zero */
  66 #define IO            4   /* V: Invalid Operation */
  67 #define UO            5   /* E: Unimplemented Operation (CAUSE field only) */
  68
  69 #define FP_FLAGS(b)   (1 << ((b) + fcsr_FLAGS_shift))
  70 #define FP_ENABLE(b)  (1 << ((b) + fcsr_ENABLES_shift))
  71 #define FP_CAUSE(b)   (1 << ((b) + fcsr_CAUSE_shift))
  72
  73
  74 /* Rounding mode bit definitions and access macros.  */
  75 #define FP_RM_NEAREST 0   /* Round to nearest (Round).  */
  76 #define FP_RM_TOZERO  1   /* Round to zero (Trunc).  */
  77 #define FP_RM_TOPINF  2   /* Round to Plus infinity (Ceil).  */
  78 #define FP_RM_TOMINF  3   /* Round to Minus infinity (Floor).  */
  79
  80 #define GETRM()       ((FCSR >> fcsr_RM_shift) & fcsr_RM_mask)
  81
  82
  83 #endif /* CP1_H */