sim/mips/mips.igen

   1 // -*- C -*-
   2 //
   3 // In mips.igen, the semantics for many of the instructions were created
   4 // using code generated by gencode.  Those semantic segments could be
   5 // greatly simplified.
   6 //
   7 //    <insn> ::=
   8 //        <insn-word> { "+" <insn-word> }
   9 //        ":" <format-name>
  10 //        ":" <filter-flags>
  11 //        ":" <options>
  12 //        ":" <name>
  13 //        <nl>
  14 //        { <insn-model> }
  15 //        { <insn-mnemonic> }
  16 //        <code-block>
  17 //
  18
  19
  20 // IGEN config - mips16
  21 // :option:16::insn-bit-size:16
  22 // :option:16::hi-bit-nr:15
  23 :option:16::insn-specifying-widths:true
  24 :option:16::gen-delayed-branch:false
  25
  26 // IGEN config - mips32/64..
  27 // :option:32::insn-bit-size:32
  28 // :option:32::hi-bit-nr:31
  29 :option:32::insn-specifying-widths:true
  30 :option:32::gen-delayed-branch:false
  31
  32
  33 // Generate separate simulators for each target
  34 // :option:::multi-sim:true
  35
  36
  37 // Models known by this simulator
  38 :model:::mipsI:mips3000:
  39 :model:::mipsII:mips6000:
  40 :model:::mipsIII:mips4000:
  41 :model:::mipsIV:mips8000:
  42 :model:::mips16:mips16:
  43 :model:::r3900:mips3900:
  44 :model:::vr4100:mips4100:
  45 :model:::vr5000:mips5000:
  46
  47
  48
  49 // Pseudo instructions known by IGEN
  50 :internal::::illegal:
  51 {
  52   SignalException (ReservedInstruction, 0);
  53 }
  54
  55
  56 // Pseudo instructions known by interp.c
  57 // For grep - RSVD_INSTRUCTION, RSVD_INSTRUCTION_MASK
  58 000000,5.*,5.*,5.*,5.OP,000101:SPECIAL:32::RSVD
  59 "rsvd <OP>"
  60 {
  61   SignalException (ReservedInstruction, instruction_0);
  62 }
  63
  64
  65
  66 // Helper:
  67 //
  68 // Simulate a 32 bit delayslot instruction
  69 //
  70
  71 :function:::address_word:delayslot32:address_word target
  72 {
  73   instruction_word delay_insn;
  74   sim_events_slip (SD, 1);
  75   DSPC = CIA;
  76   CIA = CIA + 4; /* NOTE not mips16 */
  77   STATE |= simDELAYSLOT;
  78   delay_insn = IMEM32 (CIA); /* NOTE not mips16 */
  79   idecode_issue (CPU_, delay_insn, (CIA));
  80   STATE &= ~simDELAYSLOT;
  81   return target;
  82 }
  83
  84 :function:::address_word:nullify_next_insn32:
  85 {
  86   sim_events_slip (SD, 1);
  87   dotrace (SD, CPU, tracefh, 2, CIA + 4, 4, "load instruction");
  88   return CIA + 8;
  89 }
  90
  91 // Helper:
  92 //
  93 // Check that an access to a HI/LO register meets timing requirements
  94 //
  95 // The following requirements exist:
  96 //
  97 //   -  A MT {HI,LO} update was not immediatly preceeded by a MF {HI,LO} read
  98 //   -  A OP {HI,LO} update was not immediatly preceeded by a MF {HI,LO} read
  99 //   -  A MF {HI,LO} read was not corrupted by a preceeding MT{LO,HI} update
 100 //      corruption occures when MT{LO,HI} is preceeded by a OP {HI,LO}.
 101 //
 102
 103 :function:::int:check_mf_cycles:hilo_history *history, signed64 time, const char *new
 104 {
 105   if (history->mf.timestamp + 3 > time)
 106     {
 107       sim_engine_abort (SD, CPU, CIA, "HILO: %s: %s at 0x%08lx too close to MF at 0x%08lx\n",
 108                         itable[MY_INDEX].name,
 109                         new, (long) CIA,
 110                         (long) history->mf.cia);
 111       return 0;
 112     }
 113   return 1;
 114 }
 115
 116 :function:::int:check_mt_hilo:hilo_history *history
 117 *mipsI,mipsII,mipsIII,mipsIV:
 118 *vr4100:
 119 *vr5000:
 120 {
 121   signed64 time = sim_events_time (SD);
 122   int ok = check_mf_cycles (SD_, history, time, "MT");
 123   history->mt.timestamp = time;
 124   history->mt.cia = CIA;
 125   return ok;
 126 }
 127
 128 :function:::int:check_mt_hilo:hilo_history *history
 129 *r3900:
 130 {
 131   signed64 time = sim_events_time (SD);
 132   history->mt.timestamp = time;
 133   history->mt.cia = CIA;
 134   return 1;
 135 }
 136
 137
 138 :function:::int:check_mf_hilo:hilo_history *history, hilo_history *peer
 139 *mipsI,mipsII,mipsIII,mipsIV:
 140 *vr4100:
 141 *vr5000:
 142 *r3900:
 143 {
 144   signed64 time = sim_events_time (SD);
 145   int ok = 1;
 146   if (peer != NULL
 147       && peer->mt.timestamp > history->op.timestamp
 148       && history->mt.timestamp < history->op.timestamp
 149       && ! (history->mf.timestamp > history->op.timestamp
 150             && history->mf.timestamp < peer->mt.timestamp)
 151       && ! (peer->mf.timestamp > history->op.timestamp
 152             && peer->mf.timestamp < peer->mt.timestamp))
 153     {
 154       /* The peer has been written to since the last OP yet we have
 155          not */
 156       sim_engine_abort (SD, CPU, CIA, "HILO: %s: MF at 0x%08lx following OP at 0x%08lx corrupted by MT at 0x%08lx\n",
 157                         itable[MY_INDEX].name,
 158                         (long) CIA,
 159                         (long) history->op.cia,
 160                         (long) peer->mt.cia);
 161       ok = 0;
 162     }
 163   history->mf.timestamp = time;
 164   history->mf.cia = CIA;
 165   return ok;
 166 }
 167
 168
 169
 170 :function:::int:check_mult_hilo:hilo_history *hi, hilo_history *lo
 171 *mipsI,mipsII,mipsIII,mipsIV:
 172 *vr4100:
 173 *vr5000:
 174 {
 175   signed64 time = sim_events_time (SD);
 176   int ok = (check_mf_cycles (SD_, hi, time, "OP")
 177             && check_mf_cycles (SD_, lo, time, "OP"));
 178   hi->op.timestamp = time;
 179   lo->op.timestamp = time;
 180   hi->op.cia = CIA;
 181   lo->op.cia = CIA;
 182   return ok;
 183 }
 184
 185 // The r3900 mult and multu insns _can_ be exectuted immediatly after
 186 // a mf{hi,lo}
 187 :function:::int:check_mult_hilo:hilo_history *hi, hilo_history *lo
 188 *r3900:
 189 {
 190   /* FIXME: could record the fact that a stall occured if we want */
 191   signed64 time = sim_events_time (SD);
 192   hi->op.timestamp = time;
 193   lo->op.timestamp = time;
 194   hi->op.cia = CIA;
 195   lo->op.cia = CIA;
 196   return 1;
 197 }
 198
 199
 200 :function:::int:check_div_hilo:hilo_history *hi, hilo_history *lo
 201 *mipsI,mipsII,mipsIII,mipsIV:
 202 *vr4100:
 203 *vr5000:
 204 *r3900:
 205 {
 206   signed64 time = sim_events_time (SD);
 207   int ok = (check_mf_cycles (SD_, hi, time, "OP")
 208             && check_mf_cycles (SD_, lo, time, "OP"));
 209   hi->op.timestamp = time;
 210   lo->op.timestamp = time;
 211   hi->op.cia = CIA;
 212   lo->op.cia = CIA;
 213   return ok;
 214 }
 215
 216
 217
 218
 219
 220 //
 221 // Mips Architecture:
 222 //
 223 //        CPU Instruction Set (mipsI - mipsIV)
 224 //
 225
 226
 227
 228 000000,5.RS,5.RT,5.RD,00000,100000:SPECIAL:32::ADD
 229 "add r<RD>, r<RS>, r<RT>"
 230 *mipsI,mipsII,mipsIII,mipsIV:
 231 *vr4100:
 232 *vr5000:
 233 *r3900:
 234 {
 235   TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
 236   {
 237     ALU32_BEGIN (GPR[RS]);
 238     ALU32_ADD (GPR[RT]);
 239     ALU32_END (GPR[RD]);
 240   }
 241   TRACE_ALU_RESULT (GPR[RD]);
 242 }
 243
 244
 245
 246 001000,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::ADDI
 247 "addi r<RT>, r<RS>, IMMEDIATE"
 248 *mipsI,mipsII,mipsIII,mipsIV:
 249 *vr4100:
 250 *vr5000:
 251 *r3900:
 252 {
 253   TRACE_ALU_INPUT2 (GPR[RS], EXTEND16 (IMMEDIATE));
 254   {
 255     ALU32_BEGIN (GPR[RS]);
 256     ALU32_ADD (EXTEND16 (IMMEDIATE));
 257     ALU32_END (GPR[RT]);
 258   }
 259   TRACE_ALU_RESULT (GPR[RT]);
 260 }
 261
 262
 263
 264 :function:::void:do_addiu:int rs, int rt, unsigned16 immediate
 265 {
 266   TRACE_ALU_INPUT2 (GPR[rs], EXTEND16 (immediate));
 267   GPR[rt] = EXTEND32 (GPR[rs] + EXTEND16 (immediate));
 268   TRACE_ALU_RESULT (GPR[rt]);
 269 }
 270
 271 001001,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::ADDIU
 272 "addiu r<RT>, r<RS>, <IMMEDIATE>"
 273 *mipsI,mipsII,mipsIII,mipsIV:
 274 *vr4100:
 275 *vr5000:
 276 *r3900:
 277 {
 278   do_addiu (SD_, RS, RT, IMMEDIATE);
 279 }
 280
 281
 282
 283 :function:::void:do_addu:int rs, int rt, int rd
 284 {
 285   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
 286   GPR[rd] = EXTEND32 (GPR[rs] + GPR[rt]);
 287   TRACE_ALU_RESULT (GPR[rd]);
 288 }
 289
 290 000000,5.RS,5.RT,5.RD,00000,100001:SPECIAL:32::ADDU
 291 "addu r<RD>, r<RS>, r<RT>"
 292 *mipsI,mipsII,mipsIII,mipsIV:
 293 *vr4100:
 294 *vr5000:
 295 *r3900:
 296 {
 297   do_addu (SD_, RS, RT, RD);
 298 }
 299
 300
 301
 302 :function:::void:do_and:int rs, int rt, int rd
 303 {
 304   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
 305   GPR[rd] = GPR[rs] & GPR[rt];
 306   TRACE_ALU_RESULT (GPR[rd]);
 307 }
 308
 309 000000,5.RS,5.RT,5.RD,00000,100100:SPECIAL:32::AND
 310 "and r<RD>, r<RS>, r<RT>"
 311 *mipsI,mipsII,mipsIII,mipsIV:
 312 *vr4100:
 313 *vr5000:
 314 *r3900:
 315 {
 316   do_and (SD_, RS, RT, RD);
 317 }
 318
 319
 320
 321 001100,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::ANDI
 322 "and r<RT>, r<RS>, <IMMEDIATE>"
 323 *mipsI,mipsII,mipsIII,mipsIV:
 324 *vr4100:
 325 *vr5000:
 326 *r3900:
 327 {
 328   TRACE_ALU_INPUT2 (GPR[RS], IMMEDIATE);
 329   GPR[RT] = GPR[RS] & IMMEDIATE;
 330   TRACE_ALU_RESULT (GPR[RT]);
 331 }
 332
 333
 334
 335 000100,5.RS,5.RT,16.OFFSET:NORMAL:32::BEQ
 336 "beq r<RS>, r<RT>, <OFFSET>"
 337 *mipsI,mipsII,mipsIII,mipsIV:
 338 *vr4100:
 339 *vr5000:
 340 *r3900:
 341 {
 342   address_word offset = EXTEND16 (OFFSET) << 2;
 343   check_branch_bug ();
 344   if ((signed_word) GPR[RS] == (signed_word) GPR[RT])
 345     {
 346       mark_branch_bug (NIA+offset);
 347       DELAY_SLOT (NIA + offset);
 348     }
 349 }
 350
 351
 352
 353 010100,5.RS,5.RT,16.OFFSET:NORMAL:32::BEQL
 354 "beql r<RS>, r<RT>, <OFFSET>"
 355 *mipsII:
 356 *mipsIII:
 357 *mipsIV:
 358 *vr4100:
 359 *vr5000:
 360 *r3900:
 361 {
 362   address_word offset = EXTEND16 (OFFSET) << 2;
 363   check_branch_bug ();
 364   if ((signed_word) GPR[RS] == (signed_word) GPR[RT])
 365     {
 366       mark_branch_bug (NIA+offset);
 367       DELAY_SLOT (NIA + offset);
 368     }
 369   else
 370     NULLIFY_NEXT_INSTRUCTION ();
 371 }
 372
 373
 374
 375 000001,5.RS,00001,16.OFFSET:REGIMM:32::BGEZ
 376 "bgez r<RS>, <OFFSET>"
 377 *mipsI,mipsII,mipsIII,mipsIV:
 378 *vr4100:
 379 *vr5000:
 380 *r3900:
 381 {
 382   address_word offset = EXTEND16 (OFFSET) << 2;
 383   check_branch_bug ();
 384   if ((signed_word) GPR[RS] >= 0)
 385     {
 386       mark_branch_bug (NIA+offset);
 387       DELAY_SLOT (NIA + offset);
 388     }
 389 }
 390
 391
 392
 393 000001,5.RS!31,10001,16.OFFSET:REGIMM:32::BGEZAL
 394 "bgezal r<RS>, <OFFSET>"
 395 *mipsI,mipsII,mipsIII,mipsIV:
 396 *vr4100:
 397 *vr5000:
 398 *r3900:
 399 {
 400   address_word offset = EXTEND16 (OFFSET) << 2;
 401   check_branch_bug ();
 402   RA = (CIA + 8);
 403   if ((signed_word) GPR[RS] >= 0)
 404     {
 405       mark_branch_bug (NIA+offset);
 406       DELAY_SLOT (NIA + offset);
 407     }
 408 }
 409
 410
 411
 412 000001,5.RS!31,10011,16.OFFSET:REGIMM:32::BGEZALL
 413 "bgezall r<RS>, <OFFSET>"
 414 *mipsII:
 415 *mipsIII:
 416 *mipsIV:
 417 *vr4100:
 418 *vr5000:
 419 *r3900:
 420 {
 421   address_word offset = EXTEND16 (OFFSET) << 2;
 422   check_branch_bug ();
 423   RA = (CIA + 8);
 424   /* NOTE: The branch occurs AFTER the next instruction has been
 425      executed */
 426   if ((signed_word) GPR[RS] >= 0)
 427     {
 428       mark_branch_bug (NIA+offset);
 429       DELAY_SLOT (NIA + offset);
 430     }
 431   else
 432     NULLIFY_NEXT_INSTRUCTION ();
 433 }
 434
 435
 436
 437 000001,5.RS,00011,16.OFFSET:REGIMM:32::BGEZL
 438 "bgezl r<RS>, <OFFSET>"
 439 *mipsII:
 440 *mipsIII:
 441 *mipsIV:
 442 *vr4100:
 443 *vr5000:
 444 *r3900:
 445 {
 446   address_word offset = EXTEND16 (OFFSET) << 2;
 447   check_branch_bug ();
 448   if ((signed_word) GPR[RS] >= 0)
 449     {
 450       mark_branch_bug (NIA+offset);
 451       DELAY_SLOT (NIA + offset);
 452     }
 453   else
 454     NULLIFY_NEXT_INSTRUCTION ();
 455 }
 456
 457
 458
 459 000111,5.RS,00000,16.OFFSET:NORMAL:32::BGTZ
 460 "bgtz r<RS>, <OFFSET>"
 461 *mipsI,mipsII,mipsIII,mipsIV:
 462 *vr4100:
 463 *vr5000:
 464 *r3900:
 465 {
 466   address_word offset = EXTEND16 (OFFSET) << 2;
 467   check_branch_bug ();
 468   if ((signed_word) GPR[RS] > 0)
 469     {
 470       mark_branch_bug (NIA+offset);
 471       DELAY_SLOT (NIA + offset);
 472     }
 473 }
 474
 475
 476
 477 010111,5.RS,00000,16.OFFSET:NORMAL:32::BGTZL
 478 "bgtzl r<RS>, <OFFSET>"
 479 *mipsII:
 480 *mipsIII:
 481 *mipsIV:
 482 *vr4100:
 483 *vr5000:
 484 *r3900:
 485 {
 486   address_word offset = EXTEND16 (OFFSET) << 2;
 487   check_branch_bug ();
 488   /* NOTE: The branch occurs AFTER the next instruction has been
 489      executed */
 490   if ((signed_word) GPR[RS] > 0)
 491     {
 492       mark_branch_bug (NIA+offset);
 493       DELAY_SLOT (NIA + offset);
 494     }
 495   else
 496     NULLIFY_NEXT_INSTRUCTION ();
 497 }
 498
 499
 500
 501 000110,5.RS,00000,16.OFFSET:NORMAL:32::BLEZ
 502 "blez r<RS>, <OFFSET>"
 503 *mipsI,mipsII,mipsIII,mipsIV:
 504 *vr4100:
 505 *vr5000:
 506 *r3900:
 507 {
 508   address_word offset = EXTEND16 (OFFSET) << 2;
 509   check_branch_bug ();
 510   /* NOTE: The branch occurs AFTER the next instruction has been
 511      executed */
 512   if ((signed_word) GPR[RS] <= 0)
 513     {
 514       mark_branch_bug (NIA+offset);
 515       DELAY_SLOT (NIA + offset);
 516     }
 517 }
 518
 519
 520
 521 010110,5.RS,00000,16.OFFSET:NORMAL:32::BLEZL
 522 "bgezl r<RS>, <OFFSET>"
 523 *mipsII:
 524 *mipsIII:
 525 *mipsIV:
 526 *vr4100:
 527 *vr5000:
 528 *r3900:
 529 {
 530   address_word offset = EXTEND16 (OFFSET) << 2;
 531   check_branch_bug ();
 532   if ((signed_word) GPR[RS] <= 0)
 533     {
 534       mark_branch_bug (NIA+offset);
 535       DELAY_SLOT (NIA + offset);
 536     }
 537   else
 538     NULLIFY_NEXT_INSTRUCTION ();
 539 }
 540
 541
 542
 543 000001,5.RS,00000,16.OFFSET:REGIMM:32::BLTZ
 544 "bltz r<RS>, <OFFSET>"
 545 *mipsI,mipsII,mipsIII,mipsIV:
 546 *vr4100:
 547 *vr5000:
 548 *r3900:
 549 {
 550   address_word offset = EXTEND16 (OFFSET) << 2;
 551   check_branch_bug ();
 552   if ((signed_word) GPR[RS] < 0)
 553     {
 554       mark_branch_bug (NIA+offset);
 555       DELAY_SLOT (NIA + offset);
 556     }
 557 }
 558
 559
 560
 561 000001,5.RS!31,10000,16.OFFSET:REGIMM:32::BLTZAL
 562 "bltzal r<RS>, <OFFSET>"
 563 *mipsI,mipsII,mipsIII,mipsIV:
 564 *vr4100:
 565 *vr5000:
 566 *r3900:
 567 {
 568   address_word offset = EXTEND16 (OFFSET) << 2;
 569   check_branch_bug ();
 570   RA = (CIA + 8);
 571   /* NOTE: The branch occurs AFTER the next instruction has been
 572      executed */
 573   if ((signed_word) GPR[RS] < 0)
 574     {
 575       mark_branch_bug (NIA+offset);
 576       DELAY_SLOT (NIA + offset);
 577     }
 578 }
 579
 580
 581
 582 000001,5.RS!31,10010,16.OFFSET:REGIMM:32::BLTZALL
 583 "bltzall r<RS>, <OFFSET>"
 584 *mipsII:
 585 *mipsIII:
 586 *mipsIV:
 587 *vr4100:
 588 *vr5000:
 589 *r3900:
 590 {
 591   address_word offset = EXTEND16 (OFFSET) << 2;
 592   check_branch_bug ();
 593   RA = (CIA + 8);
 594   if ((signed_word) GPR[RS] < 0)
 595     {
 596       mark_branch_bug (NIA+offset);
 597       DELAY_SLOT (NIA + offset);
 598     }
 599   else
 600     NULLIFY_NEXT_INSTRUCTION ();
 601 }
 602
 603
 604
 605 000001,5.RS,00010,16.OFFSET:REGIMM:32::BLTZL
 606 "bltzl r<RS>, <OFFSET>"
 607 *mipsII:
 608 *mipsIII:
 609 *mipsIV:
 610 *vr4100:
 611 *vr5000:
 612 *r3900:
 613 {
 614   address_word offset = EXTEND16 (OFFSET) << 2;
 615   check_branch_bug ();
 616   /* NOTE: The branch occurs AFTER the next instruction has been
 617      executed */
 618   if ((signed_word) GPR[RS] < 0)
 619     {
 620       mark_branch_bug (NIA+offset);
 621       DELAY_SLOT (NIA + offset);
 622     }
 623   else
 624     NULLIFY_NEXT_INSTRUCTION ();
 625 }
 626
 627
 628
 629 000101,5.RS,5.RT,16.OFFSET:NORMAL:32::BNE
 630 "bne r<RS>, r<RT>, <OFFSET>"
 631 *mipsI,mipsII,mipsIII,mipsIV:
 632 *vr4100:
 633 *vr5000:
 634 *r3900:
 635 {
 636   address_word offset = EXTEND16 (OFFSET) << 2;
 637   check_branch_bug ();
 638   if ((signed_word) GPR[RS] != (signed_word) GPR[RT])
 639     {
 640       mark_branch_bug (NIA+offset);
 641       DELAY_SLOT (NIA + offset);
 642     }
 643 }
 644
 645
 646
 647 010101,5.RS,5.RT,16.OFFSET:NORMAL:32::BNEL
 648 "bnel r<RS>, r<RT>, <OFFSET>"
 649 *mipsII:
 650 *mipsIII:
 651 *mipsIV:
 652 *vr4100:
 653 *vr5000:
 654 *r3900:
 655 {
 656   address_word offset = EXTEND16 (OFFSET) << 2;
 657   check_branch_bug ();
 658   if ((signed_word) GPR[RS] != (signed_word) GPR[RT])
 659     {
 660       mark_branch_bug (NIA+offset);
 661       DELAY_SLOT (NIA + offset);
 662     }
 663   else
 664     NULLIFY_NEXT_INSTRUCTION ();
 665 }
 666
 667
 668
 669 000000,20.CODE,001101:SPECIAL:32::BREAK
 670 "break"
 671 *mipsI,mipsII,mipsIII,mipsIV:
 672 *vr4100:
 673 *vr5000:
 674 *r3900:
 675 {
 676   /* Check for some break instruction which are reserved for use by the simulator.  */
 677   unsigned int break_code = instruction_0 & HALT_INSTRUCTION_MASK;
 678   if (break_code == (HALT_INSTRUCTION  & HALT_INSTRUCTION_MASK) ||
 679       break_code == (HALT_INSTRUCTION2 & HALT_INSTRUCTION_MASK))
 680     {
 681       sim_engine_halt (SD, CPU, NULL, cia,
 682                        sim_exited, (unsigned int)(A0 & 0xFFFFFFFF));
 683     }
 684   else if (break_code == (BREAKPOINT_INSTRUCTION  & HALT_INSTRUCTION_MASK) ||
 685            break_code == (BREAKPOINT_INSTRUCTION2 & HALT_INSTRUCTION_MASK))
 686     {
 687       if (STATE & simDELAYSLOT)
 688         PC = cia - 4; /* reference the branch instruction */
 689       else
 690         PC = cia;
 691       SignalException(BreakPoint, instruction_0);
 692     }
 693
 694   else
 695     {
 696       /* If we get this far, we're not an instruction reserved by the sim.  Raise
 697          the exception. */
 698       SignalException(BreakPoint, instruction_0);
 699     }
 700 }
 701
 702
 703
 704
 705
 706
 707 000000,5.RS,5.RT,5.RD,00000,101100:SPECIAL:64::DADD
 708 "dadd r<RD>, r<RS>, r<RT>"
 709 *mipsIII:
 710 *mipsIV:
 711 *vr4100:
 712 *vr5000:
 713 {
 714   /* this check's for overflow */
 715   TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
 716   {
 717     ALU64_BEGIN (GPR[RS]);
 718     ALU64_ADD (GPR[RT]);
 719     ALU64_END (GPR[RD]);
 720   }
 721   TRACE_ALU_RESULT (GPR[RD]);
 722 }
 723
 724
 725
 726 011000,5.RS,5.RT,16.IMMEDIATE:NORMAL:64::DADDI
 727 "daddi r<RT>, r<RS>, <IMMEDIATE>"
 728 *mipsIII:
 729 *mipsIV:
 730 *vr4100:
 731 *vr5000:
 732 {
 733   TRACE_ALU_INPUT2 (GPR[RS], EXTEND16 (IMMEDIATE));
 734   {
 735     ALU64_BEGIN (GPR[RS]);
 736     ALU64_ADD (EXTEND16 (IMMEDIATE));
 737     ALU64_END (GPR[RT]);
 738   }
 739   TRACE_ALU_RESULT (GPR[RT]);
 740 }
 741
 742
 743
 744 :function:::void:do_daddiu:int rs, int rt, unsigned16 immediate
 745 {
 746   TRACE_ALU_INPUT2 (GPR[rs], EXTEND16 (immediate));
 747   GPR[rt] = GPR[rs] + EXTEND16 (immediate);
 748   TRACE_ALU_RESULT (GPR[rt]);
 749 }
 750
 751 011001,5.RS,5.RT,16.IMMEDIATE:NORMAL:64::DADDIU
 752 "daddu r<RT>, r<RS>, <IMMEDIATE>"
 753 *mipsIII:
 754 *mipsIV:
 755 *vr4100:
 756 *vr5000:
 757 {
 758   do_daddiu (SD_, RS, RT, IMMEDIATE);
 759 }
 760
 761
 762
 763 :function:::void:do_daddu:int rs, int rt, int rd
 764 {
 765   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
 766   GPR[rd] = GPR[rs] + GPR[rt];
 767   TRACE_ALU_RESULT (GPR[rd]);
 768 }
 769
 770 000000,5.RS,5.RT,5.RD,00000,101101:SPECIAL:64::DADDU
 771 "daddu r<RD>, r<RS>, r<RT>"
 772 *mipsIII:
 773 *mipsIV:
 774 *vr4100:
 775 *vr5000:
 776 {
 777   do_daddu (SD_, RS, RT, RD);
 778 }
 779
 780
 781
 782 :function:::void:do_ddiv:int rs, int rt
 783 {
 784   check_div_hilo (SD_, HIHISTORY, LOHISTORY);
 785   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
 786   {
 787     signed64 n = GPR[rs];
 788     signed64 d = GPR[rt];
 789     signed64 hi;
 790     signed64 lo;
 791     if (d == 0)
 792       {
 793         lo = SIGNED64 (0x8000000000000000);
 794         hi = 0;
 795       }
 796     else if (d == -1 && n == SIGNED64 (0x8000000000000000))
 797       {
 798         lo = SIGNED64 (0x8000000000000000);
 799         hi = 0;
 800       }
 801     else
 802       {
 803         lo = (n / d);
 804         hi = (n % d);
 805       }
 806     HI = hi;
 807     LO = lo;
 808   }
 809   TRACE_ALU_RESULT2 (HI, LO);
 810 }
 811
 812 000000,5.RS,5.RT,0000000000011110:SPECIAL:64::DDIV
 813 "ddiv r<RS>, r<RT>"
 814 *mipsIII:
 815 *mipsIV:
 816 *vr4100:
 817 *vr5000:
 818 {
 819   do_ddiv (SD_, RS, RT);
 820 }
 821
 822
 823
 824 :function:::void:do_ddivu:int rs, int rt
 825 {
 826   check_div_hilo (SD_, HIHISTORY, LOHISTORY);
 827   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
 828   {
 829     unsigned64 n = GPR[rs];
 830     unsigned64 d = GPR[rt];
 831     unsigned64 hi;
 832     unsigned64 lo;
 833     if (d == 0)
 834       {
 835         lo = SIGNED64 (0x8000000000000000);
 836         hi = 0;
 837       }
 838     else
 839       {
 840         lo = (n / d);
 841         hi = (n % d);
 842       }
 843     HI = hi;
 844     LO = lo;
 845   }
 846   TRACE_ALU_RESULT2 (HI, LO);
 847 }
 848
 849 000000,5.RS,5.RT,0000000000,011111:SPECIAL:64::DDIVU
 850 "ddivu r<RS>, r<RT>"
 851 *mipsIII:
 852 *mipsIV:
 853 *vr4100:
 854 *vr5000:
 855 {
 856   do_ddivu (SD_, RS, RT);
 857 }
 858
 859
 860
 861 :function:::void:do_div:int rs, int rt
 862 {
 863   check_div_hilo (SD_, HIHISTORY, LOHISTORY);
 864   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
 865   {
 866     signed32 n = GPR[rs];
 867     signed32 d = GPR[rt];
 868     if (d == 0)
 869       {
 870         LO = EXTEND32 (0x80000000);
 871         HI = EXTEND32 (0);
 872       }
 873     else if (n == SIGNED32 (0x80000000) && d == -1)
 874       {
 875         LO = EXTEND32 (0x80000000);
 876         HI = EXTEND32 (0);
 877       }
 878     else
 879       {
 880         LO = EXTEND32 (n / d);
 881         HI = EXTEND32 (n % d);
 882       }
 883   }
 884   TRACE_ALU_RESULT2 (HI, LO);
 885 }
 886
 887 000000,5.RS,5.RT,0000000000011010:SPECIAL:32::DIV
 888 "div r<RS>, r<RT>"
 889 *mipsI,mipsII,mipsIII,mipsIV:
 890 *vr4100:
 891 *vr5000:
 892 *r3900:
 893 {
 894   do_div (SD_, RS, RT);
 895 }
 896
 897
 898
 899 :function:::void:do_divu:int rs, int rt
 900 {
 901   check_div_hilo (SD_, HIHISTORY, LOHISTORY);
 902   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
 903   {
 904     unsigned32 n = GPR[rs];
 905     unsigned32 d = GPR[rt];
 906     if (d == 0)
 907       {
 908         LO = EXTEND32 (0x80000000);
 909         HI = EXTEND32 (0);
 910       }
 911    else
 912      {
 913        LO = EXTEND32 (n / d);
 914        HI = EXTEND32 (n % d);
 915      }
 916   }
 917   TRACE_ALU_RESULT2 (HI, LO);
 918 }
 919
 920 000000,5.RS,5.RT,0000000000011011:SPECIAL:32::DIVU
 921 "divu r<RS>, r<RT>"
 922 *mipsI,mipsII,mipsIII,mipsIV:
 923 *vr4100:
 924 *vr5000:
 925 *r3900:
 926 {
 927   do_divu (SD_, RS, RT);
 928 }
 929
 930
 931
 932 :function:::void:do_dmultx:int rs, int rt, int rd, int signed_p
 933 {
 934   unsigned64 lo;
 935   unsigned64 hi;
 936   unsigned64 m00;
 937   unsigned64 m01;
 938   unsigned64 m10;
 939   unsigned64 m11;
 940   unsigned64 mid;
 941   int sign;
 942   unsigned64 op1 = GPR[rs];
 943   unsigned64 op2 = GPR[rt];
 944   check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
 945   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
 946   /* make signed multiply unsigned */
 947   sign = 0;
 948   if (signed_p)
 949     {
 950       if (op1 < 0)
 951         {
 952           op1 = - op1;
 953           ++sign;
 954         }
 955       if (op2 < 0)
 956         {
 957           op2 = - op2;
 958           ++sign;
 959         }
 960     }
 961   /* multuply out the 4 sub products */
 962   m00 = ((unsigned64) VL4_8 (op1) * (unsigned64) VL4_8 (op2));
 963   m10 = ((unsigned64) VH4_8 (op1) * (unsigned64) VL4_8 (op2));
 964   m01 = ((unsigned64) VL4_8 (op1) * (unsigned64) VH4_8 (op2));
 965   m11 = ((unsigned64) VH4_8 (op1) * (unsigned64) VH4_8 (op2));
 966   /* add the products */
 967   mid = ((unsigned64) VH4_8 (m00)
 968          + (unsigned64) VL4_8 (m10)
 969          + (unsigned64) VL4_8 (m01));
 970   lo = U8_4 (mid, m00);
 971   hi = (m11
 972         + (unsigned64) VH4_8 (mid)
 973         + (unsigned64) VH4_8 (m01)
 974         + (unsigned64) VH4_8 (m10));
 975   /* fix the sign */
 976   if (sign & 1)
 977     {
 978       lo = -lo;
 979       if (lo == 0)
 980         hi = -hi;
 981       else
 982         hi = -hi - 1;
 983     }
 984   /* save the result HI/LO (and a gpr) */
 985   LO = lo;
 986   HI = hi;
 987   if (rd != 0)
 988     GPR[rd] = lo;
 989   TRACE_ALU_RESULT2 (HI, LO);
 990 }
 991
 992 :function:::void:do_dmult:int rs, int rt, int rd
 993 {
 994   do_dmultx (SD_, rs, rt, rd, 1);
 995 }
 996
 997 000000,5.RS,5.RT,0000000000011100:SPECIAL:64::DMULT
 998 "dmult r<RS>, r<RT>"
 999 *mipsIII,mipsIV:
1000 *vr4100:
1001 {
1002   do_dmult (SD_, RS, RT, 0);
1003 }
1004
1005 000000,5.RS,5.RT,5.RD,00000011100:SPECIAL:64::DMULT
1006 "dmult r<RS>, r<RT>":RD == 0
1007 "dmult r<RD>, r<RS>, r<RT>"
1008 *vr5000:
1009 {
1010   do_dmult (SD_, RS, RT, RD);
1011 }
1012
1013
1014
1015 :function:::void:do_dmultu:int rs, int rt, int rd
1016 {
1017   do_dmultx (SD_, rs, rt, rd, 0);
1018 }
1019
1020 000000,5.RS,5.RT,0000000000011101:SPECIAL:64::DMULTU
1021 "dmultu r<RS>, r<RT>"
1022 *mipsIII,mipsIV:
1023 *vr4100:
1024 {
1025   do_dmultu (SD_, RS, RT, 0);
1026 }
1027
1028 000000,5.RS,5.RT,5.RD,00000011101:SPECIAL:64::DMULTU
1029 "dmultu r<RD>, r<RS>, r<RT>":RD == 0
1030 "dmultu r<RS>, r<RT>"
1031 *vr5000:
1032 {
1033   do_dmultu (SD_, RS, RT, RD);
1034 }
1035
1036 :function:::void:do_dsll:int rt, int rd, int shift
1037 {
1038   GPR[rd] = GPR[rt] << shift;
1039 }
1040
1041 :function:::void:do_dsllv:int rs, int rt, int rd
1042 {
1043   int s = MASKED64 (GPR[rs], 5, 0);
1044   GPR[rd] = GPR[rt] << s;
1045 }
1046
1047
1048 00000000000,5.RT,5.RD,5.SHIFT,111000:SPECIAL:64::DSLL
1049 "dsll r<RD>, r<RT>, <SHIFT>"
1050 *mipsIII:
1051 *mipsIV:
1052 *vr4100:
1053 *vr5000:
1054 {
1055   do_dsll (SD_, RT, RD, SHIFT);
1056 }
1057
1058
1059 00000000000,5.RT,5.RD,5.SHIFT,111100:SPECIAL:64::DSLL32
1060 "dsll32 r<RD>, r<RT>, <SHIFT>"
1061 *mipsIII:
1062 *mipsIV:
1063 *vr4100:
1064 *vr5000:
1065 {
1066   int s = 32 + SHIFT;
1067   GPR[RD] = GPR[RT] << s;
1068 }
1069
1070 000000,5.RS,5.RT,5.RD,00000010100:SPECIAL:64::DSLLV
1071 "dsllv r<RD>, r<RT>, r<RS>"
1072 *mipsIII:
1073 *mipsIV:
1074 *vr4100:
1075 *vr5000:
1076 {
1077   do_dsllv (SD_, RS, RT, RD);
1078 }
1079
1080 :function:::void:do_dsra:int rt, int rd, int shift
1081 {
1082   GPR[rd] = ((signed64) GPR[rt]) >> shift;
1083 }
1084
1085
1086 00000000000,5.RT,5.RD,5.SHIFT,111011:SPECIAL:64::DSRA
1087 "dsra r<RD>, r<RT>, <SHIFT>"
1088 *mipsIII:
1089 *mipsIV:
1090 *vr4100:
1091 *vr5000:
1092 {
1093   do_dsra (SD_, RT, RD, SHIFT);
1094 }
1095
1096
1097 00000000000,5.RT,5.RD,5.SHIFT,111111:SPECIAL:64::DSRA32
1098 "dsra32 r<RT>, r<RD>, <SHIFT>"
1099 *mipsIII:
1100 *mipsIV:
1101 *vr4100:
1102 *vr5000:
1103 {
1104   int s = 32 + SHIFT;
1105   GPR[RD] = ((signed64) GPR[RT]) >> s;
1106 }
1107
1108
1109 :function:::void:do_dsrav:int rs, int rt, int rd
1110 {
1111   int s = MASKED64 (GPR[rs], 5, 0);
1112   TRACE_ALU_INPUT2 (GPR[rt], s);
1113   GPR[rd] = ((signed64) GPR[rt]) >> s;
1114   TRACE_ALU_RESULT (GPR[rd]);
1115 }
1116
1117 000000,5.RS,5.RT,5.RD,00000010111:SPECIAL:64::DSRAV
1118 "dsra32 r<RT>, r<RD>, r<RS>"
1119 *mipsIII:
1120 *mipsIV:
1121 *vr4100:
1122 *vr5000:
1123 {
1124   do_dsrav (SD_, RS, RT, RD);
1125 }
1126
1127 :function:::void:do_dsrl:int rt, int rd, int shift
1128 {
1129   GPR[rd] = (unsigned64) GPR[rt] >> shift;
1130 }
1131
1132
1133 00000000000,5.RT,5.RD,5.SHIFT,111010:SPECIAL:64::DSRL
1134 "dsrl r<RD>, r<RT>, <SHIFT>"
1135 *mipsIII:
1136 *mipsIV:
1137 *vr4100:
1138 *vr5000:
1139 {
1140   do_dsrl (SD_, RT, RD, SHIFT);
1141 }
1142
1143
1144 00000000000,5.RT,5.RD,5.SHIFT,111110:SPECIAL:64::DSRL32
1145 "dsrl32 r<RD>, r<RT>, <SHIFT>"
1146 *mipsIII:
1147 *mipsIV:
1148 *vr4100:
1149 *vr5000:
1150 {
1151   int s = 32 + SHIFT;
1152   GPR[RD] = (unsigned64) GPR[RT] >> s;
1153 }
1154
1155
1156 :function:::void:do_dsrlv:int rs, int rt, int rd
1157 {
1158   int s = MASKED64 (GPR[rs], 5, 0);
1159   GPR[rd] = (unsigned64) GPR[rt] >> s;
1160 }
1161
1162
1163
1164 000000,5.RS,5.RT,5.RD,00000010110:SPECIAL:64::DSRLV
1165 "dsrl32 r<RD>, r<RT>, r<RS>"
1166 *mipsIII:
1167 *mipsIV:
1168 *vr4100:
1169 *vr5000:
1170 {
1171   do_dsrlv (SD_, RS, RT, RD);
1172 }
1173
1174
1175 000000,5.RS,5.RT,5.RD,00000101110:SPECIAL:64::DSUB
1176 "dsub r<RD>, r<RS>, r<RT>"
1177 *mipsIII:
1178 *mipsIV:
1179 *vr4100:
1180 *vr5000:
1181 {
1182   TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
1183   {
1184     ALU64_BEGIN (GPR[RS]);
1185     ALU64_SUB (GPR[RT]);
1186     ALU64_END (GPR[RD]);
1187   }
1188   TRACE_ALU_RESULT (GPR[RD]);
1189 }
1190
1191
1192 :function:::void:do_dsubu:int rs, int rt, int rd
1193 {
1194   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
1195   GPR[rd] = GPR[rs] - GPR[rt];
1196   TRACE_ALU_RESULT (GPR[rd]);
1197 }
1198
1199 000000,5.RS,5.RT,5.RD,00000101111:SPECIAL:64::DSUBU
1200 "dsubu r<RD>, r<RS>, r<RT>"
1201 *mipsIII:
1202 *mipsIV:
1203 *vr4100:
1204 *vr5000:
1205 {
1206   do_dsubu (SD_, RS, RT, RD);
1207 }
1208
1209
1210 000010,26.INSTR_INDEX:NORMAL:32::J
1211 "j <INSTR_INDEX>"
1212 *mipsI,mipsII,mipsIII,mipsIV:
1213 *vr4100:
1214 *vr5000:
1215 *r3900:
1216 {
1217   /* NOTE: The region used is that of the delay slot NIA and NOT the
1218      current instruction */
1219   address_word region = (NIA & MASK (63, 28));
1220   DELAY_SLOT (region | (INSTR_INDEX << 2));
1221 }
1222
1223
1224 000011,26.INSTR_INDEX:NORMAL:32::JAL
1225 "jal <INSTR_INDEX>"
1226 *mipsI,mipsII,mipsIII,mipsIV:
1227 *vr4100:
1228 *vr5000:
1229 *r3900:
1230 {
1231   /* NOTE: The region used is that of the delay slot and NOT the
1232      current instruction */
1233   address_word region = (NIA & MASK (63, 28));
1234   GPR[31] = CIA + 8;
1235   DELAY_SLOT (region | (INSTR_INDEX << 2));
1236 }
1237
1238 000000,5.RS,00000,5.RD,00000001001:SPECIAL:32::JALR
1239 "jalr r<RS>":RD == 31
1240 "jalr r<RD>, r<RS>"
1241 *mipsI,mipsII,mipsIII,mipsIV:
1242 *vr4100:
1243 *vr5000:
1244 *r3900:
1245 {
1246   address_word temp = GPR[RS];
1247   GPR[RD] = CIA + 8;
1248   DELAY_SLOT (temp);
1249 }
1250
1251
1252 000000,5.RS,000000000000000001000:SPECIAL:32::JR
1253 "jr r<RS>"
1254 *mipsI,mipsII,mipsIII,mipsIV:
1255 *vr4100:
1256 *vr5000:
1257 *r3900:
1258 {
1259   DELAY_SLOT (GPR[RS]);
1260 }
1261
1262
1263 :function:::unsigned_word:do_load:unsigned access, address_word base, address_word offset
1264 {
1265   address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
1266   address_word reverseendian = (ReverseEndian ? (mask ^ access) : 0);
1267   address_word bigendiancpu = (BigEndianCPU ? (mask ^ access) : 0);
1268   unsigned int byte;
1269   address_word paddr;
1270   int uncached;
1271   unsigned64 memval;
1272   address_word vaddr;
1273
1274   vaddr = base + offset;
1275   if ((vaddr & access) != 0)
1276     {
1277       SIM_CORE_SIGNAL (SD, STATE_CPU (SD, 0), cia, read_map, access+1, vaddr, read_transfer, sim_core_unaligned_signal);
1278     }
1279   AddressTranslation (vaddr, isDATA, isLOAD, &paddr, &uncached, isTARGET, isREAL);
1280   paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverseendian));
1281   LoadMemory (&memval, NULL, uncached, access, paddr, vaddr, isDATA, isREAL);
1282   byte = ((vaddr & mask) ^ bigendiancpu);
1283   return (memval >> (8 * byte));
1284 }
1285
1286
1287 100000,5.BASE,5.RT,16.OFFSET:NORMAL:32::LB
1288 "lb r<RT>, <OFFSET>(r<BASE>)"
1289 *mipsI,mipsII,mipsIII,mipsIV:
1290 *vr4100:
1291 *vr5000:
1292 *r3900:
1293 {
1294   GPR[RT] = EXTEND8 (do_load (SD_, AccessLength_BYTE, GPR[BASE], EXTEND16 (OFFSET)));
1295 }
1296
1297
1298 100100,5.BASE,5.RT,16.OFFSET:NORMAL:32::LBU
1299 "lbu r<RT>, <OFFSET>(r<BASE>)"
1300 *mipsI,mipsII,mipsIII,mipsIV:
1301 *vr4100:
1302 *vr5000:
1303 *r3900:
1304 {
1305   GPR[RT] = do_load (SD_, AccessLength_BYTE, GPR[BASE], EXTEND16 (OFFSET));
1306 }
1307
1308
1309 110111,5.BASE,5.RT,16.OFFSET:NORMAL:64::LD
1310 "ld r<RT>, <OFFSET>(r<BASE>)"
1311 *mipsIII:
1312 *mipsIV:
1313 *vr4100:
1314 *vr5000:
1315 {
1316   GPR[RT] = EXTEND64 (do_load (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET)));
1317 }
1318
1319
1320 1101,ZZ!0!1!3,5.BASE,5.RT,16.OFFSET:NORMAL:64::LDCz
1321 "ldc<ZZ> r<RT>, <OFFSET>(r<BASE>)"
1322 *mipsII:
1323 *mipsIII:
1324 *mipsIV:
1325 *vr4100:
1326 *vr5000:
1327 *r3900:
1328 {
1329   COP_LD (ZZ, RT, do_load (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET)));
1330 }
1331
1332
1333
1334
1335 011010,5.BASE,5.RT,16.OFFSET:NORMAL:64::LDL
1336 "ldl r<RT>, <OFFSET>(r<BASE>)"
1337 *mipsIII:
1338 *mipsIV:
1339 *vr4100:
1340 *vr5000:
1341 {
1342   GPR[RT] = do_load_left (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
1343 }
1344
1345
1346 011011,5.BASE,5.RT,16.OFFSET:NORMAL:64::LDR
1347 "ldr r<RT>, <OFFSET>(r<BASE>)"
1348 *mipsIII:
1349 *mipsIV:
1350 *vr4100:
1351 *vr5000:
1352 {
1353   GPR[RT] = do_load_right (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
1354 }
1355
1356
1357 100001,5.BASE,5.RT,16.OFFSET:NORMAL:32::LH
1358 "lh r<RT>, <OFFSET>(r<BASE>)"
1359 *mipsI,mipsII,mipsIII,mipsIV:
1360 *vr4100:
1361 *vr5000:
1362 *r3900:
1363 {
1364   GPR[RT] = EXTEND16 (do_load (SD_, AccessLength_HALFWORD, GPR[BASE], EXTEND16 (OFFSET)));
1365 }
1366
1367
1368 100101,5.BASE,5.RT,16.OFFSET:NORMAL:32::LHU
1369 "lhu r<RT>, <OFFSET>(r<BASE>)"
1370 *mipsI,mipsII,mipsIII,mipsIV:
1371 *vr4100:
1372 *vr5000:
1373 *r3900:
1374 {
1375   GPR[RT] = do_load (SD_, AccessLength_HALFWORD, GPR[BASE], EXTEND16 (OFFSET));
1376 }
1377
1378
1379 110000,5.BASE,5.RT,16.OFFSET:NORMAL:32::LL
1380 "ll r<RT>, <OFFSET>(r<BASE>)"
1381 *mipsII:
1382 *mipsIII:
1383 *mipsIV:
1384 *vr4100:
1385 *vr5000:
1386 {
1387   unsigned32 instruction = instruction_0;
1388   signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
1389   int destreg = ((instruction >> 16) & 0x0000001F);
1390   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
1391   {
1392     address_word vaddr = ((unsigned64)op1 + offset);
1393     address_word paddr;
1394     int uncached;
1395     if ((vaddr & 3) != 0)
1396       {
1397         SIM_CORE_SIGNAL (SD, CPU, cia, read_map, 4, vaddr, read_transfer, sim_core_unaligned_signal);
1398       }
1399     else
1400       {
1401         if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
1402           {
1403             unsigned64 memval = 0;
1404             unsigned64 memval1 = 0;
1405             unsigned64 mask = 0x7;
1406             unsigned int shift = 2;
1407             unsigned int reverse = (ReverseEndian ? (mask >> shift) : 0);
1408             unsigned int bigend = (BigEndianCPU ? (mask >> shift) : 0);
1409             unsigned int byte;
1410             paddr = ((paddr & ~mask) | ((paddr & mask) ^ (reverse << shift)));
1411             LoadMemory(&memval,&memval1,uncached,AccessLength_WORD,paddr,vaddr,isDATA,isREAL);
1412             byte = ((vaddr & mask) ^ (bigend << shift));
1413             GPR[destreg] = (SIGNEXTEND(((memval >> (8 * byte)) & 0xFFFFFFFF),32));
1414             LLBIT = 1;
1415           }
1416       }
1417   }
1418 }
1419
1420
1421 110100,5.BASE,5.RT,16.OFFSET:NORMAL:64::LLD
1422 "lld r<RT>, <OFFSET>(r<BASE>)"
1423 *mipsIII:
1424 *mipsIV:
1425 *vr4100:
1426 *vr5000:
1427 {
1428   unsigned32 instruction = instruction_0;
1429   signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
1430   int destreg = ((instruction >> 16) & 0x0000001F);
1431   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
1432   {
1433     address_word vaddr = ((unsigned64)op1 + offset);
1434     address_word paddr;
1435     int uncached;
1436     if ((vaddr & 7) != 0)
1437       {
1438         SIM_CORE_SIGNAL (SD, CPU, cia, read_map, 8, vaddr, read_transfer, sim_core_unaligned_signal);
1439       }
1440     else
1441       {
1442         if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
1443           {
1444             unsigned64 memval = 0;
1445             unsigned64 memval1 = 0;
1446             LoadMemory(&memval,&memval1,uncached,AccessLength_DOUBLEWORD,paddr,vaddr,isDATA,isREAL);
1447             GPR[destreg] = memval;
1448             LLBIT = 1;
1449           }
1450       }
1451   }
1452 }
1453
1454
1455 001111,00000,5.RT,16.IMMEDIATE:NORMAL:32::LUI
1456 "lui r<RT>, <IMMEDIATE>"
1457 *mipsI,mipsII,mipsIII,mipsIV:
1458 *vr4100:
1459 *vr5000:
1460 *r3900:
1461 {
1462   TRACE_ALU_INPUT1 (IMMEDIATE);
1463   GPR[RT] = EXTEND32 (IMMEDIATE << 16);
1464   TRACE_ALU_RESULT (GPR[RT]);
1465 }
1466
1467
1468 100011,5.BASE,5.RT,16.OFFSET:NORMAL:32::LW
1469 "lw r<RT>, <OFFSET>(r<BASE>)"
1470 *mipsI,mipsII,mipsIII,mipsIV:
1471 *vr4100:
1472 *vr5000:
1473 *r3900:
1474 {
1475   GPR[RT] = EXTEND32 (do_load (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET)));
1476 }
1477
1478
1479 1100,ZZ!0!1!3,5.BASE,5.RT,16.OFFSET:NORMAL:32::LWCz
1480 "lwc<ZZ> r<RT>, <OFFSET>(r<BASE>)"
1481 *mipsI,mipsII,mipsIII,mipsIV:
1482 *vr4100:
1483 *vr5000:
1484 *r3900:
1485 {
1486   COP_LW (ZZ, RT, do_load (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET)));
1487 }
1488
1489
1490 :function:::unsigned_word:do_load_left:unsigned access, address_word base, address_word offset, unsigned_word rt
1491 {
1492   address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
1493   address_word reverseendian = (ReverseEndian ? -1 : 0);
1494   address_word bigendiancpu = (BigEndianCPU ? -1 : 0);
1495   unsigned int byte;
1496   unsigned int word;
1497   address_word paddr;
1498   int uncached;
1499   unsigned64 memval;
1500   address_word vaddr;
1501   int nr_lhs_bits;
1502   int nr_rhs_bits;
1503   unsigned_word lhs_mask;
1504   unsigned_word temp;
1505
1506   vaddr = base + offset;
1507   AddressTranslation (vaddr, isDATA, isLOAD, &paddr, &uncached, isTARGET, isREAL);
1508   paddr = (paddr ^ (reverseendian & mask));
1509   if (BigEndianMem == 0)
1510     paddr = paddr & ~access;
1511
1512   /* compute where within the word/mem we are */
1513   byte = ((vaddr ^ bigendiancpu) & access); /* 0..access */
1514   word = ((vaddr ^ bigendiancpu) & (mask & ~access)) / (access + 1); /* 0..1 */
1515   nr_lhs_bits = 8 * byte + 8;
1516   nr_rhs_bits = 8 * access - 8 * byte;
1517   /* nr_lhs_bits + nr_rhs_bits == 8 * (accesss + 1) */
1518
1519   /* fprintf (stderr, "l[wd]l: 0x%08lx%08lx 0x%08lx%08lx %d:%d %d+%d\n",
1520            (long) ((unsigned64) vaddr >> 32), (long) vaddr,
1521            (long) ((unsigned64) paddr >> 32), (long) paddr,
1522            word, byte, nr_lhs_bits, nr_rhs_bits); */
1523
1524   LoadMemory (&memval, NULL, uncached, byte, paddr, vaddr, isDATA, isREAL);
1525   if (word == 0)
1526     {
1527       /* GPR{31..32-NR_LHS_BITS} = memval{NR_LHS_BITS-1..0} */
1528       temp = (memval << nr_rhs_bits);
1529     }
1530   else
1531     {
1532       /* GPR{31..32-NR_LHS_BITS = memval{32+NR_LHS_BITS..32} */
1533       temp = (memval >> nr_lhs_bits);
1534     }
1535   lhs_mask = LSMASK (nr_lhs_bits + nr_rhs_bits - 1, nr_rhs_bits);
1536   rt = (rt & ~lhs_mask) | (temp & lhs_mask);
1537
1538   /* fprintf (stderr, "l[wd]l: 0x%08lx%08lx -> 0x%08lx%08lx & 0x%08lx%08lx -> 0x%08lx%08lx\n",
1539            (long) ((unsigned64) memval >> 32), (long) memval,
1540            (long) ((unsigned64) temp >> 32), (long) temp,
1541            (long) ((unsigned64) lhs_mask >> 32), (long) lhs_mask,
1542            (long) (rt >> 32), (long) rt); */
1543   return rt;
1544 }
1545
1546
1547 100010,5.BASE,5.RT,16.OFFSET:NORMAL:32::LWL
1548 "lwl r<RT>, <OFFSET>(r<BASE>)"
1549 *mipsI,mipsII,mipsIII,mipsIV:
1550 *vr4100:
1551 *vr5000:
1552 *r3900:
1553 {
1554   GPR[RT] = EXTEND32 (do_load_left (SD_, AccessLength_WORD, GPR[BASE], EXTEND32 (OFFSET), GPR[RT]));
1555 }
1556
1557
1558 :function:::unsigned_word:do_load_right:unsigned access, address_word base, address_word offset, unsigned_word rt
1559 {
1560   address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
1561   address_word reverseendian = (ReverseEndian ? -1 : 0);
1562   address_word bigendiancpu = (BigEndianCPU ? -1 : 0);
1563   unsigned int byte;
1564   address_word paddr;
1565   int uncached;
1566   unsigned64 memval;
1567   address_word vaddr;
1568
1569   vaddr = base + offset;
1570   AddressTranslation (vaddr, isDATA, isLOAD, &paddr, &uncached, isTARGET, isREAL);
1571   /* NOTE: SPEC is wrong, has `BigEndianMem == 0' not `BigEndianMem != 0' */
1572   paddr = (paddr ^ (reverseendian & mask));
1573   if (BigEndianMem != 0)
1574     paddr = paddr & ~access;
1575   byte = ((vaddr & mask) ^ (bigendiancpu & mask));
1576   /* NOTE: SPEC is wrong, had `byte' not `access - byte'.  See SW. */
1577   LoadMemory (&memval, NULL, uncached, access - (access & byte), paddr, vaddr, isDATA, isREAL);
1578   /* printf ("lr: 0x%08lx %d@0x%08lx 0x%08lx\n",
1579      (long) paddr, byte, (long) paddr, (long) memval); */
1580   {
1581     unsigned_word screen = LSMASK (8 * (access - (byte & access) + 1) - 1, 0);
1582     rt &= ~screen;
1583     rt |= (memval >> (8 * byte)) & screen;
1584   }
1585   return rt;
1586 }
1587
1588
1589 100110,5.BASE,5.RT,16.OFFSET:NORMAL:32::LWR
1590 "lwr r<RT>, <OFFSET>(r<BASE>)"
1591 *mipsI,mipsII,mipsIII,mipsIV:
1592 *vr4100:
1593 *vr5000:
1594 *r3900:
1595 {
1596   GPR[RT] = EXTEND32 (do_load_right (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]));
1597 }
1598
1599
1600 100111,5.BASE,5.RT,16.OFFSET:NORMAL:32::LWU
1601 "lwu r<RT>, <OFFSET>(r<BASE>)"
1602 *mipsIII:
1603 *mipsIV:
1604 *vr4100:
1605 *vr5000:
1606 {
1607   GPR[RT] = do_load (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET));
1608 }
1609
1610
1611 :function:::void:do_mfhi:int rd
1612 {
1613   check_mf_hilo (SD_, HIHISTORY, LOHISTORY);
1614   TRACE_ALU_INPUT1 (HI);
1615   GPR[rd] = HI;
1616   TRACE_ALU_RESULT (GPR[rd]);
1617 }
1618
1619 000000,0000000000,5.RD,00000,010000:SPECIAL:32::MFHI
1620 "mfhi r<RD>"
1621 *mipsI,mipsII,mipsIII,mipsIV:
1622 *vr4100:
1623 *vr5000:
1624 *r3900:
1625 {
1626   do_mfhi (SD_, RD);
1627 }
1628
1629
1630
1631 :function:::void:do_mflo:int rd
1632 {
1633   check_mf_hilo (SD_, LOHISTORY, HIHISTORY);
1634   TRACE_ALU_INPUT1 (LO);
1635   GPR[rd] = LO;
1636   TRACE_ALU_RESULT (GPR[rd]);
1637 }
1638
1639 000000,0000000000,5.RD,00000,010010:SPECIAL:32::MFLO
1640 "mflo r<RD>"
1641 *mipsI,mipsII,mipsIII,mipsIV:
1642 *vr4100:
1643 *vr5000:
1644 *r3900:
1645 {
1646   do_mflo (SD_, RD);
1647 }
1648
1649
1650
1651 000000,5.RS,5.RT,5.RD,00000001011:SPECIAL:32::MOVN
1652 "movn r<RD>, r<RS>, r<RT>"
1653 *mipsIV:
1654 *vr5000:
1655 {
1656   if (GPR[RT] != 0)
1657     GPR[RD] = GPR[RS];
1658 }
1659
1660
1661
1662 000000,5.RS,5.RT,5.RD,00000001010:SPECIAL:32::MOVZ
1663 "movz r<RD>, r<RS>, r<RT>"
1664 *mipsIV:
1665 *vr5000:
1666 {
1667   if (GPR[RT] == 0)
1668     GPR[RD] = GPR[RS];
1669 }
1670
1671
1672
1673 000000,5.RS,000000000000000,010001:SPECIAL:32::MTHI
1674 "mthi r<RS>"
1675 *mipsI,mipsII,mipsIII,mipsIV:
1676 *vr4100:
1677 *vr5000:
1678 *r3900:
1679 {
1680   check_mt_hilo (SD_, HIHISTORY);
1681   HI = GPR[RS];
1682 }
1683
1684
1685
1686 000000,5.RS,000000000000000010011:SPECIAL:32::MTLO
1687 "mtlo r<RS>"
1688 *mipsI,mipsII,mipsIII,mipsIV:
1689 *vr4100:
1690 *vr5000:
1691 *r3900:
1692 {
1693   check_mt_hilo (SD_, LOHISTORY);
1694   LO = GPR[RS];
1695 }
1696
1697
1698
1699 :function:::void:do_mult:int rs, int rt, int rd
1700 {
1701   signed64 prod;
1702   check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
1703   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
1704   prod = (((signed64)(signed32) GPR[rs])
1705           * ((signed64)(signed32) GPR[rt]));
1706   LO = EXTEND32 (VL4_8 (prod));
1707   HI = EXTEND32 (VH4_8 (prod));
1708   if (rd != 0)
1709     GPR[rd] = LO;
1710   TRACE_ALU_RESULT2 (HI, LO);
1711 }
1712
1713 000000,5.RS,5.RT,00000,00000011000:SPECIAL:32::MULT
1714 "mult r<RS>, r<RT>"
1715 *mipsI,mipsII,mipsIII,mipsIV:
1716 *vr4100:
1717 {
1718   do_mult (SD_, RS, RT, 0);
1719 }
1720
1721
1722 000000,5.RS,5.RT,5.RD,00000011000:SPECIAL:32::MULT
1723 "mult r<RD>, r<RS>, r<RT>"
1724 *vr5000:
1725 *r3900:
1726 {
1727   do_mult (SD_, RS, RT, RD);
1728 }
1729
1730
1731 :function:::void:do_multu:int rs, int rt, int rd
1732 {
1733   unsigned64 prod;
1734   check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
1735   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
1736   prod = (((unsigned64)(unsigned32) GPR[rs])
1737           * ((unsigned64)(unsigned32) GPR[rt]));
1738   LO = EXTEND32 (VL4_8 (prod));
1739   HI = EXTEND32 (VH4_8 (prod));
1740   if (rd != 0)
1741     GPR[rd] = LO;
1742   TRACE_ALU_RESULT2 (HI, LO);
1743 }
1744
1745 000000,5.RS,5.RT,00000,00000011001:SPECIAL:32::MULTU
1746 "multu r<RS>, r<RT>"
1747 *mipsI,mipsII,mipsIII,mipsIV:
1748 *vr4100:
1749 {
1750   do_multu (SD_, RS, RT, 0);
1751 }
1752
1753 000000,5.RS,5.RT,5.RD,00000011001:SPECIAL:32::MULTU
1754 "multu r<RD>, r<RS>, r<RT>"
1755 *vr5000:
1756 *r3900:
1757 {
1758   do_multu (SD_, RS, RT, 0);
1759 }
1760
1761
1762 :function:::void:do_nor:int rs, int rt, int rd
1763 {
1764   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
1765   GPR[rd] = ~ (GPR[rs] | GPR[rt]);
1766   TRACE_ALU_RESULT (GPR[rd]);
1767 }
1768
1769 000000,5.RS,5.RT,5.RD,00000,100111:SPECIAL:32::NOR
1770 "nor r<RD>, r<RS>, r<RT>"
1771 *mipsI,mipsII,mipsIII,mipsIV:
1772 *vr4100:
1773 *vr5000:
1774 *r3900:
1775 {
1776   do_nor (SD_, RS, RT, RD);
1777 }
1778
1779
1780 :function:::void:do_or:int rs, int rt, int rd
1781 {
1782   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
1783   GPR[rd] = (GPR[rs] | GPR[rt]);
1784   TRACE_ALU_RESULT (GPR[rd]);
1785 }
1786
1787 000000,5.RS,5.RT,5.RD,00000,100101:SPECIAL:32::OR
1788 "or r<RD>, r<RS>, r<RT>"
1789 *mipsI,mipsII,mipsIII,mipsIV:
1790 *vr4100:
1791 *vr5000:
1792 *r3900:
1793 {
1794   do_or (SD_, RS, RT, RD);
1795 }
1796
1797
1798
1799 :function:::void:do_ori:int rs, int rt, unsigned immediate
1800 {
1801   TRACE_ALU_INPUT2 (GPR[rs], immediate);
1802   GPR[rt] = (GPR[rs] | immediate);
1803   TRACE_ALU_RESULT (GPR[rt]);
1804 }
1805
1806 001101,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::ORI
1807 "ori r<RT>, r<RS>, <IMMEDIATE>"
1808 *mipsI,mipsII,mipsIII,mipsIV:
1809 *vr4100:
1810 *vr5000:
1811 *r3900:
1812 {
1813   do_ori (SD_, RS, RT, IMMEDIATE);
1814 }
1815
1816
1817 110011,5.RS,nnnnn,16.OFFSET:NORMAL:32::PREF
1818 *mipsIV:
1819 *vr5000:
1820 {
1821   unsigned32 instruction = instruction_0;
1822   signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
1823   int hint = ((instruction >> 16) & 0x0000001F);
1824   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
1825   {
1826     address_word vaddr = ((unsigned64)op1 + offset);
1827     address_word paddr;
1828     int uncached;
1829     {
1830       if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
1831         Prefetch(uncached,paddr,vaddr,isDATA,hint);
1832     }
1833   }
1834 }
1835
1836 :function:::void:do_store:unsigned access, address_word base, address_word offset, unsigned_word word
1837 {
1838   address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
1839   address_word reverseendian = (ReverseEndian ? (mask ^ access) : 0);
1840   address_word bigendiancpu = (BigEndianCPU ? (mask ^ access) : 0);
1841   unsigned int byte;
1842   address_word paddr;
1843   int uncached;
1844   unsigned64 memval;
1845   address_word vaddr;
1846
1847   vaddr = base + offset;
1848   if ((vaddr & access) != 0)
1849     {
1850       SIM_CORE_SIGNAL (SD, STATE_CPU(SD, 0), cia, read_map, access+1, vaddr, write_transfer, sim_core_unaligned_signal);
1851     }
1852   AddressTranslation (vaddr, isDATA, isSTORE, &paddr, &uncached, isTARGET, isREAL);
1853   paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverseendian));
1854   byte = ((vaddr & mask) ^ bigendiancpu);
1855   memval = (word << (8 * byte));
1856   StoreMemory (uncached, access, memval, 0, paddr, vaddr, isREAL);
1857 }
1858
1859
1860 101000,5.BASE,5.RT,16.OFFSET:NORMAL:32::SB
1861 "sb r<RT>, <OFFSET>(r<BASE>)"
1862 *mipsI,mipsII,mipsIII,mipsIV:
1863 *vr4100:
1864 *vr5000:
1865 *r3900:
1866 {
1867   do_store (SD_, AccessLength_BYTE, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
1868 }
1869
1870
1871 111000,5.BASE,5.RT,16.OFFSET:NORMAL:32::SC
1872 "sc r<RT>, <OFFSET>(r<BASE>)"
1873 *mipsII:
1874 *mipsIII:
1875 *mipsIV:
1876 *vr4100:
1877 *vr5000:
1878 {
1879   unsigned32 instruction = instruction_0;
1880   signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
1881   signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
1882   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
1883   {
1884     address_word vaddr = ((unsigned64)op1 + offset);
1885     address_word paddr;
1886     int uncached;
1887     if ((vaddr & 3) != 0)
1888       {
1889         SIM_CORE_SIGNAL (SD, CPU, cia, read_map, 4, vaddr, write_transfer, sim_core_unaligned_signal);
1890       }
1891     else
1892       {
1893         if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
1894           {
1895             unsigned64 memval = 0;
1896             unsigned64 memval1 = 0;
1897             unsigned64 mask = 0x7;
1898             unsigned int byte;
1899             paddr = ((paddr & ~mask) | ((paddr & mask) ^ (ReverseEndian << 2)));
1900             byte = ((vaddr & mask) ^ (BigEndianCPU << 2));
1901             memval = ((unsigned64) op2 << (8 * byte));
1902             if (LLBIT)
1903               {
1904                 StoreMemory(uncached,AccessLength_WORD,memval,memval1,paddr,vaddr,isREAL);
1905               }
1906             GPR[(instruction >> 16) & 0x0000001F] = LLBIT;
1907           }
1908       }
1909   }
1910 }
1911
1912
1913 111100,5.BASE,5.RT,16.OFFSET:NORMAL:64::SCD
1914 "scd r<RT>, <OFFSET>(r<BASE>)"
1915 *mipsIII:
1916 *mipsIV:
1917 *vr4100:
1918 *vr5000:
1919 {
1920   unsigned32 instruction = instruction_0;
1921   signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
1922   signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
1923   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
1924   {
1925     address_word vaddr = ((unsigned64)op1 + offset);
1926     address_word paddr;
1927     int uncached;
1928     if ((vaddr & 7) != 0)
1929       {
1930         SIM_CORE_SIGNAL (SD, CPU, cia, read_map, 8, vaddr, write_transfer, sim_core_unaligned_signal);
1931       }
1932     else
1933       {
1934         if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
1935           {
1936             unsigned64 memval = 0;
1937             unsigned64 memval1 = 0;
1938             memval = op2;
1939             if (LLBIT)
1940               {
1941                 StoreMemory(uncached,AccessLength_DOUBLEWORD,memval,memval1,paddr,vaddr,isREAL);
1942               }
1943             GPR[(instruction >> 16) & 0x0000001F] = LLBIT;
1944           }
1945       }
1946   }
1947 }
1948
1949
1950 111111,5.BASE,5.RT,16.OFFSET:NORMAL:64::SD
1951 "sd r<RT>, <OFFSET>(r<BASE>)"
1952 *mipsIII:
1953 *mipsIV:
1954 *vr4100:
1955 *vr5000:
1956 {
1957   do_store (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
1958 }
1959
1960
1961 1111,ZZ!0!1!3,5.BASE,5.RT,16.OFFSET:NORMAL:64::SDCz
1962 "sdc<ZZ> r<RT>, <OFFSET>(r<BASE>)"
1963 *mipsII:
1964 *mipsIII:
1965 *mipsIV:
1966 *vr4100:
1967 *vr5000:
1968 {
1969   do_store (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), COP_SD (ZZ, RT));
1970 }
1971
1972
1973 101100,5.BASE,5.RT,16.OFFSET:NORMAL:64::SDL
1974 "sdl r<RT>, <OFFSET>(r<BASE>)"
1975 *mipsIII:
1976 *mipsIV:
1977 *vr4100:
1978 *vr5000:
1979 {
1980   do_store_left (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
1981 }
1982
1983
1984 101101,5.BASE,5.RT,16.OFFSET:NORMAL:64::SDR
1985 "sdr r<RT>, <OFFSET>(r<BASE>)"
1986 *mipsIII:
1987 *mipsIV:
1988 *vr4100:
1989 *vr5000:
1990 {
1991   do_store_right (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
1992 }
1993
1994
1995 101001,5.BASE,5.RT,16.OFFSET:NORMAL:32::SH
1996 "sh r<RT>, <OFFSET>(r<BASE>)"
1997 *mipsI,mipsII,mipsIII,mipsIV:
1998 *vr4100:
1999 *vr5000:
2000 *r3900:
2001 {
2002   do_store (SD_, AccessLength_HALFWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
2003 }
2004
2005
2006 :function:::void:do_sll:int rt, int rd, int shift
2007 {
2008   unsigned32 temp = (GPR[rt] << shift);
2009   TRACE_ALU_INPUT2 (GPR[rt], shift);
2010   GPR[rd] = EXTEND32 (temp);
2011   TRACE_ALU_RESULT (GPR[rd]);
2012 }
2013
2014 00000000000,5.RT,5.RD,5.SHIFT,000000:SPECIAL:32::SLL
2015 "sll r<RD>, r<RT>, <SHIFT>"
2016 *mipsI,mipsII,mipsIII,mipsIV:
2017 *vr4100:
2018 *vr5000:
2019 *r3900:
2020 {
2021   do_sll (SD_, RT, RD, SHIFT);
2022 }
2023
2024
2025 :function:::void:do_sllv:int rs, int rt, int rd
2026 {
2027   int s = MASKED (GPR[rs], 4, 0);
2028   unsigned32 temp = (GPR[rt] << s);
2029   TRACE_ALU_INPUT2 (GPR[rt], s);
2030   GPR[rd] = EXTEND32 (temp);
2031   TRACE_ALU_RESULT (GPR[rd]);
2032 }
2033
2034 000000,5.RS,5.RT,5.RD,00000000100:SPECIAL:32::SLLV
2035 "sllv r<RD>, r<RT>, r<RS>"
2036 *mipsI,mipsII,mipsIII,mipsIV:
2037 *vr4100:
2038 *vr5000:
2039 *r3900:
2040 {
2041   do_sllv (SD_, RS, RT, RD);
2042 }
2043
2044
2045 :function:::void:do_slt:int rs, int rt, int rd
2046 {
2047   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
2048   GPR[rd] = ((signed_word) GPR[rs] < (signed_word) GPR[rt]);
2049   TRACE_ALU_RESULT (GPR[rd]);
2050 }
2051
2052 000000,5.RS,5.RT,5.RD,00000101010:SPECIAL:32::SLT
2053 "slt r<RD>, r<RS>, r<RT>"
2054 *mipsI,mipsII,mipsIII,mipsIV:
2055 *vr4100:
2056 *vr5000:
2057 *r3900:
2058 {
2059   do_slt (SD_, RS, RT, RD);
2060 }
2061
2062
2063 :function:::void:do_slti:int rs, int rt, unsigned16 immediate
2064 {
2065   TRACE_ALU_INPUT2 (GPR[rs], EXTEND16 (immediate));
2066   GPR[rt] = ((signed_word) GPR[rs] < (signed_word) EXTEND16 (immediate));
2067   TRACE_ALU_RESULT (GPR[rt]);
2068 }
2069
2070 001010,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::SLTI
2071 "slti r<RT>, r<RS>, <IMMEDIATE>"
2072 *mipsI,mipsII,mipsIII,mipsIV:
2073 *vr4100:
2074 *vr5000:
2075 *r3900:
2076 {
2077   do_slti (SD_, RS, RT, IMMEDIATE);
2078 }
2079
2080
2081 :function:::void:do_sltiu:int rs, int rt, unsigned16 immediate
2082 {
2083   TRACE_ALU_INPUT2 (GPR[rs], EXTEND16 (immediate));
2084   GPR[rt] = ((unsigned_word) GPR[rs] < (unsigned_word) EXTEND16 (immediate));
2085   TRACE_ALU_RESULT (GPR[rt]);
2086 }
2087
2088 001011,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::SLTIU
2089 "sltiu r<RT>, r<RS>, <IMMEDIATE>"
2090 *mipsI,mipsII,mipsIII,mipsIV:
2091 *vr4100:
2092 *vr5000:
2093 *r3900:
2094 {
2095   do_sltiu (SD_, RS, RT, IMMEDIATE);
2096 }
2097
2098
2099
2100 :function:::void:do_sltu:int rs, int rt, int rd
2101 {
2102   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
2103   GPR[rd] = ((unsigned_word) GPR[rs] < (unsigned_word) GPR[rt]);
2104   TRACE_ALU_RESULT (GPR[rd]);
2105 }
2106
2107 000000,5.RS,5.RT,5.RD,00000101011:SPECIAL:32::SLTU
2108 "sltu r<RD>, r<RS>, r<RT>"
2109 *mipsI,mipsII,mipsIII,mipsIV:
2110 *vr4100:
2111 *vr5000:
2112 *r3900:
2113 {
2114   do_sltu (SD_, RS, RT, RD);
2115 }
2116
2117
2118 :function:::void:do_sra:int rt, int rd, int shift
2119 {
2120   signed32 temp = (signed32) GPR[rt] >> shift;
2121   TRACE_ALU_INPUT2 (GPR[rt], shift);
2122   GPR[rd] = EXTEND32 (temp);
2123   TRACE_ALU_RESULT (GPR[rd]);
2124 }
2125
2126 000000,00000,5.RT,5.RD,5.SHIFT,000011:SPECIAL:32::SRA
2127 "sra r<RD>, r<RT>, <SHIFT>"
2128 *mipsI,mipsII,mipsIII,mipsIV:
2129 *vr4100:
2130 *vr5000:
2131 *r3900:
2132 {
2133   do_sra (SD_, RT, RD, SHIFT);
2134 }
2135
2136
2137
2138 :function:::void:do_srav:int rs, int rt, int rd
2139 {
2140   int s = MASKED (GPR[rs], 4, 0);
2141   signed32 temp = (signed32) GPR[rt] >> s;
2142   TRACE_ALU_INPUT2 (GPR[rt], s);
2143   GPR[rd] = EXTEND32 (temp);
2144   TRACE_ALU_RESULT (GPR[rd]);
2145 }
2146
2147 000000,5.RS,5.RT,5.RD,00000000111:SPECIAL:32::SRAV
2148 "srav r<RD>, r<RT>, r<RS>"
2149 *mipsI,mipsII,mipsIII,mipsIV:
2150 *vr4100:
2151 *vr5000:
2152 *r3900:
2153 {
2154   do_srav (SD_, RS, RT, RD);
2155 }
2156
2157
2158
2159 :function:::void:do_srl:int rt, int rd, int shift
2160 {
2161   unsigned32 temp = (unsigned32) GPR[rt] >> shift;
2162   TRACE_ALU_INPUT2 (GPR[rt], shift);
2163   GPR[rd] = EXTEND32 (temp);
2164   TRACE_ALU_RESULT (GPR[rd]);
2165 }
2166
2167 000000,00000,5.RT,5.RD,5.SHIFT,000010:SPECIAL:32::SRL
2168 "srl r<RD>, r<RT>, <SHIFT>"
2169 *mipsI,mipsII,mipsIII,mipsIV:
2170 *vr4100:
2171 *vr5000:
2172 *r3900:
2173 {
2174   do_srl (SD_, RT, RD, SHIFT);
2175 }
2176
2177
2178 :function:::void:do_srlv:int rs, int rt, int rd
2179 {
2180   int s = MASKED (GPR[rs], 4, 0);
2181   unsigned32 temp = (unsigned32) GPR[rt] >> s;
2182   TRACE_ALU_INPUT2 (GPR[rt], s);
2183   GPR[rd] = EXTEND32 (temp);
2184   TRACE_ALU_RESULT (GPR[rd]);
2185 }
2186
2187 000000,5.RS,5.RT,5.RD,00000000110:SPECIAL:32::SRLV
2188 "srlv r<RD>, r<RT>, r<RS>"
2189 *mipsI,mipsII,mipsIII,mipsIV:
2190 *vr4100:
2191 *vr5000:
2192 *r3900:
2193 {
2194   do_srlv (SD_, RS, RT, RD);
2195 }
2196
2197
2198 000000,5.RS,5.RT,5.RD,00000100010:SPECIAL:32::SUB
2199 "sub r<RD>, r<RS>, r<RT>"
2200 *mipsI,mipsII,mipsIII,mipsIV:
2201 *vr4100:
2202 *vr5000:
2203 *r3900:
2204 {
2205   TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
2206   {
2207     ALU32_BEGIN (GPR[RS]);
2208     ALU32_SUB (GPR[RT]);
2209     ALU32_END (GPR[RD]);
2210   }
2211   TRACE_ALU_RESULT (GPR[RD]);
2212 }
2213
2214
2215 :function:::void:do_subu:int rs, int rt, int rd
2216 {
2217   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
2218   GPR[rd] = EXTEND32 (GPR[rs] - GPR[rt]);
2219   TRACE_ALU_RESULT (GPR[rd]);
2220 }
2221
2222 000000,5.RS,5.RT,5.RD,00000100011:SPECIAL:32::SUBU
2223 "subu r<RD>, r<RS>, r<RT>"
2224 *mipsI,mipsII,mipsIII,mipsIV:
2225 *vr4100:
2226 *vr5000:
2227 *r3900:
2228 {
2229   do_subu (SD_, RS, RT, RD);
2230 }
2231
2232
2233 101011,5.BASE,5.RT,16.OFFSET:NORMAL:32::SW
2234 "sw r<RT>, <OFFSET>(r<BASE>)"
2235 *mipsI,mipsII,mipsIII,mipsIV:
2236 *vr4100:
2237 *r3900:
2238 *vr5000:
2239 {
2240   do_store (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
2241 }
2242
2243
2244 1110,ZZ!0!1!3,5.BASE,5.RT,16.OFFSET:NORMAL:32::SWCz
2245 "swc<ZZ> r<RT>, <OFFSET>(r<BASE>)"
2246 *mipsI,mipsII,mipsIII,mipsIV:
2247 *vr4100:
2248 *vr5000:
2249 *r3900:
2250 {
2251   do_store (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), COP_SW (ZZ, RT));
2252 }
2253
2254
2255
2256 :function:::void:do_store_left:unsigned access, address_word base, address_word offset, unsigned_word rt
2257 {
2258   address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
2259   address_word reverseendian = (ReverseEndian ? -1 : 0);
2260   address_word bigendiancpu = (BigEndianCPU ? -1 : 0);
2261   unsigned int byte;
2262   unsigned int word;
2263   address_word paddr;
2264   int uncached;
2265   unsigned64 memval;
2266   address_word vaddr;
2267   int nr_lhs_bits;
2268   int nr_rhs_bits;
2269
2270   vaddr = base + offset;
2271   AddressTranslation (vaddr, isDATA, isSTORE, &paddr, &uncached, isTARGET, isREAL);
2272   paddr = (paddr ^ (reverseendian & mask));
2273   if (BigEndianMem == 0)
2274     paddr = paddr & ~access;
2275
2276   /* compute where within the word/mem we are */
2277   byte = ((vaddr ^ bigendiancpu) & access); /* 0..access */
2278   word = ((vaddr ^ bigendiancpu) & (mask & ~access)) / (access + 1); /* 0..1 */
2279   nr_lhs_bits = 8 * byte + 8;
2280   nr_rhs_bits = 8 * access - 8 * byte;
2281   /* nr_lhs_bits + nr_rhs_bits == 8 * (accesss + 1) */
2282   /* fprintf (stderr, "s[wd]l: 0x%08lx%08lx 0x%08lx%08lx %d:%d %d+%d\n",
2283            (long) ((unsigned64) vaddr >> 32), (long) vaddr,
2284            (long) ((unsigned64) paddr >> 32), (long) paddr,
2285            word, byte, nr_lhs_bits, nr_rhs_bits); */
2286
2287   if (word == 0)
2288     {
2289       memval = (rt >> nr_rhs_bits);
2290     }
2291   else
2292     {
2293       memval = (rt << nr_lhs_bits);
2294     }
2295   /* fprintf (stderr, "s[wd]l: 0x%08lx%08lx -> 0x%08lx%08lx\n",
2296            (long) ((unsigned64) rt >> 32), (long) rt,
2297            (long) ((unsigned64) memval >> 32), (long) memval); */
2298   StoreMemory (uncached, byte, memval, 0, paddr, vaddr, isREAL);
2299 }
2300
2301
2302 101010,5.BASE,5.RT,16.OFFSET:NORMAL:32::SWL
2303 "swl r<RT>, <OFFSET>(r<BASE>)"
2304 *mipsI,mipsII,mipsIII,mipsIV:
2305 *vr4100:
2306 *vr5000:
2307 *r3900:
2308 {
2309   do_store_left (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
2310 }
2311
2312
2313 :function:::void:do_store_right:unsigned access, address_word base, address_word offset, unsigned_word rt
2314 {
2315   address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
2316   address_word reverseendian = (ReverseEndian ? -1 : 0);
2317   address_word bigendiancpu = (BigEndianCPU ? -1 : 0);
2318   unsigned int byte;
2319   address_word paddr;
2320   int uncached;
2321   unsigned64 memval;
2322   address_word vaddr;
2323
2324   vaddr = base + offset;
2325   AddressTranslation (vaddr, isDATA, isSTORE, &paddr, &uncached, isTARGET, isREAL);
2326   paddr = (paddr ^ (reverseendian & mask));
2327   if (BigEndianMem != 0)
2328     paddr &= ~access;
2329   byte = ((vaddr & mask) ^ (bigendiancpu & mask));
2330   memval = (rt << (byte * 8));
2331   StoreMemory (uncached, access - (access & byte), memval, 0, paddr, vaddr, isREAL);
2332 }
2333
2334 101110,5.BASE,5.RT,16.OFFSET:NORMAL:32::SWR
2335 "swr r<RT>, <OFFSET>(r<BASE>)"
2336 *mipsI,mipsII,mipsIII,mipsIV:
2337 *vr4100:
2338 *vr5000:
2339 *r3900:
2340 {
2341   do_store_right (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
2342 }
2343
2344
2345 000000000000000000000,5.STYPE,001111:SPECIAL:32::SYNC
2346 "sync":STYPE == 0
2347 "sync <STYPE>"
2348 *mipsII:
2349 *mipsIII:
2350 *mipsIV:
2351 *vr4100:
2352 *vr5000:
2353 *r3900:
2354 {
2355   SyncOperation (STYPE);
2356 }
2357
2358
2359 000000,20.CODE,001100:SPECIAL:32::SYSCALL
2360 "syscall <CODE>"
2361 *mipsI,mipsII,mipsIII,mipsIV:
2362 *vr4100:
2363 *vr5000:
2364 *r3900:
2365 {
2366   SignalException(SystemCall, instruction_0);
2367 }
2368
2369
2370 000000,5.RS,5.RT,10.CODE,110100:SPECIAL:32::TEQ
2371 "teq r<RS>, r<RT>"
2372 *mipsII:
2373 *mipsIII:
2374 *mipsIV:
2375 *vr4100:
2376 *vr5000:
2377 {
2378   if ((signed_word) GPR[RS] == (signed_word) GPR[RT])
2379     SignalException(Trap, instruction_0);
2380 }
2381
2382
2383 000001,5.RS,01100,16.IMMEDIATE:REGIMM:32::TEQI
2384 "teqi r<RS>, <IMMEDIATE>"
2385 *mipsII:
2386 *mipsIII:
2387 *mipsIV:
2388 *vr4100:
2389 *vr5000:
2390 {
2391   if ((signed_word) GPR[RS] == (signed_word) EXTEND16 (IMMEDIATE))
2392     SignalException(Trap, instruction_0);
2393 }
2394
2395
2396 000000,5.RS,5.RT,10.CODE,110000:SPECIAL:32::TGE
2397 "tge r<RS>, r<RT>"
2398 *mipsII:
2399 *mipsIII:
2400 *mipsIV:
2401 *vr4100:
2402 *vr5000:
2403 {
2404   if ((signed_word) GPR[RS] >= (signed_word) GPR[RT])
2405     SignalException(Trap, instruction_0);
2406 }
2407
2408
2409 000001,5.RS,01000,16.IMMEDIATE:REGIMM:32::TGEI
2410 "tgei r<RS>, <IMMEDIATE>"
2411 *mipsII:
2412 *mipsIII:
2413 *mipsIV:
2414 *vr4100:
2415 *vr5000:
2416 {
2417   if ((signed_word) GPR[RS] >= (signed_word) EXTEND16 (IMMEDIATE))
2418     SignalException(Trap, instruction_0);
2419 }
2420
2421
2422 000001,5.RS,01001,16.IMMEDIATE:REGIMM:32::TGEIU
2423 "tgeiu r<RS>, <IMMEDIATE>"
2424 *mipsII:
2425 *mipsIII:
2426 *mipsIV:
2427 *vr4100:
2428 *vr5000:
2429 {
2430   if ((unsigned_word) GPR[RS] >= (unsigned_word) EXTEND16 (IMMEDIATE))
2431     SignalException(Trap, instruction_0);
2432 }
2433
2434
2435 000000,5.RS,5.RT,10.CODE,110001:SPECIAL:32::TGEU
2436 "tgeu r<RS>, r<RT>"
2437 *mipsII:
2438 *mipsIII:
2439 *mipsIV:
2440 *vr4100:
2441 *vr5000:
2442 {
2443   if ((unsigned_word) GPR[RS] >= (unsigned_word) GPR[RT])
2444     SignalException(Trap, instruction_0);
2445 }
2446
2447
2448 000000,5.RS,5.RT,10.CODE,110010:SPECIAL:32::TLT
2449 "tlt r<RS>, r<RT>"
2450 *mipsII:
2451 *mipsIII:
2452 *mipsIV:
2453 *vr4100:
2454 *vr5000:
2455 {
2456   if ((signed_word) GPR[RS] < (signed_word) GPR[RT])
2457     SignalException(Trap, instruction_0);
2458 }
2459
2460
2461 000001,5.RS,01010,16.IMMEDIATE:REGIMM:32::TLTI
2462 "tlti r<RS>, <IMMEDIATE>"
2463 *mipsII:
2464 *mipsIII:
2465 *mipsIV:
2466 *vr4100:
2467 *vr5000:
2468 {
2469   if ((signed_word) GPR[RS] < (signed_word) EXTEND16 (IMMEDIATE))
2470     SignalException(Trap, instruction_0);
2471 }
2472
2473
2474 000001,5.RS,01011,16.IMMEDIATE:REGIMM:32::TLTIU
2475 "tltiu r<RS>, <IMMEDIATE>"
2476 *mipsII:
2477 *mipsIII:
2478 *mipsIV:
2479 *vr4100:
2480 *vr5000:
2481 {
2482   if ((unsigned_word) GPR[RS] < (unsigned_word) EXTEND16 (IMMEDIATE))
2483     SignalException(Trap, instruction_0);
2484 }
2485
2486
2487 000000,5.RS,5.RT,10.CODE,110011:SPECIAL:32::TLTU
2488 "tltu r<RS>, r<RT>"
2489 *mipsII:
2490 *mipsIII:
2491 *mipsIV:
2492 *vr4100:
2493 *vr5000:
2494 {
2495   if ((unsigned_word) GPR[RS] < (unsigned_word) GPR[RT])
2496     SignalException(Trap, instruction_0);
2497 }
2498
2499
2500 000000,5.RS,5.RT,10.CODE,110110:SPECIAL:32::TNE
2501 "tne r<RS>, r<RT>"
2502 *mipsII:
2503 *mipsIII:
2504 *mipsIV:
2505 *vr4100:
2506 *vr5000:
2507 {
2508   if ((signed_word) GPR[RS] != (signed_word) GPR[RT])
2509     SignalException(Trap, instruction_0);
2510 }
2511
2512
2513 000001,5.RS,01110,16.IMMEDIATE:REGIMM:32::TNEI
2514 "tne r<RS>, <IMMEDIATE>"
2515 *mipsII:
2516 *mipsIII:
2517 *mipsIV:
2518 *vr4100:
2519 *vr5000:
2520 {
2521   if ((signed_word) GPR[RS] != (signed_word) EXTEND16 (IMMEDIATE))
2522     SignalException(Trap, instruction_0);
2523 }
2524
2525
2526 :function:::void:do_xor:int rs, int rt, int rd
2527 {
2528   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
2529   GPR[rd] = GPR[rs] ^ GPR[rt];
2530   TRACE_ALU_RESULT (GPR[rd]);
2531 }
2532
2533 000000,5.RS,5.RT,5.RD,00000100110:SPECIAL:32::XOR
2534 "xor r<RD>, r<RS>, r<RT>"
2535 *mipsI,mipsII,mipsIII,mipsIV:
2536 *vr4100:
2537 *vr5000:
2538 *r3900:
2539 {
2540   do_xor (SD_, RS, RT, RD);
2541 }
2542
2543
2544 :function:::void:do_xori:int rs, int rt, unsigned16 immediate
2545 {
2546   TRACE_ALU_INPUT2 (GPR[rs], immediate);
2547   GPR[rt] = GPR[rs] ^ immediate;
2548   TRACE_ALU_RESULT (GPR[rt]);
2549 }
2550
2551 001110,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::XORI
2552 "xori r<RT>, r<RS>, <IMMEDIATE>"
2553 *mipsI,mipsII,mipsIII,mipsIV:
2554 *vr4100:
2555 *vr5000:
2556 *r3900:
2557 {
2558   do_xori (SD_, RS, RT, IMMEDIATE);
2559 }
2560
2561 \f
2562 //
2563 // MIPS Architecture:
2564 //
2565 //        FPU Instruction Set (COP1 & COP1X)
2566 //
2567
2568
2569 :%s::::FMT:int fmt
2570 {
2571   switch (fmt)
2572     {
2573     case fmt_single: return "s";
2574     case fmt_double: return "d";
2575     case fmt_word: return "w";
2576     case fmt_long: return "l";
2577     default: return "?";
2578     }
2579 }
2580
2581 :%s::::X:int x
2582 {
2583   switch (x)
2584     {
2585     case 0: return "f";
2586     case 1: return "t";
2587     default: return "?";
2588     }
2589 }
2590
2591 :%s::::TF:int tf
2592 {
2593   if (tf)
2594     return "t";
2595   else
2596     return "f";
2597 }
2598
2599 :%s::::ND:int nd
2600 {
2601   if (nd)
2602     return "l";
2603   else
2604     return "";
2605 }
2606
2607 :%s::::COND:int cond
2608 {
2609   switch (cond)
2610     {
2611     case 00: return "f";
2612     case 01: return "un";
2613     case 02: return "eq";
2614     case 03: return "ueq";
2615     case 04: return "olt";
2616     case 05: return "ult";
2617     case 06: return "ole";
2618     case 07: return "ule";
2619     case 010: return "sf";
2620     case 011: return "ngle";
2621     case 012: return "seq";
2622     case 013: return "ngl";
2623     case 014: return "lt";
2624     case 015: return "nge";
2625     case 016: return "le";
2626     case 017: return "ngt";
2627     default: return "?";
2628     }
2629 }
2630
2631
2632 010001,10,3.FMT,00000,5.FS,5.FD,000101:COP1:32,f::ABS.fmt
2633 "abs.%s<FMT> f<FD>, f<FS>"
2634 *mipsI,mipsII,mipsIII,mipsIV:
2635 *vr4100:
2636 *vr5000:
2637 *r3900:
2638 {
2639   unsigned32 instruction = instruction_0;
2640   int destreg = ((instruction >> 6) & 0x0000001F);
2641   int fs = ((instruction >> 11) & 0x0000001F);
2642   int format = ((instruction >> 21) & 0x00000007);
2643   {
2644     if ((format != fmt_single) && (format != fmt_double))
2645       SignalException(ReservedInstruction,instruction);
2646     else
2647       StoreFPR(destreg,format,AbsoluteValue(ValueFPR(fs,format),format));
2648   }
2649 }
2650
2651
2652
2653 010001,10,3.FMT,5.FT,5.FS,5.FD,000000:COP1:32,f::ADD.fmt
2654 "add.%s<FMT> f<FD>, f<FS>, f<FT>"
2655 *mipsI,mipsII,mipsIII,mipsIV:
2656 *vr4100:
2657 *vr5000:
2658 *r3900:
2659 {
2660   unsigned32 instruction = instruction_0;
2661   int destreg = ((instruction >> 6) & 0x0000001F);
2662   int fs = ((instruction >> 11) & 0x0000001F);
2663   int ft = ((instruction >> 16) & 0x0000001F);
2664   int format = ((instruction >> 21) & 0x00000007);
2665   {
2666     if ((format != fmt_single) && (format != fmt_double))
2667       SignalException(ReservedInstruction, instruction);
2668     else
2669       StoreFPR(destreg,format,Add(ValueFPR(fs,format),ValueFPR(ft,format),format));
2670   }
2671 }
2672
2673
2674
2675 // BC1F
2676 // BC1FL
2677 // BC1T
2678 // BC1TL
2679
2680 010001,01000,3.0,1.ND,1.TF,16.OFFSET:COP1S:32,f::BC1a
2681 "bc1%s<TF>%s<ND> <OFFSET>"
2682 *mipsI,mipsII,mipsIII:
2683 {
2684   check_branch_bug ();
2685   TRACE_BRANCH_INPUT (PREVCOC1());
2686   if (PREVCOC1() == TF)
2687     {
2688       address_word dest = NIA + (EXTEND16 (OFFSET) << 2);
2689       TRACE_BRANCH_RESULT (dest);
2690       mark_branch_bug (dest);
2691       DELAY_SLOT (dest);
2692     }
2693   else if (ND)
2694     {
2695       TRACE_BRANCH_RESULT (0);
2696       NULLIFY_NEXT_INSTRUCTION ();
2697     }
2698   else
2699     {
2700       TRACE_BRANCH_RESULT (NIA);
2701     }
2702 }
2703
2704 010001,01000,3.CC,1.ND,1.TF,16.OFFSET:COP1S:32,f::BC1b
2705 "bc1%s<TF>%s<ND> <OFFSET>":CC == 0
2706 "bc1%s<TF>%s<ND> <CC>, <OFFSET>"
2707 *mipsIV:
2708 *vr5000:
2709 #*vr4100:
2710 *r3900:
2711 {
2712   check_branch_bug ();
2713   if (GETFCC(CC) == TF)
2714     {
2715       address_word dest = NIA + (EXTEND16 (OFFSET) << 2);
2716       mark_branch_bug (dest);
2717       DELAY_SLOT (dest);
2718     }
2719   else if (ND)
2720     {
2721       NULLIFY_NEXT_INSTRUCTION ();
2722     }
2723 }
2724
2725
2726
2727
2728
2729
2730 // C.EQ.S
2731 // C.EQ.D
2732 // ...
2733
2734 :function:::void:do_c_cond_fmt:int fmt, int ft, int fs, int cc, int cond, instruction_word insn
2735 {
2736   if ((fmt != fmt_single) && (fmt != fmt_double))
2737     SignalException (ReservedInstruction, insn);
2738   else
2739     {
2740       int less;
2741       int equal;
2742       int unordered;
2743       int condition;
2744       unsigned64 ofs = ValueFPR (fs, fmt);
2745       unsigned64 oft = ValueFPR (ft, fmt);
2746       if (NaN (ofs, fmt) || NaN (oft, fmt))
2747         {
2748           if (FCSR & FP_ENABLE (IO))
2749             {
2750               FCSR |= FP_CAUSE (IO);
2751               SignalExceptionFPE ();
2752             }
2753           less = 0;
2754           equal = 0;
2755           unordered = 1;
2756         }
2757       else
2758         {
2759           less = Less (ofs, oft, fmt);
2760           equal = Equal (ofs, oft, fmt);
2761           unordered = 0;
2762         }
2763       condition = (((cond & (1 << 2)) && less)
2764                    || ((cond & (1 << 1)) && equal)
2765                    || ((cond & (1 << 0)) && unordered));
2766       SETFCC (cc, condition);
2767     }
2768 }
2769
2770 010001,10,3.FMT,5.FT,5.FS,3.0,00,11,4.COND:COP1:32::C.cond.fmta
2771 "c.%s<COND>.%s<FMT> f<FS>, f<FT>"
2772 *mipsI,mipsII,mipsIII:
2773 {
2774   do_c_cond_fmt (SD_, FMT, FT, FS, 0, COND, instruction_0);
2775 }
2776
2777 010001,10,3.FMT,5.FT,5.FS,3.CC,00,11,4.COND:COP1:32::C.cond.fmtb
2778 "c.%s<COND>.%s<FMT> f<FS>, f<FT>":CC == 0
2779 "c.%s<COND>.%s<FMT> <CC>, f<FS>, f<FT>"
2780 *mipsIV:
2781 *vr4100:
2782 *vr5000:
2783 *r3900:
2784 {
2785   do_c_cond_fmt (SD_, FMT, FT, FS, CC, COND, instruction_0);
2786 }
2787
2788
2789 010001,10,3.FMT,00000,5.FS,5.FD,001010:COP1:64::CEIL.L.fmt
2790 "ceil.l.%s<FMT> f<FD>, f<FS>"
2791 *mipsIII:
2792 *mipsIV:
2793 *vr4100:
2794 *vr5000:
2795 *r3900:
2796 {
2797   unsigned32 instruction = instruction_0;
2798   int destreg = ((instruction >> 6) & 0x0000001F);
2799   int fs = ((instruction >> 11) & 0x0000001F);
2800   int format = ((instruction >> 21) & 0x00000007);
2801   {
2802     if ((format != fmt_single) && (format != fmt_double))
2803       SignalException(ReservedInstruction,instruction);
2804     else
2805       StoreFPR(destreg,fmt_long,Convert(FP_RM_TOPINF,ValueFPR(fs,format),format,fmt_long));
2806   }
2807 }
2808
2809
2810 010001,10,3.FMT,00000,5.FS,5.FD,001110:COP1:32::CEIL.W
2811 *mipsII:
2812 *mipsIII:
2813 *mipsIV:
2814 *vr4100:
2815 *vr5000:
2816 *r3900:
2817 {
2818   unsigned32 instruction = instruction_0;
2819   int destreg = ((instruction >> 6) & 0x0000001F);
2820   int fs = ((instruction >> 11) & 0x0000001F);
2821   int format = ((instruction >> 21) & 0x00000007);
2822   {
2823   if ((format != fmt_single) && (format != fmt_double))
2824    SignalException(ReservedInstruction,instruction);
2825   else
2826    StoreFPR(destreg,fmt_word,Convert(FP_RM_TOPINF,ValueFPR(fs,format),format,fmt_word));
2827   }
2828 }
2829
2830
2831 // CFC1
2832 // CTC1
2833 010001,00,X,10,5.RT,5.FS,00000000000:COP1Sa:32::CxC1
2834 "c%s<X>c1 r<RT>, f<FS>"
2835 *mipsI:
2836 *mipsII:
2837 *mipsIII:
2838 {
2839   if (X)
2840     {
2841       if (FS == 0)
2842         PENDING_FILL((FS + FCR0IDX),VL4_8(GPR[RT]));
2843       else if (FS == 31)
2844         PENDING_FILL((FS + FCR31IDX),VL4_8(GPR[RT]));
2845       /* else NOP */
2846       PENDING_FILL(COCIDX,0); /* special case */
2847     }
2848   else
2849     { /* control from */
2850       if (FS == 0)
2851         PENDING_FILL(RT,SIGNEXTEND(FCR0,32));
2852       else if (FS == 31)
2853         PENDING_FILL(RT,SIGNEXTEND(FCR31,32));
2854       /* else NOP */
2855     }
2856 }
2857 010001,00,X,10,5.RT,5.FS,00000000000:COP1Sb:32::CxC1
2858 "c%s<X>c1 r<RT>, f<FS>"
2859 *mipsIV:
2860 *vr4100:
2861 *vr5000:
2862 *r3900:
2863 {
2864   if (X)
2865     {
2866       /* control to */
2867       TRACE_ALU_INPUT1 (GPR[RT]);
2868       if (FS == 0)
2869         {
2870           FCR0 = VL4_8(GPR[RT]);
2871           TRACE_ALU_RESULT (FCR0);
2872         }
2873       else if (FS == 31)
2874         {
2875           FCR31 = VL4_8(GPR[RT]);
2876           SETFCC(0,((FCR31 & (1 << 23)) ? 1 : 0));
2877           TRACE_ALU_RESULT (FCR31);
2878         }
2879       else
2880         {
2881           TRACE_ALU_RESULT0 ();
2882         }
2883       /* else NOP */
2884     }
2885   else
2886     { /* control from */
2887       if (FS == 0)
2888         {
2889           TRACE_ALU_INPUT1 (FCR0);
2890           GPR[RT] = SIGNEXTEND (FCR0, 32);
2891         }
2892       else if (FS == 31)
2893         {
2894           TRACE_ALU_INPUT1 (FCR31);
2895           GPR[RT] = SIGNEXTEND (FCR31, 32);
2896         }
2897       TRACE_ALU_RESULT (GPR[RT]);
2898       /* else NOP */
2899     }
2900 }
2901
2902
2903 //
2904 // FIXME: Does not correctly differentiate between mips*
2905 //
2906 010001,10,3.FMT,00000,5.FS,5.FD,100001:COP1:32::CVT.D.fmt
2907 "cvt.d.%s<FMT> f<FD>, f<FS>"
2908 *mipsI,mipsII,mipsIII,mipsIV:
2909 *vr4100:
2910 *vr5000:
2911 *r3900:
2912 {
2913   unsigned32 instruction = instruction_0;
2914   int destreg = ((instruction >> 6) & 0x0000001F);
2915   int fs = ((instruction >> 11) & 0x0000001F);
2916   int format = ((instruction >> 21) & 0x00000007);
2917   {
2918     if ((format == fmt_double) | 0)
2919       SignalException(ReservedInstruction,instruction);
2920     else
2921       StoreFPR(destreg,fmt_double,Convert(GETRM(),ValueFPR(fs,format),format,fmt_double));
2922   }
2923 }
2924
2925
2926 010001,10,3.FMT,00000,5.FS,5.FD,100101:COP1:64::CVT.L.fmt
2927 "cvt.l.%s<FMT> f<FD>, f<FS>"
2928 *mipsIII:
2929 *mipsIV:
2930 *vr4100:
2931 *vr5000:
2932 *r3900:
2933 {
2934   unsigned32 instruction = instruction_0;
2935   int destreg = ((instruction >> 6) & 0x0000001F);
2936   int fs = ((instruction >> 11) & 0x0000001F);
2937   int format = ((instruction >> 21) & 0x00000007);
2938   {
2939     if ((format == fmt_long) | ((format == fmt_long) || (format == fmt_word)))
2940       SignalException(ReservedInstruction,instruction);
2941     else
2942       StoreFPR(destreg,fmt_long,Convert(GETRM(),ValueFPR(fs,format),format,fmt_long));
2943   }
2944 }
2945
2946
2947 //
2948 // FIXME: Does not correctly differentiate between mips*
2949 //
2950 010001,10,3.FMT,00000,5.FS,5.FD,100000:COP1:32::CVT.S.fmt
2951 "cvt.s.%s<FMT> f<FD>, f<FS>"
2952 *mipsI,mipsII,mipsIII,mipsIV:
2953 *vr4100:
2954 *vr5000:
2955 *r3900:
2956 {
2957   unsigned32 instruction = instruction_0;
2958   int destreg = ((instruction >> 6) & 0x0000001F);
2959   int fs = ((instruction >> 11) & 0x0000001F);
2960   int format = ((instruction >> 21) & 0x00000007);
2961   {
2962     if ((format == fmt_single) | 0)
2963       SignalException(ReservedInstruction,instruction);
2964     else
2965       StoreFPR(destreg,fmt_single,Convert(GETRM(),ValueFPR(fs,format),format,fmt_single));
2966   }
2967 }
2968
2969
2970 010001,10,3.FMT,00000,5.FS,5.FD,100100:COP1:32::CVT.W.fmt
2971 "cvt.w.%s<FMT> f<FD>, f<FS>"
2972 *mipsI,mipsII,mipsIII,mipsIV:
2973 *vr4100:
2974 *vr5000:
2975 *r3900:
2976 {
2977   unsigned32 instruction = instruction_0;
2978   int destreg = ((instruction >> 6) & 0x0000001F);
2979   int fs = ((instruction >> 11) & 0x0000001F);
2980   int format = ((instruction >> 21) & 0x00000007);
2981   {
2982     if ((format == fmt_word) | ((format == fmt_long) || (format == fmt_word)))
2983       SignalException(ReservedInstruction,instruction);
2984     else
2985       StoreFPR(destreg,fmt_word,Convert(GETRM(),ValueFPR(fs,format),format,fmt_word));
2986   }
2987 }
2988
2989
2990 010001,10,3.FMT,5.FT,5.FS,5.FD,000011:COP1:32::DIV.fmt
2991 "div.%s<FMT> f<FD>, f<FS>, f<FT>"
2992 *mipsI,mipsII,mipsIII,mipsIV:
2993 *vr4100:
2994 *vr5000:
2995 *r3900:
2996 {
2997   unsigned32 instruction = instruction_0;
2998   int destreg = ((instruction >> 6) & 0x0000001F);
2999   int fs = ((instruction >> 11) & 0x0000001F);
3000   int ft = ((instruction >> 16) & 0x0000001F);
3001   int format = ((instruction >> 21) & 0x00000007);
3002   {
3003     if ((format != fmt_single) && (format != fmt_double))
3004       SignalException(ReservedInstruction,instruction);
3005     else
3006       StoreFPR(destreg,format,Divide(ValueFPR(fs,format),ValueFPR(ft,format),format));
3007   }
3008 }
3009
3010
3011 // DMFC1
3012 // DMTC1
3013 010001,00,X,01,5.RT,5.FS,00000000000:COP1Sa:64::DMxC1
3014 "dm%s<X>c1 r<RT>, f<FS>"
3015 *mipsIII:
3016 {
3017   if (X)
3018     {
3019       if (SizeFGR() == 64)
3020         PENDING_FILL((FS + FGRIDX),GPR[RT]);
3021       else if ((FS & 0x1) == 0)
3022         {
3023           PENDING_FILL(((FS + 1) + FGRIDX),VH4_8(GPR[RT]));
3024           PENDING_FILL((FS + FGRIDX),VL4_8(GPR[RT]));
3025         }
3026     }
3027   else
3028     {
3029       if (SizeFGR() == 64)
3030         PENDING_FILL(RT,FGR[FS]);
3031       else if ((FS & 0x1) == 0)
3032         PENDING_FILL(RT,(SET64HI(FGR[FS+1]) | FGR[FS]));
3033       else
3034         PENDING_FILL(RT,SET64HI(0xDEADC0DE) | 0xBAD0BAD0);
3035     }
3036 }
3037 010001,00,X,01,5.RT,5.FS,00000000000:COP1Sb:64::DMxC1
3038 "dm%s<X>c1 r<RT>, f<FS>"
3039 *mipsIV:
3040 *vr4100:
3041 *vr5000:
3042 *r3900:
3043 {
3044   if (X)
3045     {
3046       if (SizeFGR() == 64)
3047         StoreFPR (FS, fmt_uninterpreted_64, GPR[RT]);
3048       else if ((FS & 0x1) == 0)
3049         StoreFPR (FS, fmt_uninterpreted_64, SET64HI (FGR[FS+1]) | FGR[FS]);
3050     }
3051   else
3052     {
3053       if (SizeFGR() == 64)
3054         GPR[RT] = FGR[FS];
3055       else if ((FS & 0x1) == 0)
3056         GPR[RT] = SET64HI (FGR[FS+1]) | FGR[FS];
3057       else
3058         GPR[RT] = SET64HI (0xDEADC0DE) | 0xBAD0BAD0;
3059     }
3060 }
3061
3062
3063 010001,10,3.FMT,00000,5.FS,5.FD,001011:COP1:64::FLOOR.L.fmt
3064 "floor.l.%s<FMT> f<FD>, f<FS>"
3065 *mipsIII:
3066 *mipsIV:
3067 *vr4100:
3068 *vr5000:
3069 *r3900:
3070 {
3071   unsigned32 instruction = instruction_0;
3072   int destreg = ((instruction >> 6) & 0x0000001F);
3073   int fs = ((instruction >> 11) & 0x0000001F);
3074   int format = ((instruction >> 21) & 0x00000007);
3075   {
3076     if ((format != fmt_single) && (format != fmt_double))
3077       SignalException(ReservedInstruction,instruction);
3078     else
3079       StoreFPR(destreg,fmt_long,Convert(FP_RM_TOMINF,ValueFPR(fs,format),format,fmt_long));
3080   }
3081 }
3082
3083
3084 010001,10,3.FMT,00000,5.FS,5.FD,001111:COP1:32::FLOOR.W.fmt
3085 "floor.w.%s<FMT> f<FD>, f<FS>"
3086 *mipsII:
3087 *mipsIII:
3088 *mipsIV:
3089 *vr4100:
3090 *vr5000:
3091 *r3900:
3092 {
3093   unsigned32 instruction = instruction_0;
3094   int destreg = ((instruction >> 6) & 0x0000001F);
3095   int fs = ((instruction >> 11) & 0x0000001F);
3096   int format = ((instruction >> 21) & 0x00000007);
3097   {
3098     if ((format != fmt_single) && (format != fmt_double))
3099       SignalException(ReservedInstruction,instruction);
3100     else
3101       StoreFPR(destreg,fmt_word,Convert(FP_RM_TOMINF,ValueFPR(fs,format),format,fmt_word));
3102   }
3103 }
3104
3105
3106 110101,5.BASE,5.FT,16.OFFSET:COP1:64::LDC1
3107 "ldc1 f<FT>, <OFFSET>(r<BASE>)"
3108 *mipsII:
3109 *mipsIII:
3110 *mipsIV:
3111 *vr4100:
3112 *vr5000:
3113 *r3900:
3114 {
3115   COP_LD (1, FT, do_load (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET)));
3116 }
3117
3118
3119 010011,5.BASE,5.INDEX,5.0,5.FD,000001:COP1X:64::LDXC1
3120 "ldxc1 f<FD>, r<INDEX>(r<BASE>)"
3121 *mipsIV:
3122 *vr5000:
3123 {
3124   COP_LD (1, FD, do_load (SD_, AccessLength_DOUBLEWORD, GPR[BASE], GPR[INDEX]));
3125 }
3126
3127
3128
3129 110001,5.BASE,5.FT,16.OFFSET:COP1:32::LWC1
3130 "lwc1 f<FT>, <OFFSET>(r<BASE>)"
3131 *mipsI,mipsII,mipsIII,mipsIV:
3132 *vr4100:
3133 *vr5000:
3134 *r3900:
3135 {
3136   COP_LW (1, FT, do_load (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET)));
3137 }
3138
3139
3140 010011,5.BASE,5.INDEX,5.0,5.FD,000000:COP1X:32::LWXC1
3141 "lwxc1 f<FD>, r<INDEX>(r<BASE>)"
3142 *mipsIV:
3143 *vr5000:
3144 {
3145   COP_LW (1, FD, do_load (SD_, AccessLength_WORD, GPR[BASE], GPR[INDEX]));
3146 }
3147
3148
3149
3150 //
3151 // FIXME: Not correct for mips*
3152 //
3153 010011,5.FR,5.FT,5.FS,5.FD,100,001:COP1X:32,f::MADD.D
3154 "madd.d f<FD>, f<FR>, f<FS>, f<FT>"
3155 *mipsIV:
3156 *vr5000:
3157 {
3158   unsigned32 instruction = instruction_0;
3159   int destreg = ((instruction >> 6) & 0x0000001F);
3160   int fs = ((instruction >> 11) & 0x0000001F);
3161   int ft = ((instruction >> 16) & 0x0000001F);
3162   int fr = ((instruction >> 21) & 0x0000001F);
3163   {
3164     StoreFPR(destreg,fmt_double,Add(Multiply(ValueFPR(fs,fmt_double),ValueFPR(ft,fmt_double),fmt_double),ValueFPR(fr,fmt_double),fmt_double));
3165   }
3166 }
3167
3168
3169 010011,5.FR,5.FT,5.FS,5.FD,100,000:COP1X:32,f::MADD.S
3170 "madd.s f<FD>, f<FR>, f<FS>, f<FT>"
3171 *mipsIV:
3172 *vr5000:
3173 {
3174   unsigned32 instruction = instruction_0;
3175   int destreg = ((instruction >> 6) & 0x0000001F);
3176   int fs = ((instruction >> 11) & 0x0000001F);
3177   int ft = ((instruction >> 16) & 0x0000001F);
3178   int fr = ((instruction >> 21) & 0x0000001F);
3179   {
3180     StoreFPR(destreg,fmt_single,Add(Multiply(ValueFPR(fs,fmt_single),ValueFPR(ft,fmt_single),fmt_single),ValueFPR(fr,fmt_single),fmt_single));
3181   }
3182 }
3183
3184
3185 // MFC1
3186 // MTC1
3187 010001,00,X,00,5.RT,5.FS,00000000000:COP1Sa:32::MxC1
3188 "m%s<X>c1 r<RT>, f<FS>"
3189 *mipsI:
3190 *mipsII:
3191 *mipsIII:
3192 {
3193   if (X)
3194     { /*MTC1*/
3195       if (SizeFGR() == 64)
3196         PENDING_FILL ((FS + FGRIDX), (SET64HI(0xDEADC0DE) | VL4_8(GPR[RT])));
3197       else
3198         PENDING_FILL ((FS + FGRIDX), VL4_8(GPR[RT]));
3199     }
3200   else /*MFC1*/
3201     PENDING_FILL (RT, SIGNEXTEND(FGR[FS],32));
3202 }
3203 010001,00,X,00,5.RT,5.FS,00000000000:COP1Sb:32::MxC1
3204 "m%s<X>c1 r<RT>, f<FS>"
3205 *mipsIV:
3206 *vr4100:
3207 *vr5000:
3208 *r3900:
3209 {
3210   int fs = FS;
3211   if (X)
3212     /*MTC1*/
3213     StoreFPR (FS, fmt_uninterpreted_32, VL4_8 (GPR[RT]));
3214   else /*MFC1*/
3215     GPR[RT] = SIGNEXTEND(FGR[FS],32);
3216 }
3217
3218
3219 010001,10,3.FMT,00000,5.FS,5.FD,000110:COP1:32::MOV.fmt
3220 "mov.%s<FMT> f<FD>, f<FS>"
3221 *mipsI,mipsII,mipsIII,mipsIV:
3222 *vr4100:
3223 *vr5000:
3224 *r3900:
3225 {
3226   unsigned32 instruction = instruction_0;
3227   int destreg = ((instruction >> 6) & 0x0000001F);
3228   int fs = ((instruction >> 11) & 0x0000001F);
3229   int format = ((instruction >> 21) & 0x00000007);
3230   {
3231     StoreFPR(destreg,format,ValueFPR(fs,format));
3232   }
3233 }
3234
3235
3236 // MOVF
3237 000000,5.RS,3.CC,0,1.TF,5.RD,00000000001:SPECIAL:32::MOVtf
3238 "mov%s<TF> r<RD>, r<RS>, <CC>"
3239 *mipsIV:
3240 *vr5000:
3241 {
3242   if (GETFCC(CC) == TF)
3243     GPR[RD] = GPR[RS];
3244 }
3245
3246
3247 // MOVF.fmt
3248 010001,10,3.FMT,3.CC,0,1.TF,5.FS,5.FD,010001:COP1:32::MOVtf.fmt
3249 "mov%s<TF>.%s<FMT> f<FD>, f<FS>, <CC>"
3250 *mipsIV:
3251 *vr5000:
3252 {
3253   unsigned32 instruction = instruction_0;
3254   int format = ((instruction >> 21) & 0x00000007);
3255   {
3256    if (GETFCC(CC) == TF)
3257      StoreFPR (FD, format, ValueFPR (FS, format));
3258    else
3259      StoreFPR (FD, format, ValueFPR (FD, format));
3260   }
3261 }
3262
3263
3264 010001,10,3.FMT,5.RT,5.FS,5.FD,010011:COP1:32::MOVN.fmt
3265 *mipsIV:
3266 *vr5000:
3267 {
3268   unsigned32 instruction = instruction_0;
3269   int destreg = ((instruction >> 6) & 0x0000001F);
3270   int fs = ((instruction >> 11) & 0x0000001F);
3271   int format = ((instruction >> 21) & 0x00000007);
3272   {
3273     StoreFPR(destreg,format,ValueFPR(fs,format));
3274   }
3275 }
3276
3277
3278 // MOVT see MOVtf
3279
3280
3281 // MOVT.fmt see MOVtf.fmt
3282
3283
3284
3285 010001,10,3.FMT,5.RT,5.FS,5.FD,010010:COP1:32::MOVZ.fmt
3286 "movz.%s<FMT> f<FD>, f<FS>, r<RT>"
3287 *mipsIV:
3288 *vr5000:
3289 {
3290   unsigned32 instruction = instruction_0;
3291   int destreg = ((instruction >> 6) & 0x0000001F);
3292   int fs = ((instruction >> 11) & 0x0000001F);
3293   int format = ((instruction >> 21) & 0x00000007);
3294   {
3295    StoreFPR(destreg,format,ValueFPR(fs,format));
3296   }
3297 }
3298
3299
3300 // MSUB.fmt
3301 010011,5.FR,5.FT,5.FS,5.FD,101,001:COP1X:32::MSUB.D
3302 "msub.d f<FD>, f<FR>, f<FS>, f<FT>"
3303 *mipsIV:
3304 *vr5000:
3305 {
3306   unsigned32 instruction = instruction_0;
3307   int destreg = ((instruction >> 6) & 0x0000001F);
3308   int fs = ((instruction >> 11) & 0x0000001F);
3309   int ft = ((instruction >> 16) & 0x0000001F);
3310   int fr = ((instruction >> 21) & 0x0000001F);
3311   {
3312     StoreFPR(destreg,fmt_double,Sub(Multiply(ValueFPR(fs,fmt_double),ValueFPR(ft,fmt_double),fmt_double),ValueFPR(fr,fmt_double),fmt_double));
3313   }
3314 }
3315
3316
3317 // MSUB.fmt
3318 010011,5.FR,5.FT,5.FS,5.FD,101000:COP1X:32::MSUB.S
3319 "msub.s f<FD>, f<FR>, f<FS>, f<FT>"
3320 *mipsIV:
3321 *vr5000:
3322 {
3323   unsigned32 instruction = instruction_0;
3324   int destreg = ((instruction >> 6) & 0x0000001F);
3325   int fs = ((instruction >> 11) & 0x0000001F);
3326   int ft = ((instruction >> 16) & 0x0000001F);
3327   int fr = ((instruction >> 21) & 0x0000001F);
3328   {
3329    StoreFPR(destreg,fmt_single,Sub(Multiply(ValueFPR(fs,fmt_single),ValueFPR(ft,fmt_single),fmt_single),ValueFPR(fr,fmt_single),fmt_single));
3330   }
3331 }
3332
3333
3334 // MTC1 see MxC1
3335
3336
3337 010001,10,3.FMT,5.FT,5.FS,5.FD,000010:COP1:32::MUL.fmt
3338 "mul.%s<FMT> f<FD>, f<FS>, f<FT>"
3339 *mipsI,mipsII,mipsIII,mipsIV:
3340 *vr4100:
3341 *vr5000:
3342 *r3900:
3343 {
3344   unsigned32 instruction = instruction_0;
3345   int destreg = ((instruction >> 6) & 0x0000001F);
3346   int fs = ((instruction >> 11) & 0x0000001F);
3347   int ft = ((instruction >> 16) & 0x0000001F);
3348   int format = ((instruction >> 21) & 0x00000007);
3349   {
3350     if ((format != fmt_single) && (format != fmt_double))
3351       SignalException(ReservedInstruction,instruction);
3352     else
3353       StoreFPR(destreg,format,Multiply(ValueFPR(fs,format),ValueFPR(ft,format),format));
3354   }
3355 }
3356
3357
3358 010001,10,3.FMT,00000,5.FS,5.FD,000111:COP1:32::NEG.fmt
3359 "neg.%s<FMT> f<FD>, f<FS>"
3360 *mipsI,mipsII,mipsIII,mipsIV:
3361 *vr4100:
3362 *vr5000:
3363 *r3900:
3364 {
3365   unsigned32 instruction = instruction_0;
3366   int destreg = ((instruction >> 6) & 0x0000001F);
3367   int fs = ((instruction >> 11) & 0x0000001F);
3368   int format = ((instruction >> 21) & 0x00000007);
3369   {
3370     if ((format != fmt_single) && (format != fmt_double))
3371       SignalException(ReservedInstruction,instruction);
3372     else
3373       StoreFPR(destreg,format,Negate(ValueFPR(fs,format),format));
3374   }
3375 }
3376
3377
3378 // NMADD.fmt
3379 010011,5.FR,5.FT,5.FS,5.FD,110001:COP1X:32::NMADD.D
3380 "nmadd.d f<FD>, f<FR>, f<FS>, f<FT>"
3381 *mipsIV:
3382 *vr5000:
3383 {
3384   unsigned32 instruction = instruction_0;
3385   int destreg = ((instruction >> 6) & 0x0000001F);
3386   int fs = ((instruction >> 11) & 0x0000001F);
3387   int ft = ((instruction >> 16) & 0x0000001F);
3388   int fr = ((instruction >> 21) & 0x0000001F);
3389   {
3390    StoreFPR(destreg,fmt_double,Negate(Add(Multiply(ValueFPR(fs,fmt_double),ValueFPR(ft,fmt_double),fmt_double),ValueFPR(fr,fmt_double),fmt_double),fmt_double));
3391   }
3392 }
3393
3394
3395 // NMADD.fmt
3396 010011,5.FR,5.FT,5.FS,5.FD,110000:COP1X:32::NMADD.S
3397 "nmadd.s f<FD>, f<FR>, f<FS>, f<FT>"
3398 *mipsIV:
3399 *vr5000:
3400 {
3401   unsigned32 instruction = instruction_0;
3402   int destreg = ((instruction >> 6) & 0x0000001F);
3403   int fs = ((instruction >> 11) & 0x0000001F);
3404   int ft = ((instruction >> 16) & 0x0000001F);
3405   int fr = ((instruction >> 21) & 0x0000001F);
3406   {
3407    StoreFPR(destreg,fmt_single,Negate(Add(Multiply(ValueFPR(fs,fmt_single),ValueFPR(ft,fmt_single),fmt_single),ValueFPR(fr,fmt_single),fmt_single),fmt_single));
3408   }
3409 }
3410
3411
3412 // NMSUB.fmt
3413 010011,5.FR,5.FT,5.FS,5.FD,111001:COP1X:32::NMSUB.D
3414 "nmsub.d f<FD>, f<FR>, f<FS>, f<FT>"
3415 *mipsIV:
3416 *vr5000:
3417 {
3418   unsigned32 instruction = instruction_0;
3419   int destreg = ((instruction >> 6) & 0x0000001F);
3420   int fs = ((instruction >> 11) & 0x0000001F);
3421   int ft = ((instruction >> 16) & 0x0000001F);
3422   int fr = ((instruction >> 21) & 0x0000001F);
3423   {
3424    StoreFPR(destreg,fmt_double,Negate(Sub(Multiply(ValueFPR(fs,fmt_double),ValueFPR(ft,fmt_double),fmt_double),ValueFPR(fr,fmt_double),fmt_double),fmt_double));
3425   }
3426 }
3427
3428
3429 // NMSUB.fmt
3430 010011,5.FR,5.FT,5.FS,5.FD,111000:COP1X:32::NMSUB.S
3431 "nmsub.s f<FD>, f<FR>, f<FS>, f<FT>"
3432 *mipsIV:
3433 *vr5000:
3434 {
3435   unsigned32 instruction = instruction_0;
3436   int destreg = ((instruction >> 6) & 0x0000001F);
3437   int fs = ((instruction >> 11) & 0x0000001F);
3438   int ft = ((instruction >> 16) & 0x0000001F);
3439   int fr = ((instruction >> 21) & 0x0000001F);
3440   {
3441     StoreFPR(destreg,fmt_single,Negate(Sub(Multiply(ValueFPR(fs,fmt_single),ValueFPR(ft,fmt_single),fmt_single),ValueFPR(fr,fmt_single),fmt_single),fmt_single));
3442   }
3443 }
3444
3445
3446 010011,5.BASE,5.INDEX,5.HINT,00000001111:COP1X:32::PREFX
3447 "prefx <HINT>, r<INDEX>(r<BASE>)"
3448 *mipsIV:
3449 *vr5000:
3450 {
3451   unsigned32 instruction = instruction_0;
3452   int fs = ((instruction >> 11) & 0x0000001F);
3453   signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
3454   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
3455   {
3456     address_word vaddr = ((unsigned64)op1 + (unsigned64)op2);
3457     address_word paddr;
3458     int uncached;
3459     if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
3460       Prefetch(uncached,paddr,vaddr,isDATA,fs);
3461   }
3462 }
3463
3464 010001,10,3.FMT,00000,5.FS,5.FD,010101:COP1:32::RECIP.fmt
3465 *mipsIV:
3466 "recip.%s<FMT> f<FD>, f<FS>"
3467 *vr5000:
3468 {
3469   unsigned32 instruction = instruction_0;
3470   int destreg = ((instruction >> 6) & 0x0000001F);
3471   int fs = ((instruction >> 11) & 0x0000001F);
3472   int format = ((instruction >> 21) & 0x00000007);
3473   {
3474   if ((format != fmt_single) && (format != fmt_double))
3475    SignalException(ReservedInstruction,instruction);
3476   else
3477    StoreFPR(destreg,format,Recip(ValueFPR(fs,format),format));
3478   }
3479 }
3480
3481
3482 010001,10,3.FMT,00000,5.FS,5.FD,001000:COP1:64::ROUND.L.fmt
3483 "round.l.%s<FMT> f<FD>, f<FS>"
3484 *mipsIII:
3485 *mipsIV:
3486 *vr4100:
3487 *vr5000:
3488 *r3900:
3489 {
3490   unsigned32 instruction = instruction_0;
3491   int destreg = ((instruction >> 6) & 0x0000001F);
3492   int fs = ((instruction >> 11) & 0x0000001F);
3493   int format = ((instruction >> 21) & 0x00000007);
3494   {
3495     if ((format != fmt_single) && (format != fmt_double))
3496       SignalException(ReservedInstruction,instruction);
3497     else
3498       StoreFPR(destreg,fmt_long,Convert(FP_RM_NEAREST,ValueFPR(fs,format),format,fmt_long));
3499   }
3500 }
3501
3502
3503 010001,10,3.FMT,00000,5.FS,5.FD,001100:COP1:32::ROUND.W.fmt
3504 "round.w.%s<FMT> f<FD>, f<FS>"
3505 *mipsII:
3506 *mipsIII:
3507 *mipsIV:
3508 *vr4100:
3509 *vr5000:
3510 *r3900:
3511 {
3512   unsigned32 instruction = instruction_0;
3513   int destreg = ((instruction >> 6) & 0x0000001F);
3514   int fs = ((instruction >> 11) & 0x0000001F);
3515   int format = ((instruction >> 21) & 0x00000007);
3516   {
3517   if ((format != fmt_single) && (format != fmt_double))
3518    SignalException(ReservedInstruction,instruction);
3519   else
3520    StoreFPR(destreg,fmt_word,Convert(FP_RM_NEAREST,ValueFPR(fs,format),format,fmt_word));
3521   }
3522 }
3523
3524
3525 010001,10,3.FMT,00000,5.FS,5.FD,010110:COP1:32::RSQRT.fmt
3526 *mipsIV:
3527 "rsqrt.%s<FMT> f<FD>, f<FS>"
3528 *vr5000:
3529 {
3530   unsigned32 instruction = instruction_0;
3531   int destreg = ((instruction >> 6) & 0x0000001F);
3532   int fs = ((instruction >> 11) & 0x0000001F);
3533   int format = ((instruction >> 21) & 0x00000007);
3534   {
3535   if ((format != fmt_single) && (format != fmt_double))
3536    SignalException(ReservedInstruction,instruction);
3537   else
3538    StoreFPR(destreg,format,Recip(SquareRoot(ValueFPR(fs,format),format),format));
3539   }
3540 }
3541
3542
3543 111101,5.BASE,5.FT,16.OFFSET:COP1:64::SDC1
3544 "sdc1 f<FT>, <OFFSET>(r<BASE>)"
3545 *mipsII:
3546 *mipsIII:
3547 *mipsIV:
3548 *vr4100:
3549 *vr5000:
3550 *r3900:
3551 {
3552   do_store (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), COP_SD (1, FT));
3553 }
3554
3555
3556 010011,5.BASE,5.INDEX,5.FS,00000001001:COP1X:64::SDXC1
3557 "ldxc1 f<FS>, r<INDEX>(r<BASE>)"
3558 *mipsIV:
3559 *vr5000:
3560 {
3561   do_store (SD_, AccessLength_DOUBLEWORD, GPR[BASE], GPR[INDEX], COP_SD (1, FS));
3562 }
3563
3564
3565 010001,10,3.FMT,00000,5.FS,5.FD,000100:COP1:32::SQRT.fmt
3566 "sqrt.%s<FMT> f<FD>, f<FS>"
3567 *mipsII:
3568 *mipsIII:
3569 *mipsIV:
3570 *vr4100:
3571 *vr5000:
3572 *r3900:
3573 {
3574   unsigned32 instruction = instruction_0;
3575   int destreg = ((instruction >> 6) & 0x0000001F);
3576   int fs = ((instruction >> 11) & 0x0000001F);
3577   int format = ((instruction >> 21) & 0x00000007);
3578   {
3579     if ((format != fmt_single) && (format != fmt_double))
3580       SignalException(ReservedInstruction,instruction);
3581     else
3582       StoreFPR(destreg,format,(SquareRoot(ValueFPR(fs,format),format)));
3583   }
3584 }
3585
3586
3587 010001,10,3.FMT,5.FT,5.FS,5.FD,000001:COP1:32::SUB.fmt
3588 "sub.%s<FMT> f<FD>, f<FS>, f<FT>"
3589 *mipsI,mipsII,mipsIII,mipsIV:
3590 *vr4100:
3591 *vr5000:
3592 *r3900:
3593 {
3594   unsigned32 instruction = instruction_0;
3595   int destreg = ((instruction >> 6) & 0x0000001F);
3596   int fs = ((instruction >> 11) & 0x0000001F);
3597   int ft = ((instruction >> 16) & 0x0000001F);
3598   int format = ((instruction >> 21) & 0x00000007);
3599   {
3600     if ((format != fmt_single) && (format != fmt_double))
3601       SignalException(ReservedInstruction,instruction);
3602     else
3603       StoreFPR(destreg,format,Sub(ValueFPR(fs,format),ValueFPR(ft,format),format));
3604   }
3605 }
3606
3607
3608
3609 111001,5.BASE,5.FT,16.OFFSET:COP1:32::SWC1
3610 "swc1 f<FT>, <OFFSET>(r<BASE>)"
3611 *mipsI,mipsII,mipsIII,mipsIV:
3612 *vr4100:
3613 *vr5000:
3614 *r3900:
3615 {
3616   unsigned32 instruction = instruction_0;
3617   signed_word offset = EXTEND16 (OFFSET);
3618   int destreg UNUSED = ((instruction >> 16) & 0x0000001F);
3619   signed_word op1 UNUSED = GPR[((instruction >> 21) & 0x0000001F)];
3620   {
3621     address_word vaddr = ((uword64)op1 + offset);
3622     address_word paddr;
3623     int uncached;
3624     if ((vaddr & 3) != 0)
3625       {
3626         SIM_CORE_SIGNAL (SD, CPU, cia, read_map, AccessLength_WORD+1, vaddr, write_transfer, sim_core_unaligned_signal);
3627       }
3628     else
3629       {
3630         if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
3631           {
3632             uword64 memval = 0;
3633             uword64 memval1 = 0;
3634             uword64 mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
3635             address_word reverseendian = (ReverseEndian ?(mask ^ AccessLength_WORD): 0);
3636             address_word bigendiancpu = (BigEndianCPU ?(mask ^ AccessLength_WORD): 0);
3637             unsigned int byte;
3638             paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverseendian));
3639             byte = ((vaddr & mask) ^ bigendiancpu);
3640             memval = (((uword64)COP_SW(((instruction >> 26) & 0x3),destreg)) << (8 * byte));
3641             StoreMemory(uncached,AccessLength_WORD,memval,memval1,paddr,vaddr,isREAL);
3642           }
3643       }
3644   }
3645 }
3646
3647
3648 010011,5.BASE,5.INDEX,5.FS,00000,001000:COP1X:32::SWXC1
3649 "swxc1 f<FS>, r<INDEX>(r<BASE>)"
3650 *mipsIV:
3651 *vr5000:
3652 {
3653   unsigned32 instruction = instruction_0;
3654   int fs = ((instruction >> 11) & 0x0000001F);
3655   signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
3656   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
3657   {
3658    address_word vaddr = ((unsigned64)op1 + op2);
3659    address_word paddr;
3660    int uncached;
3661    if ((vaddr & 3) != 0)
3662      {
3663        SIM_CORE_SIGNAL (SD, CPU, cia, read_map, 4, vaddr, write_transfer, sim_core_unaligned_signal);
3664      }
3665    else
3666    {
3667     if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
3668     {
3669      unsigned64 memval = 0;
3670      unsigned64 memval1 = 0;
3671      unsigned64 mask = 0x7;
3672      unsigned int byte;
3673      paddr = ((paddr & ~mask) | ((paddr & mask) ^ (ReverseEndian << 2)));
3674      byte = ((vaddr & mask) ^ (BigEndianCPU << 2));
3675      memval = (((unsigned64)COP_SW(1,fs)) << (8 * byte));
3676       {
3677        StoreMemory(uncached,AccessLength_WORD,memval,memval1,paddr,vaddr,isREAL);
3678       }
3679     }
3680    }
3681   }
3682 }
3683
3684
3685 010001,10,3.FMT,00000,5.FS,5.FD,001001:COP1:64::TRUNC.L.fmt
3686 "trunc.l.%s<FMT> f<FD>, f<FS>"
3687 *mipsIII:
3688 *mipsIV:
3689 *vr4100:
3690 *vr5000:
3691 *r3900:
3692 {
3693   unsigned32 instruction = instruction_0;
3694   int destreg = ((instruction >> 6) & 0x0000001F);
3695   int fs = ((instruction >> 11) & 0x0000001F);
3696   int format = ((instruction >> 21) & 0x00000007);
3697   {
3698   if ((format != fmt_single) && (format != fmt_double))
3699    SignalException(ReservedInstruction,instruction);
3700   else
3701    StoreFPR(destreg,fmt_long,Convert(FP_RM_TOZERO,ValueFPR(fs,format),format,fmt_long));
3702   }
3703 }
3704
3705
3706 010001,10,3.FMT,00000,5.FS,5.FD,001101:COP1:32::TRUNC.W
3707 "trunc.w.%s<FMT> f<FD>, f<FS>"
3708 *mipsII:
3709 *mipsIII:
3710 *mipsIV:
3711 *vr4100:
3712 *vr5000:
3713 *r3900:
3714 {
3715   unsigned32 instruction = instruction_0;
3716   int destreg = ((instruction >> 6) & 0x0000001F);
3717   int fs = ((instruction >> 11) & 0x0000001F);
3718   int format = ((instruction >> 21) & 0x00000007);
3719   {
3720   if ((format != fmt_single) && (format != fmt_double))
3721    SignalException(ReservedInstruction,instruction);
3722   else
3723    StoreFPR(destreg,fmt_word,Convert(FP_RM_TOZERO,ValueFPR(fs,format),format,fmt_word));
3724   }
3725 }
3726
3727 \f
3728 //
3729 // MIPS Architecture:
3730 //
3731 //        System Control Instruction Set (COP0)
3732 //
3733
3734
3735 010000,01000,00000,16.OFFSET:COP0:32::BC0F
3736 "bc0f <OFFSET>"
3737 *mipsI,mipsII,mipsIII,mipsIV:
3738 *vr4100:
3739 *vr5000:
3740
3741
3742 010000,01000,00010,16.OFFSET:COP0:32::BC0FL
3743 "bc0fl <OFFSET>"
3744 *mipsI,mipsII,mipsIII,mipsIV:
3745 *vr4100:
3746 *vr5000:
3747
3748
3749 010000,01000,00001,16.OFFSET:COP0:32::BC0T
3750 "bc0t <OFFSET>"
3751 *mipsI,mipsII,mipsIII,mipsIV:
3752 *vr4100:
3753
3754
3755 010000,01000,00011,16.OFFSET:COP0:32::BC0TL
3756 "bc0tl <OFFSET>"
3757 *mipsI,mipsII,mipsIII,mipsIV:
3758 *vr4100:
3759 *vr5000:
3760
3761
3762 101111,5.BASE,5.OP,16.OFFSET:NORMAL:32::CACHE
3763 *mipsIII:
3764 *mipsIV:
3765 *vr4100:
3766 *vr5000:
3767 *r3900:
3768 {
3769   unsigned32 instruction = instruction_0;
3770   signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
3771   int hint = ((instruction >> 16) & 0x0000001F);
3772   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
3773   {
3774     address_word vaddr = (op1 + offset);
3775     address_word paddr;
3776     int uncached;
3777     if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
3778       CacheOp(hint,vaddr,paddr,instruction);
3779   }
3780 }
3781
3782
3783 010000,10000,000000000000000,111001:COP0:32::DI
3784 "di"
3785 *mipsI,mipsII,mipsIII,mipsIV:
3786 *vr4100:
3787 *vr5000:
3788
3789
3790 010000,10000,000000000000000,111000:COP0:32::EI
3791 "ei"
3792 *mipsI,mipsII,mipsIII,mipsIV:
3793 *vr4100:
3794 *vr5000:
3795
3796
3797 010000,10000,000000000000000,011000:COP0:32::ERET
3798 "eret"
3799 *mipsIII:
3800 *mipsIV:
3801 *vr4100:
3802 *vr5000:
3803 {
3804   if (SR & status_ERL)
3805     {
3806       /* Oops, not yet available */
3807       sim_io_printf (SD, "Warning: ERET when SR[ERL] set not supported");
3808       NIA = EPC;
3809       SR &= ~status_ERL;
3810     }
3811   else
3812     {
3813       NIA = EPC;
3814       SR &= ~status_EXL;
3815     }
3816 }
3817
3818
3819 010000,00000,5.RT,5.RD,00000,6.REGX:COP0:32::MFC0
3820 "mfc0 r<RT>, r<RD> # <REGX>"
3821 *mipsI,mipsII,mipsIII,mipsIV:
3822 *r3900:
3823 *vr4100:
3824 *vr5000:
3825 {
3826   TRACE_ALU_INPUT0 ();
3827   DecodeCoproc (instruction_0);
3828   TRACE_ALU_RESULT (GPR[RT]);
3829 }
3830
3831 010000,00100,5.RT,5.RD,00000,6.REGX:COP0:32::MTC0
3832 "mtc0 r<RT>, r<RD> # <REGX>"
3833 *mipsI,mipsII,mipsIII,mipsIV:
3834 *r3900:
3835 *vr4100:
3836 *vr5000:
3837 {
3838   DecodeCoproc (instruction_0);
3839 }
3840
3841
3842 010000,10000,000000000000000,010000:COP0:32::RFE
3843 "rfe"
3844 *mipsI,mipsII,mipsIII,mipsIV:
3845 *r3900:
3846 *vr4100:
3847 *vr5000:
3848 {
3849   DecodeCoproc (instruction_0);
3850 }
3851
3852
3853 0100,ZZ!0!1!3,5.COP_FUN0!8,5.COP_FUN1,16.COP_FUN2:NORMAL:32::COPz
3854 "cop<ZZ> <COP_FUN0><COP_FUN1><COP_FUN2>"
3855 *mipsI,mipsII,mipsIII,mipsIV:
3856 *vr4100:
3857 *r3900:
3858 {
3859   DecodeCoproc (instruction_0);
3860 }
3861
3862
3863
3864 010000,10000,000000000000000,001000:COP0:32::TLBP
3865 "tlbp"
3866 *mipsI,mipsII,mipsIII,mipsIV:
3867 *vr4100:
3868 *vr5000:
3869
3870
3871 010000,10000,000000000000000,000001:COP0:32::TLBR
3872 "tlbr"
3873 *mipsI,mipsII,mipsIII,mipsIV:
3874 *vr4100:
3875 *vr5000:
3876
3877
3878 010000,10000,000000000000000,000010:COP0:32::TLBWI
3879 "tlbwi"
3880 *mipsI,mipsII,mipsIII,mipsIV:
3881 *vr4100:
3882 *vr5000:
3883
3884
3885 010000,10000,000000000000000,000110:COP0:32::TLBWR
3886 "tlbwr"
3887 *mipsI,mipsII,mipsIII,mipsIV:
3888 *vr4100:
3889 *vr5000:
3890
3891 \f
3892 :include:::m16.igen
3893 :include:::tx.igen
3894 :include:::vr.igen
3895 \f