sim/mips/sim-main.h

   1 /* MIPS Simulator definition.
   2    Copyright (C) 1997, 1998 Free Software Foundation, Inc.
   3    Contributed by Cygnus Support.
   4
   5 This file is part of GDB, the GNU debugger.
   6
   7 This program is free software; you can redistribute it and/or modify
   8 it under the terms of the GNU General Public License as published by
   9 the Free Software Foundation; either version 2, or (at your option)
  10 any later version.
  11
  12 This program is distributed in the hope that it will be useful,
  13 but WITHOUT ANY WARRANTY; without even the implied warranty of
  14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15 GNU General Public License for more details.
  16
  17 You should have received a copy of the GNU General Public License along
  18 with this program; if not, write to the Free Software Foundation, Inc.,
  19 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
  20
  21 #ifndef SIM_MAIN_H
  22 #define SIM_MAIN_H
  23
  24 /* This simulator doesn't cache the Current Instruction Address */
  25 /* #define SIM_ENGINE_HALT_HOOK(SD, LAST_CPU, CIA) */
  26 /* #define SIM_ENGINE_RESUME_HOOK(SD, LAST_CPU, CIA) */
  27
  28 #define SIM_HAVE_BIENDIAN
  29
  30
  31 /* hobble some common features for moment */
  32 #define WITH_WATCHPOINTS 1
  33 #define WITH_MODULO_MEMORY 1
  34
  35
  36 #define SIM_CORE_SIGNAL(SD,CPU,CIA,MAP,NR_BYTES,ADDR,TRANSFER,ERROR) \
  37 mips_core_signal ((SD), (CPU), (CIA), (MAP), (NR_BYTES), (ADDR), (TRANSFER), (ERROR))
  38
  39 #include "sim-basics.h"
  40
  41 typedef address_word sim_cia;
  42
  43 #include "sim-base.h"
  44
  45
  46 /* Deprecated macros and types for manipulating 64bit values.  Use
  47    ../common/sim-bits.h and ../common/sim-endian.h macros instead. */
  48
  49 typedef signed64 word64;
  50 typedef unsigned64 uword64;
  51
  52 #define WORD64LO(t)     (unsigned int)((t)&0xFFFFFFFF)
  53 #define WORD64HI(t)     (unsigned int)(((uword64)(t))>>32)
  54 #define SET64LO(t)      (((uword64)(t))&0xFFFFFFFF)
  55 #define SET64HI(t)      (((uword64)(t))<<32)
  56 #define WORD64(h,l)     ((word64)((SET64HI(h)|SET64LO(l))))
  57 #define UWORD64(h,l)     (SET64HI(h)|SET64LO(l))
  58
  59 /* Check if a value will fit within a halfword: */
  60 #define NOTHALFWORDVALUE(v) ((((((uword64)(v)>>16) == 0) && !((v) & ((unsigned)1 << 15))) || (((((uword64)(v)>>32) == 0xFFFFFFFF) && ((((uword64)(v)>>16) & 0xFFFF) == 0xFFFF)) && ((v) & ((unsigned)1 << 15)))) ? (1 == 0) : (1 == 1))
  61
  62
  63
  64 /* Floating-point operations: */
  65
  66 #include "sim-fpu.h"
  67
  68 /* FPU registers must be one of the following types. All other values
  69    are reserved (and undefined). */
  70 typedef enum {
  71  fmt_single  = 0,
  72  fmt_double  = 1,
  73  fmt_word    = 4,
  74  fmt_long    = 5,
  75  /* The following are well outside the normal acceptable format
  76     range, and are used in the register status vector. */
  77  fmt_unknown       = 0x10000000,
  78  fmt_uninterpreted = 0x20000000,
  79  fmt_uninterpreted_32 = 0x40000000,
  80  fmt_uninterpreted_64 = 0x80000000U,
  81 } FP_formats;
  82
  83 unsigned64 value_fpr PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia, int fpr, FP_formats));
  84 #define ValueFPR(FPR,FMT) value_fpr (SD, CPU, cia, (FPR), (FMT))
  85
  86 void store_fpr PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia, int fpr, FP_formats fmt, unsigned64 value));
  87 #define StoreFPR(FPR,FMT,VALUE) store_fpr (SD, CPU, cia, (FPR), (FMT), (VALUE))
  88
  89 int NaN PARAMS ((unsigned64 op, FP_formats fmt));
  90 int Infinity PARAMS ((unsigned64 op, FP_formats fmt));
  91 int Less PARAMS ((unsigned64 op1, unsigned64 op2, FP_formats fmt));
  92 int Equal PARAMS ((unsigned64 op1, unsigned64 op2, FP_formats fmt));
  93 unsigned64 AbsoluteValue PARAMS ((unsigned64 op, FP_formats fmt));
  94 unsigned64 Negate PARAMS ((unsigned64 op, FP_formats fmt));
  95 unsigned64 Add PARAMS ((unsigned64 op1, unsigned64 op2, FP_formats fmt));
  96 unsigned64 Sub PARAMS ((unsigned64 op1, unsigned64 op2, FP_formats fmt));
  97 unsigned64 Multiply PARAMS ((unsigned64 op1, unsigned64 op2, FP_formats fmt));
  98 unsigned64 Divide PARAMS ((unsigned64 op1, unsigned64 op2, FP_formats fmt));
  99 unsigned64 Recip PARAMS ((unsigned64 op, FP_formats fmt));
 100 unsigned64 SquareRoot PARAMS ((unsigned64 op, FP_formats fmt));
 101 unsigned64 Max PARAMS ((unsigned64 op1, unsigned64 op2, FP_formats fmt));
 102 unsigned64 Min PARAMS ((unsigned64 op1, unsigned64 op2, FP_formats fmt));
 103 unsigned64 convert PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia, int rm, unsigned64 op, FP_formats from, FP_formats to));
 104 #define Convert(rm,op,from,to) \
 105 convert (SD, CPU, cia, rm, op, from, to)
 106
 107 /* Macro to update FPSR condition-code field. This is complicated by
 108    the fact that there is a hole in the index range of the bits within
 109    the FCSR register. Also, the number of bits visible depends on the
 110    MIPS ISA version being supported. */
 111
 112 #define SETFCC(cc,v) {\
 113   int bit = ((cc == 0) ? 23 : (24 + (cc)));\
 114   FCSR = ((FCSR & ~(1 << bit)) | ((v) << bit));\
 115 }
 116 #define GETFCC(cc) (((((cc) == 0) ? (FCSR & (1 << 23)) : (FCSR & (1 << (24 + (cc))))) != 0) ? 1U : 0)
 117
 118 /* This should be the COC1 value at the start of the preceding
 119    instruction: */
 120 #define PREVCOC1() ((STATE & simPCOC1) ? 1 : 0)
 121
 122 #ifdef TARGET_ENABLE_FR
 123 /* FIXME: this should be enabled for all targets, but needs testing first. */
 124 #define SizeFGR() (((WITH_TARGET_FLOATING_POINT_BITSIZE) == 64) \
 125    ? ((SR & status_FR) ? 64 : 32) \
 126    : (WITH_TARGET_FLOATING_POINT_BITSIZE))
 127 #else
 128 #define SizeFGR() (WITH_TARGET_FLOATING_POINT_BITSIZE)
 129 #endif
 130
 131 /* Standard FCRS bits: */
 132 #define IR (0) /* Inexact Result */
 133 #define UF (1) /* UnderFlow */
 134 #define OF (2) /* OverFlow */
 135 #define DZ (3) /* Division by Zero */
 136 #define IO (4) /* Invalid Operation */
 137 #define UO (5) /* Unimplemented Operation */
 138
 139 /* Get masks for individual flags: */
 140 #if 1 /* SAFE version */
 141 #define FP_FLAGS(b)  (((unsigned)(b) < 5) ? (1 << ((b) + 2)) : 0)
 142 #define FP_ENABLE(b) (((unsigned)(b) < 5) ? (1 << ((b) + 7)) : 0)
 143 #define FP_CAUSE(b)  (((unsigned)(b) < 6) ? (1 << ((b) + 12)) : 0)
 144 #else
 145 #define FP_FLAGS(b)  (1 << ((b) + 2))
 146 #define FP_ENABLE(b) (1 << ((b) + 7))
 147 #define FP_CAUSE(b)  (1 << ((b) + 12))
 148 #endif
 149
 150 #define FP_FS         (1 << 24) /* MIPS III onwards : Flush to Zero */
 151
 152 #define FP_MASK_RM    (0x3)
 153 #define FP_SH_RM      (0)
 154 #define FP_RM_NEAREST (0) /* Round to nearest        (Round) */
 155 #define FP_RM_TOZERO  (1) /* Round to zero           (Trunc) */
 156 #define FP_RM_TOPINF  (2) /* Round to Plus infinity  (Ceil) */
 157 #define FP_RM_TOMINF  (3) /* Round to Minus infinity (Floor) */
 158 #define GETRM()       (int)((FCSR >> FP_SH_RM) & FP_MASK_RM)
 159
 160
 161
 162
 163
 164
 165 /* HI/LO register accesses */
 166
 167 /* For some MIPS targets, the HI/LO registers have certain timing
 168    restrictions in that, for instance, a read of a HI register must be
 169    separated by at least three instructions from a preceeding read.
 170
 171    The struct below is used to record the last access by each of A MT,
 172    MF or other OP instruction to a HI/LO register.  See mips.igen for
 173    more details. */
 174
 175 typedef struct _hilo_access {
 176   signed64 timestamp;
 177   address_word cia;
 178 } hilo_access;
 179
 180 typedef struct _hilo_history {
 181   hilo_access mt;
 182   hilo_access mf;
 183   hilo_access op;
 184 } hilo_history;
 185
 186
 187
 188
 189 /* Integer ALU operations: */
 190
 191 #include "sim-alu.h"
 192
 193 #define ALU32_END(ANS) \
 194   if (ALU32_HAD_OVERFLOW) \
 195     SignalExceptionIntegerOverflow (); \
 196   (ANS) = (signed32) ALU32_OVERFLOW_RESULT
 197
 198
 199 #define ALU64_END(ANS) \
 200   if (ALU64_HAD_OVERFLOW) \
 201     SignalExceptionIntegerOverflow (); \
 202   (ANS) = ALU64_OVERFLOW_RESULT;
 203
 204
 205
 206
 207
 208 /* The following is probably not used for MIPS IV onwards: */
 209 /* Slots for delayed register updates. For the moment we just have a
 210    fixed number of slots (rather than a more generic, dynamic
 211    system). This keeps the simulator fast. However, we only allow
 212    for the register update to be delayed for a single instruction
 213    cycle. */
 214 #define PSLOTS (8) /* Maximum number of instruction cycles */
 215
 216 typedef struct _pending_write_queue {
 217   int in;
 218   int out;
 219   int total;
 220   int slot_delay[PSLOTS];
 221   int slot_size[PSLOTS];
 222   int slot_bit[PSLOTS];
 223   void *slot_dest[PSLOTS];
 224   unsigned64 slot_value[PSLOTS];
 225 } pending_write_queue;
 226
 227 #ifndef PENDING_TRACE
 228 #define PENDING_TRACE 0
 229 #endif
 230 #define PENDING_IN ((CPU)->pending.in)
 231 #define PENDING_OUT ((CPU)->pending.out)
 232 #define PENDING_TOTAL ((CPU)->pending.total)
 233 #define PENDING_SLOT_SIZE ((CPU)->pending.slot_size)
 234 #define PENDING_SLOT_BIT ((CPU)->pending.slot_bit)
 235 #define PENDING_SLOT_DELAY ((CPU)->pending.slot_delay)
 236 #define PENDING_SLOT_DEST ((CPU)->pending.slot_dest)
 237 #define PENDING_SLOT_VALUE ((CPU)->pending.slot_value)
 238
 239 /* Invalidate the pending write queue, all pending writes are
 240    discarded. */
 241
 242 #define PENDING_INVALIDATE() \
 243 memset (&(CPU)->pending, 0, sizeof ((CPU)->pending))
 244
 245 /* Schedule a write to DEST for N cycles time.  For 64 bit
 246    destinations, schedule two writes.  For floating point registers,
 247    the caller should schedule a write to both the dest register and
 248    the FPR_STATE register.  When BIT is non-negative, only BIT of DEST
 249    is updated. */
 250
 251 #define PENDING_SCHED(DEST,VAL,DELAY,BIT)                               \
 252   do {                                                                  \
 253     if (PENDING_SLOT_DEST[PENDING_IN] != NULL)                          \
 254       sim_engine_abort (SD, CPU, cia,                                   \
 255                         "PENDING_SCHED - buffer overflow\n");           \
 256     if (PENDING_TRACE)                                                  \
 257       sim_io_eprintf (SD, "PENDING_SCHED - 0x%lx - dest 0x%lx, val 0x%lx, bit %d, size %d, pending_in %d, pending_out %d, pending_total %d\n",                  \
 258                       (unsigned long) cia, (unsigned long) &(DEST),     \
 259                       (unsigned long) (VAL), (BIT), (int) sizeof (DEST),\
 260                       PENDING_IN, PENDING_OUT, PENDING_TOTAL);          \
 261     PENDING_SLOT_DELAY[PENDING_IN] = (DELAY) + 1;                       \
 262     PENDING_SLOT_DEST[PENDING_IN] = &(DEST);                            \
 263     PENDING_SLOT_VALUE[PENDING_IN] = (VAL);                             \
 264     PENDING_SLOT_SIZE[PENDING_IN] = sizeof (DEST);                      \
 265     PENDING_SLOT_BIT[PENDING_IN] = (BIT);                               \
 266     PENDING_IN = (PENDING_IN + 1) % PSLOTS;                             \
 267     PENDING_TOTAL += 1;                                                 \
 268   } while (0)
 269
 270 #define PENDING_WRITE(DEST,VAL,DELAY) PENDING_SCHED(DEST,VAL,DELAY,-1)
 271 #define PENDING_BIT(DEST,VAL,DELAY,BIT) PENDING_SCHED(DEST,VAL,DELAY,BIT)
 272
 273 #define PENDING_TICK() pending_tick (SD, CPU, cia)
 274
 275 #define PENDING_FLUSH() abort () /* think about this one */
 276 #define PENDING_FP() abort () /* think about this one */
 277
 278 /* For backward compatibility */
 279 #define PENDING_FILL(R,VAL)                                             \
 280 do {                                                                    \
 281   if ((R) >= FGRIDX && (R) < FGRIDX + NR_FGR)                           \
 282     {                                                                   \
 283       PENDING_SCHED(FGR[(R) - FGRIDX], VAL, 1, -1);                     \
 284       PENDING_SCHED(FPR_STATE[(R) - FGRIDX], fmt_uninterpreted, 1, -1); \
 285     }                                                                   \
 286   else                                                                  \
 287     PENDING_SCHED(GPR[(R)], VAL, 1, -1);                                \
 288 } while (0)
 289
 290
 291 enum float_operation
 292   {
 293     FLOP_ADD,    FLOP_SUB,    FLOP_MUL,    FLOP_MADD,
 294     FLOP_MSUB,   FLOP_MAX=10, FLOP_MIN,    FLOP_ABS,
 295     FLOP_ITOF0=14, FLOP_FTOI0=18, FLOP_NEG=23
 296   };
 297
 298
 299 /* The internal representation of an MDMX accumulator.
 300    Note that 24 and 48 bit accumulator elements are represented in
 301    32 or 64 bits.  Since the accumulators are 2's complement with
 302    overflow suppressed, high-order bits can be ignored in most contexts.  */
 303
 304 typedef signed32 signed24;
 305 typedef signed64 signed48;
 306
 307 typedef union {
 308   signed24  ob[8];
 309   signed48  qh[4];
 310 } MDMX_accumulator;
 311
 312
 313 /* Conventional system arguments.  */
 314 #define SIM_STATE  sim_cpu *cpu, address_word cia
 315 #define SIM_ARGS   CPU, cia
 316
 317 struct _sim_cpu {
 318
 319
 320   /* The following are internal simulator state variables: */
 321 #define CIA_GET(CPU) ((CPU)->registers[PCIDX] + 0)
 322 #define CIA_SET(CPU,CIA) ((CPU)->registers[PCIDX] = (CIA))
 323   address_word dspc;  /* delay-slot PC */
 324 #define DSPC ((CPU)->dspc)
 325
 326 #define DELAY_SLOT(TARGET) NIA = delayslot32 (SD_, (TARGET))
 327 #define NULLIFY_NEXT_INSTRUCTION() NIA = nullify_next_insn32 (SD_)
 328
 329
 330   /* State of the simulator */
 331   unsigned int state;
 332   unsigned int dsstate;
 333 #define STATE ((CPU)->state)
 334 #define DSSTATE ((CPU)->dsstate)
 335
 336 /* Flags in the "state" variable: */
 337 #define simHALTEX       (1 << 2)  /* 0 = run; 1 = halt on exception */
 338 #define simHALTIN       (1 << 3)  /* 0 = run; 1 = halt on interrupt */
 339 #define simTRACE        (1 << 8)  /* 0 = do nothing; 1 = trace address activity */
 340 #define simPCOC0        (1 << 17) /* COC[1] from current */
 341 #define simPCOC1        (1 << 18) /* COC[1] from previous */
 342 #define simDELAYSLOT    (1 << 24) /* 0 = do nothing; 1 = delay slot entry exists */
 343 #define simSKIPNEXT     (1 << 25) /* 0 = do nothing; 1 = skip instruction */
 344 #define simSIGINT       (1 << 28)  /* 0 = do nothing; 1 = SIGINT has occured */
 345 #define simJALDELAYSLOT (1 << 29) /* 1 = in jal delay slot */
 346
 347 #ifndef ENGINE_ISSUE_PREFIX_HOOK
 348 #define ENGINE_ISSUE_PREFIX_HOOK() \
 349   { \
 350     /* Perform any pending writes */ \
 351     PENDING_TICK(); \
 352     /* Set previous flag, depending on current: */ \
 353     if (STATE & simPCOC0) \
 354      STATE |= simPCOC1; \
 355     else \
 356      STATE &= ~simPCOC1; \
 357     /* and update the current value: */ \
 358     if (GETFCC(0)) \
 359      STATE |= simPCOC0; \
 360     else \
 361      STATE &= ~simPCOC0; \
 362   }
 363 #endif /* ENGINE_ISSUE_PREFIX_HOOK */
 364
 365
 366 /* This is nasty, since we have to rely on matching the register
 367    numbers used by GDB. Unfortunately, depending on the MIPS target
 368    GDB uses different register numbers. We cannot just include the
 369    relevant "gdb/tm.h" link, since GDB may not be configured before
 370    the sim world, and also the GDB header file requires too much other
 371    state. */
 372
 373 #ifndef TM_MIPS_H
 374 #define LAST_EMBED_REGNUM (89)
 375 #define NUM_REGS (LAST_EMBED_REGNUM + 1)
 376
 377
 378 #endif
 379
 380
 381 /* To keep this default simulator simple, and fast, we use a direct
 382    vector of registers. The internal simulator engine then uses
 383    manifests to access the correct slot. */
 384
 385   unsigned_word registers[LAST_EMBED_REGNUM + 1];
 386
 387   int register_widths[NUM_REGS];
 388 #define REGISTERS       ((CPU)->registers)
 389
 390 #define GPR     (&REGISTERS[0])
 391 #define GPR_SET(N,VAL) (REGISTERS[(N)] = (VAL))
 392
 393   /* While space is allocated for the floating point registers in the
 394      main registers array, they are stored separatly.  This is because
 395      their size may not necessarily match the size of either the
 396      general-purpose or system specific registers */
 397 #define NR_FGR  (32)
 398 #define FGRIDX  (38)
 399   fp_word fgr[NR_FGR];
 400 #define FGR     ((CPU)->fgr)
 401
 402 #define LO      (REGISTERS[33])
 403 #define HI      (REGISTERS[34])
 404 #define PCIDX   37
 405 #define PC      (REGISTERS[PCIDX])
 406 #define CAUSE   (REGISTERS[36])
 407 #define SRIDX   (32)
 408 #define SR      (REGISTERS[SRIDX])      /* CPU status register */
 409 #define FCR0IDX  (71)
 410 #define FCR0    (REGISTERS[FCR0IDX])    /* really a 32bit register */
 411 #define FCR31IDX (70)
 412 #define FCR31   (REGISTERS[FCR31IDX])   /* really a 32bit register */
 413 #define FCSR    (FCR31)
 414 #define Debug   (REGISTERS[86])
 415 #define DEPC    (REGISTERS[87])
 416 #define EPC     (REGISTERS[88])
 417
 418   /* All internal state modified by signal_exception() that may need to be
 419      rolled back for passing moment-of-exception image back to gdb. */
 420   unsigned_word exc_trigger_registers[LAST_EMBED_REGNUM + 1];
 421   unsigned_word exc_suspend_registers[LAST_EMBED_REGNUM + 1];
 422   int exc_suspended;
 423
 424 #define SIM_CPU_EXCEPTION_TRIGGER(SD,CPU,CIA) mips_cpu_exception_trigger(SD,CPU,CIA)
 425 #define SIM_CPU_EXCEPTION_SUSPEND(SD,CPU,EXC) mips_cpu_exception_suspend(SD,CPU,EXC)
 426 #define SIM_CPU_EXCEPTION_RESUME(SD,CPU,EXC) mips_cpu_exception_resume(SD,CPU,EXC)
 427
 428   unsigned_word c0_config_reg;
 429 #define C0_CONFIG ((CPU)->c0_config_reg)
 430
 431 /* The following are pseudonyms for standard registers */
 432 #define ZERO    (REGISTERS[0])
 433 #define V0      (REGISTERS[2])
 434 #define A0      (REGISTERS[4])
 435 #define A1      (REGISTERS[5])
 436 #define A2      (REGISTERS[6])
 437 #define A3      (REGISTERS[7])
 438 #define T8IDX   24
 439 #define T8      (REGISTERS[T8IDX])
 440 #define SPIDX   29
 441 #define SP      (REGISTERS[SPIDX])
 442 #define RAIDX   31
 443 #define RA      (REGISTERS[RAIDX])
 444
 445   /* While space is allocated in the main registers arrray for some of
 446      the COP0 registers, that space isn't sufficient.  Unknown COP0
 447      registers overflow into the array below */
 448
 449 #define NR_COP0_GPR     32
 450   unsigned_word cop0_gpr[NR_COP0_GPR];
 451 #define COP0_GPR        ((CPU)->cop0_gpr)
 452 #define COP0_BADVADDR ((unsigned32)(COP0_GPR[8]))
 453
 454   /* Keep the current format state for each register: */
 455   FP_formats fpr_state[32];
 456 #define FPR_STATE ((CPU)->fpr_state)
 457
 458   pending_write_queue pending;
 459
 460   /* The MDMX accumulator (used only for MDMX ASE).  */
 461   MDMX_accumulator acc;
 462 #define ACC             ((CPU)->acc)
 463
 464   /* LLBIT = Load-Linked bit. A bit of "virtual" state used by atomic
 465      read-write instructions. It is set when a linked load occurs. It
 466      is tested and cleared by the conditional store. It is cleared
 467      (during other CPU operations) when a store to the location would
 468      no longer be atomic. In particular, it is cleared by exception
 469      return instructions. */
 470   int llbit;
 471 #define LLBIT ((CPU)->llbit)
 472
 473
 474 /* The HIHISTORY and LOHISTORY timestamps are used to ensure that
 475    corruptions caused by using the HI or LO register too close to a
 476    following operation is spotted. See mips.igen for more details. */
 477
 478   hilo_history hi_history;
 479 #define HIHISTORY (&(CPU)->hi_history)
 480   hilo_history lo_history;
 481 #define LOHISTORY (&(CPU)->lo_history)
 482
 483 #define check_branch_bug()
 484 #define mark_branch_bug(TARGET)
 485
 486
 487
 488   sim_cpu_base base;
 489 };
 490
 491
 492 /* MIPS specific simulator watch config */
 493
 494 void watch_options_install PARAMS ((SIM_DESC sd));
 495
 496 struct swatch {
 497   sim_event *pc;
 498   sim_event *clock;
 499   sim_event *cycles;
 500 };
 501
 502
 503 /* FIXME: At present much of the simulator is still static */
 504 struct sim_state {
 505
 506   struct swatch watch;
 507
 508   sim_cpu cpu[MAX_NR_PROCESSORS];
 509 #if (WITH_SMP)
 510 #define STATE_CPU(sd,n) (&(sd)->cpu[n])
 511 #else
 512 #define STATE_CPU(sd,n) (&(sd)->cpu[0])
 513 #endif
 514
 515
 516   sim_state_base base;
 517 };
 518
 519
 520
 521 /* Status information: */
 522
 523 /* TODO : these should be the bitmasks for these bits within the
 524    status register. At the moment the following are VR4300
 525    bit-positions: */
 526 #define status_KSU_mask  (0x18)         /* mask for KSU bits */
 527 #define status_KSU_shift (3)            /* shift for field */
 528 #define ksu_kernel       (0x0)
 529 #define ksu_supervisor   (0x1)
 530 #define ksu_user         (0x2)
 531 #define ksu_unknown      (0x3)
 532
 533 #define SR_KSU           ((SR & status_KSU_mask) >> status_KSU_shift)
 534
 535 #define status_IE        (1 <<  0)      /* Interrupt enable */
 536 #define status_EIE       (1 << 16)      /* Enable Interrupt Enable */
 537 #define status_EXL       (1 <<  1)      /* Exception level */
 538 #define status_RE        (1 << 25)      /* Reverse Endian in user mode */
 539 #define status_FR        (1 << 26)      /* enables MIPS III additional FP registers */
 540 #define status_SR        (1 << 20)      /* soft reset or NMI */
 541 #define status_BEV       (1 << 22)      /* Location of general exception vectors */
 542 #define status_TS        (1 << 21)      /* TLB shutdown has occurred */
 543 #define status_ERL       (1 <<  2)      /* Error level */
 544 #define status_IM7       (1 << 15)      /* Timer Interrupt Mask */
 545 #define status_RP        (1 << 27)      /* Reduced Power mode */
 546
 547 /* Specializations for TX39 family */
 548 #define status_IEc       (1 << 0)       /* Interrupt enable (current) */
 549 #define status_KUc       (1 << 1)       /* Kernel/User mode */
 550 #define status_IEp       (1 << 2)       /* Interrupt enable (previous) */
 551 #define status_KUp       (1 << 3)       /* Kernel/User mode */
 552 #define status_IEo       (1 << 4)       /* Interrupt enable (old) */
 553 #define status_KUo       (1 << 5)       /* Kernel/User mode */
 554 #define status_IM_mask   (0xff)         /* Interrupt mask */
 555 #define status_IM_shift  (8)
 556 #define status_NMI       (1 << 20)      /* NMI */
 557 #define status_NMI       (1 << 20)      /* NMI */
 558
 559 /* Status bits used by MIPS32/MIPS64.  */
 560 #define status_UX        (1 <<  5)      /* 64-bit user addrs */
 561 #define status_SX        (1 <<  6)      /* 64-bit supervisor addrs */
 562 #define status_KX        (1 <<  7)      /* 64-bit kernel addrs */
 563 #define status_TS        (1 << 21)      /* TLB shutdown has occurred */
 564 #define status_PX        (1 << 23)      /* Enable 64 bit operations */
 565 #define status_MX        (1 << 24)      /* Enable MDMX resources */
 566 #define status_CU0       (1 << 28)      /* Coprocessor 0 usable */
 567 #define status_CU1       (1 << 29)      /* Coprocessor 1 usable */
 568 #define status_CU2       (1 << 30)      /* Coprocessor 2 usable */
 569 #define status_CU3       (1 << 31)      /* Coprocessor 3 usable */
 570 /* Bits reserved for implementations:  */
 571 #define status_SBX       (1 << 16)      /* Enable SiByte SB-1 extensions.  */
 572
 573 #define cause_BD ((unsigned)1 << 31)    /* L1 Exception in branch delay slot */
 574 #define cause_BD2         (1 << 30)     /* L2 Exception in branch delay slot */
 575 #define cause_CE_mask     0x30000000    /* Coprocessor exception */
 576 #define cause_CE_shift    28
 577 #define cause_EXC2_mask   0x00070000
 578 #define cause_EXC2_shift  16
 579 #define cause_IP7         (1 << 15)     /* Interrupt pending */
 580 #define cause_SIOP        (1 << 12)     /* SIO pending */
 581 #define cause_IP3         (1 << 11)     /* Int 0 pending */
 582 #define cause_IP2         (1 << 10)     /* Int 1 pending */
 583
 584 #define cause_EXC_mask  (0x1c)          /* Exception code */
 585 #define cause_EXC_shift (2)
 586
 587 #define cause_SW0       (1 << 8)        /* Software interrupt 0 */
 588 #define cause_SW1       (1 << 9)        /* Software interrupt 1 */
 589 #define cause_IP_mask   (0x3f)          /* Interrupt pending field */
 590 #define cause_IP_shift  (10)
 591
 592 #define cause_set_EXC(x)  CAUSE = (CAUSE & ~cause_EXC_mask)  | ((x << cause_EXC_shift)  & cause_EXC_mask)
 593 #define cause_set_EXC2(x) CAUSE = (CAUSE & ~cause_EXC2_mask) | ((x << cause_EXC2_shift) & cause_EXC2_mask)
 594
 595
 596 /* NOTE: We keep the following status flags as bit values (1 for true,
 597    0 for false). This allows them to be used in binary boolean
 598    operations without worrying about what exactly the non-zero true
 599    value is. */
 600
 601 /* UserMode */
 602 #ifdef SUBTARGET_R3900
 603 #define UserMode        ((SR & status_KUc) ? 1 : 0)
 604 #else
 605 #define UserMode        ((((SR & status_KSU_mask) >> status_KSU_shift) == ksu_user) ? 1 : 0)
 606 #endif /* SUBTARGET_R3900 */
 607
 608 /* BigEndianMem */
 609 /* Hardware configuration. Affects endianness of LoadMemory and
 610    StoreMemory and the endianness of Kernel and Supervisor mode
 611    execution. The value is 0 for little-endian; 1 for big-endian. */
 612 #define BigEndianMem    (CURRENT_TARGET_BYTE_ORDER == BIG_ENDIAN)
 613 /*(state & simBE) ? 1 : 0)*/
 614
 615 /* ReverseEndian */
 616 /* This mode is selected if in User mode with the RE bit being set in
 617    SR (Status Register). It reverses the endianness of load and store
 618    instructions. */
 619 #define ReverseEndian   (((SR & status_RE) && UserMode) ? 1 : 0)
 620
 621 /* BigEndianCPU */
 622 /* The endianness for load and store instructions (0=little;1=big). In
 623    User mode this endianness may be switched by setting the state_RE
 624    bit in the SR register. Thus, BigEndianCPU may be computed as
 625    (BigEndianMem EOR ReverseEndian). */
 626 #define BigEndianCPU    (BigEndianMem ^ ReverseEndian) /* Already bits */
 627
 628
 629
 630 /* Exceptions: */
 631
 632 /* NOTE: These numbers depend on the processor architecture being
 633    simulated: */
 634 enum ExceptionCause {
 635   Interrupt               = 0,
 636   TLBModification         = 1,
 637   TLBLoad                 = 2,
 638   TLBStore                = 3,
 639   AddressLoad             = 4,
 640   AddressStore            = 5,
 641   InstructionFetch        = 6,
 642   DataReference           = 7,
 643   SystemCall              = 8,
 644   BreakPoint              = 9,
 645   ReservedInstruction     = 10,
 646   CoProcessorUnusable     = 11,
 647   IntegerOverflow         = 12,    /* Arithmetic overflow (IDT monitor raises SIGFPE) */
 648   Trap                    = 13,
 649   FPE                     = 15,
 650   DebugBreakPoint         = 16,    /* Impl. dep. in MIPS32/MIPS64.  */
 651   MDMX                    = 22,
 652   Watch                   = 23,
 653   MCheck                  = 24,
 654   CacheErr                = 30,
 655   NMIReset                = 31,    /* Reserved in MIPS32/MIPS64.  */
 656
 657
 658 /* The following exception code is actually private to the simulator
 659    world. It is *NOT* a processor feature, and is used to signal
 660    run-time errors in the simulator. */
 661   SimulatorFault          = 0xFFFFFFFF
 662 };
 663
 664 #define TLB_REFILL  (0)
 665 #define TLB_INVALID (1)
 666
 667
 668 /* The following break instructions are reserved for use by the
 669    simulator.  The first is used to halt the simulation.  The second
 670    is used by gdb for break-points.  NOTE: Care must be taken, since
 671    this value may be used in later revisions of the MIPS ISA. */
 672 #define HALT_INSTRUCTION_MASK   (0x03FFFFC0)
 673
 674 #define HALT_INSTRUCTION        (0x03ff000d)
 675 #define HALT_INSTRUCTION2       (0x0000ffcd)
 676
 677
 678 #define BREAKPOINT_INSTRUCTION  (0x0005000d)
 679 #define BREAKPOINT_INSTRUCTION2 (0x0000014d)
 680
 681
 682
 683 void interrupt_event (SIM_DESC sd, void *data);
 684
 685 void signal_exception (SIM_DESC sd, sim_cpu *cpu, address_word cia, int exception, ...);
 686 #define SignalException(exc,instruction)     signal_exception (SD, CPU, cia, (exc), (instruction))
 687 #define SignalExceptionInterrupt(level)      signal_exception (SD, CPU, cia, Interrupt, level)
 688 #define SignalExceptionInstructionFetch()    signal_exception (SD, CPU, cia, InstructionFetch)
 689 #define SignalExceptionAddressStore()        signal_exception (SD, CPU, cia, AddressStore)
 690 #define SignalExceptionAddressLoad()         signal_exception (SD, CPU, cia, AddressLoad)
 691 #define SignalExceptionDataReference()       signal_exception (SD, CPU, cia, DataReference)
 692 #define SignalExceptionSimulatorFault(buf)   signal_exception (SD, CPU, cia, SimulatorFault, buf)
 693 #define SignalExceptionFPE()                 signal_exception (SD, CPU, cia, FPE)
 694 #define SignalExceptionIntegerOverflow()     signal_exception (SD, CPU, cia, IntegerOverflow)
 695 #define SignalExceptionCoProcessorUnusable(cop) signal_exception (SD, CPU, cia, CoProcessorUnusable)
 696 #define SignalExceptionNMIReset()            signal_exception (SD, CPU, cia, NMIReset)
 697 #define SignalExceptionTLBRefillStore()      signal_exception (SD, CPU, cia, TLBStore, TLB_REFILL)
 698 #define SignalExceptionTLBRefillLoad()       signal_exception (SD, CPU, cia, TLBLoad, TLB_REFILL)
 699 #define SignalExceptionTLBInvalidStore()     signal_exception (SD, CPU, cia, TLBStore, TLB_INVALID)
 700 #define SignalExceptionTLBInvalidLoad()      signal_exception (SD, CPU, cia, TLBLoad, TLB_INVALID)
 701 #define SignalExceptionTLBModification()     signal_exception (SD, CPU, cia, TLBModification)
 702 #define SignalExceptionMDMX()                signal_exception (SD, CPU, cia, MDMX)
 703 #define SignalExceptionWatch()               signal_exception (SD, CPU, cia, Watch)
 704 #define SignalExceptionMCheck()              signal_exception (SD, CPU, cia, MCheck)
 705 #define SignalExceptionCacheErr()            signal_exception (SD, CPU, cia, CacheErr)
 706
 707 /* Co-processor accesses */
 708
 709 /* XXX FIXME: For now, assume that FPU (cp1) is always usable.  */
 710 #define COP_Usable(coproc_num)          (coproc_num == 1)
 711
 712 void cop_lw  PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia, int coproc_num, int coproc_reg, unsigned int memword));
 713 void cop_ld  PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia, int coproc_num, int coproc_reg, uword64 memword));
 714 unsigned int cop_sw PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia, int coproc_num, int coproc_reg));
 715 uword64 cop_sd PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia, int coproc_num, int coproc_reg));
 716
 717 #define COP_LW(coproc_num,coproc_reg,memword) \
 718 cop_lw (SD, CPU, cia, coproc_num, coproc_reg, memword)
 719 #define COP_LD(coproc_num,coproc_reg,memword) \
 720 cop_ld (SD, CPU, cia, coproc_num, coproc_reg, memword)
 721 #define COP_SW(coproc_num,coproc_reg) \
 722 cop_sw (SD, CPU, cia, coproc_num, coproc_reg)
 723 #define COP_SD(coproc_num,coproc_reg) \
 724 cop_sd (SD, CPU, cia, coproc_num, coproc_reg)
 725
 726
 727 void decode_coproc PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia, unsigned int instruction));
 728 #define DecodeCoproc(instruction) \
 729 decode_coproc (SD, CPU, cia, (instruction))
 730
 731 int sim_monitor (SIM_DESC sd, sim_cpu *cpu, address_word cia, unsigned int arg);
 732
 733
 734 /* MDMX access.  */
 735
 736 typedef unsigned int MX_fmtsel;   /* MDMX format select field (5 bits).  */
 737 #define ob_fmtsel(sel) (((sel)<<1)|0x0)
 738 #define qh_fmtsel(sel) (((sel)<<2)|0x1)
 739
 740 #define fmt_mdmx fmt_uninterpreted
 741
 742 #define MX_VECT_AND  (0)
 743 #define MX_VECT_NOR  (1)
 744 #define MX_VECT_OR   (2)
 745 #define MX_VECT_XOR  (3)
 746 #define MX_VECT_SLL  (4)
 747 #define MX_VECT_SRL  (5)
 748 #define MX_VECT_ADD  (6)
 749 #define MX_VECT_SUB  (7)
 750 #define MX_VECT_MIN  (8)
 751 #define MX_VECT_MAX  (9)
 752 #define MX_VECT_MUL  (10)
 753 #define MX_VECT_MSGN (11)
 754 #define MX_VECT_SRA  (12)
 755 #define MX_VECT_ABSD (13)               /* SB-1 only.  */
 756 #define MX_VECT_AVG  (14)               /* SB-1 only.  */
 757
 758 unsigned64 mdmx_cpr_op (SIM_STATE, int op, unsigned64 op1, int vt, MX_fmtsel fmtsel);
 759 #define MX_Add(op1,vt,fmtsel) mdmx_cpr_op(SIM_ARGS, MX_VECT_ADD, op1, vt, fmtsel)
 760 #define MX_And(op1,vt,fmtsel) mdmx_cpr_op(SIM_ARGS, MX_VECT_AND, op1, vt, fmtsel)
 761 #define MX_Max(op1,vt,fmtsel) mdmx_cpr_op(SIM_ARGS, MX_VECT_MAX, op1, vt, fmtsel)
 762 #define MX_Min(op1,vt,fmtsel) mdmx_cpr_op(SIM_ARGS, MX_VECT_MIN, op1, vt, fmtsel)
 763 #define MX_Msgn(op1,vt,fmtsel) mdmx_cpr_op(SIM_ARGS, MX_VECT_MSGN, op1, vt, fmtsel)
 764 #define MX_Mul(op1,vt,fmtsel) mdmx_cpr_op(SIM_ARGS, MX_VECT_MUL, op1, vt, fmtsel)
 765 #define MX_Nor(op1,vt,fmtsel) mdmx_cpr_op(SIM_ARGS, MX_VECT_NOR, op1, vt, fmtsel)
 766 #define MX_Or(op1,vt,fmtsel)  mdmx_cpr_op(SIM_ARGS, MX_VECT_OR,  op1, vt, fmtsel)
 767 #define MX_ShiftLeftLogical(op1,vt,fmtsel) mdmx_cpr_op(SIM_ARGS, MX_VECT_SLL, op1, vt, fmtsel)
 768 #define MX_ShiftRightArith(op1,vt,fmtsel) mdmx_cpr_op(SIM_ARGS, MX_VECT_SRA, op1, vt, fmtsel)
 769 #define MX_ShiftRightLogical(op1,vt,fmtsel) mdmx_cpr_op(SIM_ARGS, MX_VECT_SRL, op1, vt, fmtsel)
 770 #define MX_Sub(op1,vt,fmtsel) mdmx_cpr_op(SIM_ARGS, MX_VECT_SUB, op1, vt, fmtsel)
 771 #define MX_Xor(op1,vt,fmtsel) mdmx_cpr_op(SIM_ARGS, MX_VECT_XOR, op1, vt, fmtsel)
 772 #define MX_AbsDiff(op1,vt,fmtsel) mdmx_cpr_op(SIM_ARGS, MX_VECT_ABSD, op1, vt, fmtsel)
 773 #define MX_Avg(op1,vt,fmtsel) mdmx_cpr_op(SIM_ARGS, MX_VECT_AVG, op1, vt, fmtsel)
 774
 775 #define MX_C_EQ  0x1
 776 #define MX_C_LT  0x4
 777
 778 void mdmx_cc_op (SIM_STATE, int cond, unsigned64 op1, int vt, MX_fmtsel fmtsel);
 779 #define MX_Comp(op1,cond,vt,fmtsel) mdmx_cc_op(SIM_ARGS, cond, op1, vt, fmtsel)
 780
 781 unsigned64 mdmx_pick_op (SIM_STATE, int tf, unsigned64 op1, int vt, MX_fmtsel fmtsel);
 782 #define MX_Pick(tf,op1,vt,fmtsel) mdmx_pick_op(SIM_ARGS, tf, op1, vt, fmtsel)
 783
 784 #define MX_VECT_ADDA  (0)
 785 #define MX_VECT_ADDL  (1)
 786 #define MX_VECT_MULA  (2)
 787 #define MX_VECT_MULL  (3)
 788 #define MX_VECT_MULS  (4)
 789 #define MX_VECT_MULSL (5)
 790 #define MX_VECT_SUBA  (6)
 791 #define MX_VECT_SUBL  (7)
 792 #define MX_VECT_ABSDA (8)               /* SB-1 only.  */
 793
 794 void mdmx_acc_op (SIM_STATE, int op, unsigned64 op1, int vt, MX_fmtsel fmtsel);
 795 #define MX_AddA(op1,vt,fmtsel) mdmx_acc_op(SIM_ARGS, MX_VECT_ADDA, op1, vt, fmtsel)
 796 #define MX_AddL(op1,vt,fmtsel) mdmx_acc_op(SIM_ARGS, MX_VECT_ADDL, op1, vt, fmtsel)
 797 #define MX_MulA(op1,vt,fmtsel) mdmx_acc_op(SIM_ARGS, MX_VECT_MULA, op1, vt, fmtsel)
 798 #define MX_MulL(op1,vt,fmtsel) mdmx_acc_op(SIM_ARGS, MX_VECT_MULL, op1, vt, fmtsel)
 799 #define MX_MulS(op1,vt,fmtsel) mdmx_acc_op(SIM_ARGS, MX_VECT_MULS, op1, vt, fmtsel)
 800 #define MX_MulSL(op1,vt,fmtsel) mdmx_acc_op(SIM_ARGS, MX_VECT_MULSL, op1, vt, fmtsel)
 801 #define MX_SubA(op1,vt,fmtsel) mdmx_acc_op(SIM_ARGS, MX_VECT_SUBA, op1, vt, fmtsel)
 802 #define MX_SubL(op1,vt,fmtsel) mdmx_acc_op(SIM_ARGS, MX_VECT_SUBL, op1, vt, fmtsel)
 803 #define MX_AbsDiffC(op1,vt,fmtsel) mdmx_acc_op(SIM_ARGS, MX_VECT_ABSDA, op1, vt, fmtsel)
 804
 805 #define MX_FMT_OB   (0)
 806 #define MX_FMT_QH   (1)
 807
 808 /* The following codes chosen to indicate the units of shift.  */
 809 #define MX_RAC_L    (0)
 810 #define MX_RAC_M    (1)
 811 #define MX_RAC_H    (2)
 812
 813 unsigned64 mdmx_rac_op (SIM_STATE, int, int);
 814 #define MX_RAC(op,fmt) mdmx_rac_op(SIM_ARGS, op, fmt)
 815
 816 void mdmx_wacl (SIM_STATE, int, unsigned64, unsigned64);
 817 #define MX_WACL(fmt,vs,vt) mdmx_wacl(SIM_ARGS, fmt, vs, vt)
 818 void mdmx_wach (SIM_STATE, int, unsigned64);
 819 #define MX_WACH(fmt,vs) mdmx_wach(SIM_ARGS, fmt, vs)
 820
 821 #define MX_RND_AS   (0)
 822 #define MX_RND_AU   (1)
 823 #define MX_RND_ES   (2)
 824 #define MX_RND_EU   (3)
 825 #define MX_RND_ZS   (4)
 826 #define MX_RND_ZU   (5)
 827
 828 unsigned64 mdmx_round_op (SIM_STATE, int, int, MX_fmtsel);
 829 #define MX_RNAS(vt,fmt) mdmx_round_op(SIM_ARGS, MX_RND_AS, vt, fmt)
 830 #define MX_RNAU(vt,fmt) mdmx_round_op(SIM_ARGS, MX_RND_AU, vt, fmt)
 831 #define MX_RNES(vt,fmt) mdmx_round_op(SIM_ARGS, MX_RND_ES, vt, fmt)
 832 #define MX_RNEU(vt,fmt) mdmx_round_op(SIM_ARGS, MX_RND_EU, vt, fmt)
 833 #define MX_RZS(vt,fmt)  mdmx_round_op(SIM_ARGS, MX_RND_ZS, vt, fmt)
 834 #define MX_RZU(vt,fmt)  mdmx_round_op(SIM_ARGS, MX_RND_ZU, vt, fmt)
 835
 836 unsigned64 mdmx_shuffle (SIM_STATE, int, unsigned64, unsigned64);
 837 #define MX_SHFL(shop,op1,op2) mdmx_shuffle(SIM_ARGS, shop, op1, op2)
 838
 839
 840
 841 /* Memory accesses */
 842
 843 /* The following are generic to all versions of the MIPS architecture
 844    to date: */
 845
 846 /* Memory Access Types (for CCA): */
 847 #define Uncached                (0)
 848 #define CachedNoncoherent       (1)
 849 #define CachedCoherent          (2)
 850 #define Cached                  (3)
 851
 852 #define isINSTRUCTION   (1 == 0) /* FALSE */
 853 #define isDATA          (1 == 1) /* TRUE */
 854 #define isLOAD          (1 == 0) /* FALSE */
 855 #define isSTORE         (1 == 1) /* TRUE */
 856 #define isREAL          (1 == 0) /* FALSE */
 857 #define isRAW           (1 == 1) /* TRUE */
 858 /* The parameter HOST (isTARGET / isHOST) is ignored */
 859 #define isTARGET        (1 == 0) /* FALSE */
 860 /* #define isHOST          (1 == 1) TRUE */
 861
 862 /* The "AccessLength" specifications for Loads and Stores. NOTE: This
 863    is the number of bytes minus 1. */
 864 #define AccessLength_BYTE       (0)
 865 #define AccessLength_HALFWORD   (1)
 866 #define AccessLength_TRIPLEBYTE (2)
 867 #define AccessLength_WORD       (3)
 868 #define AccessLength_QUINTIBYTE (4)
 869 #define AccessLength_SEXTIBYTE  (5)
 870 #define AccessLength_SEPTIBYTE  (6)
 871 #define AccessLength_DOUBLEWORD (7)
 872 #define AccessLength_QUADWORD   (15)
 873
 874 #define LOADDRMASK (WITH_TARGET_WORD_BITSIZE == 64 \
 875                     ? AccessLength_DOUBLEWORD /*7*/ \
 876                     : AccessLength_WORD /*3*/)
 877 #define PSIZE (WITH_TARGET_ADDRESS_BITSIZE)
 878
 879
 880 INLINE_SIM_MAIN (int) address_translation PARAMS ((SIM_DESC sd, sim_cpu *, address_word cia, address_word vAddr, int IorD, int LorS, address_word *pAddr, int *CCA, int raw));
 881 #define AddressTranslation(vAddr,IorD,LorS,pAddr,CCA,host,raw) \
 882 address_translation (SD, CPU, cia, vAddr, IorD, LorS, pAddr, CCA, raw)
 883
 884 INLINE_SIM_MAIN (void) load_memory PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia, uword64* memvalp, uword64* memval1p, int CCA, unsigned int AccessLength, address_word pAddr, address_word vAddr, int IorD));
 885 #define LoadMemory(memvalp,memval1p,CCA,AccessLength,pAddr,vAddr,IorD,raw) \
 886 load_memory (SD, CPU, cia, memvalp, memval1p, CCA, AccessLength, pAddr, vAddr, IorD)
 887
 888 INLINE_SIM_MAIN (void) store_memory PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia, int CCA, unsigned int AccessLength, uword64 MemElem, uword64 MemElem1, address_word pAddr, address_word vAddr));
 889 #define StoreMemory(CCA,AccessLength,MemElem,MemElem1,pAddr,vAddr,raw) \
 890 store_memory (SD, CPU, cia, CCA, AccessLength, MemElem, MemElem1, pAddr, vAddr)
 891
 892 INLINE_SIM_MAIN (void) cache_op PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia, int op, address_word pAddr, address_word vAddr, unsigned int instruction));
 893 #define CacheOp(op,pAddr,vAddr,instruction) \
 894 cache_op (SD, CPU, cia, op, pAddr, vAddr, instruction)
 895
 896 INLINE_SIM_MAIN (void) sync_operation PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia, int stype));
 897 #define SyncOperation(stype) \
 898 sync_operation (SD, CPU, cia, (stype))
 899
 900 INLINE_SIM_MAIN (void) prefetch PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia, int CCA, address_word pAddr, address_word vAddr, int DATA, int hint));
 901 #define Prefetch(CCA,pAddr,vAddr,DATA,hint) \
 902 prefetch (SD, CPU, cia, CCA, pAddr, vAddr, DATA, hint)
 903
 904 void unpredictable_action (sim_cpu *cpu, address_word cia);
 905 #define NotWordValue(val)       not_word_value (SD_, (val))
 906 #define Unpredictable()         unpredictable (SD_)
 907 #define UnpredictableResult()   /* For now, do nothing.  */
 908
 909 INLINE_SIM_MAIN (unsigned32) ifetch32 PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia, address_word vaddr));
 910 #define IMEM32(CIA) ifetch32 (SD, CPU, (CIA), (CIA))
 911 INLINE_SIM_MAIN (unsigned16) ifetch16 PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia, address_word vaddr));
 912 #define IMEM16(CIA) ifetch16 (SD, CPU, (CIA), ((CIA) & ~1))
 913 #define IMEM16_IMMED(CIA,NR) ifetch16 (SD, CPU, (CIA), ((CIA) & ~1) + 2 * (NR))
 914
 915 void dotrace PARAMS ((SIM_DESC sd, sim_cpu *cpu, FILE *tracefh, int type, SIM_ADDR address, int width, char *comment, ...));
 916 extern FILE *tracefh;
 917
 918 INLINE_SIM_MAIN (void) pending_tick PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia));
 919 extern SIM_CORE_SIGNAL_FN mips_core_signal;
 920
 921 char* pr_addr PARAMS ((SIM_ADDR addr));
 922 char* pr_uword64 PARAMS ((uword64 addr));
 923
 924
 925 #define GPR_CLEAR(N) do { GPR_SET((N),0); } while (0)
 926
 927 void mips_cpu_exception_trigger(SIM_DESC sd, sim_cpu* cpu, address_word pc);
 928 void mips_cpu_exception_suspend(SIM_DESC sd, sim_cpu* cpu, int exception);
 929 void mips_cpu_exception_resume(SIM_DESC sd, sim_cpu* cpu, int exception);
 930
 931
 932 #if H_REVEALS_MODULE_P (SIM_MAIN_INLINE)
 933 #include "sim-main.c"
 934 #endif
 935
 936 #endif