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[thirdparty/binutils-gdb.git] / sim / mn10200 / simops.c
1 #include "config.h"
2
3 #include <signal.h>
4 #ifdef HAVE_UNISTD_H
5 #include <unistd.h>
6 #endif
7 #include "mn10200_sim.h"
8 #include "simops.h"
9 #include "targ-vals.h"
10 #include "bfd.h"
11 #include <errno.h>
12 #include <sys/stat.h>
13 #include <sys/times.h>
14 #include <sys/time.h>
15
16 #define REG0(X) ((X) & 0x3)
17 #define REG1(X) (((X) & 0xc) >> 2)
18 #define REG0_4(X) (((X) & 0x30) >> 4)
19 #define REG0_8(X) (((X) & 0x300) >> 8)
20 #define REG1_8(X) (((X) & 0xc00) >> 10)
21 #define REG0_16(X) (((X) & 0x30000) >> 16)
22 #define REG1_16(X) (((X) & 0xc0000) >> 18)
23 #define TRUNC(X) ((X) & 0xffffff)
24 \f
25 /* mov imm8, dn */
26 void OP_8000 (insn, extension)
27 unsigned long insn, extension;
28 {
29 State.regs[REG_D0 + REG0_8 (insn)] = SEXT8 (insn & 0xff);
30 }
31
32 /* mov dn, dm */
33 void OP_80 (insn, extension)
34 unsigned long insn, extension;
35 {
36 State.regs[REG_D0 + REG0 (insn)] = State.regs[REG_D0 + REG1 (insn)];
37 }
38
39 /* mov dm, an */
40 void OP_F230 (insn, extension)
41 unsigned long insn, extension;
42 {
43 State.regs[REG_A0 + REG0 (insn)] = State.regs[REG_D0 + REG1 (insn)];
44 }
45
46 /* mov an, dm */
47 void OP_F2F0 (insn, extension)
48 unsigned long insn, extension;
49 {
50 State.regs[REG_D0 + REG0 (insn)] = State.regs[REG_A0 + REG1 (insn)];
51 }
52
53 /* mov an, am */
54 void OP_F270 (insn, extension)
55 unsigned long insn, extension;
56 {
57 State.regs[REG_A0 + REG0 (insn)] = State.regs[REG_A0 + REG1 (insn)];
58 }
59
60 /* mov psw, dn */
61 void OP_F3F0 (insn, extension)
62 unsigned long insn, extension;
63 {
64 State.regs[REG_D0 + REG0 (insn)] = PSW & 0xffff;
65 }
66
67 /* mov dn, psw */
68 void OP_F3D0 (insn, extension)
69 unsigned long insn, extension;
70 {
71 PSW = State.regs[REG_D0 + REG1 (insn)] & 0xffff ;
72 }
73
74 /* mov mdr, dn */
75 void OP_F3E0 (insn, extension)
76 unsigned long insn, extension;
77 {
78 State.regs[REG_D0 + REG0 (insn)] = State.regs[REG_MDR] & 0xffff;
79 }
80
81 /* mov dn, mdr */
82 void OP_F3C0 (insn, extension)
83 unsigned long insn, extension;
84 {
85 State.regs[REG_MDR] = State.regs[REG_D0 + REG1 (insn)] & 0xffff;
86 }
87
88 /* mov (an), dm */
89 void OP_20 (insn, extension)
90 unsigned long insn, extension;
91 {
92 State.regs[REG_D0 + REG0 (insn)]
93 = SEXT16 (load_half (State.regs[REG_A0 + REG1 (insn)]));
94 }
95
96 /* mov (d8,an), dm */
97 void OP_6000 (insn, extension)
98 unsigned long insn, extension;
99 {
100 State.regs[REG_D0 + REG0_8 (insn)]
101 = SEXT16 (load_half ((State.regs[REG_A0 + REG1_8 (insn)]
102 + SEXT8 (insn & 0xff))));
103 }
104
105 /* mov (d16,an), dm */
106 void OP_F7C00000 (insn, extension)
107 unsigned long insn, extension;
108 {
109 State.regs[REG_D0 + REG0_16 (insn)]
110 = SEXT16 (load_half ((State.regs[REG_A0 + REG1_16 (insn)]
111 + SEXT16 (insn & 0xffff))));
112 }
113
114 /* mov (d24,am), dn */
115 void OP_F4800000 (insn, extension)
116 unsigned long insn, extension;
117 {
118 State.regs[REG_D0 + REG0_16 (insn)]
119 = SEXT16 (load_half ((State.regs[REG_A0 + REG1_16 (insn)]
120 + SEXT24 (((insn & 0xffff) << 8) + extension))));
121 }
122
123 /* mov (di,an), dm */
124 void OP_F140 (insn, extension)
125 unsigned long insn, extension;
126 {
127 State.regs[REG_D0 + REG0 (insn)]
128 = SEXT16 (load_half ((State.regs[REG_A0 + REG1 (insn)]
129 + State.regs[REG_D0 + REG0_4 (insn)])));
130 }
131
132 /* mov (abs16), dn */
133 void OP_C80000 (insn, extension)
134 unsigned long insn, extension;
135 {
136 State.regs[REG_D0 + REG0_16 (insn)] = SEXT16 (load_half ((insn & 0xffff)));
137 }
138
139 /* mov (abs24), dn */
140 void OP_F4C00000 (insn, extension)
141 unsigned long insn, extension;
142 {
143 State.regs[REG_D0 + REG0_16 (insn)]
144 = SEXT16 (load_half ((((insn & 0xffff) << 8) + extension)));
145 }
146
147 /* mov (d8,an), am */
148 void OP_7000 (insn, extension)
149 unsigned long insn, extension;
150 {
151 State.regs[REG_A0 + REG0_8 (insn)]
152 = SEXT24 (load_3_byte ((State.regs[REG_A0 + REG1_8 (insn)]
153 + SEXT8 (insn & 0xff))));
154 }
155
156 /* mov (d16,an), am */
157 void OP_F7B00000 (insn, extension)
158 unsigned long insn, extension;
159 {
160 State.regs[REG_A0 + REG0_16 (insn)]
161 = SEXT24 (load_3_byte ((State.regs[REG_A0 + REG1_16 (insn)]
162 + SEXT16 (insn & 0xffff))));
163 }
164
165 /* mov (d24,am), an */
166 void OP_F4F00000 (insn, extension)
167 unsigned long insn, extension;
168 {
169 State.regs[REG_A0 + REG0_16 (insn)]
170 = SEXT24 (load_3_byte ((State.regs[REG_A0 + REG1_16 (insn)]
171 + SEXT24 (((insn & 0xffff) << 8) + extension))));
172 }
173
174 /* mov (di,an), am */
175 void OP_F100 (insn, extension)
176 unsigned long insn, extension;
177 {
178 State.regs[REG_A0 + REG0 (insn)]
179 = SEXT24 (load_3_byte ((State.regs[REG_A0 + REG1 (insn)]
180 + State.regs[REG_D0 + REG0_4 (insn)])));
181 }
182
183 /* mov (abs16), an */
184 void OP_F7300000 (insn, extension)
185 unsigned long insn, extension;
186 {
187 State.regs[REG_A0 + REG0_16 (insn)] = SEXT24 (load_3_byte ((insn & 0xffff)));
188 }
189
190 /* mov (abs24), an */
191 void OP_F4D00000 (insn, extension)
192 unsigned long insn, extension;
193 {
194 State.regs[REG_A0 + REG0_16 (insn)]
195 = SEXT24 (load_3_byte ((((insn & 0xffff) << 8) + extension)));
196 }
197
198 /* mov dm, (an) */
199 void OP_0 (insn, extension)
200 unsigned long insn, extension;
201 {
202 store_half (State.regs[REG_A0 + REG1 (insn)],
203 State.regs[REG_D0 + REG0 (insn)]);
204 }
205
206 /* mov dm, (d8,an) */
207 void OP_4000 (insn, extension)
208 unsigned long insn, extension;
209 {
210 store_half (State.regs[REG_A0 + REG1_8 (insn)] + SEXT8 (insn & 0xff),
211 State.regs[REG_D0 + REG0_8 (insn)]);
212 }
213
214 /* mov dm, (d16,an) */
215 void OP_F7800000 (insn, extension)
216 unsigned long insn, extension;
217 {
218 store_half (State.regs[REG_A0 + REG1_16 (insn)] + SEXT16 (insn & 0xffff),
219 State.regs[REG_D0 + REG0_16 (insn)]);
220 }
221
222 /* mov dm, (d24,am) */
223 void OP_F4000000 (insn, extension)
224 unsigned long insn, extension;
225 {
226 store_half ((State.regs[REG_A0 + REG1_16 (insn)]
227 + SEXT24 (((insn & 0xffff) << 8) + extension)),
228 State.regs[REG_D0 + REG0_16 (insn)]);
229 }
230
231 /* mov dm, (di,an) */
232 void OP_F1C0 (insn, extension)
233 unsigned long insn, extension;
234 {
235 store_half ((State.regs[REG_A0 + REG1 (insn)]
236 + State.regs[REG_D0 + REG0_4 (insn)]),
237 State.regs[REG_D0 + REG0 (insn)]);
238 }
239
240 /* mov dn, (abs16) */
241 void OP_C00000 (insn, extension)
242 unsigned long insn, extension;
243 {
244 store_half ((insn & 0xffff), State.regs[REG_D0 + REG0_16 (insn)]);
245 }
246
247 /* mov dn, (abs24) */
248 void OP_F4400000 (insn, extension)
249 unsigned long insn, extension;
250 {
251 store_half (SEXT24 (((insn & 0xffff) << 8) + extension),
252 State.regs[REG_D0 + REG0_16 (insn)]);
253 }
254
255 /* mov am, (d8,an) */
256 void OP_5000 (insn, extension)
257 unsigned long insn, extension;
258 {
259 store_3_byte (State.regs[REG_A0 + REG1_8 (insn)] + SEXT8 (insn & 0xff),
260 State.regs[REG_A0 + REG0_8 (insn)]);
261 }
262
263 /* mov am, (d16,an) */
264 void OP_F7A00000 (insn, extension)
265 unsigned long insn, extension;
266 {
267 store_3_byte (State.regs[REG_A0 + REG1_16 (insn)] + SEXT16 (insn & 0xffff),
268 State.regs[REG_A0 + REG0_16 (insn)]);
269 }
270
271 /* mov am, (d24,an) */
272 void OP_F4100000 (insn, extension)
273 unsigned long insn, extension;
274 {
275 store_3_byte ((State.regs[REG_A0 + REG1_16 (insn)]
276 + SEXT24 (((insn & 0xffff) << 8) + extension)),
277 State.regs[REG_A0 + REG0_16 (insn)]);
278 }
279
280 /* mov am, (di,an) */
281 void OP_F180 (insn, extension)
282 unsigned long insn, extension;
283 {
284 store_3_byte ((State.regs[REG_A0 + REG1 (insn)]
285 + State.regs[REG_D0 + REG0_4 (insn)]),
286 State.regs[REG_A0 + REG0 (insn)]);
287 }
288
289 /* mov an, (abs16) */
290 void OP_F7200000 (insn, extension)
291 unsigned long insn, extension;
292 {
293 store_3_byte ((insn & 0xffff), State.regs[REG_A0 + REG0_16 (insn)]);
294 }
295
296 /* mov an, (abs24) */
297 void OP_F4500000 (insn, extension)
298 unsigned long insn, extension;
299 {
300 store_3_byte (SEXT24 (((insn & 0xffff) << 8) + extension),
301 State.regs[REG_A0 + REG0_16 (insn)]);
302 }
303
304 /* mov imm16, dn */
305 void OP_F80000 (insn, extension)
306 unsigned long insn, extension;
307 {
308 State.regs[REG_D0 + REG0_16 (insn)] = SEXT16 (insn & 0xffff);
309 }
310
311 /* mov imm24, dn */
312 void OP_F4700000 (insn, extension)
313 unsigned long insn, extension;
314 {
315 State.regs[REG_D0 + REG0_16 (insn)]
316 = SEXT24 (((insn & 0xffff) << 8) + extension);
317 }
318
319 /* mov imm16, an */
320 void OP_DC0000 (insn, extension)
321 unsigned long insn, extension;
322 {
323 State.regs[REG_A0 + REG0_16 (insn)] = insn & 0xffff;
324 }
325
326 /* mov imm24, an */
327 void OP_F4740000 (insn, extension)
328 unsigned long insn, extension;
329 {
330 State.regs[REG_A0 + REG0_16 (insn)]
331 = SEXT24 (((insn & 0xffff) << 8) + extension);
332 }
333
334 /* movx (d8,an), dm */
335 void OP_F57000 (insn, extension)
336 unsigned long insn, extension;
337 {
338 State.regs[REG_D0 + REG0_8 (insn)]
339 = SEXT24 (load_3_byte ((State.regs[REG_A0 + REG1_8 (insn)]
340 + SEXT8 (insn & 0xff))));
341 }
342
343 /* movx (d16,an), dm */
344 void OP_F7700000 (insn, extension)
345 unsigned long insn, extension;
346 {
347 State.regs[REG_D0 + REG0_16 (insn)]
348 = SEXT24 (load_3_byte ((State.regs[REG_A0 + REG1_16 (insn)]
349 + SEXT16 (insn & 0xffff))));
350 }
351
352 /* movx (d24,am), dn */
353 void OP_F4B00000 (insn, extension)
354 unsigned long insn, extension;
355 {
356 State.regs[REG_D0 + REG0_16 (insn)]
357 = SEXT24 (load_3_byte ((State.regs[REG_A0 + REG1_16 (insn)]
358 + SEXT24 (((insn & 0xffff) << 8) + extension))));
359 }
360
361 /* movx dm, (d8,an) */
362 void OP_F55000 (insn, extension)
363 unsigned long insn, extension;
364 {
365 store_3_byte (State.regs[REG_A0 + REG1_8 (insn)] + SEXT8 (insn & 0xff),
366 State.regs[REG_D0 + REG0_8 (insn)]);
367 }
368
369 /* movx dm, (d16,an) */
370 void OP_F7600000 (insn, extension)
371 unsigned long insn, extension;
372 {
373 store_3_byte (State.regs[REG_A0 + REG1_16 (insn)] + SEXT16 (insn & 0xffff),
374 State.regs[REG_D0 + REG0_16 (insn)]);
375 }
376
377 /* movx dm, (d24,am) */
378 void OP_F4300000 (insn, extension)
379 unsigned long insn, extension;
380 {
381 store_3_byte ((State.regs[REG_A0 + REG1_16 (insn)]
382 + SEXT24 (((insn & 0xffff) << 8) + extension)),
383 State.regs[REG_D0 + REG0_16 (insn)]);
384 }
385
386 /* movb (d8,an), dm */
387 void OP_F52000 (insn, extension)
388 unsigned long insn, extension;
389 {
390 State.regs[REG_D0 + REG0_8 (insn)]
391 = SEXT8 (load_byte ((State.regs[REG_A0 + REG1_8 (insn)]
392 + SEXT8 (insn & 0xff))));
393 }
394
395 /* movb (d16,an), dm */
396 void OP_F7D00000 (insn, extension)
397 unsigned long insn, extension;
398 {
399 State.regs[REG_D0 + REG0_16 (insn)]
400 = SEXT8 (load_byte ((State.regs[REG_A0 + REG1_16 (insn)]
401 + SEXT16 (insn & 0xffff))));
402 }
403
404 /* movb (d24,am), dn */
405 void OP_F4A00000 (insn, extension)
406 unsigned long insn, extension;
407 {
408 State.regs[REG_D0 + REG0_16 (insn)]
409 = SEXT8 (load_byte ((State.regs[REG_A0 + REG1_16 (insn)]
410 + SEXT24 (((insn & 0xffff) << 8) + extension))));
411 }
412
413 /* movb (di,an), dm */
414 void OP_F040 (insn, extension)
415 unsigned long insn, extension;
416 {
417 State.regs[REG_D0 + REG0 (insn)]
418 = SEXT8 (load_byte ((State.regs[REG_A0 + REG1 (insn)]
419 + State.regs[REG_D0 + REG0_4 (insn)])));
420 }
421
422 /* mov (abs24), dn */
423 void OP_F4C40000 (insn, extension)
424 unsigned long insn, extension;
425 {
426 State.regs[REG_D0 + REG0_16 (insn)]
427 = SEXT8 (load_byte ((((insn & 0xffff) << 8) + extension)));
428 }
429
430 /* movb dm, (an) */
431 void OP_10 (insn, extension)
432 unsigned long insn, extension;
433 {
434 store_byte (State.regs[REG_A0 + REG1 (insn)],
435 State.regs[REG_D0 + REG0 (insn)]);
436 }
437
438 /* movb dm, (d8,an) */
439 void OP_F51000 (insn, extension)
440 unsigned long insn, extension;
441 {
442 store_byte (State.regs[REG_A0 + REG1_8 (insn)] + SEXT8 (insn & 0xff),
443 State.regs[REG_D0 + REG0_8 (insn)]);
444 }
445
446 /* movb dm, (d16,an) */
447 void OP_F7900000 (insn, extension)
448 unsigned long insn, extension;
449 {
450 store_byte (State.regs[REG_A0 + REG1_16 (insn)] + SEXT16 (insn & 0xffff),
451 State.regs[REG_D0 + REG0_16 (insn)]);
452 }
453
454 /* movb dm, (d24,am) */
455 void OP_F4200000 (insn, extension)
456 unsigned long insn, extension;
457 {
458 store_byte ((State.regs[REG_A0 + REG1_16 (insn)]
459 + SEXT24 (((insn & 0xffff) << 8) + extension)),
460 State.regs[REG_D0 + REG0_16 (insn)]);
461 }
462
463 /* movb dm, (di,an) */
464 void OP_F0C0 (insn, extension)
465 unsigned long insn, extension;
466 {
467 store_byte ((State.regs[REG_A0 + REG1 (insn)]
468 + State.regs[REG_D0 + REG0_4 (insn)]),
469 State.regs[REG_D0 + REG0 (insn)]);
470 }
471
472 /* movb dn, (abs16) */
473 void OP_C40000 (insn, extension)
474 unsigned long insn, extension;
475 {
476 store_byte ((insn & 0xffff), State.regs[REG_D0 + REG0_16 (insn)]);
477 }
478
479 /* movb dn, (abs24) */
480 void OP_F4440000 (insn, extension)
481 unsigned long insn, extension;
482 {
483 store_byte (SEXT24 (((insn & 0xffff) << 8) + extension),
484 State.regs[REG_D0 + REG0_16 (insn)]);
485 }
486
487 /* movbu (an), dm */
488 void OP_30 (insn, extension)
489 unsigned long insn, extension;
490 {
491 State.regs[REG_D0 + REG0 (insn)]
492 = load_byte (State.regs[REG_A0 + REG1 (insn)]);
493 }
494
495 /* movbu (d8,an), dm */
496 void OP_F53000 (insn, extension)
497 unsigned long insn, extension;
498 {
499 State.regs[REG_D0 + REG0_8 (insn)]
500 = load_byte ((State.regs[REG_A0 + REG1_8 (insn)] + SEXT8 (insn & 0xff)));
501 }
502
503 /* movbu (d16,an), dm */
504 void OP_F7500000 (insn, extension)
505 unsigned long insn, extension;
506 {
507 State.regs[REG_D0 + REG0_16 (insn)]
508 = load_byte ((State.regs[REG_A0 + REG1_16 (insn)]
509 + SEXT16 (insn & 0xffff)));
510 }
511
512 /* movbu (d24,am), dn */
513 void OP_F4900000 (insn, extension)
514 unsigned long insn, extension;
515 {
516 State.regs[REG_D0 + REG0_16 (insn)]
517 = load_byte ((State.regs[REG_A0 + REG1_16 (insn)]
518 + SEXT24 (((insn & 0xffff) << 8) + extension)));
519 }
520
521 /* movbu (di,an), dm */
522 void OP_F080 (insn, extension)
523 unsigned long insn, extension;
524 {
525 State.regs[REG_D0 + REG0 (insn)]
526 = load_byte ((State.regs[REG_A0 + REG1 (insn)]
527 + State.regs[REG_D0 + REG0_4 (insn)]));
528 }
529
530 /* movbu (abs16), dn */
531 void OP_CC0000 (insn, extension)
532 unsigned long insn, extension;
533 {
534 State.regs[REG_D0 + REG0_16 (insn)] = load_byte ((insn & 0xffff));
535 }
536
537 /* movbu (abs24), dn */
538 void OP_F4C80000 (insn, extension)
539 unsigned long insn, extension;
540 {
541 State.regs[REG_D0 + REG0_16 (insn)]
542 = load_byte ((((insn & 0xffff) << 8) + extension));
543 }
544
545 /* ext dn */
546 void OP_F3C1 (insn, extension)
547 unsigned long insn, extension;
548 {
549 if (State.regs[REG_D0 + REG1 (insn)] & 0x8000)
550 State.regs[REG_MDR] = 0xffff;
551 else
552 State.regs[REG_MDR] = 0;
553 }
554
555 /* extx dn */
556 void OP_B0 (insn, extension)
557 unsigned long insn, extension;
558 {
559 State.regs[REG_D0 + REG0 (insn)] = SEXT16 (State.regs[REG_D0 + REG0 (insn)]);
560 }
561
562 /* extxu dn */
563 void OP_B4 (insn, extension)
564 unsigned long insn, extension;
565 {
566 State.regs[REG_D0 + REG0 (insn)] = State.regs[REG_D0 + REG0 (insn)] & 0xffff;
567 }
568
569 /* extxb dn */
570 void OP_B8 (insn, extension)
571 unsigned long insn, extension;
572 {
573 State.regs[REG_D0 + REG0 (insn)] = SEXT8 (State.regs[REG_D0 + REG0 (insn)]);
574 }
575
576 /* extxbu dn */
577 void OP_BC (insn, extension)
578 unsigned long insn, extension;
579 {
580 State.regs[REG_D0 + REG0 (insn)] = State.regs[REG_D0 + REG0 (insn)] & 0xff;
581 }
582
583 /* add dn,dm */
584 void OP_90 (insn, extension)
585 unsigned long insn, extension;
586 {
587 int z, c, n, v, zx, cx, nx, vx;
588 unsigned long reg1, reg2, value;
589
590 reg1 = TRUNC (State.regs[REG_D0 + REG1 (insn)]);
591 reg2 = TRUNC (State.regs[REG_D0 + REG0 (insn)]);
592 value = TRUNC (reg1 + reg2);
593 State.regs[REG_D0 + REG0 (insn)] = value;
594
595 z = ((value & 0xffff) == 0);
596 zx = (value == 0);
597 n = (value & 0x8000);
598 nx = (value & 0x800000);
599 c = ((value & 0xffff) < (reg1 & 0xffff))
600 || ((value & 0xffff) < (reg2 & 0xffff));
601 cx = (value < reg1) || (value < reg2);
602 v = ((reg2 & 0x8000) == (reg1 & 0x8000)
603 && (reg2 & 0x8000) != (value & 0x8000));
604 vx = ((reg2 & 0x800000) == (reg1 & 0x800000)
605 && (reg2 & 0x800000) != (value & 0x800000));
606
607 PSW &= ~(PSW_ZF | PSW_NF | PSW_CF | PSW_VF
608 | PSW_ZX | PSW_NX | PSW_CX | PSW_VX);
609 PSW |= ((z ? PSW_ZF : 0) | (n ? PSW_NF : 0)
610 | (c ? PSW_CF : 0) | (v ? PSW_VF : 0)
611 | (zx ? PSW_ZX : 0) | (nx ? PSW_NX : 0)
612 | (cx ? PSW_CX : 0) | (vx ? PSW_VX : 0));
613 }
614
615 /* add dm, an */
616 void OP_F200 (insn, extension)
617 unsigned long insn, extension;
618 {
619 int z, c, n, v, zx, cx, nx, vx;
620 unsigned long reg1, reg2, value;
621
622 reg1 = TRUNC (State.regs[REG_D0 + REG1 (insn)]);
623 reg2 = TRUNC (State.regs[REG_A0 + REG0 (insn)]);
624 value = TRUNC (reg1 + reg2);
625 State.regs[REG_A0 + REG0 (insn)] = value;
626
627 z = ((value & 0xffff) == 0);
628 zx = (value == 0);
629 n = (value & 0x8000);
630 nx = (value & 0x800000);
631 c = ((value & 0xffff) < (reg1 & 0xffff))
632 || ((value & 0xffff) < (reg2 & 0xffff));
633 cx = (value < reg1) || (value < reg2);
634 v = ((reg2 & 0x8000) == (reg1 & 0x8000)
635 && (reg2 & 0x8000) != (value & 0x8000));
636 vx = ((reg2 & 0x800000) == (reg1 & 0x800000)
637 && (reg2 & 0x800000) != (value & 0x800000));
638
639 PSW &= ~(PSW_ZF | PSW_NF | PSW_CF | PSW_VF
640 | PSW_ZX | PSW_NX | PSW_CX | PSW_VX);
641 PSW |= ((z ? PSW_ZF : 0) | (n ? PSW_NF : 0)
642 | (c ? PSW_CF : 0) | (v ? PSW_VF : 0)
643 | (zx ? PSW_ZX : 0) | (nx ? PSW_NX : 0)
644 | (cx ? PSW_CX : 0) | (vx ? PSW_VX : 0));
645 }
646
647 /* add an, dm */
648 void OP_F2C0 (insn, extension)
649 unsigned long insn, extension;
650 {
651 int z, c, n, v, zx, cx, nx, vx;
652 unsigned long reg1, reg2, value;
653
654 reg1 = TRUNC (State.regs[REG_A0 + REG1 (insn)]);
655 reg2 = TRUNC (State.regs[REG_D0 + REG0 (insn)]);
656 value = TRUNC (reg1 + reg2);
657 State.regs[REG_D0 + REG0 (insn)] = value;
658
659 z = ((value & 0xffff) == 0);
660 zx = (value == 0);
661 n = (value & 0x8000);
662 nx = (value & 0x800000);
663 c = ((value & 0xffff) < (reg1 & 0xffff))
664 || ((value & 0xffff) < (reg2 & 0xffff));
665 cx = (value < reg1) || (value < reg2);
666 v = ((reg2 & 0x8000) == (reg1 & 0x8000)
667 && (reg2 & 0x8000) != (value & 0x8000));
668 vx = ((reg2 & 0x800000) == (reg1 & 0x800000)
669 && (reg2 & 0x800000) != (value & 0x800000));
670
671 PSW &= ~(PSW_ZF | PSW_NF | PSW_CF | PSW_VF
672 | PSW_ZX | PSW_NX | PSW_CX | PSW_VX);
673 PSW |= ((z ? PSW_ZF : 0) | (n ? PSW_NF : 0)
674 | (c ? PSW_CF : 0) | (v ? PSW_VF : 0)
675 | (zx ? PSW_ZX : 0) | (nx ? PSW_NX : 0)
676 | (cx ? PSW_CX : 0) | (vx ? PSW_VX : 0));
677 }
678
679 /* add an,am */
680 void OP_F240 (insn, extension)
681 unsigned long insn, extension;
682 {
683 int z, c, n, v, zx, cx, nx, vx;
684 unsigned long reg1, reg2, value;
685
686 reg1 = TRUNC (State.regs[REG_A0 + REG1 (insn)]);
687 reg2 = TRUNC (State.regs[REG_A0 + REG0 (insn)]);
688 value = TRUNC (reg1 + reg2);
689 State.regs[REG_A0 + REG0 (insn)] = value;
690
691 z = ((value & 0xffff) == 0);
692 zx = (value == 0);
693 n = (value & 0x8000);
694 nx = (value & 0x800000);
695 c = ((value & 0xffff) < (reg1 & 0xffff))
696 || ((value & 0xffff) < (reg2 & 0xffff));
697 cx = (value < reg1) || (value < reg2);
698 v = ((reg2 & 0x8000) == (reg1 & 0x8000)
699 && (reg2 & 0x8000) != (value & 0x8000));
700 vx = ((reg2 & 0x800000) == (reg1 & 0x800000)
701 && (reg2 & 0x800000) != (value & 0x800000));
702
703 PSW &= ~(PSW_ZF | PSW_NF | PSW_CF | PSW_VF
704 | PSW_ZX | PSW_NX | PSW_CX | PSW_VX);
705 PSW |= ((z ? PSW_ZF : 0) | (n ? PSW_NF : 0)
706 | (c ? PSW_CF : 0) | (v ? PSW_VF : 0)
707 | (zx ? PSW_ZX : 0) | (nx ? PSW_NX : 0)
708 | (cx ? PSW_CX : 0) | (vx ? PSW_VX : 0));
709 }
710
711 /* add imm8, dn */
712 void OP_D400 (insn, extension)
713 unsigned long insn, extension;
714 {
715 int z, c, n, v, zx, cx, nx, vx;
716 unsigned long reg1, imm, value;
717
718 reg1 = TRUNC (State.regs[REG_D0 + REG0_8 (insn)]);
719 imm = TRUNC (SEXT8 (insn & 0xff));
720 value = TRUNC (reg1 + imm);
721 State.regs[REG_D0 + REG0_8 (insn)] = value;
722
723 z = ((value & 0xffff) == 0);
724 zx = (value == 0);
725 n = (value & 0x8000);
726 nx = (value & 0x800000);
727 c = ((value & 0xffff) < (reg1 & 0xffff))
728 || ((value & 0xffff) < (imm & 0xffff));
729 cx = (value < reg1) || (value < imm);
730 v = ((reg1 & 0x8000) == (imm & 0x8000)
731 && (reg1 & 0x8000) != (value & 0x8000));
732 vx = ((reg1 & 0x800000) == (imm & 0x800000)
733 && (reg1 & 0x800000) != (value & 0x800000));
734
735 PSW &= ~(PSW_ZF | PSW_NF | PSW_CF | PSW_VF
736 | PSW_ZX | PSW_NX | PSW_CX | PSW_VX);
737 PSW |= ((z ? PSW_ZF : 0) | (n ? PSW_NF : 0)
738 | (c ? PSW_CF : 0) | (v ? PSW_VF : 0)
739 | (zx ? PSW_ZX : 0) | (nx ? PSW_NX : 0)
740 | (cx ? PSW_CX : 0) | (vx ? PSW_VX : 0));
741 }
742
743 /* add imm16, dn */
744 void OP_F7180000 (insn, extension)
745 unsigned long insn, extension;
746 {
747 int z, c, n, v, zx, cx, nx, vx;
748 unsigned long reg1, imm, value;
749
750 reg1 = TRUNC (State.regs[REG_D0 + REG0_16 (insn)]);
751 imm = TRUNC (SEXT16 (insn & 0xffff));
752 value = TRUNC (reg1 + imm);
753 State.regs[REG_D0 + REG0_16 (insn)] = value;
754
755 z = ((value & 0xffff) == 0);
756 zx = (value == 0);
757 n = (value & 0x8000);
758 nx = (value & 0x800000);
759 c = ((value & 0xffff) < (reg1 & 0xffff))
760 || ((value & 0xffff) < (imm & 0xffff));
761 cx = (value < reg1) || (value < imm);
762 v = ((reg1 & 0x8000) == (imm & 0x8000)
763 && (reg1 & 0x8000) != (value & 0x8000));
764 vx = ((reg1 & 0x800000) == (imm & 0x800000)
765 && (reg1 & 0x800000) != (value & 0x800000));
766
767 PSW &= ~(PSW_ZF | PSW_NF | PSW_CF | PSW_VF
768 | PSW_ZX | PSW_NX | PSW_CX | PSW_VX);
769 PSW |= ((z ? PSW_ZF : 0) | (n ? PSW_NF : 0)
770 | (c ? PSW_CF : 0) | (v ? PSW_VF : 0)
771 | (zx ? PSW_ZX : 0) | (nx ? PSW_NX : 0)
772 | (cx ? PSW_CX : 0) | (vx ? PSW_VX : 0));
773 }
774
775 /* add imm24,dn */
776 void OP_F4600000 (insn, extension)
777 unsigned long insn, extension;
778 {
779 int z, c, n, v, zx, cx, nx, vx;
780 unsigned long reg1, imm, value;
781
782 reg1 = TRUNC (State.regs[REG_D0 + REG0_16 (insn)]);
783 imm = TRUNC (((insn & 0xffff) << 8) + extension);
784 value = TRUNC (reg1 + imm);
785 State.regs[REG_D0 + REG0_16 (insn)] = value;
786
787 z = ((value & 0xffff) == 0);
788 zx = (value == 0);
789 n = (value & 0x8000);
790 nx = (value & 0x800000);
791 c = ((value & 0xffff) < (reg1 & 0xffff))
792 || ((value & 0xffff) < (imm & 0xffff));
793 cx = (value < reg1) || (value < imm);
794 v = ((reg1 & 0x8000) == (imm & 0x8000)
795 && (reg1 & 0x8000) != (value & 0x8000));
796 vx = ((reg1 & 0x800000) == (imm & 0x800000)
797 && (reg1 & 0x800000) != (value & 0x800000));
798
799 PSW &= ~(PSW_ZF | PSW_NF | PSW_CF | PSW_VF
800 | PSW_ZX | PSW_NX | PSW_CX | PSW_VX);
801 PSW |= ((z ? PSW_ZF : 0) | (n ? PSW_NF : 0)
802 | (c ? PSW_CF : 0) | (v ? PSW_VF : 0)
803 | (zx ? PSW_ZX : 0) | (nx ? PSW_NX : 0)
804 | (cx ? PSW_CX : 0) | (vx ? PSW_VX : 0));
805 }
806
807 /* add imm8, an */
808 void OP_D000 (insn, extension)
809 unsigned long insn, extension;
810 {
811 int z, c, n, v, zx, cx, nx, vx;
812 unsigned long reg1, imm, value;
813
814 reg1 = TRUNC (State.regs[REG_A0 + REG0_8 (insn)]);
815 imm = TRUNC (SEXT8 (insn & 0xff));
816 value = TRUNC (reg1 + imm);
817 State.regs[REG_A0 + REG0_8 (insn)] = value;
818
819 z = ((value & 0xffff) == 0);
820 zx = (value == 0);
821 n = (value & 0x8000);
822 nx = (value & 0x800000);
823 c = ((value & 0xffff) < (reg1 & 0xffff))
824 || ((value & 0xffff) < (imm & 0xffff));
825 cx = (value < reg1) || (value < imm);
826 v = ((reg1 & 0x8000) == (imm & 0x8000)
827 && (reg1 & 0x8000) != (value & 0x8000));
828 vx = ((reg1 & 0x800000) == (imm & 0x800000)
829 && (reg1 & 0x800000) != (value & 0x800000));
830
831 PSW &= ~(PSW_ZF | PSW_NF | PSW_CF | PSW_VF
832 | PSW_ZX | PSW_NX | PSW_CX | PSW_VX);
833 PSW |= ((z ? PSW_ZF : 0) | (n ? PSW_NF : 0)
834 | (c ? PSW_CF : 0) | (v ? PSW_VF : 0)
835 | (zx ? PSW_ZX : 0) | (nx ? PSW_NX : 0)
836 | (cx ? PSW_CX : 0) | (vx ? PSW_VX : 0));
837 }
838
839 /* add imm16, an */
840 void OP_F7080000 (insn, extension)
841 unsigned long insn, extension;
842 {
843 int z, c, n, v, zx, cx, nx, vx;
844 unsigned long reg1, imm, value;
845
846 reg1 = TRUNC (State.regs[REG_A0 + REG0_16 (insn)]);
847 imm = TRUNC (SEXT16 (insn & 0xffff));
848 value = TRUNC (reg1 + imm);
849 State.regs[REG_A0 + REG0_16 (insn)] = value;
850
851 z = ((value & 0xffff) == 0);
852 zx = (value == 0);
853 n = (value & 0x8000);
854 nx = (value & 0x800000);
855 c = ((value & 0xffff) < (reg1 & 0xffff))
856 || ((value & 0xffff) < (imm & 0xffff));
857 cx = (value < reg1) || (value < imm);
858 v = ((reg1 & 0x8000) == (imm & 0x8000)
859 && (reg1 & 0x8000) != (value & 0x8000));
860 vx = ((reg1 & 0x800000) == (imm & 0x800000)
861 && (reg1 & 0x800000) != (value & 0x800000));
862
863 PSW &= ~(PSW_ZF | PSW_NF | PSW_CF | PSW_VF
864 | PSW_ZX | PSW_NX | PSW_CX | PSW_VX);
865 PSW |= ((z ? PSW_ZF : 0) | (n ? PSW_NF : 0)
866 | (c ? PSW_CF : 0) | (v ? PSW_VF : 0)
867 | (zx ? PSW_ZX : 0) | (nx ? PSW_NX : 0)
868 | (cx ? PSW_CX : 0) | (vx ? PSW_VX : 0));
869 }
870
871 /* add imm24, an */
872 void OP_F4640000 (insn, extension)
873 unsigned long insn, extension;
874 {
875 int z, c, n, v, zx, cx, nx, vx;
876 unsigned long reg1, imm, value;
877
878 reg1 = TRUNC (State.regs[REG_A0 + REG0_16 (insn)]);
879 imm = TRUNC (((insn & 0xffff) << 8) + extension);
880 value = TRUNC (reg1 + imm);
881 State.regs[REG_A0 + REG0_16 (insn)] = value;
882
883 z = ((value & 0xffff) == 0);
884 zx = (value == 0);
885 n = (value & 0x8000);
886 nx = (value & 0x800000);
887 c = ((value & 0xffff) < (reg1 & 0xffff)) || ((value & 0xffff) < (imm & 0xffff));
888 cx = (value < reg1) || (value < imm);
889 v = ((reg1 & 0x8000) == (imm & 0x8000)
890 && (reg1 & 0x8000) != (value & 0x8000));
891 vx = ((reg1 & 0x800000) == (imm & 0x800000)
892 && (reg1 & 0x800000) != (value & 0x800000));
893
894 PSW &= ~(PSW_ZF | PSW_NF | PSW_CF | PSW_VF
895 | PSW_ZX | PSW_NX | PSW_CX | PSW_VX);
896 PSW |= ((z ? PSW_ZF : 0) | (n ? PSW_NF : 0)
897 | (c ? PSW_CF : 0) | (v ? PSW_VF : 0)
898 | (zx ? PSW_ZX : 0) | (nx ? PSW_NX : 0)
899 | (cx ? PSW_CX : 0) | (vx ? PSW_VX : 0));
900 }
901
902 /* addc dm,dn */
903 void OP_F280 (insn, extension)
904 unsigned long insn, extension;
905 {
906 int z, c, n, v, zx, cx, nx, vx;
907 unsigned long reg1, reg2, value;
908
909 reg1 = TRUNC (State.regs[REG_D0 + REG1 (insn)]);
910 reg2 = TRUNC (State.regs[REG_D0 + REG0 (insn)]);
911 value = TRUNC (reg1 + reg2 + ((PSW & PSW_CF) != 0));
912 State.regs[REG_D0 + REG0 (insn)] = value;
913
914 z = ((value & 0xffff) == 0);
915 zx = (value == 0);
916 n = (value & 0x8000);
917 nx = (value & 0x800000);
918 c = ((value & 0xffff) < (reg1 & 0xffff))
919 || ((value & 0xffff) < (reg2 & 0xffff));
920 cx = (value < reg1) || (value < reg2);
921 v = ((reg2 & 0x8000) == (reg1 & 0x8000)
922 && (reg2 & 0x8000) != (value & 0x8000));
923 vx = ((reg2 & 0x800000) == (reg1 & 0x800000)
924 && (reg2 & 0x800000) != (value & 0x800000));
925
926 PSW &= ~(PSW_ZF | PSW_NF | PSW_CF | PSW_VF
927 | PSW_ZX | PSW_NX | PSW_CX | PSW_VX);
928 PSW |= ((z ? PSW_ZF : 0) | (n ? PSW_NF : 0)
929 | (c ? PSW_CF : 0) | (v ? PSW_VF : 0)
930 | (zx ? PSW_ZX : 0) | (nx ? PSW_NX : 0)
931 | (cx ? PSW_CX : 0) | (vx ? PSW_VX : 0));
932 }
933
934 /* addnf imm8, an */
935 void OP_F50C00 (insn, extension)
936 unsigned long insn, extension;
937 {
938 unsigned long reg1, imm, value;
939
940 reg1 = State.regs[REG_A0 + REG0_8 (insn)];
941 imm = SEXT8 (insn & 0xff);
942 value = reg1 + imm;
943 State.regs[REG_A0 + REG0_8 (insn)] = TRUNC (value);
944 }
945
946 /* sub dn, dm */
947 void OP_A0 (insn, extension)
948 unsigned long insn, extension;
949 {
950 int z, c, n, v, zx, cx, nx, vx;
951 unsigned long reg1, reg2, value;
952
953 reg1 = TRUNC (State.regs[REG_D0 + REG1 (insn)]);
954 reg2 = TRUNC (State.regs[REG_D0 + REG0 (insn)]);
955 value = TRUNC (reg2 - reg1);
956 State.regs[REG_D0 + REG0 (insn)] = value;
957
958 z = ((value & 0xffff) == 0);
959 zx = (value == 0);
960 n = (value & 0x8000);
961 nx = (value & 0x800000);
962 c = ((reg1 & 0xffff) > (reg2 & 0xffff));
963 cx = (reg1 > reg2);
964 v = ((reg2 & 0x8000) != (reg1 & 0x8000)
965 && (reg2 & 0x8000) != (value & 0x8000));
966 vx = ((reg2 & 0x800000) != (reg1 & 0x800000)
967 && (reg2 & 0x800000) != (value & 0x800000));
968
969 PSW &= ~(PSW_ZF | PSW_NF | PSW_CF | PSW_VF
970 | PSW_ZX | PSW_NX | PSW_CX | PSW_VX);
971 PSW |= ((z ? PSW_ZF : 0) | (n ? PSW_NF : 0)
972 | (c ? PSW_CF : 0) | (v ? PSW_VF : 0)
973 | (zx ? PSW_ZX : 0) | (nx ? PSW_NX : 0)
974 | (cx ? PSW_CX : 0) | (vx ? PSW_VX : 0));
975 }
976
977 /* sub dm, an */
978 void OP_F210 (insn, extension)
979 unsigned long insn, extension;
980 {
981 int z, c, n, v, zx, cx, nx, vx;
982 unsigned long reg1, reg2, value;
983
984 reg1 = TRUNC (State.regs[REG_D0 + REG1 (insn)]);
985 reg2 = TRUNC (State.regs[REG_A0 + REG0 (insn)]);
986 value = TRUNC (reg2 - reg1);
987 State.regs[REG_A0 + REG0 (insn)] = value;
988
989 z = ((value & 0xffff) == 0);
990 zx = (value == 0);
991 n = (value & 0x8000);
992 nx = (value & 0x800000);
993 c = ((reg1 & 0xffff) > (reg2 & 0xffff));
994 cx = (reg1 > reg2);
995 v = ((reg2 & 0x8000) != (reg1 & 0x8000)
996 && (reg2 & 0x8000) != (value & 0x8000));
997 vx = ((reg2 & 0x800000) != (reg1 & 0x800000)
998 && (reg2 & 0x800000) != (value & 0x800000));
999
1000 PSW &= ~(PSW_ZF | PSW_NF | PSW_CF | PSW_VF
1001 | PSW_ZX | PSW_NX | PSW_CX | PSW_VX);
1002 PSW |= ((z ? PSW_ZF : 0) | (n ? PSW_NF : 0)
1003 | (c ? PSW_CF : 0) | (v ? PSW_VF : 0)
1004 | (zx ? PSW_ZX : 0) | (nx ? PSW_NX : 0)
1005 | (cx ? PSW_CX : 0) | (vx ? PSW_VX : 0));
1006 }
1007
1008 /* sub an, dm */
1009 void OP_F2D0 (insn, extension)
1010 unsigned long insn, extension;
1011 {
1012 int z, c, n, v, zx, cx, nx, vx;
1013 unsigned long reg1, reg2, value;
1014
1015 reg1 = TRUNC (State.regs[REG_A0 + REG1 (insn)]);
1016 reg2 = TRUNC (State.regs[REG_D0 + REG0 (insn)]);
1017 value = TRUNC (reg2 - reg1);
1018 State.regs[REG_D0 + REG0 (insn)] = value;
1019
1020 z = ((value & 0xffff) == 0);
1021 zx = (value == 0);
1022 n = (value & 0x8000);
1023 nx = (value & 0x800000);
1024 c = ((reg1 & 0xffff) > (reg2 & 0xffff));
1025 cx = (reg1 > reg2);
1026 v = ((reg2 & 0x8000) != (reg1 & 0x8000)
1027 && (reg2 & 0x8000) != (value & 0x8000));
1028 vx = ((reg2 & 0x800000) != (reg1 & 0x800000)
1029 && (reg2 & 0x800000) != (value & 0x800000));
1030
1031 PSW &= ~(PSW_ZF | PSW_NF | PSW_CF | PSW_VF
1032 | PSW_ZX | PSW_NX | PSW_CX | PSW_VX);
1033 PSW |= ((z ? PSW_ZF : 0) | (n ? PSW_NF : 0)
1034 | (c ? PSW_CF : 0) | (v ? PSW_VF : 0)
1035 | (zx ? PSW_ZX : 0) | (nx ? PSW_NX : 0)
1036 | (cx ? PSW_CX : 0) | (vx ? PSW_VX : 0));
1037 }
1038
1039 /* sub an, am */
1040 void OP_F250 (insn, extension)
1041 unsigned long insn, extension;
1042 {
1043 int z, c, n, v, zx, cx, nx, vx;
1044 unsigned long reg1, reg2, value;
1045
1046 reg1 = TRUNC (State.regs[REG_A0 + REG1 (insn)]);
1047 reg2 = TRUNC (State.regs[REG_A0 + REG0 (insn)]);
1048 value = TRUNC (reg2 - reg1);
1049 State.regs[REG_A0 + REG0 (insn)] = value;
1050
1051 z = ((value & 0xffff) == 0);
1052 zx = (value == 0);
1053 n = (value & 0x8000);
1054 nx = (value & 0x800000);
1055 c = ((reg1 & 0xffff) > (reg2 & 0xffff));
1056 cx = (reg1 > reg2);
1057 v = ((reg2 & 0x8000) != (reg1 & 0x8000)
1058 && (reg2 & 0x8000) != (value & 0x8000));
1059 vx = ((reg2 & 0x800000) != (reg1 & 0x800000)
1060 && (reg2 & 0x800000) != (value & 0x800000));
1061
1062 PSW &= ~(PSW_ZF | PSW_NF | PSW_CF | PSW_VF
1063 | PSW_ZX | PSW_NX | PSW_CX | PSW_VX);
1064 PSW |= ((z ? PSW_ZF : 0) | (n ? PSW_NF : 0)
1065 | (c ? PSW_CF : 0) | (v ? PSW_VF : 0)
1066 | (zx ? PSW_ZX : 0) | (nx ? PSW_NX : 0)
1067 | (cx ? PSW_CX : 0) | (vx ? PSW_VX : 0));
1068 }
1069
1070 /* sub imm16, dn */
1071 void OP_F71C0000 (insn, extension)
1072 unsigned long insn, extension;
1073 {
1074 int z, c, n, v, zx, cx, nx, vx;
1075 unsigned long reg1, imm, value;
1076
1077 reg1 = TRUNC (State.regs[REG_D0 + REG0_16 (insn)]);
1078 imm = TRUNC (SEXT16 (insn & 0xffff));
1079 value = TRUNC (reg1 - imm);
1080 State.regs[REG_D0 + REG0_16 (insn)] = value;
1081
1082 z = ((value & 0xffff) == 0);
1083 zx = (value == 0);
1084 n = (value & 0x8000);
1085 nx = (value & 0x800000);
1086 c = ((reg1 & 0xffff) < (imm & 0xffff));
1087 cx = (reg1 < imm);
1088 v = ((reg1 & 0x8000) != (imm & 0x8000)
1089 && (reg1 & 0x8000) != (value & 0x8000));
1090 vx = ((reg1 & 0x800000) != (imm & 0x800000)
1091 && (reg1 & 0x800000) != (value & 0x800000));
1092
1093 PSW &= ~(PSW_ZF | PSW_NF | PSW_CF | PSW_VF
1094 | PSW_ZX | PSW_NX | PSW_CX | PSW_VX);
1095 PSW |= ((z ? PSW_ZF : 0) | (n ? PSW_NF : 0)
1096 | (c ? PSW_CF : 0) | (v ? PSW_VF : 0)
1097 | (zx ? PSW_ZX : 0) | (nx ? PSW_NX : 0)
1098 | (cx ? PSW_CX : 0) | (vx ? PSW_VX : 0));
1099 }
1100
1101 /* sub imm24, dn */
1102 void OP_F4680000 (insn, extension)
1103 unsigned long insn, extension;
1104 {
1105 int z, c, n, v, zx, cx, nx, vx;
1106 unsigned long reg1, imm, value;
1107
1108 reg1 = TRUNC (State.regs[REG_D0 + REG0_16 (insn)]);
1109 imm = TRUNC (((insn & 0xffff) << 8) + extension);
1110 value = TRUNC (reg1 - imm);
1111 State.regs[REG_D0 + REG0_16 (insn)] = value;
1112
1113 z = ((value & 0xffff) == 0);
1114 zx = (value == 0);
1115 n = (value & 0x8000);
1116 nx = (value & 0x800000);
1117 c = ((reg1 & 0xffff) < (imm & 0xffff));
1118 cx = (reg1 < imm);
1119 v = ((reg1 & 0x8000) != (imm & 0x8000)
1120 && (reg1 & 0x8000) != (value & 0x8000));
1121 vx = ((reg1 & 0x800000) != (imm & 0x800000)
1122 && (reg1 & 0x800000) != (value & 0x800000));
1123
1124 PSW &= ~(PSW_ZF | PSW_NF | PSW_CF | PSW_VF
1125 | PSW_ZX | PSW_NX | PSW_CX | PSW_VX);
1126 PSW |= ((z ? PSW_ZF : 0) | (n ? PSW_NF : 0)
1127 | (c ? PSW_CF : 0) | (v ? PSW_VF : 0)
1128 | (zx ? PSW_ZX : 0) | (nx ? PSW_NX : 0)
1129 | (cx ? PSW_CX : 0) | (vx ? PSW_VX : 0));
1130 }
1131
1132 /* sub imm16, an */
1133 void OP_F70C0000 (insn, extension)
1134 unsigned long insn, extension;
1135 {
1136 int z, c, n, v, zx, cx, nx, vx;
1137 unsigned long reg1, imm, value;
1138
1139 reg1 = TRUNC (State.regs[REG_A0 + REG0_16 (insn)]);
1140 imm = TRUNC (SEXT16 (insn & 0xffff));
1141 value = TRUNC (reg1 - imm);
1142 State.regs[REG_A0 + REG0_16 (insn)] = value;
1143
1144 z = ((value & 0xffff) == 0);
1145 zx = (value == 0);
1146 n = (value & 0x8000);
1147 nx = (value & 0x800000);
1148 c = ((reg1 & 0xffff) < (imm & 0xffff));
1149 cx = (reg1 < imm);
1150 v = ((reg1 & 0x8000) != (imm & 0x8000)
1151 && (reg1 & 0x8000) != (value & 0x8000));
1152 vx = ((reg1 & 0x800000) != (imm & 0x800000)
1153 && (reg1 & 0x800000) != (value & 0x800000));
1154
1155 PSW &= ~(PSW_ZF | PSW_NF | PSW_CF | PSW_VF
1156 | PSW_ZX | PSW_NX | PSW_CX | PSW_VX);
1157 PSW |= ((z ? PSW_ZF : 0) | (n ? PSW_NF : 0)
1158 | (c ? PSW_CF : 0) | (v ? PSW_VF : 0)
1159 | (zx ? PSW_ZX : 0) | (nx ? PSW_NX : 0)
1160 | (cx ? PSW_CX : 0) | (vx ? PSW_VX : 0));
1161 }
1162
1163 /* sub imm24, an */
1164 void OP_F46C0000 (insn, extension)
1165 unsigned long insn, extension;
1166 {
1167 int z, c, n, v, zx, cx, nx, vx;
1168 unsigned long reg1, imm, value;
1169
1170 reg1 = TRUNC (State.regs[REG_A0 + REG0_16 (insn)]);
1171 imm = TRUNC (((insn & 0xffff) << 8) + extension);
1172 value = TRUNC (reg1 - imm);
1173 State.regs[REG_A0 + REG0_16 (insn)] = value;
1174
1175 z = ((value & 0xffff) == 0);
1176 zx = (value == 0);
1177 n = (value & 0x8000);
1178 nx = (value & 0x800000);
1179 c = ((reg1 & 0xffff) < (imm & 0xffff));
1180 cx = (reg1 < imm);
1181 v = ((reg1 & 0x8000) != (imm & 0x8000)
1182 && (reg1 & 0x8000) != (value & 0x8000));
1183 vx = ((reg1 & 0x800000) != (imm & 0x800000)
1184 && (reg1 & 0x800000) != (value & 0x800000));
1185
1186 PSW &= ~(PSW_ZF | PSW_NF | PSW_CF | PSW_VF
1187 | PSW_ZX | PSW_NX | PSW_CX | PSW_VX);
1188 PSW |= ((z ? PSW_ZF : 0) | (n ? PSW_NF : 0)
1189 | (c ? PSW_CF : 0) | (v ? PSW_VF : 0)
1190 | (zx ? PSW_ZX : 0) | (nx ? PSW_NX : 0)
1191 | (cx ? PSW_CX : 0) | (vx ? PSW_VX : 0));
1192 }
1193
1194 /* subc dm, dn */
1195 void OP_F290 (insn, extension)
1196 unsigned long insn, extension;
1197 {
1198 int z, c, n, v, zx, cx, nx, vx;
1199 unsigned long reg1, reg2, value;
1200
1201 reg1 = TRUNC (State.regs[REG_D0 + REG1 (insn)]);
1202 reg2 = TRUNC (State.regs[REG_D0 + REG0 (insn)]);
1203 value = TRUNC (reg2 - reg1 - ((PSW & PSW_CF) != 0));
1204 State.regs[REG_D0 + REG0 (insn)] = value;
1205
1206 z = ((value & 0xffff) == 0);
1207 zx = (value == 0);
1208 n = (value & 0x8000);
1209 nx = (value & 0x800000);
1210 c = ((reg1 & 0xffff) > (reg2 & 0xffff));
1211 cx = (reg1 > reg2);
1212 v = ((reg2 & 0x8000) != (reg1 & 0x8000)
1213 && (reg2 & 0x8000) != (value & 0x8000));
1214 vx = ((reg2 & 0x800000) != (reg1 & 0x800000)
1215 && (reg2 & 0x800000) != (value & 0x800000));
1216
1217 PSW &= ~(PSW_ZF | PSW_NF | PSW_CF | PSW_VF
1218 | PSW_ZX | PSW_NX | PSW_CX | PSW_VX);
1219 PSW |= ((z ? PSW_ZF : 0) | (n ? PSW_NF : 0)
1220 | (c ? PSW_CF : 0) | (v ? PSW_VF : 0)
1221 | (zx ? PSW_ZX : 0) | (nx ? PSW_NX : 0)
1222 | (cx ? PSW_CX : 0) | (vx ? PSW_VX : 0));
1223 }
1224
1225 /* mul dn, dm */
1226 void OP_F340 (insn, extension)
1227 unsigned long insn, extension;
1228 {
1229 unsigned long temp;
1230 int n, z;
1231
1232 temp = (SEXT16 (State.regs[REG_D0 + REG0 (insn)] & 0xffff)
1233 * SEXT16 ((State.regs[REG_D0 + REG1 (insn)] & 0xffff)));
1234 State.regs[REG_D0 + REG0 (insn)] = temp & 0xffffff;
1235 State.regs[REG_MDR] = temp >> 16;
1236 z = (State.regs[REG_D0 + REG0 (insn)] & 0xffff) == 0;
1237 n = (State.regs[REG_D0 + REG0 (insn)] & 0x8000) != 0;
1238 PSW &= ~(PSW_ZF | PSW_NF | PSW_VF);
1239 PSW |= ((z ? PSW_ZF : 0) | (n ? PSW_NF : 0));
1240 }
1241
1242 /* mulu dn, dm */
1243 void OP_F350 (insn, extension)
1244 unsigned long insn, extension;
1245 {
1246 unsigned long temp;
1247 int n, z;
1248
1249 temp = ((State.regs[REG_D0 + REG0 (insn)] & 0xffff)
1250 * (State.regs[REG_D0 + REG1 (insn)] & 0xffff));
1251 State.regs[REG_D0 + REG0 (insn)] = temp & 0xffffff;
1252 State.regs[REG_MDR] = temp >> 16;
1253 z = (State.regs[REG_D0 + REG0 (insn)] & 0xffff) == 0;
1254 n = (State.regs[REG_D0 + REG0 (insn)] & 0x8000) != 0;
1255 PSW &= ~(PSW_ZF | PSW_NF | PSW_VF);
1256 PSW |= ((z ? PSW_ZF : 0) | (n ? PSW_NF : 0));
1257 }
1258
1259
1260 /* divu dm, dn */
1261 void OP_F360 (insn, extension)
1262 unsigned long insn, extension;
1263 {
1264 unsigned long temp;
1265 int n, z;
1266
1267 temp = State.regs[REG_MDR];
1268 temp &= 0xffff;
1269 temp <<= 16;
1270 temp |= (State.regs[REG_D0 + REG0 (insn)] & 0xffff);
1271 State.regs[REG_MDR] = (temp
1272 % (unsigned long)(State.regs[REG_D0 + REG1 (insn)] & 0xffff));
1273 temp /= (unsigned long)(State.regs[REG_D0 + REG1 (insn)] & 0xffff);
1274 State.regs[REG_D0 + REG0 (insn)] = temp & 0xffff;
1275 z = (State.regs[REG_D0 + REG0 (insn)] & 0xffff) == 0;
1276 n = (State.regs[REG_D0 + REG0 (insn)] & 0x8000) != 0;
1277 PSW &= ~(PSW_ZF | PSW_NF | PSW_CF | PSW_VF);
1278 PSW |= ((z ? PSW_ZF : 0) | (n ? PSW_NF : 0));
1279 }
1280
1281 /* cmp imm8, dn */
1282 void OP_D800 (insn, extension)
1283 unsigned long insn, extension;
1284 {
1285 int z, c, n, v, zx, cx, nx, vx;
1286 unsigned long reg1, imm, value;
1287
1288 reg1 = TRUNC (State.regs[REG_D0 + REG0_8 (insn)]);
1289 imm = TRUNC (SEXT8 (insn & 0xff));
1290 value = TRUNC (reg1 - imm);
1291
1292 z = ((value & 0xffff) == 0);
1293 zx = (value == 0);
1294 n = (value & 0x8000);
1295 nx = (value & 0x800000);
1296 c = ((reg1 & 0xffff) < (imm & 0xffff));
1297 cx = (reg1 < imm);
1298 v = ((reg1 & 0x8000) != (imm & 0x8000)
1299 && (reg1 & 0x8000) != (value & 0x8000));
1300 vx = ((reg1 & 0x800000) != (imm & 0x800000)
1301 && (reg1 & 0x800000) != (value & 0x800000));
1302
1303 PSW &= ~(PSW_ZF | PSW_NF | PSW_CF | PSW_VF
1304 | PSW_ZX | PSW_NX | PSW_CX | PSW_VX);
1305 PSW |= ((z ? PSW_ZF : 0) | (n ? PSW_NF : 0)
1306 | (c ? PSW_CF : 0) | (v ? PSW_VF : 0)
1307 | (zx ? PSW_ZX : 0) | (nx ? PSW_NX : 0)
1308 | (cx ? PSW_CX : 0) | (vx ? PSW_VX : 0));
1309 }
1310
1311 /* cmp dn, dm */
1312 void OP_F390 (insn, extension)
1313 unsigned long insn, extension;
1314 {
1315 int z, c, n, v, zx, cx, nx, vx;
1316 unsigned long reg1, reg2, value;
1317
1318 reg1 = TRUNC (State.regs[REG_D0 + REG1 (insn)]);
1319 reg2 = TRUNC (State.regs[REG_D0 + REG0 (insn)]);
1320 value = TRUNC (reg2 - reg1);
1321
1322 z = ((value & 0xffff) == 0);
1323 zx = (value == 0);
1324 n = (value & 0x8000);
1325 nx = (value & 0x800000);
1326 c = ((reg1 & 0xffff) > (reg2 & 0xffff));
1327 cx = (reg1 > reg2);
1328 v = ((reg2 & 0x8000) != (reg1 & 0x8000)
1329 && (reg2 & 0x8000) != (value & 0x8000));
1330 vx = ((reg2 & 0x800000) != (reg1 & 0x800000)
1331 && (reg2 & 0x800000) != (value & 0x800000));
1332
1333 PSW &= ~(PSW_ZF | PSW_NF | PSW_CF | PSW_VF
1334 | PSW_ZX | PSW_NX | PSW_CX | PSW_VX);
1335 PSW |= ((z ? PSW_ZF : 0) | (n ? PSW_NF : 0)
1336 | (c ? PSW_CF : 0) | (v ? PSW_VF : 0)
1337 | (zx ? PSW_ZX : 0) | (nx ? PSW_NX : 0)
1338 | (cx ? PSW_CX : 0) | (vx ? PSW_VX : 0));
1339
1340 PSW &= ~(PSW_ZF | PSW_NF | PSW_CF | PSW_VF);
1341 PSW |= ((z ? PSW_ZF : 0) | ( n ? PSW_NF : 0)
1342 | (c ? PSW_CF : 0) | (v ? PSW_VF : 0));
1343 }
1344
1345 /* cmp dm, an */
1346 void OP_F220 (insn, extension)
1347 unsigned long insn, extension;
1348 {
1349 int z, c, n, v, zx, cx, nx, vx;
1350 unsigned long reg1, reg2, value;
1351
1352 reg1 = TRUNC (State.regs[REG_D0 + REG1 (insn)]);
1353 reg2 = TRUNC (State.regs[REG_A0 + REG0 (insn)]);
1354 value = TRUNC (reg2 - reg1);
1355
1356 z = ((value & 0xffff) == 0);
1357 zx = (value == 0);
1358 n = (value & 0x8000);
1359 nx = (value & 0x800000);
1360 c = ((reg1 & 0xffff) > (reg2 & 0xffff));
1361 cx = (reg1 > reg2);
1362 v = ((reg2 & 0x8000) != (reg1 & 0x8000)
1363 && (reg2 & 0x8000) != (value & 0x8000));
1364 vx = ((reg2 & 0x800000) != (reg1 & 0x800000)
1365 && (reg2 & 0x800000) != (value & 0x800000));
1366
1367 PSW &= ~(PSW_ZF | PSW_NF | PSW_CF | PSW_VF
1368 | PSW_ZX | PSW_NX | PSW_CX | PSW_VX);
1369 PSW |= ((z ? PSW_ZF : 0) | (n ? PSW_NF : 0)
1370 | (c ? PSW_CF : 0) | (v ? PSW_VF : 0)
1371 | (zx ? PSW_ZX : 0) | (nx ? PSW_NX : 0)
1372 | (cx ? PSW_CX : 0) | (vx ? PSW_VX : 0));
1373
1374 PSW &= ~(PSW_ZF | PSW_NF | PSW_CF | PSW_VF);
1375 PSW |= ((z ? PSW_ZF : 0) | ( n ? PSW_NF : 0)
1376 | (c ? PSW_CF : 0) | (v ? PSW_VF : 0));
1377 }
1378
1379 /* cmp an, dm */
1380 void OP_F2E0 (insn, extension)
1381 unsigned long insn, extension;
1382 {
1383 int z, c, n, v, zx, cx, nx, vx;
1384 unsigned long reg1, reg2, value;
1385
1386 reg1 = TRUNC (State.regs[REG_A0 + REG1 (insn)]);
1387 reg2 = TRUNC (State.regs[REG_D0 + REG0 (insn)]);
1388 value = TRUNC (reg2 - reg1);
1389
1390 z = ((value & 0xffff) == 0);
1391 zx = (value == 0);
1392 n = (value & 0x8000);
1393 nx = (value & 0x800000);
1394 c = ((reg1 & 0xffff) > (reg2 & 0xffff));
1395 cx = (reg1 > reg2);
1396 v = ((reg2 & 0x8000) != (reg1 & 0x8000)
1397 && (reg2 & 0x8000) != (value & 0x8000));
1398 vx = ((reg2 & 0x800000) != (reg1 & 0x800000)
1399 && (reg2 & 0x800000) != (value & 0x800000));
1400
1401 PSW &= ~(PSW_ZF | PSW_NF | PSW_CF | PSW_VF
1402 | PSW_ZX | PSW_NX | PSW_CX | PSW_VX);
1403 PSW |= ((z ? PSW_ZF : 0) | (n ? PSW_NF : 0)
1404 | (c ? PSW_CF : 0) | (v ? PSW_VF : 0)
1405 | (zx ? PSW_ZX : 0) | (nx ? PSW_NX : 0)
1406 | (cx ? PSW_CX : 0) | (vx ? PSW_VX : 0));
1407
1408 PSW &= ~(PSW_ZF | PSW_NF | PSW_CF | PSW_VF);
1409 PSW |= ((z ? PSW_ZF : 0) | ( n ? PSW_NF : 0)
1410 | (c ? PSW_CF : 0) | (v ? PSW_VF : 0));
1411 }
1412
1413 /* cmp an, am */
1414 void OP_F260 (insn, extension)
1415 unsigned long insn, extension;
1416 {
1417 int z, c, n, v, zx, cx, nx, vx;
1418 unsigned long reg1, reg2, value;
1419
1420 reg1 = TRUNC (State.regs[REG_A0 + REG1 (insn)]);
1421 reg2 = TRUNC (State.regs[REG_A0 + REG0 (insn)]);
1422 value = TRUNC (reg2 - reg1);
1423
1424 z = ((value & 0xffff) == 0);
1425 zx = (value == 0);
1426 n = (value & 0x8000);
1427 nx = (value & 0x800000);
1428 c = ((reg1 & 0xffff) > (reg2 & 0xffff));
1429 cx = (reg1 > reg2);
1430 v = ((reg2 & 0x8000) != (reg1 & 0x8000)
1431 && (reg2 & 0x8000) != (value & 0x8000));
1432 vx = ((reg2 & 0x800000) != (reg1 & 0x800000)
1433 && (reg2 & 0x800000) != (value & 0x800000));
1434
1435 PSW &= ~(PSW_ZF | PSW_NF | PSW_CF | PSW_VF
1436 | PSW_ZX | PSW_NX | PSW_CX | PSW_VX);
1437 PSW |= ((z ? PSW_ZF : 0) | (n ? PSW_NF : 0)
1438 | (c ? PSW_CF : 0) | (v ? PSW_VF : 0)
1439 | (zx ? PSW_ZX : 0) | (nx ? PSW_NX : 0)
1440 | (cx ? PSW_CX : 0) | (vx ? PSW_VX : 0));
1441
1442 PSW &= ~(PSW_ZF | PSW_NF | PSW_CF | PSW_VF);
1443 PSW |= ((z ? PSW_ZF : 0) | ( n ? PSW_NF : 0)
1444 | (c ? PSW_CF : 0) | (v ? PSW_VF : 0));
1445 }
1446
1447 /* cmp imm16, dn */
1448 void OP_F7480000 (insn, extension)
1449 unsigned long insn, extension;
1450 {
1451 int z, c, n, v, zx, cx, nx, vx;
1452 unsigned long reg1, imm, value;
1453
1454 reg1 = TRUNC (State.regs[REG_D0 + REG0_16 (insn)]);
1455 imm = TRUNC (SEXT16 (insn & 0xffff));
1456 value = TRUNC (reg1 - imm);
1457
1458 z = ((value & 0xffff) == 0);
1459 zx = (value == 0);
1460 n = (value & 0x8000);
1461 nx = (value & 0x800000);
1462 c = ((reg1 & 0xffff) < (imm & 0xffff));
1463 cx = (reg1 < imm);
1464 v = ((reg1 & 0x8000) != (imm & 0x8000)
1465 && (reg1 & 0x8000) != (value & 0x8000));
1466 vx = ((reg1 & 0x800000) != (imm & 0x800000)
1467 && (reg1 & 0x800000) != (value & 0x800000));
1468
1469 PSW &= ~(PSW_ZF | PSW_NF | PSW_CF | PSW_VF
1470 | PSW_ZX | PSW_NX | PSW_CX | PSW_VX);
1471 PSW |= ((z ? PSW_ZF : 0) | (n ? PSW_NF : 0)
1472 | (c ? PSW_CF : 0) | (v ? PSW_VF : 0)
1473 | (zx ? PSW_ZX : 0) | (nx ? PSW_NX : 0)
1474 | (cx ? PSW_CX : 0) | (vx ? PSW_VX : 0));
1475
1476 PSW &= ~(PSW_ZF | PSW_NF | PSW_CF | PSW_VF);
1477 PSW |= ((z ? PSW_ZF : 0) | ( n ? PSW_NF : 0)
1478 | (c ? PSW_CF : 0) | (v ? PSW_VF : 0));
1479 }
1480
1481 /* cmp imm24, dn */
1482 void OP_F4780000 (insn, extension)
1483 unsigned long insn, extension;
1484 {
1485 int z, c, n, v, zx, cx, nx, vx;
1486 unsigned long reg1, imm, value;
1487
1488 reg1 = TRUNC (State.regs[REG_D0 + REG0_16 (insn)]);
1489 imm = TRUNC (((insn & 0xffff) << 8) + extension);
1490 value = TRUNC (reg1 - imm);
1491
1492 z = ((value & 0xffff) == 0);
1493 zx = (value == 0);
1494 n = (value & 0x8000);
1495 nx = (value & 0x800000);
1496 c = ((reg1 & 0xffff) < (imm & 0xffff));
1497 cx = (reg1 < imm);
1498 v = ((reg1 & 0x8000) != (imm & 0x8000)
1499 && (reg1 & 0x8000) != (value & 0x8000));
1500 vx = ((reg1 & 0x800000) != (imm & 0x800000)
1501 && (reg1 & 0x800000) != (value & 0x800000));
1502
1503 PSW &= ~(PSW_ZF | PSW_NF | PSW_CF | PSW_VF
1504 | PSW_ZX | PSW_NX | PSW_CX | PSW_VX);
1505 PSW |= ((z ? PSW_ZF : 0) | (n ? PSW_NF : 0)
1506 | (c ? PSW_CF : 0) | (v ? PSW_VF : 0)
1507 | (zx ? PSW_ZX : 0) | (nx ? PSW_NX : 0)
1508 | (cx ? PSW_CX : 0) | (vx ? PSW_VX : 0));
1509
1510 PSW &= ~(PSW_ZF | PSW_NF | PSW_CF | PSW_VF);
1511 PSW |= ((z ? PSW_ZF : 0) | ( n ? PSW_NF : 0)
1512 | (c ? PSW_CF : 0) | (v ? PSW_VF : 0));
1513 }
1514
1515 /* cmp imm16, an */
1516 void OP_EC0000 (insn, extension)
1517 unsigned long insn, extension;
1518 {
1519 int z, c, n, v, zx, cx, nx, vx;
1520 unsigned long reg1, imm, value;
1521
1522 reg1 = TRUNC (State.regs[REG_A0 + REG0_16 (insn)]);
1523 imm = TRUNC (insn & 0xffff);
1524 value = TRUNC (reg1 - imm);
1525
1526 z = ((value & 0xffff) == 0);
1527 zx = (value == 0);
1528 n = (value & 0x8000);
1529 nx = (value & 0x800000);
1530 c = ((reg1 & 0xffff) < (imm & 0xffff));
1531 cx = (reg1 < imm);
1532 v = ((reg1 & 0x8000) != (imm & 0x8000)
1533 && (reg1 & 0x8000) != (value & 0x8000));
1534 vx = ((reg1 & 0x800000) != (imm & 0x800000)
1535 && (reg1 & 0x800000) != (value & 0x800000));
1536
1537 PSW &= ~(PSW_ZF | PSW_NF | PSW_CF | PSW_VF
1538 | PSW_ZX | PSW_NX | PSW_CX | PSW_VX);
1539 PSW |= ((z ? PSW_ZF : 0) | (n ? PSW_NF : 0)
1540 | (c ? PSW_CF : 0) | (v ? PSW_VF : 0)
1541 | (zx ? PSW_ZX : 0) | (nx ? PSW_NX : 0)
1542 | (cx ? PSW_CX : 0) | (vx ? PSW_VX : 0));
1543
1544 PSW &= ~(PSW_ZF | PSW_NF | PSW_CF | PSW_VF);
1545 PSW |= ((z ? PSW_ZF : 0) | ( n ? PSW_NF : 0)
1546 | (c ? PSW_CF : 0) | (v ? PSW_VF : 0));
1547 }
1548
1549 /* cmp imm24, an */
1550 void OP_F47C0000 (insn, extension)
1551 unsigned long insn, extension;
1552 {
1553 int z, c, n, v, zx, cx, nx, vx;
1554 unsigned long reg1, imm, value;
1555
1556 reg1 = TRUNC (State.regs[REG_A0 + REG0_16 (insn)]);
1557 imm = TRUNC (((insn & 0xffff) << 8) + extension);
1558 value = TRUNC (reg1 - imm);
1559
1560 z = ((value & 0xffff) == 0);
1561 zx = (value == 0);
1562 n = (value & 0x8000);
1563 nx = (value & 0x800000);
1564 c = ((reg1 & 0xffff) < (imm & 0xffff));
1565 cx = (reg1 < imm);
1566 v = ((reg1 & 0x8000) != (imm & 0x8000)
1567 && (reg1 & 0x8000) != (value & 0x8000));
1568 vx = ((reg1 & 0x800000) != (imm & 0x800000)
1569 && (reg1 & 0x800000) != (value & 0x800000));
1570
1571 PSW &= ~(PSW_ZF | PSW_NF | PSW_CF | PSW_VF
1572 | PSW_ZX | PSW_NX | PSW_CX | PSW_VX);
1573 PSW |= ((z ? PSW_ZF : 0) | (n ? PSW_NF : 0)
1574 | (c ? PSW_CF : 0) | (v ? PSW_VF : 0)
1575 | (zx ? PSW_ZX : 0) | (nx ? PSW_NX : 0)
1576 | (cx ? PSW_CX : 0) | (vx ? PSW_VX : 0));
1577
1578 PSW &= ~(PSW_ZF | PSW_NF | PSW_CF | PSW_VF);
1579 PSW |= ((z ? PSW_ZF : 0) | ( n ? PSW_NF : 0)
1580 | (c ? PSW_CF : 0) | (v ? PSW_VF : 0));
1581 }
1582
1583 /* and dn, dm */
1584 void OP_F300 (insn, extension)
1585 unsigned long insn, extension;
1586 {
1587 int n, z;
1588 unsigned long temp;
1589
1590 temp = State.regs[REG_D0 + REG0 (insn)] & State.regs[REG_D0 + REG1 (insn)];
1591 temp &= 0xffff;
1592 State.regs[REG_D0 + REG0 (insn)] &= ~0xffff;
1593 State.regs[REG_D0 + REG0 (insn)] |= temp;
1594 z = (State.regs[REG_D0 + REG0 (insn)] & 0xffff) == 0;
1595 n = (State.regs[REG_D0 + REG0 (insn)] & 0x8000) != 0;
1596 PSW &= ~(PSW_ZF | PSW_NF | PSW_CF | PSW_VF);
1597 PSW |= ((z ? PSW_ZF : 0) | (n ? PSW_NF : 0));
1598 }
1599
1600 /* and imm8, dn */
1601 void OP_F50000 (insn, extension)
1602 unsigned long insn, extension;
1603 {
1604 int n, z;
1605 unsigned long temp;
1606
1607 temp = State.regs[REG_D0 + REG0_8 (insn)] & (insn & 0xff);
1608 temp &= 0xffff;
1609 State.regs[REG_D0 + REG0_8 (insn)] &= ~0xffff;
1610 State.regs[REG_D0 + REG0_8 (insn)] |= temp;
1611 z = (State.regs[REG_D0 + REG0_8 (insn)] & 0xffff) == 0;
1612 n = (State.regs[REG_D0 + REG0_8 (insn)] & 0x8000) != 0;
1613 PSW &= ~(PSW_ZF | PSW_NF | PSW_CF | PSW_VF);
1614 PSW |= ((z ? PSW_ZF : 0) | (n ? PSW_NF : 0));
1615 }
1616
1617 /* and imm16, dn */
1618 void OP_F7000000 (insn, extension)
1619 unsigned long insn, extension;
1620 {
1621 int n, z;
1622 unsigned long temp;
1623
1624 temp = State.regs[REG_D0 + REG0_16 (insn)] & (insn & 0xffff);
1625 temp &= 0xffff;
1626 State.regs[REG_D0 + REG0_16 (insn)] &= ~0xffff;
1627 State.regs[REG_D0 + REG0_16 (insn)] |= temp;
1628 z = (State.regs[REG_D0 + REG0_16 (insn)] & 0xffff) == 0;
1629 n = (State.regs[REG_D0 + REG0_16 (insn)] & 0x8000) != 0;
1630 PSW &= ~(PSW_ZF | PSW_NF | PSW_CF | PSW_VF);
1631 PSW |= ((z ? PSW_ZF : 0) | (n ? PSW_NF : 0));
1632 }
1633
1634 /* and imm16, psw */
1635 void OP_F7100000 (insn, extension)
1636 unsigned long insn, extension;
1637 {
1638 PSW &= (insn & 0xffff);
1639 }
1640
1641 /* or dn, dm */
1642 void OP_F310 (insn, extension)
1643 unsigned long insn, extension;
1644 {
1645 int n, z;
1646 unsigned long temp;
1647
1648 temp = State.regs[REG_D0 + REG0 (insn)] | State.regs[REG_D0 + REG1 (insn)];
1649 temp &= 0xffff;
1650 State.regs[REG_D0 + REG0 (insn)] &= ~0xffff;
1651 State.regs[REG_D0 + REG0 (insn)] |= temp;
1652 z = (State.regs[REG_D0 + REG0 (insn)] & 0xffff) == 0;
1653 n = (State.regs[REG_D0 + REG0 (insn)] & 0x8000) != 0;
1654 PSW &= ~(PSW_ZF | PSW_NF | PSW_CF | PSW_VF);
1655 PSW |= ((z ? PSW_ZF : 0) | (n ? PSW_NF : 0));
1656 }
1657
1658 /* or imm8, dn */
1659 void OP_F50800 (insn, extension)
1660 unsigned long insn, extension;
1661 {
1662 int n, z;
1663 unsigned long temp;
1664
1665 temp = State.regs[REG_D0 + REG0_8 (insn)] | (insn & 0xff);
1666 temp &= 0xffff;
1667 State.regs[REG_D0 + REG0_8 (insn)] &= ~0xffff;
1668 State.regs[REG_D0 + REG0_8 (insn)] |= temp;
1669 z = (State.regs[REG_D0 + REG0_8 (insn)] & 0xffff) == 0;
1670 n = (State.regs[REG_D0 + REG0_8 (insn)] & 0x8000) != 0;
1671 PSW &= ~(PSW_ZF | PSW_NF | PSW_CF | PSW_VF);
1672 PSW |= ((z ? PSW_ZF : 0) | (n ? PSW_NF : 0));
1673 }
1674
1675 /* or imm16, dn */
1676 void OP_F7400000 (insn, extension)
1677 unsigned long insn, extension;
1678 {
1679 int n, z;
1680 unsigned long temp;
1681
1682 temp = State.regs[REG_D0 + REG0_16 (insn)] | (insn & 0xffff);
1683 temp &= 0xffff;
1684 State.regs[REG_D0 + REG0_16 (insn)] &= ~0xffff;
1685 State.regs[REG_D0 + REG0_16 (insn)] |= temp;
1686 z = (State.regs[REG_D0 + REG0_16 (insn)] & 0xffff) == 0;
1687 n = (State.regs[REG_D0 + REG0_16 (insn)] & 0x8000) != 0;
1688 PSW &= ~(PSW_ZF | PSW_NF | PSW_CF | PSW_VF);
1689 PSW |= ((z ? PSW_ZF : 0) | (n ? PSW_NF : 0));
1690 }
1691
1692 /* or imm16, psw */
1693 void OP_F7140000 (insn, extension)
1694 unsigned long insn, extension;
1695 {
1696 PSW |= (insn & 0xffff);
1697 }
1698
1699 /* xor dn, dm */
1700 void OP_F320 (insn, extension)
1701 unsigned long insn, extension;
1702 {
1703 int n, z;
1704 unsigned long temp;
1705
1706 temp = State.regs[REG_D0 + REG0 (insn)] ^ State.regs[REG_D0 + REG1 (insn)];
1707 temp &= 0xffff;
1708 State.regs[REG_D0 + REG0 (insn)] &= ~0xffff;
1709 State.regs[REG_D0 + REG0 (insn)] |= temp;
1710 z = (State.regs[REG_D0 + REG0 (insn)] & 0xffff) == 0;
1711 n = (State.regs[REG_D0 + REG0 (insn)] & 0x8000) != 0;
1712 PSW &= ~(PSW_ZF | PSW_NF | PSW_CF | PSW_VF);
1713 PSW |= ((z ? PSW_ZF : 0) | (n ? PSW_NF : 0));
1714 }
1715
1716 /* xor imm16, dn */
1717 void OP_F74C0000 (insn, extension)
1718 unsigned long insn, extension;
1719 {
1720 int n, z;
1721 unsigned long temp;
1722
1723 temp = State.regs[REG_D0 + REG0_16 (insn)] ^ (insn & 0xffff);
1724 temp &= 0xffff;
1725 State.regs[REG_D0 + REG0_16 (insn)] &= ~0xffff;
1726 State.regs[REG_D0 + REG0_16 (insn)] |= temp;
1727 z = (State.regs[REG_D0 + REG0_16 (insn)] & 0xffff) == 0;
1728 n = (State.regs[REG_D0 + REG0_16 (insn)] & 0x8000) != 0;
1729 PSW &= ~(PSW_ZF | PSW_NF | PSW_CF | PSW_VF);
1730 PSW |= ((z ? PSW_ZF : 0) | (n ? PSW_NF : 0));
1731 }
1732
1733 /* not dn */
1734 void OP_F3E4 (insn, extension)
1735 unsigned long insn, extension;
1736 {
1737 int n, z;
1738 unsigned long temp;
1739
1740 temp = ~State.regs[REG_D0 + REG0 (insn)];
1741 temp &= 0xffff;
1742 State.regs[REG_D0 + REG0 (insn)] &= ~0xffff;
1743 State.regs[REG_D0 + REG0 (insn)] |= temp;
1744 z = (State.regs[REG_D0 + REG0 (insn)] & 0xffff) == 0;
1745 n = (State.regs[REG_D0 + REG0 (insn)] & 0x8000) != 0;
1746 PSW &= ~(PSW_ZF | PSW_NF | PSW_CF | PSW_VF);
1747 PSW |= ((z ? PSW_ZF : 0) | (n ? PSW_NF : 0));
1748 }
1749
1750 /* asr dn */
1751 void OP_F338 (insn, extension)
1752 unsigned long insn, extension;
1753 {
1754 long temp;
1755 int z, n, c, high;
1756
1757 temp = State.regs[REG_D0 + REG0 (insn)] & 0xffff;
1758 c = temp & 1;
1759 high = temp & 0x8000;
1760 temp >>= 1;
1761 temp |= high;
1762 temp &= 0xffff;
1763 State.regs[REG_D0 + REG0 (insn)] &= ~0xffff;
1764 State.regs[REG_D0 + REG0 (insn)] |= temp;
1765 z = (State.regs[REG_D0 + REG0 (insn)] & 0xffff) == 0;
1766 n = (State.regs[REG_D0 + REG0 (insn)] & 0x8000) != 0;
1767 PSW &= ~(PSW_ZF | PSW_NF | PSW_CF);
1768 PSW |= ((z ? PSW_ZF : 0) | (n ? PSW_NF : 0) | (c ? PSW_CF : 0));
1769 }
1770
1771 /* lsr dn */
1772 void OP_F33C (insn, extension)
1773 unsigned long insn, extension;
1774 {
1775 int z, n, c;
1776 long temp;
1777
1778 temp = State.regs[REG_D0 + REG0 (insn)] & 0xffff;
1779 c = temp & 1;
1780 temp >>= 1;
1781 temp &= 0xffff;
1782 State.regs[REG_D0 + REG0 (insn)] &= ~0xffff;
1783 State.regs[REG_D0 + REG0 (insn)] |= temp;
1784 z = (State.regs[REG_D0 + REG0 (insn)] & 0xffff) == 0;
1785 n = (State.regs[REG_D0 + REG0 (insn)] & 0x8000) != 0;
1786 PSW &= ~(PSW_ZF | PSW_NF | PSW_CF);
1787 PSW |= ((z ? PSW_ZF : 0) | (n ? PSW_NF : 0) | (c ? PSW_CF : 0));
1788 }
1789
1790 /* ror dn */
1791 void OP_F334 (insn, extension)
1792 unsigned long insn, extension;
1793 {
1794 unsigned long value;
1795 int c,n,z;
1796
1797 value = State.regs[REG_D0 + REG0 (insn)] & 0xffff;
1798 c = (value & 0x1);
1799
1800 value >>= 1;
1801 value |= (PSW & PSW_CF ? 0x8000 : 0);
1802 value &= 0xffff;
1803 State.regs[REG_D0 + REG0 (insn)] &= ~0xffff;
1804 State.regs[REG_D0 + REG0 (insn)] |= value;
1805 z = (value == 0);
1806 n = (value & 0x8000) != 0;
1807 PSW &= ~(PSW_ZF | PSW_NF | PSW_CF | PSW_VF);
1808 PSW |= ((z ? PSW_ZF : 0) | (n ? PSW_NF : 0) | (c ? PSW_CF : 0));
1809 }
1810
1811 /* rol dn */
1812 void OP_F330 (insn, extension)
1813 unsigned long insn, extension;
1814 {
1815 unsigned long value;
1816 int c,n,z;
1817
1818 value = State.regs[REG_D0 + REG0 (insn)] & 0xffff;
1819 c = (value & 0x8000) ? 1 : 0;
1820
1821 value <<= 1;
1822 value |= (PSW & PSW_CF ? 0x1 : 0);
1823 value &= 0xffff;
1824 State.regs[REG_D0 + REG0 (insn)] &= ~0xffff;
1825 State.regs[REG_D0 + REG0 (insn)] |= value;
1826 z = (value == 0);
1827 n = (value & 0x8000) != 0;
1828 PSW &= ~(PSW_ZF | PSW_NF | PSW_CF | PSW_VF);
1829 PSW |= ((z ? PSW_ZF : 0) | (n ? PSW_NF : 0) | (c ? PSW_CF : 0));
1830 }
1831
1832 /* btst imm8, dn */
1833 void OP_F50400 (insn, extension)
1834 unsigned long insn, extension;
1835 {
1836 unsigned long temp;
1837 int z;
1838
1839 temp = State.regs[REG_D0 + REG0_8 (insn)];
1840 temp &= (insn & 0xff);
1841 z = (temp == 0);
1842 PSW &= ~(PSW_ZF | PSW_NF | PSW_CF | PSW_VF);
1843 PSW |= (z ? PSW_ZF : 0);
1844 }
1845
1846 /* btst imm16, dn */
1847 void OP_F7040000 (insn, extension)
1848 unsigned long insn, extension;
1849 {
1850 unsigned long temp;
1851 int z, n, c;
1852
1853 temp = State.regs[REG_D0 + REG0_16 (insn)];
1854 c = temp & 0x1;
1855 temp &= (insn & 0xffff);
1856 n = (temp & 0x8000) != 0;
1857 z = (temp == 0);
1858 PSW &= ~(PSW_ZF | PSW_NF | PSW_CF | PSW_VF);
1859 PSW |= (z ? PSW_ZF : 0) | (n ? PSW_NF : 0) | (c ? PSW_CF : 0);
1860 }
1861
1862 /* bset dm, (an) */
1863 void OP_F020 (insn, extension)
1864 unsigned long insn, extension;
1865 {
1866 unsigned long temp;
1867 int z;
1868
1869 temp = load_byte (State.regs[REG_A0 + REG1 (insn)]);
1870 z = (temp & State.regs[REG_D0 + REG0 (insn)]) == 0;
1871 temp |= State.regs[REG_D0 + REG0 (insn)];
1872 store_byte (State.regs[REG_A0 + REG1 (insn)], temp);
1873 PSW &= ~(PSW_ZF | PSW_NF | PSW_CF | PSW_VF);
1874 PSW |= (z ? PSW_ZF : 0);
1875 }
1876
1877 /* bclr dm, (an) */
1878 void OP_F030 (insn, extension)
1879 unsigned long insn, extension;
1880 {
1881 unsigned long temp;
1882 int z;
1883
1884 temp = load_byte (State.regs[REG_A0 + REG1 (insn)]);
1885 z = (temp & State.regs[REG_D0 + REG0 (insn)]) == 0;
1886 temp = temp & ~State.regs[REG_D0 + REG0 (insn)];
1887 store_byte (State.regs[REG_A0 + REG1 (insn)], temp);
1888 PSW &= ~(PSW_ZF | PSW_NF | PSW_CF | PSW_VF);
1889 PSW |= (z ? PSW_ZF : 0);
1890 }
1891
1892 /* beqx label:8 */
1893 void OP_F5E800 (insn, extension)
1894 unsigned long insn, extension;
1895 {
1896 /* The dispatching code will add 3 after we return, so
1897 we subtract two here to make things right. */
1898 if (PSW & PSW_ZX)
1899 State.regs[REG_PC] = TRUNC (State.regs[REG_PC] + SEXT8 (insn & 0xff));
1900 }
1901
1902 /* bnex label:8 */
1903 void OP_F5E900 (insn, extension)
1904 unsigned long insn, extension;
1905 {
1906 /* The dispatching code will add 3 after we return, so
1907 we subtract two here to make things right. */
1908 if (!(PSW & PSW_ZX))
1909 State.regs[REG_PC] = TRUNC (State.regs[REG_PC] + SEXT8 (insn & 0xff));
1910 }
1911
1912 /* bgtx label:8 */
1913 void OP_F5E100 (insn, extension)
1914 unsigned long insn, extension;
1915 {
1916 /* The dispatching code will add 3 after we return, so
1917 we subtract two here to make things right. */
1918 if (!((PSW & PSW_ZX)
1919 || (((PSW & PSW_NX) != 0) ^ ((PSW & PSW_VX) != 0))))
1920 State.regs[REG_PC] = TRUNC (State.regs[REG_PC] + SEXT8 (insn & 0xff));
1921 }
1922
1923 /* bgex label:8 */
1924 void OP_F5E200 (insn, extension)
1925 unsigned long insn, extension;
1926 {
1927 /* The dispatching code will add 3 after we return, so
1928 we subtract two here to make things right. */
1929 if (!(((PSW & PSW_NX) != 0) ^ ((PSW & PSW_VX) != 0)))
1930 State.regs[REG_PC] = TRUNC (State.regs[REG_PC] + SEXT8 (insn & 0xff));
1931 }
1932
1933 /* blex label:8 */
1934 void OP_F5E300 (insn, extension)
1935 unsigned long insn, extension;
1936 {
1937 /* The dispatching code will add 3 after we return, so
1938 we subtract two here to make things right. */
1939 if ((PSW & PSW_ZX)
1940 || (((PSW & PSW_NX) != 0) ^ ((PSW & PSW_VX) != 0)))
1941 State.regs[REG_PC] = TRUNC (State.regs[REG_PC] + SEXT8 (insn & 0xff));
1942 }
1943
1944 /* bltx label:8 */
1945 void OP_F5E000 (insn, extension)
1946 unsigned long insn, extension;
1947 {
1948 /* The dispatching code will add 3 after we return, so
1949 we subtract two here to make things right. */
1950 if (((PSW & PSW_NX) != 0) ^ ((PSW & PSW_VX) != 0))
1951 State.regs[REG_PC] = TRUNC (State.regs[REG_PC] + SEXT8 (insn & 0xff));
1952 }
1953
1954 /* bhix label:8 */
1955 void OP_F5E500 (insn, extension)
1956 unsigned long insn, extension;
1957 {
1958 /* The dispatching code will add 3 after we return, so
1959 we subtract two here to make things right. */
1960 if (!(((PSW & PSW_CX) != 0) || (PSW & PSW_ZX) != 0))
1961 State.regs[REG_PC] = TRUNC (State.regs[REG_PC] + SEXT8 (insn & 0xff));
1962 }
1963
1964 /* bccx label:8 */
1965 void OP_F5E600 (insn, extension)
1966 unsigned long insn, extension;
1967 {
1968 /* The dispatching code will add 3 after we return, so
1969 we subtract two here to make things right. */
1970 if (!(PSW & PSW_CX))
1971 State.regs[REG_PC] = TRUNC (State.regs[REG_PC] + SEXT8 (insn & 0xff));
1972 }
1973
1974 /* blsx label:8 */
1975 void OP_F5E700 (insn, extension)
1976 unsigned long insn, extension;
1977 {
1978 /* The dispatching code will add 3 after we return, so
1979 we subtract two here to make things right. */
1980 if (((PSW & PSW_CX) != 0) || (PSW & PSW_ZX) != 0)
1981 State.regs[REG_PC] = TRUNC (State.regs[REG_PC] + SEXT8 (insn & 0xff));
1982 }
1983
1984 /* bcsx label:8 */
1985 void OP_F5E400 (insn, extension)
1986 unsigned long insn, extension;
1987 {
1988 /* The dispatching code will add 3 after we return, so
1989 we subtract two here to make things right. */
1990 if (PSW & PSW_CX)
1991 State.regs[REG_PC] = TRUNC (State.regs[REG_PC] + SEXT8 (insn & 0xff));
1992 }
1993
1994 /* bvcx label:8 */
1995 void OP_F5EC00 (insn, extension)
1996 unsigned long insn, extension;
1997 {
1998 /* The dispatching code will add 3 after we return, so
1999 we subtract two here to make things right. */
2000 if (!(PSW & PSW_VX))
2001 State.regs[REG_PC] = TRUNC (State.regs[REG_PC] + SEXT8 (insn & 0xff));
2002 }
2003
2004 /* bvsx label:8 */
2005 void OP_F5ED00 (insn, extension)
2006 unsigned long insn, extension;
2007 {
2008 /* The dispatching code will add 3 after we return, so
2009 we subtract two here to make things right. */
2010 if (PSW & PSW_VX)
2011 State.regs[REG_PC] = TRUNC (State.regs[REG_PC] + SEXT8 (insn & 0xff));
2012 }
2013
2014 /* bncx label:8 */
2015 void OP_F5EE00 (insn, extension)
2016 unsigned long insn, extension;
2017 {
2018 /* The dispatching code will add 3 after we return, so
2019 we subtract two here to make things right. */
2020 if (!(PSW & PSW_NX))
2021 State.regs[REG_PC] = TRUNC (State.regs[REG_PC] + SEXT8 (insn & 0xff));
2022 }
2023
2024 /* bnsx label:8 */
2025 void OP_F5EF00 (insn, extension)
2026 unsigned long insn, extension;
2027 {
2028 /* The dispatching code will add 3 after we return, so
2029 we subtract two here to make things right. */
2030 if (PSW & PSW_NX)
2031 State.regs[REG_PC] = TRUNC (State.regs[REG_PC] + SEXT8 (insn & 0xff));
2032 }
2033
2034 /* beq label:8 */
2035 void OP_E800 (insn, extension)
2036 unsigned long insn, extension;
2037 {
2038 /* The dispatching code will add 2 after we return, so
2039 we subtract two here to make things right. */
2040 if (PSW & PSW_ZF)
2041 State.regs[REG_PC] = TRUNC (State.regs[REG_PC] + SEXT8 (insn & 0xff));
2042 }
2043
2044 /* bne label:8 */
2045 void OP_E900 (insn, extension)
2046 unsigned long insn, extension;
2047 {
2048 /* The dispatching code will add 2 after we return, so
2049 we subtract two here to make things right. */
2050 if (!(PSW & PSW_ZF))
2051 State.regs[REG_PC] = TRUNC (State.regs[REG_PC] + SEXT8 (insn & 0xff));
2052 }
2053
2054 /* bgt label:8 */
2055 void OP_E100 (insn, extension)
2056 unsigned long insn, extension;
2057 {
2058 /* The dispatching code will add 2 after we return, so
2059 we subtract two here to make things right. */
2060 if (!((PSW & PSW_ZF)
2061 || (((PSW & PSW_NF) != 0) ^ ((PSW & PSW_VF) != 0))))
2062 State.regs[REG_PC] = TRUNC (State.regs[REG_PC] + SEXT8 (insn & 0xff));
2063 }
2064
2065 /* bge label:8 */
2066 void OP_E200 (insn, extension)
2067 unsigned long insn, extension;
2068 {
2069 /* The dispatching code will add 2 after we return, so
2070 we subtract two here to make things right. */
2071 if (!(((PSW & PSW_NF) != 0) ^ ((PSW & PSW_VF) != 0)))
2072 State.regs[REG_PC] = TRUNC (State.regs[REG_PC] + SEXT8 (insn & 0xff));
2073 }
2074
2075 /* ble label:8 */
2076 void OP_E300 (insn, extension)
2077 unsigned long insn, extension;
2078 {
2079 /* The dispatching code will add 2 after we return, so
2080 we subtract two here to make things right. */
2081 if ((PSW & PSW_ZF)
2082 || (((PSW & PSW_NF) != 0) ^ ((PSW & PSW_VF) != 0)))
2083 State.regs[REG_PC] = TRUNC (State.regs[REG_PC] + SEXT8 (insn & 0xff));
2084 }
2085
2086 /* blt label:8 */
2087 void OP_E000 (insn, extension)
2088 unsigned long insn, extension;
2089 {
2090 /* The dispatching code will add 2 after we return, so
2091 we subtract two here to make things right. */
2092 if (((PSW & PSW_NF) != 0) ^ ((PSW & PSW_VF) != 0))
2093 State.regs[REG_PC] = TRUNC (State.regs[REG_PC] + SEXT8 (insn & 0xff));
2094 }
2095
2096 /* bhi label:8 */
2097 void OP_E500 (insn, extension)
2098 unsigned long insn, extension;
2099 {
2100 /* The dispatching code will add 2 after we return, so
2101 we subtract two here to make things right. */
2102 if (!(((PSW & PSW_CF) != 0) || (PSW & PSW_ZF) != 0))
2103 State.regs[REG_PC] = TRUNC (State.regs[REG_PC] + SEXT8 (insn & 0xff));
2104 }
2105
2106 /* bcc label:8 */
2107 void OP_E600 (insn, extension)
2108 unsigned long insn, extension;
2109 {
2110 /* The dispatching code will add 2 after we return, so
2111 we subtract two here to make things right. */
2112 if (!(PSW & PSW_CF))
2113 State.regs[REG_PC] = TRUNC (State.regs[REG_PC] + SEXT8 (insn & 0xff));
2114 }
2115
2116 /* bls label:8 */
2117 void OP_E700 (insn, extension)
2118 unsigned long insn, extension;
2119 {
2120 /* The dispatching code will add 2 after we return, so
2121 we subtract two here to make things right. */
2122 if (((PSW & PSW_CF) != 0) || (PSW & PSW_ZF) != 0)
2123 State.regs[REG_PC] = TRUNC (State.regs[REG_PC] + SEXT8 (insn & 0xff));
2124 }
2125
2126 /* bcs label:8 */
2127 void OP_E400 (insn, extension)
2128 unsigned long insn, extension;
2129 {
2130 /* The dispatching code will add 2 after we return, so
2131 we subtract two here to make things right. */
2132 if (PSW & PSW_CF)
2133 State.regs[REG_PC] = TRUNC (State.regs[REG_PC] + SEXT8 (insn & 0xff));
2134 }
2135
2136 /* bvc label:8 */
2137 void OP_F5FC00 (insn, extension)
2138 unsigned long insn, extension;
2139 {
2140 /* The dispatching code will add 3 after we return, so
2141 we subtract two here to make things right. */
2142 if (!(PSW & PSW_VF))
2143 State.regs[REG_PC] = TRUNC (State.regs[REG_PC] + SEXT8 (insn & 0xff));
2144 }
2145
2146 /* bvs label:8 */
2147 void OP_F5FD00 (insn, extension)
2148 unsigned long insn, extension;
2149 {
2150 /* The dispatching code will add 3 after we return, so
2151 we subtract two here to make things right. */
2152 if (PSW & PSW_VF)
2153 State.regs[REG_PC] = TRUNC (State.regs[REG_PC] + SEXT8 (insn & 0xff));
2154 }
2155
2156 /* bnc label:8 */
2157 void OP_F5FE00 (insn, extension)
2158 unsigned long insn, extension;
2159 {
2160 /* The dispatching code will add 3 after we return, so
2161 we subtract two here to make things right. */
2162 if (!(PSW & PSW_NF))
2163 State.regs[REG_PC] = TRUNC (State.regs[REG_PC] + SEXT8 (insn & 0xff));
2164 }
2165
2166 /* bns label:8 */
2167 void OP_F5FF00 (insn, extension)
2168 unsigned long insn, extension;
2169 {
2170 /* The dispatching code will add 3 after we return, so
2171 we subtract two here to make things right. */
2172 if (PSW & PSW_NF)
2173 State.regs[REG_PC] = TRUNC (State.regs[REG_PC] + SEXT8 (insn & 0xff));
2174 }
2175
2176 /* bra label:8 */
2177 void OP_EA00 (insn, extension)
2178 unsigned long insn, extension;
2179 {
2180 /* The dispatching code will add 2 after we return, so
2181 we subtract two here to make things right. */
2182 State.regs[REG_PC] = TRUNC (State.regs[REG_PC] + SEXT8 (insn & 0xff));
2183 }
2184
2185 /* jmp (an) */
2186 void OP_F000 (insn, extension)
2187 unsigned long insn, extension;
2188 {
2189 State.regs[REG_PC] = TRUNC (State.regs[REG_A0 + REG1 (insn)] - 2);
2190 }
2191
2192 /* jmp label:16 */
2193 void OP_FC0000 (insn, extension)
2194 unsigned long insn, extension;
2195 {
2196 State.regs[REG_PC] = TRUNC (State.regs[REG_PC] + SEXT16 (insn & 0xffff));
2197 }
2198
2199 /* jmp label:24 */
2200 void OP_F4E00000 (insn, extension)
2201 unsigned long insn, extension;
2202 {
2203 State.regs[REG_PC]
2204 = TRUNC (State.regs[REG_PC] + (((insn & 0xffff) << 8) + extension));
2205 }
2206
2207 /* jsr (an) */
2208 void OP_F001 (insn, extension)
2209 unsigned long insn, extension;
2210 {
2211 unsigned int next_pc, sp;
2212
2213 sp = State.regs[REG_SP];
2214 sp -= 4;
2215 State.regs[REG_SP] = sp;
2216 next_pc = State.regs[REG_PC] + 2;
2217 State.mem[sp] = next_pc & 0xff;
2218 State.mem[sp+1] = (next_pc & 0xff00) >> 8;
2219 State.mem[sp+2] = (next_pc & 0xff0000) >> 16;
2220 State.regs[REG_PC] = TRUNC (State.regs[REG_A0 + REG1 (insn)] - 2);
2221 }
2222
2223 /* jsr label:16 */
2224 void OP_FD0000 (insn, extension)
2225 unsigned long insn, extension;
2226 {
2227 unsigned int next_pc, sp;
2228
2229 sp = State.regs[REG_SP];
2230 sp -= 4;
2231 State.regs[REG_SP] = sp;
2232 next_pc = State.regs[REG_PC] + 3;
2233 State.mem[sp] = next_pc & 0xff;
2234 State.mem[sp+1] = (next_pc & 0xff00) >> 8;
2235 State.mem[sp+2] = (next_pc & 0xff0000) >> 16;
2236 State.regs[REG_PC] = TRUNC (State.regs[REG_PC] + SEXT16 (insn & 0xffff));
2237 }
2238
2239 /* jsr label:24 */
2240 void OP_F4E10000 (insn, extension)
2241 unsigned long insn, extension;
2242 {
2243 unsigned int next_pc, sp;
2244
2245 sp = State.regs[REG_SP];
2246 sp -= 4;
2247 State.regs[REG_SP] = sp;
2248 next_pc = State.regs[REG_PC] + 5;
2249 State.mem[sp] = next_pc & 0xff;
2250 State.mem[sp+1] = (next_pc & 0xff00) >> 8;
2251 State.mem[sp+2] = (next_pc & 0xff0000) >> 16;
2252 State.regs[REG_PC]
2253 = TRUNC (State.regs[REG_PC] + (((insn & 0xffff) << 8) + extension));
2254 }
2255
2256 /* rts */
2257 void OP_FE (insn, extension)
2258 unsigned long insn, extension;
2259 {
2260 unsigned int sp;
2261
2262 sp = State.regs[REG_SP];
2263 State.regs[REG_PC] = (State.mem[sp] | (State.mem[sp+1] << 8)
2264 | (State.mem[sp+2] << 16));
2265 State.regs[REG_PC] -= 1;
2266 State.regs[REG_SP] += 4;
2267 }
2268
2269 /* rti */
2270 void OP_EB (insn, extension)
2271 unsigned long insn, extension;
2272 {
2273 PSW = load_half (State.regs[REG_A0 + 3]);
2274 State.regs[REG_PC] = load_3_byte (State.regs[REG_A0 + 3] + 2) - 1;
2275 State.regs[REG_A0 + 3] += 6;
2276 }
2277
2278 /* syscall */
2279 void OP_F010 (insn, extension)
2280 unsigned long insn, extension;
2281 {
2282 /* We use this for simulated system calls; we may need to change
2283 it to a reserved instruction if we conflict with uses at
2284 Matsushita. */
2285 int save_errno = errno;
2286 int offset = 6;
2287 errno = 0;
2288
2289 /* Registers passed to syscall 0 */
2290
2291 /* Function number. */
2292 #define FUNC (State.regs[0])
2293
2294 #define PARM1 (State.regs[1])
2295
2296 /* Parameters. */
2297 #define PARM(x, y) (load_mem (State.regs[REG_SP] + x, y))
2298
2299 /* Registers set by syscall 0 */
2300
2301 #define RETVAL State.regs[0] /* return value */
2302 #define RETERR State.regs[1] /* return error code */
2303
2304 /* Turn a pointer in a register into a pointer into real memory. */
2305
2306 #define MEMPTR(x) (State.mem + (x & 0xffffff))
2307
2308 switch (FUNC)
2309 {
2310 #if !defined(__GO32__) && !defined(_WIN32)
2311 #ifdef TARGET_SYS_fork
2312 case TARGET_SYS_fork:
2313 RETVAL = fork ();
2314 break;
2315 #endif
2316 #ifdef TARGET_SYS_execve
2317 case TARGET_SYS_execve:
2318 RETVAL = execve (MEMPTR (PARM1), (char **) MEMPTR (PARM (4, 4)),
2319 (char **)MEMPTR (PARM (8, 4)));
2320 break;
2321 #endif
2322 #ifdef TARGET_SYS_execv
2323 case TARGET_SYS_execv:
2324 RETVAL = execve (MEMPTR (PARM1), (char **) MEMPTR (PARM (4, 4)), NULL);
2325 break;
2326 #endif
2327 #endif
2328
2329 case TARGET_SYS_read:
2330 RETVAL = mn10200_callback->read (mn10200_callback, PARM1,
2331 MEMPTR (PARM (4, 4)), PARM (8, 4));
2332 break;
2333 case TARGET_SYS_write:
2334 RETVAL = (int)mn10200_callback->write (mn10200_callback, PARM1,
2335 MEMPTR (PARM (4, 4)),
2336 PARM (8, 4));
2337 break;
2338 case TARGET_SYS_lseek:
2339 RETVAL = mn10200_callback->lseek (mn10200_callback, PARM1,
2340 PARM (4, 4), PARM (8, 2));
2341 break;
2342 case TARGET_SYS_close:
2343 RETVAL = mn10200_callback->close (mn10200_callback, PARM1);
2344 break;
2345 case TARGET_SYS_open:
2346 RETVAL = mn10200_callback->open (mn10200_callback, MEMPTR (PARM1),
2347 PARM (4, 2));
2348 break;
2349 case TARGET_SYS_exit:
2350 /* EXIT - caller can look in PARM1 to work out the
2351 reason */
2352 if (PARM1 == 0xdead)
2353 State.exception = SIGABRT;
2354 else
2355 State.exception = SIGQUIT;
2356 State.exited = 1;
2357 break;
2358
2359 case TARGET_SYS_stat: /* added at hmsi */
2360 /* stat system call */
2361 {
2362 struct stat host_stat;
2363 reg_t buf;
2364
2365 RETVAL = stat (MEMPTR (PARM1), &host_stat);
2366
2367 buf = PARM (4, 4);
2368
2369 /* Just wild-assed guesses. */
2370 store_half (buf, host_stat.st_dev);
2371 store_half (buf + 2, host_stat.st_ino);
2372 store_word (buf + 4, host_stat.st_mode);
2373 store_half (buf + 8, host_stat.st_nlink);
2374 store_half (buf + 10, host_stat.st_uid);
2375 store_half (buf + 12, host_stat.st_gid);
2376 store_half (buf + 14, host_stat.st_rdev);
2377 store_word (buf + 16, host_stat.st_size);
2378 store_word (buf + 20, host_stat.st_atime);
2379 store_word (buf + 28, host_stat.st_mtime);
2380 store_word (buf + 36, host_stat.st_ctime);
2381 }
2382 break;
2383
2384 #ifdef TARGET_SYS_chown
2385 case TARGET_SYS_chown:
2386 RETVAL = chown (MEMPTR (PARM1), PARM (4, 2), PARM (6, 2));
2387 break;
2388 #endif
2389 case TARGET_SYS_chmod:
2390 RETVAL = chmod (MEMPTR (PARM1), PARM (4, 2));
2391 break;
2392 #ifdef TARGET_SYS_time
2393 case TARGET_SYS_time:
2394 RETVAL = time ((time_t *)MEMPTR (PARM1));
2395 break;
2396 #endif
2397 #ifdef TARGET_SYS_times
2398 case TARGET_SYS_times:
2399 {
2400 struct tms tms;
2401 RETVAL = times (&tms);
2402 store_word (PARM1, tms.tms_utime);
2403 store_word (PARM1 + 4, tms.tms_stime);
2404 store_word (PARM1 + 8, tms.tms_cutime);
2405 store_word (PARM1 + 12, tms.tms_cstime);
2406 break;
2407 }
2408 #endif
2409 #ifdef TARGET_SYS_gettimeofday
2410 case TARGET_SYS_gettimeofday:
2411 {
2412 struct timeval t;
2413 struct timezone tz;
2414 RETVAL = gettimeofday (&t, &tz);
2415 store_word (PARM1, t.tv_sec);
2416 store_word (PARM1 + 4, t.tv_usec);
2417 store_word (PARM (4, 4), tz.tz_minuteswest);
2418 store_word (PARM (4, 4) + 4, tz.tz_dsttime);
2419 break;
2420 }
2421 #endif
2422 #ifdef TARGET_SYS_utime
2423 case TARGET_SYS_utime:
2424 /* Cast the second argument to void *, to avoid type mismatch
2425 if a prototype is present. */
2426 RETVAL = utime (MEMPTR (PARM1), (void *) MEMPTR (PARM (4, 4)));
2427 break;
2428 #endif
2429 default:
2430 abort ();
2431 }
2432 RETERR = errno;
2433 errno = save_errno;
2434 }
2435
2436 /* nop */
2437 void OP_F6 (insn, extension)
2438 unsigned long insn, extension;
2439 {
2440 }
2441
2442 /* breakpoint */
2443 void
2444 OP_FF (insn, extension)
2445 unsigned long insn, extension;
2446 {
2447 State.exception = SIGTRAP;
2448 PC -= 1;
2449 }
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