sim/mn10300/am33-2.igen

   1 // data cache pre-fetch:
   2
   3 // 1111 1001 1010 0110 Rm.. 0000; dcpf (Rm)
   4 8.0xf9+8.0xa6+4.RN2,4.0000:D1a:::dcpf
   5 "dcpf"
   6 *am33_2
   7 {
   8   int srcreg;
   9
  10   PC = cia;
  11
  12   srcreg = translate_rreg (SD_, RN2);
  13   load_word (State.regs[srcreg]);
  14 }
  15
  16 // 1111 1001 1010 0111 0000 0000; dcpf (sp)
  17 8.0xf9+8.0xa7+8.0x00:D1b:::dcpf
  18 "dcpf"
  19 *am33_2
  20 {
  21   PC = cia;
  22
  23   load_word (SP);
  24 }
  25
  26 // 1111 1011 1010 0110 Ri.. Rm.. 0000 0000; dcpf (Ri,Rm)
  27 8.0xfb+8.0xa6+4.RN2,4.RN0+8.0x00:D2a:::dcpf
  28 "dcpf"
  29 *am33_2
  30 {
  31   int srci, srcm;
  32
  33   PC = cia;
  34
  35   srci = translate_rreg (SD_, RN2);
  36   srcm = translate_rreg (SD_, RN0);
  37
  38   load_word (State.regs[srci] + State.regs[srcm]);
  39 }
  40
  41 // 1111 1011 1010 0111 Rm.. 0000 IMM8; dcpf (d8,Rm)
  42 8.0xfb+8.0xa7+4.RN2,4.0000+8.IMM8:D2b:::dcpf
  43 "dcpf"
  44 *am33_2
  45 {
  46   int srcreg;
  47
  48   PC = cia;
  49
  50   srcreg = translate_rreg (SD_, RN2);
  51
  52   load_word (State.regs[srcreg] + EXTEND8 (IMM8));
  53 }
  54
  55 // 1111 1101 1010 0111 Rm.. 0000 IMM24; dcpf (d24,Rm)
  56 8.0xfd+8.0xa7+4.RN2,4.0000+8.IMM24A+8.IMM24B+8.IMM24C:D4a:::dcpf
  57 "dcpf"
  58 *am33_2
  59 {
  60   int srcreg;
  61
  62   PC = cia;
  63
  64   srcreg = translate_rreg (SD_, RN2);
  65
  66   load_word (State.regs[srcreg] + EXTEND24 (FETCH24 (IMM24A,
  67                                                      IMM24B, IMM24C)));
  68 }
  69
  70 // 1111 1110 0100 0110 Rm.. 0000 IMM32; dcpf (d32,Rm)
  71 8.0xfe+8.0x46+4.RN2,4.0000+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5a:::dcpf
  72 "dcpf"
  73 *am33_2
  74 {
  75   int srcreg;
  76
  77   PC = cia;
  78
  79   srcreg = translate_rreg (SD_, RN2);
  80
  81   load_word (State.regs[srcreg]
  82              + FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
  83 }
  84
  85 // bit operations with imm8,(abs16) addressing mode:
  86
  87 // 1111 1110 1000 0010 ABS16 IMM8; btst imm8,(abs16)
  88 8.0xfe+8.0x82+8.IMM16A+8.IMM16B+8.IMM8:D3:::btst
  89 "btst"
  90 *am33_2
  91 {
  92   PC = cia;
  93   genericBtst (IMM8, FETCH16 (IMM16A, IMM16B));
  94 }
  95
  96 // 1111 1110 1000 0000 ABS16 IMM8; bset imm8,(abs16)
  97 8.0xfe+8.0x80+8.IMM16A+8.IMM16B+8.IMM8:D3:::bset
  98 "bset"
  99 *am33_2
 100 {
 101   uint32_t temp;
 102   int z;
 103
 104   PC = cia;
 105   temp = load_byte (FETCH16 (IMM16A, IMM16B));
 106   z = (temp & IMM8) == 0;
 107   temp |= IMM8;
 108   store_byte (FETCH16 (IMM16A, IMM16B), temp);
 109   PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
 110   PSW |= (z ? PSW_Z : 0);
 111 }
 112
 113 // 1111 1110 1000 0001 ABS16 IMM8; bclr imm8,(abs16)
 114 8.0xfe+8.0x81+8.IMM16A+8.IMM16B+8.IMM8:D3:::bclr
 115 "bclr"
 116 *am33_2
 117 {
 118   uint32_t temp;
 119   int z;
 120
 121   PC = cia;
 122   temp = load_byte (FETCH16 (IMM16A, IMM16B));
 123   z = (temp & IMM8) == 0;
 124   temp = temp & ~(IMM8);
 125   store_byte (FETCH16 (IMM16A, IMM16B), temp);
 126   PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
 127   PSW |= (z ? PSW_Z : 0);
 128 }
 129
 130 // single precision fmov:
 131
 132 // 1111 1001 0010 000X Rm.. Sn..; fmov (Rm),FSn
 133 8.0xf9+4.2,3.0,1.X+4.Rm,4.Sn:D1a:::fmov
 134 "fmov"
 135 *am33_2
 136 {
 137   PC = cia;
 138
 139   if (FPU_DISABLED)
 140     fpu_disabled_exception (SD, CPU, cia);
 141   else
 142     {
 143       int reg = translate_rreg (SD_, Rm);
 144       XS2FS (X,Sn) = load_word (State.regs[reg]);
 145     }
 146 }
 147
 148 // 1111 1001 0010 001X Rm.. Sn..; fmov (Rm+),FSn
 149 8.0xf9+4.2,3.1,1.X+4.Rm,4.Sn:D1b:::fmov
 150 "fmov"
 151 *am33_2
 152 {
 153   PC = cia;
 154
 155   if (FPU_DISABLED)
 156     fpu_disabled_exception (SD, CPU, cia);
 157   else
 158     {
 159       int reg = translate_rreg (SD_, Rm);
 160       XS2FS (X,Sn) = load_word (State.regs[reg]);
 161       State.regs[reg] += 4;
 162     }
 163 }
 164
 165 // 1111 1001 0010 010X ---- Sn..; fmov (SP),FSn
 166 8.0xf9+4.2,3.2,1.X+4.0,4.Sn:D1c:::fmov
 167 "fmov"
 168 *am33_2
 169 {
 170   PC = cia;
 171
 172   if (FPU_DISABLED)
 173     fpu_disabled_exception (SD, CPU, cia);
 174   else
 175     {
 176       int reg = REG_SP;
 177       XS2FS (X,Sn) = load_word (State.regs[reg]);
 178     }
 179 }
 180
 181 // 1111 1001 0010 011X Rm.. Sn..; fmov Rm,FSn
 182 8.0xf9+4.2,3.3,1.X+4.Rm,4.Sn:D1d:::fmov
 183 "fmov"
 184 *am33_2
 185 {
 186   PC = cia;
 187
 188   if (FPU_DISABLED)
 189     fpu_disabled_exception (SD, CPU, cia);
 190   else
 191     {
 192       int reg = translate_rreg (SD_, Rm);
 193       XS2FS (X,Sn) = State.regs[reg];
 194     }
 195 }
 196
 197 // 1111 1001 0011 00Y0 Sm.. Rn..; fmov FSm,(Rn)
 198 8.0xf9+4.3,2.0,1.Y,1.0+4.Sm,4.Rn:D1e:::fmov
 199 "fmov"
 200 *am33_2
 201 {
 202   PC = cia;
 203
 204   if (FPU_DISABLED)
 205     fpu_disabled_exception (SD, CPU, cia);
 206   else
 207     {
 208       int reg = translate_rreg (SD_, Rn);
 209       store_word (State.regs[reg], XS2FS (Y,Sm));
 210     }
 211 }
 212
 213 // 1111 1001 0011 00Y1 Sm.. Rn..; fmov FSm,(Rn+)
 214 8.0xf9+4.3,2.0,1.Y,1.1+4.Sm,4.Rn:D1f:::fmov
 215 "fmov"
 216 *am33_2
 217 {
 218   PC = cia;
 219
 220   if (FPU_DISABLED)
 221     fpu_disabled_exception (SD, CPU, cia);
 222   else
 223     {
 224       int reg = translate_rreg (SD_, Rn);
 225       store_word (State.regs[reg], XS2FS (Y,Sm));
 226       State.regs[reg] += 4;
 227     }
 228 }
 229
 230 // 1111 1001 0011 01Y0 Sm.. ----; fmov FSm,(SP)
 231 8.0xf9+4.3,2.1,1.Y,1.0+4.Sm,4.0:D1g:::fmov
 232 "fmov"
 233 *am33_2
 234 {
 235   PC = cia;
 236
 237   if (FPU_DISABLED)
 238     fpu_disabled_exception (SD, CPU, cia);
 239   else
 240     {
 241       int reg = REG_SP;
 242       store_word (State.regs[reg], XS2FS (Y,Sm));
 243     }
 244 }
 245
 246 // 1111 1001 0011 01Y1 Sm.. Rn..; fmov FSm,Rn
 247 8.0xf9+4.3,2.1,1.Y,1.1+4.Sm,4.Rn:D1h:::fmov
 248 "fmov"
 249 *am33_2
 250 {
 251   PC = cia;
 252
 253   if (FPU_DISABLED)
 254     fpu_disabled_exception (SD, CPU, cia);
 255   else
 256     {
 257       int reg = translate_rreg (SD_, Rn);
 258       State.regs[reg] = XS2FS (Y,Sm);
 259     }
 260 }
 261
 262 // 1111 1001 0100 00YX Sm.. Sn..; fmov FSm,FSn
 263 8.0xf9+4.4,2.0,1.Y,1.X+4.Sm,4.Sn:D1i:::fmov
 264 "fmov"
 265 *am33_2
 266 {
 267   PC = cia;
 268
 269   if (FPU_DISABLED)
 270     fpu_disabled_exception (SD, CPU, cia);
 271   else
 272     XS2FS (X,Sn) = XS2FS (Y,Sm);
 273 }
 274
 275 // 1111 1011 0010 000X Rm.. Sn.. d8; fmov (d8,Rm),FSn
 276 8.0xfb+4.2,3.0,1.X+4.Rm,4.Sn+8.IMM8:D2a:::fmov
 277 "fmov"
 278 *am33_2
 279 {
 280   PC = cia;
 281
 282   if (FPU_DISABLED)
 283     fpu_disabled_exception (SD, CPU, cia);
 284   else
 285     {
 286       int reg = translate_rreg (SD_, Rm);
 287       XS2FS (X, Sn) = load_word (State.regs[reg] + EXTEND8 (IMM8));
 288     }
 289 }
 290
 291 // 1111 1011 0010 001X Rm.. Sn.. d8; fmov (Rm+,imm8),FSn
 292 8.0xfb+4.2,3.1,1.X+4.Rm,4.Sn+8.IMM8:D2b:::fmov
 293 "fmov"
 294 *am33_2
 295 {
 296   PC = cia;
 297
 298   if (FPU_DISABLED)
 299     fpu_disabled_exception (SD, CPU, cia);
 300   else
 301     {
 302       int reg = translate_rreg (SD_, Rm);
 303       XS2FS (X, Sn) = load_word (State.regs[reg] + EXTEND8 (IMM8));
 304       State.regs[reg] += 4;
 305     }
 306 }
 307
 308 // 1111 1011 0010 010X ---- Sn.. d8; fmov (d8,SP),FSn
 309 8.0xfb+4.2,3.2,1.X+4.0,4.Sn+8.IMM8:D2c:::fmov
 310 "fmov"
 311 *am33_2
 312 {
 313   PC = cia;
 314
 315   if (FPU_DISABLED)
 316     fpu_disabled_exception (SD, CPU, cia);
 317   else
 318     {
 319       int reg = REG_SP;
 320       XS2FS (X, Sn) = load_word (State.regs[reg] + IMM8);
 321     }
 322 }
 323
 324 // 1111 1011 0010 0111 Ri.. Rm.. Sn.. --Z-; fmov (Ri,Rm),FSn
 325 8.0xfb+8.0x27+4.Ri,4.Rm+4.Sn,2.0,1.Z,1.0:D2d:::fmov
 326 "fmov"
 327 *am33_2
 328 {
 329   PC = cia;
 330
 331   if (FPU_DISABLED)
 332     fpu_disabled_exception (SD, CPU, cia);
 333   else
 334     {
 335       int ri = translate_rreg (SD_, Ri);
 336       int rm = translate_rreg (SD_, Rm);
 337       XS2FS (Z, Sn) = load_word (State.regs[ri] + State.regs[rm]);
 338     }
 339 }
 340
 341 // 1111 1011 0011 00Y0 Sm.. Rn.. d8; fmov FSm,(d8,Rn)
 342 8.0xfb+4.3,2.0,1.Y,1.0+4.Sm,4.Rn+8.IMM8:D2e:::fmov
 343 "fmov"
 344 *am33_2
 345 {
 346   PC = cia;
 347
 348   if (FPU_DISABLED)
 349     fpu_disabled_exception (SD, CPU, cia);
 350   else
 351     {
 352       int reg = translate_rreg (SD_, Rn);
 353       store_word (State.regs[reg] + EXTEND8 (IMM8), XS2FS (Y, Sm));
 354     }
 355 }
 356
 357 // 1111 1011 0011 00Y1 Sm.. Rn.. d8; fmov FSm,(Rn+,d8)
 358 8.0xfb+4.3,2.0,1.Y,1.1+4.Sm,4.Rn+8.IMM8:D2f:::fmov
 359 "fmov"
 360 *am33_2
 361 {
 362   PC = cia;
 363
 364   if (FPU_DISABLED)
 365     fpu_disabled_exception (SD, CPU, cia);
 366   else
 367     {
 368       int reg = translate_rreg (SD_, Rn);
 369       store_word (State.regs[reg] + EXTEND8 (IMM8), XS2FS (Y, Sm));
 370       State.regs[reg] += 4;
 371     }
 372 }
 373
 374 // 1111 1011 0011 01Y0 Sm.. ---- d8; fmov FSm,(d8,SP)
 375 8.0xfb+4.3,2.1,1.Y,1.0+4.Sm,4.0+8.IMM8:D2g:::fmov
 376 "fmov"
 377 *am33_2
 378 {
 379   PC = cia;
 380
 381   if (FPU_DISABLED)
 382     fpu_disabled_exception (SD, CPU, cia);
 383   else
 384     {
 385       int reg = REG_SP;
 386       store_word (State.regs[reg] + IMM8, XS2FS (Y, Sm));
 387     }
 388 }
 389
 390 // 1111 1011 0011 0111 Ri.. Rm.. Sm.. --Z-; fmov FSm,(Ri,Rm)
 391 8.0xfb+8.0x37+4.Ri,4.Rm+4.Sm,2.0,1.Z,1.0:D2h:::fmov
 392 "fmov"
 393 *am33_2
 394 {
 395   PC = cia;
 396
 397   if (FPU_DISABLED)
 398     fpu_disabled_exception (SD, CPU, cia);
 399   else
 400     {
 401       int ri = translate_rreg (SD_, Ri);
 402       int rm = translate_rreg (SD_, Rm);
 403       store_word (State.regs[ri] + State.regs[rm], XS2FS (Z, Sm));
 404     }
 405 }
 406
 407 // 1111 1101 0010 000X Rm.. Sn.. d24; fmov (d24,Rm),FSn
 408 8.0xfd+4.2,3.0,1.X+4.Rm,4.Sn+8.IMM24A+8.IMM24B+8.IMM24C:D4a:::fmov
 409 "fmov"
 410 *am33_2
 411 {
 412   PC = cia;
 413
 414   if (FPU_DISABLED)
 415     fpu_disabled_exception (SD, CPU, cia);
 416   else
 417     {
 418       int reg = translate_rreg (SD_, Rm);
 419       XS2FS (X, Sn) = load_word (State.regs[reg]
 420                                  + EXTEND24 (FETCH24 (IMM24A,
 421                                                       IMM24B, IMM24C)));
 422     }
 423 }
 424
 425 // 1111 1101 0010 001X Rm.. Sn.. d24; fmov (Rm+,imm24),FSn
 426 8.0xfd+4.2,3.1,1.X+4.Rm,4.Sn+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::fmov
 427 "fmov"
 428 *am33_2
 429 {
 430   PC = cia;
 431
 432   if (FPU_DISABLED)
 433     fpu_disabled_exception (SD, CPU, cia);
 434   else
 435     {
 436       int reg = translate_rreg (SD_, Rm);
 437       XS2FS (X, Sn) = load_word (State.regs[reg]
 438                                  + EXTEND24 (FETCH24 (IMM24A,
 439                                                       IMM24B, IMM24C)));
 440       State.regs[reg] += 4;
 441     }
 442 }
 443
 444 // 1111 1101 0010 010X ---- Sn.. d24; fmov (d24,SP),FSn
 445 8.0xfd+4.2,3.2,1.X+4.0,4.Sn+8.IMM24A+8.IMM24B+8.IMM24C:D4c:::fmov
 446 "fmov"
 447 *am33_2
 448 {
 449   PC = cia;
 450
 451   if (FPU_DISABLED)
 452     fpu_disabled_exception (SD, CPU, cia);
 453   else
 454     {
 455       int reg = REG_SP;
 456       XS2FS (X, Sn) = load_word (State.regs[reg] + FETCH24 (IMM24A,
 457                                                             IMM24B, IMM24C));
 458     }
 459 }
 460
 461 // 1111 1101 0011 00Y0 Sm.. Rn.. d24; fmov FSm,(d24,Rn)
 462 8.0xfd+4.3,2.0,1.Y,1.0+4.Sm,4.Rn+8.IMM24A+8.IMM24B+8.IMM24C:D4e:::fmov
 463 "fmov"
 464 *am33_2
 465 {
 466   PC = cia;
 467
 468   if (FPU_DISABLED)
 469     fpu_disabled_exception (SD, CPU, cia);
 470   else
 471     {
 472       int reg = translate_rreg (SD_, Rn);
 473       store_word (State.regs[reg]
 474                   + EXTEND24 (FETCH24 (IMM24A,
 475                                        IMM24B, IMM24C)), XS2FS (Y, Sm));
 476     }
 477 }
 478
 479 // 1111 1101 0011 00Y1 Sm.. Rn.. d24; fmov FSm,(Rn+,d24)
 480 8.0xfd+4.3,2.0,1.Y,1.1+4.Sm,4.Rn+8.IMM24A+8.IMM24B+8.IMM24C:D4f:::fmov
 481 "fmov"
 482 *am33_2
 483 {
 484   PC = cia;
 485
 486   if (FPU_DISABLED)
 487     fpu_disabled_exception (SD, CPU, cia);
 488   else
 489     {
 490       int reg = translate_rreg (SD_, Rn);
 491       store_word (State.regs[reg]
 492                   + EXTEND24 (FETCH24 (IMM24A,
 493                                        IMM24B, IMM24C)), XS2FS (Y, Sm));
 494       State.regs[reg] += 4;
 495     }
 496 }
 497
 498 // 1111 1101 0011 01Y0 Sm.. ---- d24; fmov FSm,(d24,SP)
 499 8.0xfd+4.3,2.1,1.Y,1.0+4.Sm,4.0+8.IMM24A+8.IMM24B+8.IMM24C:D4g:::fmov
 500 "fmov"
 501 *am33_2
 502 {
 503   PC = cia;
 504
 505   if (FPU_DISABLED)
 506     fpu_disabled_exception (SD, CPU, cia);
 507   else
 508     {
 509       int reg = REG_SP;
 510       store_word (State.regs[reg]
 511                   + FETCH24 (IMM24A,
 512                              IMM24B, IMM24C), XS2FS (Y, Sm));
 513     }
 514 }
 515
 516 // 1111 1110 0010 000X Rm.. Sn.. d32; fmov (d32,Rm),FSn
 517 8.0xfe+4.2,3.0,1.X+4.Rm,4.Sn+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5a:::fmov
 518 "fmov"
 519 *am33_2
 520 {
 521   PC = cia;
 522
 523   if (FPU_DISABLED)
 524     fpu_disabled_exception (SD, CPU, cia);
 525   else
 526     {
 527       int reg = translate_rreg (SD_, Rm);
 528       XS2FS (X, Sn) = load_word (State.regs[reg]
 529                                  + EXTEND32 (FETCH32 (IMM32A, IMM32B,
 530                                                       IMM32C, IMM32D)));
 531     }
 532 }
 533
 534 // 1111 1110 0010 001X Rm.. Sn.. d32; fmov (Rm+,imm32),FSn
 535 8.0xfe+4.2,3.1,1.X+4.Rm,4.Sn+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5b:::fmov
 536 "fmov"
 537 *am33_2
 538 {
 539   PC = cia;
 540
 541   if (FPU_DISABLED)
 542     fpu_disabled_exception (SD, CPU, cia);
 543   else
 544     {
 545       int reg = translate_rreg (SD_, Rm);
 546       XS2FS (X, Sn) = load_word (State.regs[reg]
 547                                  + EXTEND32 (FETCH32 (IMM32A, IMM32B,
 548                                                       IMM32C, IMM32D)));
 549       State.regs[reg] += 4;
 550     }
 551 }
 552
 553 // 1111 1110 0010 010X ---- Sn.. d32; fmov (d32,SP),FSn
 554 8.0xfe+4.2,3.2,1.X+4.0,4.Sn+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5c:::fmov
 555 "fmov"
 556 *am33_2
 557 {
 558   PC = cia;
 559
 560   if (FPU_DISABLED)
 561     fpu_disabled_exception (SD, CPU, cia);
 562   else
 563     {
 564       int reg = REG_SP;
 565       XS2FS (X, Sn) = load_word (State.regs[reg]
 566                                  + FETCH32 (IMM32A, IMM32B,
 567                                             IMM32C, IMM32D));
 568     }
 569 }
 570
 571 // 1111 1110 0010 011X ---- Sn.. d32; fmov imm32,FSn
 572 8.0xfe+4.2,3.3,1.X+4.0,4.Sn+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5d:::fmov
 573 "fmov"
 574 *am33_2
 575 {
 576   PC = cia;
 577
 578   if (FPU_DISABLED)
 579     fpu_disabled_exception (SD, CPU, cia);
 580   else
 581     XS2FS (X, Sn) = FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D);
 582 }
 583
 584 // 1111 1110 0011 00Y0 Sm.. Rn.. d32; fmov FSm,(d32,Rn)
 585 8.0xfe+4.3,2.0,1.Y,1.0+4.Sm,4.Rn+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5e:::fmov
 586 "fmov"
 587 *am33_2
 588 {
 589   PC = cia;
 590
 591   if (FPU_DISABLED)
 592     fpu_disabled_exception (SD, CPU, cia);
 593   else
 594     {
 595       int reg = translate_rreg (SD_, Rn);
 596       store_word (State.regs[reg]
 597                   + EXTEND32 (FETCH32 (IMM32A, IMM32B,
 598                                        IMM32C, IMM32D)), XS2FS (Y, Sm));
 599     }
 600 }
 601
 602 // 1111 1110 0011 00Y1 Sm.. Rn.. d32; fmov FSm,(Rn+,d32)
 603 8.0xfe+4.3,2.0,1.Y,1.1+4.Sm,4.Rn+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5f:::fmov
 604 "fmov"
 605 *am33_2
 606 {
 607   PC = cia;
 608
 609   if (FPU_DISABLED)
 610     fpu_disabled_exception (SD, CPU, cia);
 611   else
 612     {
 613       int reg = translate_rreg (SD_, Rn);
 614       store_word (State.regs[reg]
 615                   + EXTEND32 (FETCH32 (IMM32A, IMM32B,
 616                                        IMM32C, IMM32D)), XS2FS (Y, Sm));
 617       State.regs[reg] += 4;
 618     }
 619 }
 620
 621 // 1111 1110 0011 01Y0 Sm.. ---- d32; fmov FSm,(d32,SP)
 622 8.0xfe+4.3,2.1,1.Y,1.0+4.Sm,4.0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5g:::fmov
 623 "fmov"
 624 *am33_2
 625 {
 626   PC = cia;
 627
 628   if (FPU_DISABLED)
 629     fpu_disabled_exception (SD, CPU, cia);
 630   else
 631     {
 632       int reg = REG_SP;
 633       store_word (State.regs[reg]
 634                   + FETCH32 (IMM32A, IMM32B,
 635                              IMM32C, IMM32D), XS2FS (Y, Sm));
 636     }
 637 }
 638
 639 // double precision fmov:
 640
 641 // 1111 1001 1010 000X Rm.. fn.-; fmov (Rm),FDn
 642 8.0xf9+4.0xa,3.0,1.X+4.Rm,3.fn,1.0:D1j:::fmov
 643 "fmov"
 644 *am33_2
 645 {
 646   PC = cia;
 647
 648   if (FPU_DISABLED)
 649     fpu_disabled_exception (SD, CPU, cia);
 650   else
 651     {
 652       int reg = translate_rreg (SD_, Rm);
 653       Xf2FD (X,fn) = load_dword (State.regs[reg]);
 654     }
 655 }
 656
 657 // 1111 1001 1010 001X Rm.. fn.-; fmov (Rm+),FDn
 658 8.0xf9+4.0xa,3.1,1.X+4.Rm,3.fn,1.0:D1k:::fmov
 659 "fmov"
 660 *am33_2
 661 {
 662   PC = cia;
 663
 664   if (FPU_DISABLED)
 665     fpu_disabled_exception (SD, CPU, cia);
 666   else
 667     {
 668       int reg = translate_rreg (SD_, Rm);
 669       Xf2FD (X,fn) = load_dword (State.regs[reg]);
 670       State.regs[reg] += 8;
 671     }
 672 }
 673
 674 // 1111 1001 1010 010X ---- fn.-; fmov (SP),FDn
 675 8.0xf9+4.0xa,3.2,1.X+4.0,3.fn,1.0:D1l:::fmov
 676 "fmov"
 677 *am33_2
 678 {
 679   PC = cia;
 680
 681   if (FPU_DISABLED)
 682     fpu_disabled_exception (SD, CPU, cia);
 683   else
 684     {
 685       int reg = REG_SP;
 686       Xf2FD (X,fn) = load_dword (State.regs[reg]);
 687     }
 688 }
 689
 690 // 1111 1001 1011 00Y0 fm.- Rn..; fmov FDm,(Rn)
 691 8.0xf9+4.0xb,2.0,1.Y,1.0+3.fm,1.0,4.Rn:D1m:::fmov
 692 "fmov"
 693 *am33_2
 694 {
 695   PC = cia;
 696
 697   if (FPU_DISABLED)
 698     fpu_disabled_exception (SD, CPU, cia);
 699   else
 700     {
 701       int reg = translate_rreg (SD_, Rn);
 702       store_dword (State.regs[reg], Xf2FD (Y,fm));
 703     }
 704 }
 705
 706 // 1111 1001 1011 00Y1 fm.- Rn..; fmov FDm,(Rn+)
 707 8.0xf9+4.0xb,2.0,1.Y,1.1+3.fm,1.0,4.Rn:D1n:::fmov
 708 "fmov"
 709 *am33_2
 710 {
 711   PC = cia;
 712
 713   if (FPU_DISABLED)
 714     fpu_disabled_exception (SD, CPU, cia);
 715   else
 716     {
 717       int reg = translate_rreg (SD_, Rn);
 718       store_dword (State.regs[reg], Xf2FD (Y,fm));
 719       State.regs[reg] += 8;
 720     }
 721 }
 722
 723 // 1111 1001 1011 01Y0 fm.- ----; fmov FDm,(SP)
 724 8.0xf9+4.0xb,2.1,1.Y,1.0+3.fm,1.0,4.0:D1o:::fmov
 725 "fmov"
 726 *am33_2
 727 {
 728   PC = cia;
 729
 730   if (FPU_DISABLED)
 731     fpu_disabled_exception (SD, CPU, cia);
 732   else
 733     {
 734       int reg = REG_SP;
 735       store_dword (State.regs[reg], Xf2FD (Y,fm));
 736     }
 737 }
 738
 739 // 1111 1001 1100 00YX fm.- fn.-; fmov FDm,FDn
 740 8.0xf9+4.0xc,2.0,1.Y,1.X+3.fm,1.0,3.fn,1.0:D1p:::fmov
 741 "fmov"
 742 *am33_2
 743 {
 744   PC = cia;
 745
 746   if (FPU_DISABLED)
 747     fpu_disabled_exception (SD, CPU, cia);
 748   else
 749     fpu_unimp_exception (SD, CPU, cia);
 750 }
 751
 752 // 1111 1011 0100 0111 Ri.. Rm.. fn.- --Z-; fmov (Ri,Rm),FDn
 753 8.0xfb+8.0x47+4.Ri,4.Rm+3.fn,1.0,2.0,1.Z,1.0:D2i:::fmov
 754 "fmov"
 755 *am33_2
 756 {
 757   PC = cia;
 758
 759   if (FPU_DISABLED)
 760     fpu_disabled_exception (SD, CPU, cia);
 761   else
 762     {
 763       int ri = translate_rreg (SD_, Ri);
 764       int rm = translate_rreg (SD_, Rm);
 765       Xf2FD (Z,fn) = load_dword (State.regs[ri] + State.regs[rm]);
 766     }
 767 }
 768
 769 // 1111 1011 0101 0111 Ri.. Rn.. fm.- --Z-; fmov FDm,(Ri,Rn)
 770 8.0xfb+8.0x57+4.Ri,4.Rn+3.fm,1.0,2.0,1.Z,1.0:D2j:::fmov
 771 "fmov"
 772 *am33_2
 773 {
 774   PC = cia;
 775
 776   if (FPU_DISABLED)
 777     fpu_disabled_exception (SD, CPU, cia);
 778   else
 779     {
 780       int ri = translate_rreg (SD_, Ri);
 781       int rn = translate_rreg (SD_, Rn);
 782       store_dword (State.regs[ri] + State.regs[rn], Xf2FD (Z,fm));
 783     }
 784 }
 785
 786 // 1111 1011 1010 000X Rm.. fn.- d8; fmov (d8,Rm),FDn
 787 8.0xfb+4.0xa,3.0,1.X+4.Rm,4.fn+8.IMM8:D2k:::fmov
 788 "fmov"
 789 *am33_2
 790 {
 791   PC = cia;
 792
 793   if (FPU_DISABLED)
 794     fpu_disabled_exception (SD, CPU, cia);
 795   else
 796     {
 797       int reg = translate_rreg (SD_, Rm);
 798       Xf2FD (X, fn) = load_dword (State.regs[reg] + EXTEND8 (IMM8));
 799     }
 800 }
 801
 802 // 1111 1011 1010 001X Rm.. fn.- d8; fmov (Rm+,imm8),FDn
 803 8.0xfb+4.0xa,3.1,1.X+4.Rm,4.fn+8.IMM8:D2l:::fmov
 804 "fmov"
 805 *am33_2
 806 {
 807   PC = cia;
 808
 809   if (FPU_DISABLED)
 810     fpu_disabled_exception (SD, CPU, cia);
 811   else
 812     {
 813       int reg = translate_rreg (SD_, Rm);
 814       Xf2FD (X, fn) = load_dword (State.regs[reg] + EXTEND8 (IMM8));
 815       State.regs[reg] += 8;
 816     }
 817 }
 818
 819 // 1111 1011 1010 010X ---- fn.- d8; fmov (d8,SP),FDn
 820 8.0xfb+4.0xa,3.2,1.X+4.0,4.fn+8.IMM8:D2m:::fmov
 821 "fmov"
 822 *am33_2
 823 {
 824   PC = cia;
 825
 826   if (FPU_DISABLED)
 827     fpu_disabled_exception (SD, CPU, cia);
 828   else
 829     {
 830       int reg = REG_SP;
 831       Xf2FD (X, fn) = load_dword (State.regs[reg] + IMM8);
 832     }
 833 }
 834
 835 // 1111 1011 1011 00Y0 fm.- Rn.. d8; fmov FDm,(d8,Rn)
 836 8.0xfb+4.0xb,2.0,1.Y,1.0+4.fm,4.Rn+8.IMM8:D2n:::fmov
 837 "fmov"
 838 *am33_2
 839 {
 840   PC = cia;
 841
 842   if (FPU_DISABLED)
 843     fpu_disabled_exception (SD, CPU, cia);
 844   else
 845     {
 846       int reg = translate_rreg (SD_, Rn);
 847       store_dword (State.regs[reg] + EXTEND8 (IMM8), Xf2FD (Y, fm));
 848     }
 849 }
 850
 851 // 1111 1011 1011 00Y1 fm.- Rn.. d8; fmov FDm,(Rn+,d8)
 852 8.0xfb+4.0xb,2.0,1.Y,1.1+4.fm,4.Rn+8.IMM8:D2o:::fmov
 853 "fmov"
 854 *am33_2
 855 {
 856   PC = cia;
 857
 858   if (FPU_DISABLED)
 859     fpu_disabled_exception (SD, CPU, cia);
 860   else
 861     {
 862       int reg = translate_rreg (SD_, Rn);
 863       store_dword (State.regs[reg] + EXTEND8 (IMM8), Xf2FD (Y, fm));
 864       State.regs[reg] += 8;
 865     }
 866 }
 867
 868 // 1111 1011 1011 01Y0 fm.- ---- d8; fmov FDm,(d8,SP)
 869 8.0xfb+4.0xb,2.1,1.Y,1.0+4.fm,4.0+8.IMM8:D2p:::fmov
 870 "fmov"
 871 *am33_2
 872 {
 873   PC = cia;
 874
 875   if (FPU_DISABLED)
 876     fpu_disabled_exception (SD, CPU, cia);
 877   else
 878     {
 879       int reg = REG_SP;
 880       store_dword (State.regs[reg] + IMM8, Xf2FD (Y, fm));
 881     }
 882 }
 883
 884 // 1111 1101 1010 000X Rm.. fn.- d24; fmov (d24,Rm),FDn
 885 8.0xfd+4.0xa,3.0,1.X+4.Rm,4.fn+8.IMM24A+8.IMM24B+8.IMM24C:D4k:::fmov
 886 "fmov"
 887 *am33_2
 888 {
 889   PC = cia;
 890
 891   if (FPU_DISABLED)
 892     fpu_disabled_exception (SD, CPU, cia);
 893   else
 894     {
 895       int reg = translate_rreg (SD_, Rm);
 896       Xf2FD (X, fn) = load_dword (State.regs[reg]
 897                                   + EXTEND24 (FETCH24 (IMM24A,
 898                                                        IMM24B, IMM24C)));
 899     }
 900 }
 901
 902 // 1111 1101 1010 001X Rm.. fn.- d24; fmov (Rm+,imm24),FDn
 903 8.0xfd+4.0xa,3.1,1.X+4.Rm,4.fn+8.IMM24A+8.IMM24B+8.IMM24C:D4l:::fmov
 904 "fmov"
 905 *am33_2
 906 {
 907   PC = cia;
 908
 909   if (FPU_DISABLED)
 910     fpu_disabled_exception (SD, CPU, cia);
 911   else
 912     {
 913       int reg = translate_rreg (SD_, Rm);
 914       Xf2FD (X, fn) = load_dword (State.regs[reg]
 915                                   + EXTEND24 (FETCH24 (IMM24A,
 916                                                        IMM24B, IMM24C)));
 917       State.regs[reg] += 8;
 918     }
 919 }
 920
 921 // 1111 1101 1010 010X ---- fn.- d24; fmov (d24,SP),FDn
 922 8.0xfd+4.0xa,3.2,1.X+4.0,4.fn+8.IMM24A+8.IMM24B+8.IMM24C:D4m:::fmov
 923 "fmov"
 924 *am33_2
 925 {
 926   PC = cia;
 927
 928   if (FPU_DISABLED)
 929     fpu_disabled_exception (SD, CPU, cia);
 930   else
 931     {
 932       int reg = REG_SP;
 933       Xf2FD (X, fn) = load_dword (State.regs[reg]
 934                                   + FETCH24 (IMM24A,
 935                                              IMM24B, IMM24C));
 936     }
 937 }
 938
 939 // 1111 1101 1011 00Y0 fm.- Rn.. d24; fmov FDm,(d24,Rn)
 940 8.0xfd+4.0xb,2.0,1.Y,1.0+4.fm,4.Rn+8.IMM24A+8.IMM24B+8.IMM24C:D4n:::fmov
 941 "fmov"
 942 *am33_2
 943 {
 944   PC = cia;
 945
 946   if (FPU_DISABLED)
 947     fpu_disabled_exception (SD, CPU, cia);
 948   else
 949     {
 950       int reg = translate_rreg (SD_, Rn);
 951       store_dword (State.regs[reg]
 952                    + EXTEND24 (FETCH24 (IMM24A,
 953                                         IMM24B, IMM24C)), Xf2FD (Y, fm));
 954     }
 955 }
 956
 957 // 1111 1101 1011 00Y1 fm.- Rn.. d24; fmov FDm,(Rn+,d24)
 958 8.0xfd+4.0xb,2.0,1.Y,1.1+4.fm,4.Rn+8.IMM24A+8.IMM24B+8.IMM24C:D4o:::fmov
 959 "fmov"
 960 *am33_2
 961 {
 962   PC = cia;
 963
 964   if (FPU_DISABLED)
 965     fpu_disabled_exception (SD, CPU, cia);
 966   else
 967     {
 968       int reg = translate_rreg (SD_, Rn);
 969       store_dword (State.regs[reg]
 970                    + EXTEND24 (FETCH24 (IMM24A,
 971                                         IMM24B, IMM24C)), Xf2FD (Y, fm));
 972       State.regs[reg] += 8;
 973     }
 974 }
 975
 976 // 1111 1101 1011 01Y0 fm.- ---- d24; fmov FDm,(d24,SP)
 977 8.0xfd+4.0xb,2.1,1.Y,1.0+4.fm,4.0+8.IMM24A+8.IMM24B+8.IMM24C:D4p:::fmov
 978 "fmov"
 979 *am33_2
 980 {
 981   PC = cia;
 982
 983   if (FPU_DISABLED)
 984     fpu_disabled_exception (SD, CPU, cia);
 985   else
 986     {
 987       int reg = REG_SP;
 988       store_dword (State.regs[reg] + FETCH24 (IMM24A,
 989                                               IMM24B, IMM24C), Xf2FD (Y, fm));
 990     }
 991 }
 992
 993 // 1111 1110 1010 000X Rm.. fn.- d32; fmov (d32,Rm),FDn
 994 8.0xfe+4.0xa,3.0,1.X+4.Rm,4.fn+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5k:::fmov
 995 "fmov"
 996 *am33_2
 997 {
 998   PC = cia;
 999
1000   if (FPU_DISABLED)
1001     fpu_disabled_exception (SD, CPU, cia);
1002   else
1003     {
1004       int reg = translate_rreg (SD_, Rm);
1005       Xf2FD (X, fn) = load_dword (State.regs[reg]
1006                                   + EXTEND32 (FETCH32 (IMM32A, IMM32B,
1007                                                        IMM32C, IMM32D)));
1008     }
1009 }
1010
1011 // 1111 1110 1010 001X Rm.. fn.- d32; fmov (Rm+,imm32),FDn
1012 8.0xfe+4.0xa,3.1,1.X+4.Rm,4.fn+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5l:::fmov
1013 "fmov"
1014 *am33_2
1015 {
1016   PC = cia;
1017
1018   if (FPU_DISABLED)
1019     fpu_disabled_exception (SD, CPU, cia);
1020   else
1021     {
1022       int reg = translate_rreg (SD_, Rm);
1023       Xf2FD (X, fn) = load_dword (State.regs[reg]
1024                                   + EXTEND32 (FETCH32 (IMM32A, IMM32B,
1025                                                        IMM32C, IMM32D)));
1026       State.regs[reg] += 8;
1027     }
1028 }
1029
1030 // 1111 1110 1010 010X ---- fn.- d32; fmov (d32,SP),FDn
1031 8.0xfe+4.0xa,3.2,1.X+4.0,4.fn+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5m:::fmov
1032 "fmov"
1033 *am33_2
1034 {
1035   PC = cia;
1036
1037   if (FPU_DISABLED)
1038     fpu_disabled_exception (SD, CPU, cia);
1039   else
1040     {
1041       int reg = REG_SP;
1042       Xf2FD (X, fn) = load_dword (State.regs[reg]
1043                                   + FETCH32 (IMM32A, IMM32B,
1044                                              IMM32C, IMM32D));
1045     }
1046 }
1047
1048 // 1111 1110 1011 00Y0 fm.- Rn.. d32; fmov FDm,(d32,Rn)
1049 8.0xfe+4.0xb,2.0,1.Y,1.0+4.fm,4.Rn+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5n:::fmov
1050 "fmov"
1051 *am33_2
1052 {
1053   PC = cia;
1054
1055   if (FPU_DISABLED)
1056     fpu_disabled_exception (SD, CPU, cia);
1057   else
1058     {
1059       int reg = translate_rreg (SD_, Rn);
1060       store_dword (State.regs[reg]
1061                    + EXTEND32 (FETCH32 (IMM32A, IMM32B,
1062                                         IMM32C, IMM32D)), Xf2FD (Y, fm));
1063     }
1064 }
1065
1066 // 1111 1110 1011 00Y1 fm.- Rn.. d32; fmov FDm,(Rn+,d32)
1067 8.0xfe+4.0xb,2.0,1.Y,1.1+4.fm,4.Rn+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5o:::fmov
1068 "fmov"
1069 *am33_2
1070 {
1071   PC = cia;
1072
1073   if (FPU_DISABLED)
1074     fpu_disabled_exception (SD, CPU, cia);
1075   else
1076     {
1077       int reg = translate_rreg (SD_, Rn);
1078       store_dword (State.regs[reg]
1079                    + EXTEND32 (FETCH32 (IMM32A, IMM32B,
1080                                         IMM32C, IMM32D)), Xf2FD (Y, fm));
1081       State.regs[reg] += 8;
1082     }
1083 }
1084
1085 // 1111 1110 1011 01Y0 fm.- ---- d32; fmov FDm,(d32,SP)
1086 8.0xfe+4.0xb,2.1,1.Y,1.0+4.fm,4.0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5p:::fmov
1087 "fmov"
1088 *am33_2
1089 {
1090   PC = cia;
1091
1092   if (FPU_DISABLED)
1093     fpu_disabled_exception (SD, CPU, cia);
1094   else
1095     {
1096       int reg = REG_SP;
1097       store_dword (State.regs[reg]
1098                    + FETCH32 (IMM32A, IMM32B,
1099                               IMM32C, IMM32D), Xf2FD (Y, fm));
1100     }
1101 }
1102
1103 // FPCR fmov:
1104
1105 // 1111 1001 1011 0101 Rm.. ----; fmov Rm,FPCR
1106 8.0xf9+8.0xb5+4.Rm,4.0:D1q:::fmov
1107 "fmov"
1108 *am33_2
1109 {
1110   PC = cia;
1111
1112   if (FPU_DISABLED)
1113     fpu_disabled_exception (SD, CPU, cia);
1114   else
1115     {
1116       int reg = translate_rreg (SD_, Rm);
1117       uint32_t val = State.regs[reg];
1118       FPCR = (val & (EC_MASK | EE_MASK | FCC_MASK))
1119         | ((FPCR & ~val) & EF_MASK);
1120     }
1121 }
1122
1123 // 1111 1001 1011 0111 ---- Rn..; fmov FPCR,Rn
1124 8.0xf9+8.0xb7+4.0,4.Rn:D1r:::fmov
1125 "fmov"
1126 *am33_2
1127 {
1128   PC = cia;
1129
1130   if (FPU_DISABLED)
1131     fpu_disabled_exception (SD, CPU, cia);
1132   else
1133     {
1134       int reg = translate_rreg (SD_, Rn);
1135       State.regs[reg] = FPCR & FPCR_MASK;
1136     }
1137 }
1138
1139 // 1111 1101 1011 0101 imm32; fmov imm32,FPCR
1140 8.0xfd+8.0xb5+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::fmov
1141 "fmov"
1142 *am33_2
1143 {
1144   PC = cia;
1145
1146   if (FPU_DISABLED)
1147     fpu_disabled_exception (SD, CPU, cia);
1148   else
1149     {
1150       uint32_t val = FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D);
1151       FPCR = (val & (EC_MASK | EE_MASK | FCC_MASK))
1152         | ((FPCR & ~val) & EF_MASK);
1153     }
1154 }
1155
1156 // fabs:
1157
1158 // 1111 1001 0100 010X ---- Sn..; fabs FSn
1159 8.0xf9+4.4,3.2,1.X+4.0,4.Sn:D1a:::fabs
1160 "fabs"
1161 *am33_2
1162 {
1163   PC = cia;
1164
1165   if (FPU_DISABLED)
1166     fpu_disabled_exception (SD, CPU, cia);
1167   else
1168     {
1169       sim_fpu in, out;
1170
1171       FS2FPU (XS2FS (X,Sn), in);
1172       sim_fpu_abs (&out, &in);
1173       FPU2FS (out, XS2FS (X,Sn));
1174     }
1175 }
1176
1177 // 1111 1001 1100 010X ---- Sn..; fabs FDn
1178 8.0xf9+4.0xc,3.2,1.X+4.0,3.fn,1.0:D1b:::fabs
1179 "fabs"
1180 *am33_2
1181 {
1182   PC = cia;
1183
1184   if (FPU_DISABLED)
1185     fpu_disabled_exception (SD, CPU, cia);
1186   else
1187     fpu_unimp_exception (SD, CPU, cia);
1188 }
1189
1190 // 1111 1011 0100 0100 Sm.. ---- Sn.. X-Z-; fabs FSm,FSn
1191 8.0xfb+8.0x44+4.Sm,4.0+4.Sn,1.X,1.0,1.Z,1.0:D2a:::fabs
1192 "fabs"
1193 *am33_2
1194 {
1195   PC = cia;
1196
1197   if (FPU_DISABLED)
1198     fpu_disabled_exception (SD, CPU, cia);
1199   else
1200     {
1201       sim_fpu in, out;
1202
1203       FS2FPU (XS2FS (X,Sm), in);
1204       sim_fpu_abs (&out, &in);
1205       FPU2FS (out, XS2FS (Z,Sn));
1206     }
1207 }
1208
1209 // 1111 1011 1100 0100 fm.- ---- fn.- X-Z-; fabs FDm,FDn
1210 8.0xfb+8.0xc4+3.fm,1.0,4.0+3.fn,1.0,1.X,1.0,1.Z,1.0:D2b:::fabs
1211 "fabs"
1212 *am33_2
1213 {
1214   PC = cia;
1215
1216   if (FPU_DISABLED)
1217     fpu_disabled_exception (SD, CPU, cia);
1218   else
1219     fpu_unimp_exception (SD, CPU, cia);
1220 }
1221
1222 // 1111 1001 0100 011X ---- Sn..; fneg FSn
1223 8.0xf9+4.4,3.3,1.X+4.0,4.Sn:D1a:::fneg
1224 "fneg"
1225 *am33_2
1226 {
1227   PC = cia;
1228
1229   if (FPU_DISABLED)
1230     fpu_disabled_exception (SD, CPU, cia);
1231   else
1232     {
1233       sim_fpu in, out;
1234
1235       FS2FPU (XS2FS (X,Sn), in);
1236       sim_fpu_neg (&out, &in);
1237       FPU2FS (out, XS2FS (X,Sn));
1238     }
1239 }
1240
1241 // 1111 1001 1100 011X ---- Sn..; fneg FDn
1242 8.0xf9+4.0xc,3.3,1.X+4.0,3.fn,1.0:D1b:::fneg
1243 "fneg"
1244 *am33_2
1245 {
1246   PC = cia;
1247
1248   if (FPU_DISABLED)
1249     fpu_disabled_exception (SD, CPU, cia);
1250   else
1251     fpu_unimp_exception (SD, CPU, cia);
1252 }
1253
1254 // 1111 1011 0100 0110 Sm.. ---- Sn.. X-Z-; fneg FSm,FSn
1255 8.0xfb+8.0x46+4.Sm,4.0+4.Sn,1.X,1.0,1.Z,1.0:D2a:::fneg
1256 "fneg"
1257 *am33_2
1258 {
1259   PC = cia;
1260
1261   if (FPU_DISABLED)
1262     fpu_disabled_exception (SD, CPU, cia);
1263   else
1264     {
1265       sim_fpu in, out;
1266
1267       FS2FPU (XS2FS (X,Sm), in);
1268       sim_fpu_neg (&out, &in);
1269       FPU2FS (out, XS2FS (Z,Sn));
1270     }
1271 }
1272
1273 // 1111 1011 1100 0110 fm.- ---- fn.- X-Z-; fneg FDm,FDn
1274 8.0xfb+8.0xc6+3.fm,1.0,4.0+3.fn,1.0,1.X,1.0,1.Z,1.0:D2b:::fneg
1275 "fneg"
1276 *am33_2
1277 {
1278   PC = cia;
1279
1280   if (FPU_DISABLED)
1281     fpu_disabled_exception (SD, CPU, cia);
1282   else
1283     fpu_unimp_exception (SD, CPU, cia);
1284 }
1285
1286 // 1111 1001 0101 000X ---- Sn..; frsqrt FSn
1287 8.0xf9+4.5,3.0,1.X+4.0,4.Sn:D1a:::frsqrt
1288 "frsqrt"
1289 *am33_2
1290 {
1291   PC = cia;
1292
1293   if (FPU_DISABLED)
1294     fpu_disabled_exception (SD, CPU, cia);
1295   else
1296     fpu_rsqrt (SD, CPU, cia, &XS2FS (X,Sn), &XS2FS (X,Sn), FP_SINGLE);
1297 }
1298
1299 // 1111 1001 1101 000X ---- fn.-; frsqrt FDn
1300 8.0xf9+4.0xd,3.0,1.X+4.0,3.fn,1.0:D1b:::frsqrt
1301 "frsqrt"
1302 *am33_2
1303 {
1304   PC = cia;
1305
1306   if (FPU_DISABLED)
1307     fpu_disabled_exception (SD, CPU, cia);
1308   else
1309     fpu_unimp_exception (SD, CPU, cia);
1310 }
1311
1312 // 1111 1011 0101 0000 Sm.. ---- Sn.. X-Z-; frsqrt FSm,FSn
1313 8.0xfb+8.0x50+4.Sm,4.0+4.Sn,1.X,1.0,1.Z,1.0:D2a:::frsqrt
1314 "frsqrt"
1315 *am33_2
1316 {
1317   PC = cia;
1318
1319   if (FPU_DISABLED)
1320     fpu_disabled_exception (SD, CPU, cia);
1321   else
1322     fpu_rsqrt (SD, CPU, cia, &XS2FS (X,Sm), &XS2FS (Z,Sn), FP_SINGLE);
1323 }
1324
1325 // 1111 1011 1101 0000 fm.- ---- fn.- X-Z-; frsqrt FDm,FDn
1326 8.0xfb+8.0xd0+3.fm,1.0,4.0+3.fn,1.0,1.X,1.0,1.Z,1.0:D2b:::frsqrt
1327 "frsqrt"
1328 *am33_2
1329 {
1330   PC = cia;
1331
1332   if (FPU_DISABLED)
1333     fpu_disabled_exception (SD, CPU, cia);
1334   else
1335     fpu_unimp_exception (SD, CPU, cia);
1336 }
1337
1338 // 1111 1001 0101 001X ---- Sn..; fsqrt FSn
1339 8.0xf9+4.5,3.1,1.X+4.0,4.Sn:D1a:::fsqrt
1340 "fsqrt"
1341 *am33_2
1342 {
1343   PC = cia;
1344
1345   if (FPU_DISABLED)
1346     fpu_disabled_exception (SD, CPU, cia);
1347   else
1348     fpu_unimp_exception (SD, CPU, cia);
1349 }
1350
1351 // 1111 1001 1101 001X ---- fn.-; fsqrt FDn
1352 8.0xf9+4.0xd,3.1,1.X+4.0,3.fn,1.0:D1b:::fsqrt
1353 "fsqrt"
1354 *am33_2
1355 {
1356   PC = cia;
1357
1358   if (FPU_DISABLED)
1359     fpu_disabled_exception (SD, CPU, cia);
1360   else
1361     fpu_unimp_exception (SD, CPU, cia);
1362 }
1363
1364 // 1111 1011 0101 0100 Sm.. ---- Sn.. X-Z-; fsqrt FSm,FSn
1365 8.0xfb+8.0x54+4.Sm,4.0+4.Sn,1.X,1.0,1.Z,1.0:D2a:::fsqrt
1366 "fsqrt"
1367 *am33_2
1368 {
1369   PC = cia;
1370
1371   if (FPU_DISABLED)
1372     fpu_disabled_exception (SD, CPU, cia);
1373   else
1374     fpu_unimp_exception (SD, CPU, cia);
1375 }
1376
1377 // 1111 1011 1101 0100 fm.- ---- fn.- X-Z-; fsqrt FDm,FDn
1378 8.0xfb+8.0xd4+3.fm,1.0,4.0+3.fn,1.0,1.X,1.0,1.Z,1.0:D2b:::fsqrt
1379 "fsqrt"
1380 *am33_2
1381 {
1382   PC = cia;
1383
1384   if (FPU_DISABLED)
1385     fpu_disabled_exception (SD, CPU, cia);
1386   else
1387     fpu_unimp_exception (SD, CPU, cia);
1388 }
1389
1390 // 1111 1001 0101 01YX Sm.. Sn..; fcmp FSm, FSn
1391 8.0xf9+4.5,2.1,1.Y,1.X+4.Sm,4.Sn:D1a:::fcmp
1392 "fcmp"
1393 *am33_2
1394 {
1395   PC = cia;
1396
1397   if (FPU_DISABLED)
1398     fpu_disabled_exception (SD, CPU, cia);
1399   else
1400     fpu_cmp (SD, CPU, cia, &XS2FS (X,Sn), &XS2FS (Y,Sm), FP_SINGLE);
1401 }
1402
1403 // 1111 1001 1101 01YX fm.- fn.-; fcmp FDm, FDn
1404 8.0xf9+4.0xd,2.1,1.Y,1.X+3.fm,1.0,3.fn,1.0:D1b:::fcmp
1405 "fcmp"
1406 *am33_2
1407 {
1408   PC = cia;
1409
1410   if (FPU_DISABLED)
1411     fpu_disabled_exception (SD, CPU, cia);
1412   else
1413     fpu_unimp_exception (SD, CPU, cia);
1414 }
1415
1416 // 1111 1110 0011 01Y1 Sm.. ---- IMM32; fcmp imm32, FSm
1417 8.0xfe+4.3,2.1,1.Y,1.1+4.Sm,4.0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::fcmp
1418 "fcmp"
1419 *am33_2
1420 {
1421   PC = cia;
1422
1423   if (FPU_DISABLED)
1424     fpu_disabled_exception (SD, CPU, cia);
1425   else
1426     {
1427       uint32_t imm = FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D);
1428
1429       fpu_cmp (SD, CPU, cia, &XS2FS (Y,Sm), &imm, FP_SINGLE);
1430     }
1431 }
1432
1433 // 1111 1001 0110 00YX Sm.. Sn..; fadd FSm, FSn
1434 8.0xf9+4.6,2.0,1.Y,1.X+4.Sm,4.Sn:D1a:::fadd
1435 "fadd"
1436 *am33_2
1437 {
1438   PC = cia;
1439
1440   if (FPU_DISABLED)
1441     fpu_disabled_exception (SD, CPU, cia);
1442   else
1443     fpu_add (SD, CPU, cia,
1444              &XS2FS (Y,Sm), &XS2FS (X,Sn), &XS2FS (X,Sn), FP_SINGLE);
1445 }
1446
1447 // 1111 1001 1110 00YX fm.- fn.-; fadd FDm, FDn
1448 8.0xf9+4.0xe,2.0,1.Y,1.X+3.fm,1.0,3.fn,1.0:D1b:::fadd
1449 "fadd"
1450 *am33_2
1451 {
1452   PC = cia;
1453
1454   if (FPU_DISABLED)
1455     fpu_disabled_exception (SD, CPU, cia);
1456   else
1457     fpu_unimp_exception (SD, CPU, cia);
1458 }
1459
1460 // 1111 1011 0110 0000 Sm1. Sm2. Sn.. XYZ-; fadd FSm1, FSm2, FSn
1461 8.0xfb+8.0x60+4.Sm1,4.Sm2+4.Sn,1.X,1.Y,1.Z,1.0:D2a:::fadd
1462 "fadd"
1463 *am33_2
1464 {
1465   PC = cia;
1466
1467   if (FPU_DISABLED)
1468     fpu_disabled_exception (SD, CPU, cia);
1469   else
1470     fpu_add (SD, CPU, cia,
1471              &XS2FS (X,Sm1), &XS2FS (Y,Sm2), &XS2FS (Z,Sn), FP_SINGLE);
1472 }
1473
1474 // 1111 1011 1110 0000 fm1- fm2- fn.- XYZ-; fadd FDm1, FDm2, FDn
1475 8.0xfb+8.0xe0+3.fm1,1.0,3.fm2,1.0+3.fn,1.0,1.X,1.Y,1.Z,1.0:D2b:::fadd
1476 "fadd"
1477 *am33_2
1478 {
1479   PC = cia;
1480
1481   if (FPU_DISABLED)
1482     fpu_disabled_exception (SD, CPU, cia);
1483   else
1484     fpu_unimp_exception (SD, CPU, cia);
1485 }
1486
1487
1488 // 1111 1110 0110 00YX Sm.. Sn.. IMM32; fadd imm32, FSm, FSn
1489 8.0xfe+4.6,2.0,1.Y,1.X+4.Sm,4.Sn+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::fadd
1490 "fadd"
1491 *am33_2
1492 {
1493   PC = cia;
1494
1495   if (FPU_DISABLED)
1496     fpu_disabled_exception (SD, CPU, cia);
1497   else
1498     {
1499       uint32_t imm = FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D);
1500
1501       fpu_add (SD, CPU, cia,
1502                &XS2FS (Y,Sm), &imm, &XS2FS (X,Sn), FP_SINGLE);
1503     }
1504 }
1505
1506 // 1111 1001 0110 01YX Sm.. Sn..; fsub FSm, FSn
1507 8.0xf9+4.6,2.1,1.Y,1.X+4.Sm,4.Sn:D1a:::fsub
1508 "fsub"
1509 *am33_2
1510 {
1511   PC = cia;
1512
1513   if (FPU_DISABLED)
1514     fpu_disabled_exception (SD, CPU, cia);
1515   else
1516     fpu_sub (SD, CPU, cia,
1517              &XS2FS (X,Sn), &XS2FS (Y,Sm), &XS2FS (X,Sn), FP_SINGLE);
1518 }
1519
1520 // 1111 1001 1110 01YX fm.- fn.-; fsub FDm, FDn
1521 8.0xf9+4.0xe,2.1,1.Y,1.X+3.fm,1.0,3.fn,1.0:D1b:::fsub
1522 "fsub"
1523 *am33_2
1524 {
1525   PC = cia;
1526
1527   if (FPU_DISABLED)
1528     fpu_disabled_exception (SD, CPU, cia);
1529   else
1530     fpu_unimp_exception (SD, CPU, cia);
1531 }
1532
1533 // 1111 1011 0110 0100 Sm1. Sm2. Sn.. XYZ-; fsub FSm1, FSm2, FSn
1534 8.0xfb+8.0x64+4.Sm1,4.Sm2+4.Sn,1.X,1.Y,1.Z,1.0:D2a:::fsub
1535 "fsub"
1536 *am33_2
1537 {
1538   PC = cia;
1539
1540   if (FPU_DISABLED)
1541     fpu_disabled_exception (SD, CPU, cia);
1542   else
1543     fpu_sub (SD, CPU, cia,
1544              &XS2FS (Y,Sm2), &XS2FS (X,Sm1), &XS2FS (Z,Sn), FP_SINGLE);
1545 }
1546
1547 // 1111 1011 1110 0100 fm1- fm2- fn.- XYZ-; fsub FDm1, FDm2, FDn
1548 8.0xfb+8.0xe4+3.fm1,1.0,3.fm2,1.0+3.fn,1.0,1.X,1.Y,1.Z,1.0:D2b:::fsub
1549 "fsub"
1550 *am33_2
1551 {
1552   PC = cia;
1553
1554   if (FPU_DISABLED)
1555     fpu_disabled_exception (SD, CPU, cia);
1556   else
1557     fpu_unimp_exception (SD, CPU, cia);
1558 }
1559
1560
1561 // 1111 1110 0110 01YX Sm.. Sn.. IMM32; fsub imm32, FSm, FSn
1562 8.0xfe+4.6,2.1,1.Y,1.X+4.Sm,4.Sn+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::fsub
1563 "fsub"
1564 *am33_2
1565 {
1566   PC = cia;
1567
1568   if (FPU_DISABLED)
1569     fpu_disabled_exception (SD, CPU, cia);
1570   else
1571     {
1572       uint32_t imm = FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D);
1573
1574       fpu_sub (SD, CPU, cia,
1575                &XS2FS (Y,Sm), &imm, &XS2FS (X,Sn), FP_SINGLE);
1576     }
1577 }
1578
1579 // 1111 1001 0111 00YX Sm.. Sn..; fmul FSm, FSn
1580 8.0xf9+4.7,2.0,1.Y,1.X+4.Sm,4.Sn:D1a:::fmul
1581 "fmul"
1582 *am33_2
1583 {
1584   PC = cia;
1585
1586   if (FPU_DISABLED)
1587     fpu_disabled_exception (SD, CPU, cia);
1588   else
1589     fpu_mul (SD, CPU, cia,
1590              &XS2FS (Y,Sm), &XS2FS (X,Sn), &XS2FS (X,Sn), FP_SINGLE);
1591 }
1592
1593 // 1111 1001 1111 00YX fm.- fn.-; fmul FDm, FDn
1594 8.0xf9+4.0xf,2.0,1.Y,1.X+3.fm,1.0,3.fn,1.0:D1b:::fmul
1595 "fmul"
1596 *am33_2
1597 {
1598   PC = cia;
1599
1600   if (FPU_DISABLED)
1601     fpu_disabled_exception (SD, CPU, cia);
1602   else
1603     fpu_unimp_exception (SD, CPU, cia);
1604 }
1605
1606 // 1111 1011 0111 0000 Sm1. Sm2. Sn.. XYZ-; fmul FSm1, FSm2, FSn
1607 8.0xfb+8.0x70+4.Sm1,4.Sm2+4.Sn,1.X,1.Y,1.Z,1.0:D2a:::fmul
1608 "fmul"
1609 *am33_2
1610 {
1611   PC = cia;
1612
1613   if (FPU_DISABLED)
1614     fpu_disabled_exception (SD, CPU, cia);
1615   else
1616     fpu_mul (SD, CPU, cia,
1617              &XS2FS (X,Sm1), &XS2FS (Y,Sm2), &XS2FS (Z,Sn), FP_SINGLE);
1618 }
1619
1620 // 1111 1011 1111 0000 fm1- fm2- fn.- XYZ-; fmul FDm1, FDm2, FDn
1621 8.0xfb+8.0xf0+3.fm1,1.0,3.fm2,1.0+3.fn,1.0,1.X,1.Y,1.Z,1.0:D2b:::fmul
1622 "fmul"
1623 *am33_2
1624 {
1625   PC = cia;
1626
1627   if (FPU_DISABLED)
1628     fpu_disabled_exception (SD, CPU, cia);
1629   else
1630     fpu_unimp_exception (SD, CPU, cia);
1631 }
1632
1633
1634 // 1111 1110 0111 00YX Sm.. Sn.. IMM32; fmul imm32, FSm, FSn
1635 8.0xfe+4.7,2.0,1.Y,1.X+4.Sm,4.Sn+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::fmul
1636 "fmul"
1637 *am33_2
1638 {
1639   PC = cia;
1640
1641   if (FPU_DISABLED)
1642     fpu_disabled_exception (SD, CPU, cia);
1643   else
1644     {
1645       uint32_t imm = FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D);
1646
1647       fpu_mul (SD, CPU, cia,
1648                &imm, &XS2FS (Y,Sm), &XS2FS (X,Sn), FP_SINGLE);
1649     }
1650 }
1651
1652 // 1111 1001 0111 01YX Sm.. Sn..; fdiv FSm, FSn
1653 8.0xf9+4.7,2.1,1.Y,1.X+4.Sm,4.Sn:D1a:::fdiv
1654 "fdiv"
1655 *am33_2
1656 {
1657   PC = cia;
1658
1659   if (FPU_DISABLED)
1660     fpu_disabled_exception (SD, CPU, cia);
1661   else
1662     fpu_div (SD, CPU, cia,
1663              &XS2FS (X,Sn), &XS2FS (Y,Sm), &XS2FS (X,Sn), FP_SINGLE);
1664 }
1665
1666 // 1111 1001 1111 01YX fm.- fn.-; fdiv FDm, FDn
1667 8.0xf9+4.0xf,2.1,1.Y,1.X+3.fm,1.0,3.fn,1.0:D1b:::fdiv
1668 "fdiv"
1669 *am33_2
1670 {
1671   PC = cia;
1672
1673   if (FPU_DISABLED)
1674     fpu_disabled_exception (SD, CPU, cia);
1675   else
1676     fpu_unimp_exception (SD, CPU, cia);
1677 }
1678
1679 // 1111 1011 0111 0100 Sm1. Sm2. Sn.. XYZ-; fdiv FSm1, FSm2, FSn
1680 8.0xfb+8.0x74+4.Sm1,4.Sm2+4.Sn,1.X,1.Y,1.Z,1.0:D2a:::fdiv
1681 "fdiv"
1682 *am33_2
1683 {
1684   PC = cia;
1685
1686   if (FPU_DISABLED)
1687     fpu_disabled_exception (SD, CPU, cia);
1688   else
1689     fpu_div (SD, CPU, cia,
1690              &XS2FS (Y,Sm2), &XS2FS (X,Sm1), &XS2FS (Z,Sn), FP_SINGLE);
1691 }
1692
1693 // 1111 1011 1111 0100 fm1- fm2- fn.- XYZ-; fdiv FDm1, FDm2, FDn
1694 8.0xfb+8.0xf4+3.fm1,1.0,3.fm2,1.0+3.fn,1.0,1.X,1.Y,1.Z,1.0:D2b:::fdiv
1695 "fdiv"
1696 *am33_2
1697 {
1698   PC = cia;
1699
1700   if (FPU_DISABLED)
1701     fpu_disabled_exception (SD, CPU, cia);
1702   else
1703     fpu_unimp_exception (SD, CPU, cia);
1704 }
1705
1706
1707 // 1111 1110 0111 01YX Sm.. Sn.. IMM32; fdiv imm32, FSm, FSn
1708 8.0xfe+4.7,2.1,1.Y,1.X+4.Sm,4.Sn+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::fdiv
1709 "fdiv"
1710 *am33_2
1711 {
1712   PC = cia;
1713
1714   if (FPU_DISABLED)
1715     fpu_disabled_exception (SD, CPU, cia);
1716   else
1717     {
1718       uint32_t imm = FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D);
1719
1720       fpu_div (SD, CPU, cia,
1721                &XS2FS (Y,Sm), &imm, &XS2FS (X,Sn), FP_SINGLE);
1722     }
1723 }
1724
1725 // 1111 1011 1000 00Sn Sm1. Sm2. Sm3. XYZA; fmadd FSm1, FSm2, FSm3, FSn
1726 8.0xfb+4.8,2.0,2.Sn+4.Sm1,4.Sm2+4.Sm3,1.X,1.Y,1.Z,1.A:D2:::fmadd
1727 "fmadd"
1728 *am33_2
1729 {
1730   PC = cia;
1731
1732   if (FPU_DISABLED)
1733     fpu_disabled_exception (SD, CPU, cia);
1734   else
1735     fpu_fmadd (SD, CPU, cia,
1736                &XS2FS (X,Sm1), &XS2FS (Y,Sm2), &XS2FS (Z,Sm3),
1737                &AS2FS (A,Sn), FP_SINGLE);
1738 }
1739
1740 // 1111 1011 1000 01Sn Sm1. Sm2. Sm3. XYZA; fmsub FSm1, FSm2, FSm3, FSn
1741 8.0xfb+4.8,2.1,2.Sn+4.Sm1,4.Sm2+4.Sm3,1.X,1.Y,1.Z,1.A:D2:::fmsub
1742 "fmsub"
1743 *am33_2
1744 {
1745   PC = cia;
1746
1747   if (FPU_DISABLED)
1748     fpu_disabled_exception (SD, CPU, cia);
1749   else
1750     fpu_fmsub (SD, CPU, cia,
1751                &XS2FS (X,Sm1), &XS2FS (Y,Sm2), &XS2FS (Z,Sm3),
1752                &AS2FS (A,Sn), FP_SINGLE);
1753 }
1754
1755 // 1111 1011 1001 00Sn Sm1. Sm2. Sm3. XYZA; fnmadd FSm1, FSm2, FSm3, FSn
1756 8.0xfb+4.9,2.0,2.Sn+4.Sm1,4.Sm2+4.Sm3,1.X,1.Y,1.Z,1.A:D2:::fnmadd
1757 "fnmadd"
1758 *am33_2
1759 {
1760   PC = cia;
1761
1762   if (FPU_DISABLED)
1763     fpu_disabled_exception (SD, CPU, cia);
1764   else
1765     fpu_fnmadd (SD, CPU, cia,
1766                 &XS2FS (X,Sm1), &XS2FS (Y,Sm2), &XS2FS (Z,Sm3),
1767                 &AS2FS (A,Sn), FP_SINGLE);
1768 }
1769
1770 // 1111 1011 1001 01Sn Sm1. Sm2. Sm3. XYZA; fnmsub FSm1, FSm2, FSm3, FSn
1771 8.0xfb+4.9,2.1,2.Sn+4.Sm1,4.Sm2+4.Sm3,1.X,1.Y,1.Z,1.A:D2:::fnmsub
1772 "fnmsub"
1773 *am33_2
1774 {
1775   PC = cia;
1776
1777   if (FPU_DISABLED)
1778     fpu_disabled_exception (SD, CPU, cia);
1779   else
1780     fpu_fnmsub (SD, CPU, cia,
1781                 &XS2FS (X,Sm1), &XS2FS (Y,Sm2), &XS2FS (Z,Sm3),
1782                 &AS2FS (A,Sn), FP_SINGLE);
1783 }
1784
1785 // conversion:
1786
1787 // 1111 1011 0100 0000 Sm.. ---- Sn.. X-Z-; ftoi FSm,FSn
1788 8.0xfb+8.0x40+4.Sm,4.0+4.Sn,1.X,1.0,1.Z,1.0:D2:::ftoi
1789 "ftoi"
1790 *am33_2
1791 {
1792   PC = cia;
1793
1794   if (FPU_DISABLED)
1795     fpu_disabled_exception (SD, CPU, cia);
1796   else
1797     fpu_unimp_exception (SD, CPU, cia);
1798 }
1799
1800 // 1111 1011 0100 0010 Sm.. ---- Sn.. X-Z-; itof FSm,FSn
1801 8.0xfb+8.0x42+4.Sm,4.0+4.Sn,1.X,1.0,1.Z,1.0:D2:::itof
1802 "itof"
1803 *am33_2
1804 {
1805   PC = cia;
1806
1807   if (FPU_DISABLED)
1808     fpu_disabled_exception (SD, CPU, cia);
1809   else
1810     fpu_unimp_exception (SD, CPU, cia);
1811 }
1812
1813 // 1111 1011 0101 0010 Sm.. ---- fn.- X-Z-; ftod FSm,FDn
1814 8.0xfb+8.0x52+4.Sm,4.0+3.fn,1.0,1.X,1.0,1.Z,1.0:D2:::ftod
1815 "ftod"
1816 *am33_2
1817 {
1818   PC = cia;
1819
1820   if (FPU_DISABLED)
1821     fpu_disabled_exception (SD, CPU, cia);
1822   else
1823     fpu_unimp_exception (SD, CPU, cia);
1824 }
1825
1826 // 1111 1011 0101 0110 fm.- ---- Sn.. X-Z-; dtof FDm,FSn
1827 8.0xfb+8.0x56+3.fm,1.0,4.0+4.Sn,1.X,1.0,1.Z,1.0:D2:::dtof
1828 "dtof"
1829 *am33_2
1830 {
1831   PC = cia;
1832
1833   if (FPU_DISABLED)
1834     fpu_disabled_exception (SD, CPU, cia);
1835   else
1836     fpu_unimp_exception (SD, CPU, cia);
1837 }
1838
1839 // branching:
1840
1841 // 1111 1000 1101 0000 d8; fbeq (d8,PC) (d8 is sign-extended)
1842 8.0xf8+8.0xd0+8.D8:D1:::fbeq
1843 "fbeq"
1844 *am33_2
1845 {
1846   PC = cia;
1847
1848   if (FPU_DISABLED)
1849     fpu_disabled_exception (SD, CPU, cia);
1850   else if ((FPCR & FCC_E))
1851     {
1852       State.regs[REG_PC] += EXTEND8 (D8);
1853       nia = PC;
1854     }
1855 }
1856
1857 // 1111 1000 1101 0001 d8; fbne (d8,PC) (d8 is sign-extended)
1858 8.0xf8+8.0xd1+8.D8:D1:::fbne
1859 "fbne"
1860 *am33_2
1861 {
1862   PC = cia;
1863
1864   if (FPU_DISABLED)
1865     fpu_disabled_exception (SD, CPU, cia);
1866   else if ((FPCR & (FCC_U | FCC_L | FCC_G)))
1867     {
1868       State.regs[REG_PC] += EXTEND8 (D8);
1869       nia = PC;
1870     }
1871 }
1872
1873 // 1111 1000 1101 0010 d8; fbgt (d8,PC) (d8 is sign-extended)
1874 8.0xf8+8.0xd2+8.D8:D1:::fbgt
1875 "fbgt"
1876 *am33_2
1877 {
1878   PC = cia;
1879
1880   if (FPU_DISABLED)
1881     fpu_disabled_exception (SD, CPU, cia);
1882   else if ((FPCR & FCC_G))
1883     {
1884       State.regs[REG_PC] += EXTEND8 (D8);
1885       nia = PC;
1886     }
1887 }
1888
1889 // 1111 1000 1101 0011 d8; fbge (d8,PC) (d8 is sign-extended)
1890 8.0xf8+8.0xd3+8.D8:D1:::fbge
1891 "fbge"
1892 *am33_2
1893 {
1894   PC = cia;
1895
1896   if (FPU_DISABLED)
1897     fpu_disabled_exception (SD, CPU, cia);
1898   else if ((FPCR & (FCC_G | FCC_E)))
1899     {
1900       State.regs[REG_PC] += EXTEND8 (D8);
1901       nia = PC;
1902     }
1903 }
1904
1905 // 1111 1000 1101 0100 d8; fblt (d8,PC) (d8 is sign-extended)
1906 8.0xf8+8.0xd4+8.D8:D1:::fblt
1907 "fblt"
1908 *am33_2
1909 {
1910   PC = cia;
1911
1912   if (FPU_DISABLED)
1913     fpu_disabled_exception (SD, CPU, cia);
1914   else if ((FPCR & FCC_L))
1915     {
1916       State.regs[REG_PC] += EXTEND8 (D8);
1917       nia = PC;
1918     }
1919 }
1920
1921 // 1111 1000 1101 0101 d8; fble (d8,PC) (d8 is sign-extended)
1922 8.0xf8+8.0xd5+8.D8:D1:::fble
1923 "fble"
1924 *am33_2
1925 {
1926   PC = cia;
1927
1928   if (FPU_DISABLED)
1929     fpu_disabled_exception (SD, CPU, cia);
1930   else if ((FPCR & (FCC_L | FCC_E)))
1931     {
1932       State.regs[REG_PC] += EXTEND8 (D8);
1933       nia = PC;
1934     }
1935 }
1936
1937 // 1111 1000 1101 0110 d8; fbuo (d8,PC) (d8 is sign-extended)
1938 8.0xf8+8.0xd6+8.D8:D1:::fbuo
1939 "fbuo"
1940 *am33_2
1941 {
1942   PC = cia;
1943
1944   if (FPU_DISABLED)
1945     fpu_disabled_exception (SD, CPU, cia);
1946   else if ((FPCR & FCC_U))
1947     {
1948       State.regs[REG_PC] += EXTEND8 (D8);
1949       nia = PC;
1950     }
1951 }
1952
1953 // 1111 1000 1101 0111 d8; fblg (d8,PC) (d8 is sign-extended)
1954 8.0xf8+8.0xd7+8.D8:D1:::fblg
1955 "fblg"
1956 *am33_2
1957 {
1958   PC = cia;
1959
1960   if (FPU_DISABLED)
1961     fpu_disabled_exception (SD, CPU, cia);
1962   else if ((FPCR & (FCC_L | FCC_G)))
1963     {
1964       State.regs[REG_PC] += EXTEND8 (D8);
1965       nia = PC;
1966     }
1967 }
1968 // 1111 1000 1101 1000 d8; fbleg (d8,PC) (d8 is sign-extended)
1969 8.0xf8+8.0xd8+8.D8:D1:::fbleg
1970 "fbleg"
1971 *am33_2
1972 {
1973   PC = cia;
1974
1975   if (FPU_DISABLED)
1976     fpu_disabled_exception (SD, CPU, cia);
1977   else if ((FPCR & (FCC_L | FCC_E | FCC_G)))
1978     {
1979       State.regs[REG_PC] += EXTEND8 (D8);
1980       nia = PC;
1981     }
1982 }
1983
1984 // 1111 1000 1101 1001 d8; fbug (d8,PC) (d8 is sign-extended)
1985 8.0xf8+8.0xd9+8.D8:D1:::fbug
1986 "fbug"
1987 *am33_2
1988 {
1989   PC = cia;
1990
1991   if (FPU_DISABLED)
1992     fpu_disabled_exception (SD, CPU, cia);
1993   else if ((FPCR & (FCC_U | FCC_G)))
1994     {
1995       State.regs[REG_PC] += EXTEND8 (D8);
1996       nia = PC;
1997     }
1998 }
1999
2000 // 1111 1000 1101 1010 d8; fbuge (d8,PC) (d8 is sign-extended)
2001 8.0xf8+8.0xda+8.D8:D1:::fbuge
2002 "fbuge"
2003 *am33_2
2004 {
2005   PC = cia;
2006
2007   if (FPU_DISABLED)
2008     fpu_disabled_exception (SD, CPU, cia);
2009   else if ((FPCR & (FCC_U | FCC_G | FCC_E)))
2010     {
2011       State.regs[REG_PC] += EXTEND8 (D8);
2012       nia = PC;
2013     }
2014 }
2015
2016 // 1111 1000 1101 1011 d8; fbul (d8,PC) (d8 is sign-extended)
2017 8.0xf8+8.0xdb+8.D8:D1:::fbul
2018 "fbul"
2019 *am33_2
2020 {
2021   PC = cia;
2022
2023   if (FPU_DISABLED)
2024     fpu_disabled_exception (SD, CPU, cia);
2025   else if ((FPCR & (FCC_U | FCC_L)))
2026     {
2027       State.regs[REG_PC] += EXTEND8 (D8);
2028       nia = PC;
2029     }
2030 }
2031
2032 // 1111 1000 1101 1100 d8; fbule (d8,PC) (d8 is sign-extended)
2033 8.0xf8+8.0xdc+8.D8:D1:::fbule
2034 "fbule"
2035 *am33_2
2036 {
2037   PC = cia;
2038
2039   if (FPU_DISABLED)
2040     fpu_disabled_exception (SD, CPU, cia);
2041   else if ((FPCR & (FCC_U | FCC_L | FCC_E)))
2042     {
2043       State.regs[REG_PC] += EXTEND8 (D8);
2044       nia = PC;
2045     }
2046 }
2047
2048 // 1111 1000 1101 1101 d8; fbue (d8,PC) (d8 is sign-extended)
2049 8.0xf8+8.0xdd+8.D8:D1:::fbue
2050 "fbue"
2051 *am33_2
2052 {
2053   PC = cia;
2054
2055   if (FPU_DISABLED)
2056     fpu_disabled_exception (SD, CPU, cia);
2057   else if ((FPCR & (FCC_U | FCC_E)))
2058     {
2059       State.regs[REG_PC] += EXTEND8 (D8);
2060       nia = PC;
2061     }
2062 }
2063
2064 // 1111 0000 1101 0000; fleq
2065 8.0xf0+8.0xd0:D0:::fleq
2066 "fleq"
2067 *am33_2
2068 {
2069   PC = cia;
2070
2071   if (FPU_DISABLED)
2072     fpu_disabled_exception (SD, CPU, cia);
2073   else if ((FPCR & FCC_E))
2074     {
2075       State.regs[REG_PC] = State.regs[REG_LAR] - 4;
2076       nia = PC;
2077     }
2078 }
2079
2080 // 1111 0000 1101 0001; flne
2081 8.0xf0+8.0xd1:D0:::flne
2082 "flne"
2083 *am33_2
2084 {
2085   PC = cia;
2086
2087   if (FPU_DISABLED)
2088     fpu_disabled_exception (SD, CPU, cia);
2089   else if ((FPCR & (FCC_U | FCC_L | FCC_G)))
2090     {
2091       State.regs[REG_PC] = State.regs[REG_LAR] - 4;
2092       nia = PC;
2093     }
2094 }
2095
2096 // 1111 0000 1101 0010; flgt
2097 8.0xf0+8.0xd2:D0:::flgt
2098 "flgt"
2099 *am33_2
2100 {
2101   PC = cia;
2102
2103   if (FPU_DISABLED)
2104     fpu_disabled_exception (SD, CPU, cia);
2105   else if ((FPCR & FCC_G))
2106     {
2107       State.regs[REG_PC] = State.regs[REG_LAR] - 4;
2108       nia = PC;
2109     }
2110 }
2111
2112 // 1111 0000 1101 0011; flge
2113 8.0xf0+8.0xd3:D0:::flge
2114 "flge"
2115 *am33_2
2116 {
2117   PC = cia;
2118
2119   if (FPU_DISABLED)
2120     fpu_disabled_exception (SD, CPU, cia);
2121   else if ((FPCR & (FCC_G | FCC_E)))
2122     {
2123       State.regs[REG_PC] = State.regs[REG_LAR] - 4;
2124       nia = PC;
2125     }
2126 }
2127
2128 // 1111 0000 1101 0100; fllt
2129 8.0xf0+8.0xd4:D0:::fllt
2130 "fllt"
2131 *am33_2
2132 {
2133   PC = cia;
2134
2135   if (FPU_DISABLED)
2136     fpu_disabled_exception (SD, CPU, cia);
2137   else if ((FPCR & FCC_L))
2138     {
2139       State.regs[REG_PC] = State.regs[REG_LAR] - 4;
2140       nia = PC;
2141     }
2142 }
2143
2144 // 1111 0000 1101 0101; flle
2145 8.0xf0+8.0xd5:D0:::flle
2146 "flle"
2147 *am33_2
2148 {
2149   PC = cia;
2150
2151   if (FPU_DISABLED)
2152     fpu_disabled_exception (SD, CPU, cia);
2153   else if ((FPCR & (FCC_L | FCC_E)))
2154     {
2155       State.regs[REG_PC] = State.regs[REG_LAR] - 4;
2156       nia = PC;
2157     }
2158 }
2159
2160 // 1111 0000 1101 0110; fluo
2161 8.0xf0+8.0xd6:D0:::fluo
2162 "fluo"
2163 *am33_2
2164 {
2165   PC = cia;
2166
2167   if (FPU_DISABLED)
2168     fpu_disabled_exception (SD, CPU, cia);
2169   else if ((FPCR & FCC_U))
2170     {
2171       State.regs[REG_PC] = State.regs[REG_LAR] - 4;
2172       nia = PC;
2173     }
2174 }
2175
2176 // 1111 0000 1101 0111; fllg
2177 8.0xf0+8.0xd7:D0:::fllg
2178 "fllg"
2179 *am33_2
2180 {
2181   PC = cia;
2182
2183   if (FPU_DISABLED)
2184     fpu_disabled_exception (SD, CPU, cia);
2185   else if ((FPCR & (FCC_L | FCC_G)))
2186     {
2187       State.regs[REG_PC] = State.regs[REG_LAR] - 4;
2188       nia = PC;
2189     }
2190 }
2191 // 1111 0000 1101 1000; flleg
2192 8.0xf0+8.0xd8:D0:::flleg
2193 "flleg"
2194 *am33_2
2195 {
2196   PC = cia;
2197
2198   if (FPU_DISABLED)
2199     fpu_disabled_exception (SD, CPU, cia);
2200   else if ((FPCR & (FCC_L | FCC_E | FCC_G)))
2201     {
2202       State.regs[REG_PC] = State.regs[REG_LAR] - 4;
2203       nia = PC;
2204     }
2205 }
2206
2207 // 1111 0000 1101 1001; flug
2208 8.0xf0+8.0xd9:D0:::flug
2209 "flug"
2210 *am33_2
2211 {
2212   PC = cia;
2213
2214   if (FPU_DISABLED)
2215     fpu_disabled_exception (SD, CPU, cia);
2216   else if ((FPCR & (FCC_U | FCC_G)))
2217     {
2218       State.regs[REG_PC] = State.regs[REG_LAR] - 4;
2219       nia = PC;
2220     }
2221 }
2222
2223 // 1111 0000 1101 1010; fluge
2224 8.0xf0+8.0xda:D0:::fluge
2225 "fluge"
2226 *am33_2
2227 {
2228   PC = cia;
2229
2230   if (FPU_DISABLED)
2231     fpu_disabled_exception (SD, CPU, cia);
2232   else if ((FPCR & (FCC_U | FCC_G | FCC_E)))
2233     {
2234       State.regs[REG_PC] = State.regs[REG_LAR] - 4;
2235       nia = PC;
2236     }
2237 }
2238
2239 // 1111 0000 1101 1011; flul
2240 8.0xf0+8.0xdb:D0:::flul
2241 "flul"
2242 *am33_2
2243 {
2244   PC = cia;
2245
2246   if (FPU_DISABLED)
2247     fpu_disabled_exception (SD, CPU, cia);
2248   else if ((FPCR & (FCC_U | FCC_L)))
2249     {
2250       State.regs[REG_PC] = State.regs[REG_LAR] - 4;
2251       nia = PC;
2252     }
2253 }
2254
2255 // 1111 0000 1101 1100; flule
2256 8.0xf0+8.0xdc:D0:::flule
2257 "flule"
2258 *am33_2
2259 {
2260   PC = cia;
2261
2262   if (FPU_DISABLED)
2263     fpu_disabled_exception (SD, CPU, cia);
2264   else if ((FPCR & (FCC_U | FCC_L | FCC_E)))
2265     {
2266       State.regs[REG_PC] = State.regs[REG_LAR] - 4;
2267       nia = PC;
2268     }
2269 }
2270
2271 // 1111 0000 1101 1101; flue
2272 8.0xf0+8.0xdd:D0:::flue
2273 "flue"
2274 *am33_2
2275 {
2276   PC = cia;
2277
2278   if (FPU_DISABLED)
2279     fpu_disabled_exception (SD, CPU, cia);
2280   else if ((FPCR & (FCC_U | FCC_E)))
2281     {
2282       State.regs[REG_PC] = State.regs[REG_LAR] - 4;
2283       nia = PC;
2284     }
2285 }