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[thirdparty/binutils-gdb.git] / sim / mn10300 / mn10300.igen
1 // -*- C -*-
2 :option:::insn-bit-size:8
3 :option:::insn-specifying-widths:true
4 :option:::hi-bit-nr:7
5 :model:::mn10300:mn10300:
6
7 // What do we do with an illegal instruction?
8 :internal::::illegal:
9 {
10 PC = cia;
11 program_interrupt(SD, CPU, cia, SIM_SIGILL);
12 }
13
14 // 1000 DnDn imm8....; mov imm8,Dn (imm8 is sign extended)
15 4.0x8,2.DM1,2.DN0=DM1+8.IMM8:S0i:::mov
16 "mov"
17 *mn10300
18 {
19 /* OP_8000 (); */
20 signed32 immed = EXTEND8 (IMM8);
21 State.regs[REG_D0+DN0] = immed;
22 PC = cia;
23 }
24
25 // 1000 DmDn; mov Dm,Dn (Dm != Dn, see above when Dm == Dn)
26 4.0x8,2.DM1,2.DN0!DM1:S0:::mov
27 "mov"
28 *mn10300
29 {
30 PC = cia;
31 /* OP_80 (); */
32 State.regs[REG_D0+DN0] = State.regs[REG_D0+DM1];
33 }
34
35
36 // 1111 0001 1110 DmAn; mov Dm,An
37 8.0xf1+1110,2.DM1,2.AN0:D0:::mov
38 "mov"
39 *mn10300
40 {
41 /* OP_F1E0 (); */
42 PC = cia;
43 State.regs[REG_A0 + AN0] = State.regs[REG_D0 + DM1];
44 }
45
46
47 // 1111 0001 1101 AmDn; mov Am,Dn
48 8.0xf1+1101,2.AM1,2.DN0:D0a:::mov
49 "mov"
50 *mn10300
51 {
52 /* OP_F1D0 (); */
53 PC = cia;
54 State.regs[REG_D0 + DN0] = State.regs[REG_A0 + AM1];
55 }
56
57
58 // 1001 AnAn imm8....; mov imm8,An (imm8 is zero-extended)
59 4.0x9,2.AM1,2.AN0=AM1+8.IMM8:S0ai:::mov
60 "mov"
61 *mn10300
62 {
63 PC = cia;
64 /* OP_9000 (); */
65 State.regs[REG_A0+AN0] = IMM8;
66 }
67
68
69 // 1001 AmAn; mov Am,An (Am != An, save above when Am == An)
70 4.0x9,2.AM1,2.AN0!AM1:S0a:::mov
71 "mov"
72 *mn10300
73 {
74 PC = cia;
75 /* OP_90 (); */
76 State.regs[REG_A0+AN0] = State.regs[REG_A0+AM1];
77 }
78
79
80 // 0011 11An; mov SP,An
81 4.0x3,11,2.AN0:S0b:::mov
82 "mov"
83 *mn10300
84 {
85 /* OP_3C (); */
86 PC = cia;
87 State.regs[REG_A0 + AN0] = State.regs[REG_SP];
88 }
89
90
91 // 1111 0010 1111 Am00; mov Am,SP
92 8.0xf2+4.0xf,2.AM1,00:D0b:::mov
93 "mov"
94 *mn10300
95 {
96 /* OP_F2F0 (); */
97 PC = cia;
98 State.regs[REG_SP] = State.regs[REG_A0 + AM1];
99 }
100
101
102 // 1111 0010 1110 01Dn; mov PSW,Dn
103 8.0xf2+4.0xe,01,2.DN0:D0c:::mov
104 "mov"
105 *mn10300
106 {
107 /* OP_F2E4 (); */
108 PC = cia;
109 State.regs[REG_D0 + DN0] = PSW;
110 }
111
112
113 // 1111 0010 1111 Dm11; mov Dm,PSW
114 8.0xf2+4.0xf,2.DM1,11:D0d:::mov
115 "mov"
116 *mn10300
117 {
118 /* OP_F2F3 (); */
119 PC = cia;
120 PSW = State.regs[REG_D0 + DM1];
121 }
122
123
124 // 1111 0010 1110 00Dn; mov MDR,Dn
125 8.0xf2+4.0xe,00,2.DN0:D0e:::mov
126 "mov"
127 *mn10300
128 {
129 /* OP_F2E0 (); */
130 PC = cia;
131 State.regs[REG_D0 + DN0] = State.regs[REG_MDR];
132 }
133
134
135 // 1111 0010 1111 Dm10; mov Dm,MDR
136 8.0xf2+4.0xf,2.DM1,10:D0f:::mov
137 "mov"
138 *mn10300
139 {
140 /* OP_F2F2 (); */
141 PC = cia;
142 State.regs[REG_MDR] = State.regs[REG_D0 + DM1];
143 }
144
145
146 // 0111 DnAm; mov (Am),Dn
147 4.0x7,2.DN1,2.AM0:S0c:::mov
148 "mov"
149 *mn10300
150 {
151 /* OP_70 (); */
152 PC = cia;
153 State.regs[REG_D0 + DN1] = load_word (State.regs[REG_A0 + AM0]);
154 }
155
156
157 // 1111 1000 0000 DnAm d8......; mov (d8,Am),Dn (d8 is sign-extended)
158 8.0xf8+4.0x0,2.DN1,2.AM0+8.D8:D1:::mov
159 "mov"
160 *mn10300
161 {
162 /* OP_F80000 (); */
163 PC = cia;
164 State.regs[REG_D0 + DN1]
165 = load_word ((State.regs[REG_A0 + AM0] + EXTEND8 (D8)));
166 }
167
168
169 // 1111 1010 0000 DnAm d16.....; mov (d16,Am),Dn (d16 is sign-extended.)
170 8.0xfa+4.0x0,2.DN1,2.AM0+8.D16A+8.D16B:D2:::mov
171 "mov"
172 *mn10300
173 {
174 /* OP_FA000000 (); */
175 PC = cia;
176 State.regs[REG_D0 + DN1]
177 = load_word ((State.regs[REG_A0 + AM0] + EXTEND16 (FETCH16(D16A, D16B))));
178 }
179
180
181 // 1111 1100 0000 DnAm d32.....; mov (d32,Am),Dn
182 8.0xfc+4.0x0,2.DN1,2.AM0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4:::mov
183 "mov"
184 *mn10300
185 {
186 /* OP_FC000000 (); */
187 PC = cia;
188 State.regs[REG_D0 + DN1]
189 = load_word ((State.regs[REG_A0 + AM0]
190 + FETCH32(IMM32A, IMM32B, IMM32C, IMM32D)));
191 }
192
193
194 // 0101 10Dn d8......; mov (d8,SP),Dn (d8 is zero-extended)
195 4.0x5,10,2.DN0+8.D8:S1:::mov
196 "mov"
197 *mn10300
198 {
199 /* OP_5800 (); */
200 PC = cia;
201 State.regs[REG_D0 + DN0] = load_word (State.regs[REG_SP] + D8);
202 }
203
204
205 // 1111 1010 1011 01Dn d16.....; mov (d16,SP),Dn (d16 is zero-extended.)
206 8.0xfa+4.0xb,01,2.DN0+8.IMM16A+8.IMM16B:D2a:::mov
207 "mov"
208 *mn10300
209 {
210 /* OP_FAB40000 (); */
211 PC = cia;
212 State.regs[REG_D0 + DN0]
213 = load_word (State.regs[REG_SP] + FETCH16(IMM16A, IMM16B));
214 }
215
216
217 // 1111 1010 1011 01Dn d32.....; mov (d32,SP),Dn
218 8.0xfc+4.0xb,01,2.DN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4a:::mov
219 "mov"
220 *mn10300
221 {
222 /* OP_FCB40000 (); */
223 PC = cia;
224 State.regs[REG_D0 + DN0]
225 = load_word (State.regs[REG_SP] + FETCH32(IMM32A, IMM32B, IMM32C, IMM32D));
226 }
227
228
229 // 1111 0011 00Dn DiAm; mov (Di,Am),Dn
230 8.0xf3+00,2.DN2,2.DI,2.AM0:D0g:::mov
231 "mov"
232 *mn10300
233 {
234 /* OP_F300 (); */
235 PC = cia;
236 State.regs[REG_D0 + DN2]
237 = load_word ((State.regs[REG_A0 + AM0] + State.regs[REG_D0 + DI]));
238 }
239
240
241 // 0011 00Dn abs16...; mov (abs16),Dn (abs16 is zero-extended)
242 4.0x3,00,2.DN0+8.IMM16A+8.IMM16B:S2:::mov
243 "mov"
244 *mn10300
245 {
246 /* OP_300000 (); */
247 PC = cia;
248 State.regs[REG_D0 + DN0] = load_word (FETCH16(IMM16A, IMM16B));
249 }
250
251 // 1111 1100 1010 01Dn abs32...; mov (abs32),Dn
252 8.0xfc+4.0xa,01,2.DN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4b:::mov
253 "mov"
254 *mn10300
255 {
256 /* OP_FCA40000 (); */
257 PC = cia;
258 State.regs[REG_D0 + DN0] = load_word (FETCH32(IMM32A, IMM32B, IMM32C, IMM32D));
259 }
260
261
262 // 1111 0000 0000 AnAm; mov (Am),An
263 8.0xf0+4.0x0,2.AN1,2.AM0:D0h:::mov
264 "mov"
265 *mn10300
266 {
267 /* OP_F000 (); */
268 PC = cia;
269 State.regs[REG_A0 + AN1] = load_word (State.regs[REG_A0 + AM0]);
270 }
271
272
273 // 1111 1000 0010 AnAm d8......; mov (d8,Am),An (d8 is sign-extended)
274 8.0xf8+4.0x2,2.AN1,2.AM0+8.D8:D1a:::mov
275 "mov"
276 *mn10300
277 {
278 /* OP_F82000 (); */
279 PC = cia;
280 State.regs[REG_A0 + AN1]
281 = load_word ((State.regs[REG_A0 + AM0] + EXTEND8 (D8)));
282 }
283
284
285 // 1111 1010 0010 AnAm d16.....; mov (d16,Am),An (d16 is sign-extended.)
286 8.0xfa+4.0x2,2.AN1,2.AM0+8.D16A+8.D16B:D2b:::mov
287 "mov"
288 *mn10300
289 {
290 /* OP_FA200000 (); */
291 PC = cia;
292 State.regs[REG_A0 + AN1]
293 = load_word ((State.regs[REG_A0 + AM0]
294 + EXTEND16 (FETCH16(D16A, D16B))));
295 }
296
297
298 // 1111 1100 0010 AnAm d32.....; mov (d32,Am),An
299 8.0xfc+4.0x2,2.AN1,2.AM0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4c:::mov
300 "mov"
301 *mn10300
302 {
303 /* OP_FC200000 (); */
304 PC = cia;
305 State.regs[REG_A0 + AN1]
306 = load_word ((State.regs[REG_A0 + AM0]
307 + FETCH32(IMM32A, IMM32B, IMM32C, IMM32D)));
308 }
309
310
311 // 0101 11An d8......; mov (d8,SP),An (d8 is zero-extended)
312 4.0x5,11,2.AN0+8.D8:S1a:::mov
313 "mov"
314 *mn10300
315 {
316 /* OP_5C00 (); */
317 PC = cia;
318 State.regs[REG_A0 + AN0]
319 = load_word (State.regs[REG_SP] + D8);
320 }
321
322
323 // 1111 1010 1011 00An d16.....; mov (d16,SP),An (d16 is zero-extended.)
324 8.0xfa+4.0xb,00,2.AN0+8.IMM16A+8.IMM16B:D2c:::mov
325 "mov"
326 *mn10300
327 {
328 /* OP_FAB00000 (); */
329 PC = cia;
330 State.regs[REG_A0 + AN0]
331 = load_word (State.regs[REG_SP] + FETCH16(IMM16A, IMM16B));
332 }
333
334
335 // 1111 1100 1011 00An d32.....; mov (d32,SP),An
336 8.0xfc+4.0xb,00,2.AN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4d:::mov
337 "mov"
338 *mn10300
339 {
340 /* OP_FCB00000 (); */
341 PC = cia;
342 State.regs[REG_A0 + AN0]
343 = load_word (State.regs[REG_SP]
344 + FETCH32(IMM32A, IMM32B, IMM32C, IMM32D));
345 }
346
347
348 // 1111 0011 10An DiAm; mov (Di,Am),An
349 8.0xf3+10,2.AN2,2.DI,2.AM0:D0i:::mov
350 "mov"
351 *mn10300
352 {
353 /* OP_F380 (); */
354 PC = cia;
355 State.regs[REG_A0 + AN2]
356 = load_word ((State.regs[REG_A0 + AM0]
357 + State.regs[REG_D0 + DI]));
358 }
359
360
361 // 1111 1010 1010 00An abs16...; mov (abs16),An (abs16 is zero-extended)
362 8.0xfa+4.0xa,00,2.AN0+8.IMM16A+8.IMM16B:D2d:::mov
363 "mov"
364 *mn10300
365 {
366 /* OP_FAA00000 (); */
367 PC = cia;
368 State.regs[REG_A0 + AN0] = load_word (FETCH16(IMM16A, IMM16B));
369 }
370
371
372 // 1111 1100 1010 00An abs32...; mov (abs32),An
373 8.0xfc+4.0xa,00,2.AN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4e:::mov
374 "mov"
375 *mn10300
376 {
377 /* OP_FCA00000 (); */
378 PC = cia;
379 State.regs[REG_A0 + AN0]
380 = load_word (FETCH32(IMM32A, IMM32B, IMM32C, IMM32D));
381 }
382
383
384 // 1111 1000 1111 00Am d8......; mov (d8,Am),SP (d8 is sign-extended)
385 8.0xf8+4.0xf,00,2.AM0+8.D8:D1b:::mov
386 "mov"
387 *mn10300
388 {
389 /* OP_F8F000 (); */
390 PC = cia;
391 State.regs[REG_SP]
392 = load_word ((State.regs[REG_A0 + AM0] + EXTEND8 (D8)));
393 }
394
395
396 // 0110 DmAn; mov Dm,(An)
397 4.0x6,2.DM1,2.AN0:S0d:::mov
398 "mov"
399 *mn10300
400 {
401 /* OP_60 (); */
402 PC = cia;
403 store_word (State.regs[REG_A0 + AN0], State.regs[REG_D0 + DM1]);
404 }
405
406
407 // 1111 1000 0001 DmAn d8......; mov Dm,(d8,An) (d8 is sign-extended)
408 8.0xf8+4.0x1,2.DM1,2.AN0+8.D8:D1c:::mov
409 "mov"
410 *mn10300
411 {
412 /* OP_F81000 (); */
413 PC = cia;
414 store_word ((State.regs[REG_A0 + AN0] + EXTEND8 (D8)),
415 State.regs[REG_D0 + DM1]);
416 }
417
418
419 // 1111 1010 0001 DmAn d16.....; mov Dm,(d16,An) (d16 is sign-extended.)
420 8.0xfa+4.0x1,2.DM1,2.AN0+8.D16A+8.D16B:D2e:::mov
421 "mov"
422 *mn10300
423 {
424 /* OP_FA100000 (); */
425 PC = cia;
426 store_word ((State.regs[REG_A0 + AN0] + EXTEND16 (FETCH16(D16A, D16B))),
427 State.regs[REG_D0 + DM1]);
428 }
429
430
431 // 1111 1100 0001 DmAn d32.....; mov Dm,(d32,An)
432 8.0xfc+4.0x1,2.DM1,2.AN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4f:::mov
433 "mov"
434 *mn10300
435 {
436 /* OP_FC100000 (); */
437 PC = cia;
438 store_word ((State.regs[REG_A0 + AN0]
439 + FETCH32(IMM32A, IMM32B, IMM32C, IMM32D)),
440 State.regs[REG_D0 + DM1]);
441 }
442
443
444 // 0100 Dm10 d8......; mov Dm,(d8,SP) (d8 is zero-extended)
445 4.0x4,2.DM1,10+8.D8:S1b:::mov
446 "mov"
447 *mn10300
448 {
449 /* OP_4200 (); */
450 PC = cia;
451 store_word (State.regs[REG_SP] + D8, State.regs[REG_D0 + DM1]);
452 }
453
454
455 // 1111 1010 1001 Dm01 d16.....; mov Dm,(d16,SP) (d16 is zero-extended.)
456 8.0xfa+4.0x9,2.DM1,01+8.IMM16A+8.IMM16B:D2f:::mov
457 "mov"
458 *mn10300
459 {
460 /* OP_FA910000 (); */
461 PC = cia;
462 store_word (State.regs[REG_SP] + FETCH16(IMM16A, IMM16B),
463 State.regs[REG_D0 + DM1]);
464 }
465
466
467 // 1111 1100 1001 Dm01 d32.....; mov Dm,(d32,SP)
468 8.0xfc+4.0x9,2.DM1,01+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4g:::mov
469 "mov"
470 *mn10300
471 {
472 /* OP_FC910000 (); */
473 PC = cia;
474 store_word (State.regs[REG_SP] + FETCH32(IMM32A, IMM32B, IMM32C, IMM32D),
475 State.regs[REG_D0 + DM1]);
476 }
477
478
479 // 1111 0011 01Dm DiAn; mov Dm,(Di,An)
480 8.0xf3+01,2.DM2,2.DI,2.AN0:D0j:::mov
481 "mov"
482 *mn10300
483 {
484 /* OP_F340 (); */
485 PC = cia;
486 store_word ((State.regs[REG_A0 + AN0] + State.regs[REG_D0 + DI]),
487 State.regs[REG_D0 + DM2]);
488 }
489
490
491 // 0000 Dm01 abs16..., mov Dm,(abs16) (abs16 is zero-extended).
492 4.0x0,2.DM1,01+8.IMM16A+8.IMM16B:S2a:::mov
493 "mov"
494 *mn10300
495 {
496 /* OP_10000 (); */
497 PC = cia;
498 store_word (FETCH16(IMM16A, IMM16B), State.regs[REG_D0 + DM1]);
499 }
500
501
502 // 1111 1100 1000 Dm01 abs32...; mov Dm,(abs32)
503 8.0xfc+4.0x8,2.DM1,01+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4h:::mov
504 "mov"
505 *mn10300
506 {
507 /* OP_FC810000 (); */
508 PC = cia;
509 store_word (FETCH32(IMM32A, IMM32B, IMM32C, IMM32D),
510 State.regs[REG_D0 + DM1]);
511 }
512
513
514 // 1111 0000 0001 AmAn; mov Am,(An)
515 8.0xf0+4.0x1,2.AM1,2.AN0:D0k:::mov
516 "mov"
517 *mn10300
518 {
519 /* OP_F010 (); */
520 PC = cia;
521 store_word (State.regs[REG_A0 + AN0], State.regs[REG_A0 + AM1]);
522 }
523
524
525 // 1111 1000 0011 AmAn d8......; mov Am,(d8,An) (d8 is sign-extended)
526 8.0xf8+4.0x3,2.AM1,2.AN0+8.D8:D1d:::mov
527 "mov"
528 *mn10300
529 {
530 /* OP_F83000 (); */
531 PC = cia;
532 store_word ((State.regs[REG_A0 + AN0] + EXTEND8 (D8)),
533 State.regs[REG_A0 + AM1]);
534 }
535
536
537 // 1111 1010 0011 AmAn d16.....; mov Am,(d16,An) (d16 is sign-extended.)
538 8.0xfa+4.0x3,2.AM1,2.AN0+8.D16A+8.D16B:D2g:::mov
539 "mov"
540 *mn10300
541 {
542 /* OP_FA300000 (); */
543 PC = cia;
544 store_word ((State.regs[REG_A0 + AN0] + EXTEND16 (FETCH16(D16A, D16B))),
545 State.regs[REG_A0 + AM1]);
546 }
547
548
549 // 1111 1100 0011 AmAn d32.....; mov Am,(d32,An)
550 8.0xfc+4.0x3,2.AM1,2.AN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4i:::mov
551 "mov"
552 *mn10300
553 {
554 /* OP_FC300000 (); */
555 PC = cia;
556 store_word ((State.regs[REG_A0 + AN0]
557 + FETCH32(IMM32A, IMM32B, IMM32C, IMM32D)),
558 State.regs[REG_A0 + AM1]);
559 }
560
561
562 // 0100 Am11 d8......; mov Am,(d8,SP) (d8 is zero-extended)
563 4.0x4,2.AM1,11+8.D8:S1c:::mov
564 "mov"
565 *mn10300
566 {
567 /* OP_4300 (); */
568 PC = cia;
569 store_word (State.regs[REG_SP] + (D8), State.regs[REG_A0 + (AM1)]);
570 }
571
572
573 // 1111 1010 1001 Am00 d16.....; mov Am,(d16,SP) (d16 is zero-extended.)
574 8.0xfa+4.0x9,2.AM1,00+8.IMM16A+8.IMM16B:D2h:::mov
575 "mov"
576 *mn10300
577 {
578 /* OP_FA900000 (); */
579 PC = cia;
580 store_word (State.regs[REG_SP] + FETCH16(IMM16A, IMM16B),
581 State.regs[REG_A0 + AM1]);
582 }
583
584
585 // 1111 1100 1001 Am00 d32.....; mov Am,(d32,SP)
586 8.0xfc+4.0x9,2.AM1,00+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4j:::mov
587 "mov"
588 *mn10300
589 {
590 /* OP_FC900000 (); */
591 PC = cia;
592 store_word (State.regs[REG_SP] + FETCH32(IMM32A, IMM32B, IMM32C, IMM32D),
593 State.regs[REG_A0 + AM1]);
594 }
595
596
597 // 1111 0011 11Am DiAn; mov Am,(Di,An)
598 8.0xf3+11,2.AM2,2.DI,2.AN0:D0l:::mov
599 "mov"
600 *mn10300
601 {
602 /* OP_F3C0 (); */
603 PC = cia;
604 store_word ((State.regs[REG_A0 + AN0] + State.regs[REG_D0 + DI]),
605 State.regs[REG_A0 + AM2]);
606 }
607
608
609 // 1111 1010 1000 Am00 abs16...; mov Am,(abs16) (abs16 is zero-extended)
610 8.0xfa+4.0x8,2.AM1,00+8.IMM16A+8.IMM16B:D2i:::mov
611 "mov"
612 *mn10300
613 {
614 /* OP_FA800000 (); */
615 PC = cia;
616 store_word (FETCH16(IMM16A, IMM16B),
617 State.regs[REG_A0 + AM1]);
618 }
619
620
621 // 1111 1100 1000 Am00 abs32...; mov Am,(abs32)
622 8.0xfc+4.0x8,2.AM1,00+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4k:::mov
623 "mov"
624 *mn10300
625 {
626 /* OP_FC800000 (); */
627 PC = cia;
628 store_word (FETCH32(IMM32A, IMM32B, IMM32C, IMM32D),
629 State.regs[REG_A0 + AM1]);
630 }
631
632
633 // 1111 1000 1111 01An d8......; mov SP,(d8,An) (d8 is sign-extended)
634 8.0xf8+4.0xf,01,2.AN0+8.D8:D1e:::mov
635 "mov"
636 *mn10300
637 {
638 /* OP_F8F400 (); */
639 PC = cia;
640 store_word (State.regs[REG_A0 + AN0] + EXTEND8 (D8),
641 State.regs[REG_SP]);
642 }
643
644
645 // 0010 11Dn imm16...; mov imm16,Dn (imm16 is sign-extended)
646 4.0x2,11,2.DN0+8.IMM16A+8.IMM16B:S2b:::mov
647 "mov"
648 *mn10300
649 {
650 /* OP_2C0000 (); */
651 unsigned long value;
652
653 PC = cia;
654 value = EXTEND16 (FETCH16(IMM16A, IMM16B));
655 State.regs[REG_D0 + DN0] = value;
656 }
657
658
659 // 1111 1100 1100 11Dn imm32...; mov imm32,Dn
660 8.0xfc+4.0xc,11,2.DN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4l:::mov
661 "mov"
662 *mn10300
663 {
664 /* OP_FCCC0000 (); */
665 unsigned long value;
666
667 PC = cia;
668 value = FETCH32(IMM32A, IMM32B, IMM32C, IMM32D);
669 State.regs[REG_D0 + DN0] = value;
670 }
671
672
673 // 0010 01An imm16...; mov imm16,An (imm16 is zero-extended)
674 4.0x2,01,2.AN0+8.IMM16A+8.IMM16B:S2c:::mov
675 "mov"
676 *mn10300
677 {
678 /* OP_240000 (); */
679 unsigned long value;
680
681 PC = cia;
682 value = FETCH16(IMM16A, IMM16B);
683 State.regs[REG_A0 + AN0] = value;
684 }
685
686
687 // 1111 1100 1101 11An imm32...; mov imm32,An
688 8.0xfc+4.0xd,11,2.AN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4m:::mov
689 "mov"
690 *mn10300
691 {
692 /* OP_FCDC0000 (); */
693 PC = cia;
694 State.regs[REG_A0 + AN0] = FETCH32(IMM32A, IMM32B, IMM32C, IMM32D);
695 }
696
697
698 // 1111 0000 0100 DnAm; movbu (Am),Dn
699 8.0xf0+4.0x4,2.DN1,2.AM0:D0:::movbu
700 "movbu"
701 *mn10300
702 {
703 /* OP_F040 (); */
704 PC = cia;
705 State.regs[REG_D0 + DN1]
706 = load_byte (State.regs[REG_A0 + AM0]);
707 }
708
709
710 // 1111 1000 0100 DnAm d8......; movbu (d8,Am),Dn (d8 is sign-extended)
711 8.0xf8+4.0x4,2.DN1,2.AM0+8.D8:D1f:::movbu
712 "movbu"
713 *mn10300
714 {
715 /* OP_F84000 (); */
716 PC = cia;
717 State.regs[REG_D0 + DN1]
718 = load_byte ((State.regs[REG_A0 + AM0] + EXTEND8 (D8)));
719 }
720
721
722 // 1111 1010 0100 DnAm d16.....; movbu (d16,Am),Dn (d16 is sign-extended.)
723 8.0xfa+4.0x4,2.DN1,2.AM0+8.D16A+8.D16B:D2:::movbu
724 "movbu"
725 *mn10300
726 {
727 /* OP_FA400000 (); */
728 PC = cia;
729 State.regs[REG_D0 + DN1]
730 = load_byte ((State.regs[REG_A0 + AM0]
731 + EXTEND16 (FETCH16(D16A, D16B))));
732 }
733
734
735 // 1111 1100 0100 DnAm d32.....; movbu (d32,Am),Dn
736 8.0xfc+4.0x4,2.DN1,2.AM0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4:::movbu
737 "movbu"
738 *mn10300
739 {
740 /* OP_FC400000 (); */
741 PC = cia;
742 State.regs[REG_D0 + DN1]
743 = load_byte ((State.regs[REG_A0 + AM0]
744 + FETCH32(IMM32A, IMM32B, IMM32C, IMM32D)));
745 }
746
747
748 // 1111 1000 1011 10Dn d8......; movbu (d8,SP),Dn (d8 is zero-extended)
749 8.0xf8+4.0xb,10,2.DN0+8.D8:D1a:::movbu
750 "movbu"
751 *mn10300
752 {
753 /* OP_F8B800 (); */
754 PC = cia;
755 State.regs[REG_D0 + DN0]
756 = load_byte ((State.regs[REG_SP] + (D8)));
757 }
758
759
760 // 1111 1010 1011 10Dn d16.....; movbu (d16,SP),Dn (d16 is zero-extended.)
761 8.0xfa+4.0xb,10,2.DN0+8.IMM16A+8.IMM16B:D2a:::movbu
762 "movbu"
763 *mn10300
764 {
765 /* OP_FAB80000 (); */
766 PC = cia;
767 State.regs[REG_D0 + DN0]
768 = load_byte ((State.regs[REG_SP]
769 + FETCH16(IMM16A, IMM16B)));
770 }
771
772
773 // 1111 1100 1011 10Dn d32.....; movbu (d32,SP),Dn
774 8.0xfc+4.0xb,10,2.DN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4a:::movbu
775 "movbu"
776 *mn10300
777 {
778 /* OP_FCB80000 (); */
779 PC = cia;
780 State.regs[REG_D0 + DN0]
781 = load_byte (State.regs[REG_SP]
782 + FETCH32(IMM32A, IMM32B, IMM32C, IMM32D));
783 }
784
785
786 // 1111 0100 00Dn DiAm; movbu (Di,Am),Dn
787 8.0xf4+00,2.DN2,2.DI,2.AM0:D0a:::movbu
788 "movbu"
789 *mn10300
790 {
791 /* OP_F400 (); */
792 PC = cia;
793 State.regs[REG_D0 + DN2]
794 = load_byte ((State.regs[REG_A0 + AM0]
795 + State.regs[REG_D0 + DI]));
796 }
797
798
799 // 0011 01Dn abs16...; movbu (abs16),Dn (abs16 is zero-extended)
800 4.0x3,01,2.DN0+8.IMM16A+8.IMM16B:S2:::movbu
801 "movbu"
802 *mn10300
803 {
804 /* OP_340000 (); */
805 PC = cia;
806 State.regs[REG_D0 + DN0] = load_byte (FETCH16(IMM16A, IMM16B));
807 }
808
809
810 // 1111 1100 1010 10Dn abs32...; movbu (abs32),Dn
811 8.0xfc+4.0xa,10,2.DN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4b:::movbu
812 "movbu"
813 *mn10300
814 {
815 /* OP_FCA80000 (); */
816 PC = cia;
817 State.regs[REG_D0 + DN0]
818 = load_byte (FETCH32(IMM32A, IMM32B, IMM32C, IMM32D));
819 }
820
821
822 // 1111 0000 0101 DmAn; movbu Dm,(An)
823 8.0xf0+4.0x5,2.DM1,2.AN0:D0b:::movbu
824 "movbu"
825 *mn10300
826 {
827 /* OP_F050 (); */
828 PC = cia;
829 store_byte (State.regs[REG_A0 + AN0], State.regs[REG_D0 + DM1]);
830 }
831
832
833 // 1111 1000 0101 DmAn d8......; movbu Dm,(d8,An) (d8 is sign-extended)
834 8.0xf8+4.0x5,2.DM1,2.AN0+8.D8:D1b:::movbu
835 "movbu"
836 *mn10300
837 {
838 /* OP_F85000 (); */
839 PC = cia;
840 store_byte ((State.regs[REG_A0 + AN0] + EXTEND8 (D8)),
841 State.regs[REG_D0 + DM1]);
842 }
843
844
845 // 1111 1010 0101 DmAn d16.....; movbu Dm,(d16,An) (d16 is sign-extended.)
846 8.0xfa+4.0x5,2.DM1,2.AN0+8.D16A+8.D16B:D2b:::movbu
847 "movbu"
848 *mn10300
849 {
850 /* OP_FA500000 (); */
851 PC = cia;
852 store_byte ((State.regs[REG_A0 + AN0] + EXTEND16 (FETCH16(D16A, D16B))),
853 State.regs[REG_D0 + DM1]);
854 }
855
856
857 // 1111 1100 0101 DmAn d32.....; movbu Dm,(d32,An)
858 8.0xfc+4.0x5,2.DM1,2.AN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4c:::movbu
859 "movbu"
860 *mn10300
861 {
862 /* OP_FC500000 (); */
863 PC = cia;
864 store_byte ((State.regs[REG_A0 + AN0]
865 + FETCH32(IMM32A, IMM32B, IMM32C, IMM32D)),
866 State.regs[REG_D0 + DM1]);
867 }
868
869
870 // 1111 1000 1001 Dm10 d8......; movbu Dm,(d8,SP) (d8 is zero-extended)
871 8.0xf8+4.0x9,2.DM1,10+8.D8:D1c:::movbu
872 "movbu"
873 *mn10300
874 {
875 /* OP_F89200 (); */
876 PC = cia;
877 store_byte (State.regs[REG_SP] + (D8), State.regs[REG_D0 + DM1]);
878 }
879
880
881 // 1111 1010 1001 Dm10 d16.....; movbu Dm,(d16,SP) (d16 is zero-extended.)
882 8.0xfa+4.0x9,2.DM1,10+8.IMM16A+8.IMM16B:D2c:::movbu
883 "movbu"
884 *mn10300
885 {
886 /* OP_FA920000 (); */
887 PC = cia;
888 store_byte (State.regs[REG_SP] + FETCH16(IMM16A, IMM16B),
889 State.regs[REG_D0 + DM1]);
890 }
891
892
893 // 1111 1100 1001 Dm10 d32.....; movbu Dm,(d32,SP)
894 8.0xfc+4.0x9,2.DM1,10+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4d:::movbu
895 "movbu"
896 *mn10300
897 {
898 /* OP_FC920000 (); */
899 PC = cia;
900 store_byte (State.regs[REG_SP] + FETCH32(IMM32A, IMM32B, IMM32C, IMM32D),
901 State.regs[REG_D0 + DM1]);
902 }
903
904
905 // 1111 0100 01Dm DiAn; movbu Dm,(Di,An)
906 8.0xf4+01,2.DM2,2.DI,2.AN0:D0c:::movbu
907 "movbu"
908 *mn10300
909 {
910 /* OP_F440 (); */
911 PC = cia;
912 store_byte ((State.regs[REG_A0 + AN0] + State.regs[REG_D0 + DI]),
913 State.regs[REG_D0 + DM2]);
914 }
915
916
917 // 0000 Dm10 abs16...; movbu Dm,(abs16) (abs16 is zero-extended)
918 4.0x0,2.DM1,10+8.IMM16A+8.IMM16B:S2a:::movbu
919 "movbu"
920 *mn10300
921 {
922 /* OP_20000 (); */
923 PC = cia;
924 store_byte (FETCH16(IMM16A, IMM16B),
925 State.regs[REG_D0 + DM1]);
926 }
927
928
929 // 1111 1100 1000 Dm10 abs32...; movbu Dm,(abs32)
930 8.0xfc+4.0x8,2.DM1,10+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4e:::movbu
931 "movbu"
932 *mn10300
933 {
934 /* OP_FC820000 (); */
935 PC = cia;
936 store_byte (FETCH32(IMM32A, IMM32B, IMM32C, IMM32D),
937 State.regs[REG_D0 + DM1]);
938 }
939
940
941 // 1111 0000 0110 DnAm; movhu (Am),Dn
942 8.0xf0+4.0x6,2.DN1,2.AM0:D0:::movhu
943 "movhu"
944 *mn10300
945 {
946 /* OP_F060 (); */
947 PC = cia;
948 State.regs[REG_D0 + DN1]
949 = load_half (State.regs[REG_A0 + AM0]);
950 }
951
952
953 // 1111 1000 0110 DnAm d8......; movhu (d8,Am),Dn (d8 is sign-extended)
954 8.0xf8+4.0x6,2.DN1,2.AM0+8.D8:D1d:::movhu
955 "movhu"
956 *mn10300
957 {
958 /* OP_F86000 (); */
959 PC = cia;
960 State.regs[REG_D0 + DN1]
961 = load_half ((State.regs[REG_A0 + AM0] + EXTEND8 (D8)));
962 }
963
964
965 // 1111 1010 0110 DnAm d16.....; movhu (d16,Am),Dn (d16 is sign-extended.)
966 8.0xfa+4.0x6,2.DN1,2.AM0+8.D16A+8.D16B:D2:::movhu
967 "movhu"
968 *mn10300
969 {
970 /* OP_FA600000 (); */
971 PC = cia;
972 State.regs[REG_D0 + DN1]
973 = load_half ((State.regs[REG_A0 + AM0]
974 + EXTEND16 (FETCH16(D16A, D16B))));
975 }
976
977
978 // 1111 1100 0110 DnAm d32.....; movhu (d32,Am),Dn
979 8.0xfc+4.0x6,2.DN1,2.AM0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4:::movhu
980 "movhu"
981 *mn10300
982 {
983 /* OP_FC600000 (); */
984 PC = cia;
985 State.regs[REG_D0 + DN1]
986 = load_half ((State.regs[REG_A0 + AM0]
987 + FETCH32(IMM32A, IMM32B, IMM32C, IMM32D)));
988 }
989
990
991 // 1111 1000 1011 11Dn d8.....; movhu (d8,SP),Dn (d8 is zero-extended)
992 8.0xf8+4.0xb,11,2.DN0+8.D8:D1a:::movhu
993 "movhu"
994 *mn10300
995 {
996 /* OP_F8BC00 (); */
997 PC = cia;
998 State.regs[REG_D0 + DN0]
999 = load_half ((State.regs[REG_SP] + (D8)));
1000 }
1001
1002
1003 // 1111 1010 1011 11Dn d16.....; movhu (d16,SP),Dn (d16 is zero-extended.)
1004 8.0xfa+4.0xb,11,2.DN0+8.IMM16A+8.IMM16B:D2a:::movhu
1005 "movhu"
1006 *mn10300
1007 {
1008 /* OP_FABC0000 (); */
1009 PC = cia;
1010 State.regs[REG_D0 + DN0]
1011 = load_half ((State.regs[REG_SP] + FETCH16(IMM16A, IMM16B)));
1012 }
1013
1014
1015 // 1111 1100 1011 11Dn d32.....; movhu (d32,SP),Dn
1016 8.0xfc+4.0xb,11,2.DN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4a:::movhu
1017 "movhu"
1018 *mn10300
1019 {
1020 /* OP_FCBC0000 (); */
1021 PC = cia;
1022 State.regs[REG_D0 + DN0]
1023 = load_half (State.regs[REG_SP] + FETCH32(IMM32A, IMM32B, IMM32C, IMM32D));
1024 }
1025
1026
1027 // 1111 0100 10Dn DiAm; movhu (Di,Am),Dn
1028 8.0xf4+10,2.DN2,2.DI,2.AM0:D0a:::movhu
1029 "movhu"
1030 *mn10300
1031 {
1032 /* OP_F480 (); */
1033 PC = cia;
1034 State.regs[REG_D0 + DN2]
1035 = load_half ((State.regs[REG_A0 + AM0] + State.regs[REG_D0 + DI]));
1036 }
1037
1038
1039 // 0011 10Dn abs16...; movhu (abs16),Dn (abs16 is zero-extended)
1040 4.0x3,10,2.DN0+8.IMM16A+8.IMM16B:S2:::movhu
1041 "movhu"
1042 *mn10300
1043 {
1044 /* OP_380000 (); */
1045 PC = cia;
1046 State.regs[REG_D0 + DN0] = load_half (FETCH16(IMM16A, IMM16B));
1047 }
1048
1049
1050 // 1111 1100 1010 11Dn abs32...; movhu (abs32),Dn
1051 8.0xfc+4.0xa,11,2.DN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4b:::movhu
1052 "movhu"
1053 *mn10300
1054 {
1055 /* OP_FCAC0000 (); */
1056 PC = cia;
1057 State.regs[REG_D0 + DN0]
1058 = load_half (FETCH32(IMM32A, IMM32B, IMM32C, IMM32D));
1059 }
1060
1061
1062 // 1111 0000 0111 DmAn; movhu Dm,(An)
1063 8.0xf0+4.0x7,2.DM1,2.AN0:D0b:::movhu
1064 "movhu"
1065 *mn10300
1066 {
1067 /* OP_F070 (); */
1068 PC = cia;
1069 store_half (State.regs[REG_A0 + AN0],
1070 State.regs[REG_D0 + DM1]);
1071 }
1072
1073
1074 // 1111 1000 0111 DmAn d8......; movhu Dm,(d8,An) (d8 is sign-extended)
1075 8.0xf8+4.0x7,2.DM1,2.AN0+8.D8:D1b:::movhu
1076 "movhu"
1077 *mn10300
1078 {
1079 /* OP_F87000 (); */
1080 PC = cia;
1081 store_half ((State.regs[REG_A0 + AN0] + EXTEND8 (D8)),
1082 State.regs[REG_D0 + DM1]);
1083 }
1084
1085
1086 // 1111 1010 0111 DnAm d16.....; movhu Dm,(d16,An) (d16 is sign-extended.)
1087 8.0xfa+4.0x7,2.DM1,2.AN0+8.D16A+8.D16B:D2b:::movhu
1088 "movhu"
1089 *mn10300
1090 {
1091 /* OP_FA700000 (); */
1092 PC = cia;
1093 store_half ((State.regs[REG_A0 + AN0] + EXTEND16 (FETCH16(D16A, D16B))),
1094 State.regs[REG_D0 + DM1]);
1095 }
1096
1097
1098 // 1111 1100 0111 DmAn d32.....; movhu Dm,(d32,An)
1099 8.0xfc+4.0x7,2.DM1,2.AN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4c:::movhu
1100 "movhu"
1101 *mn10300
1102 {
1103 /* OP_FC700000 (); */
1104 PC = cia;
1105 store_half ((State.regs[REG_A0 + AN0]
1106 + FETCH32(IMM32A, IMM32B, IMM32C, IMM32D)),
1107 State.regs[REG_D0 + DM1]);
1108 }
1109
1110
1111 // 1111 1000 1001 Dm11 d8....; movhu Dm,(d8,SP) (d8 is zero-extended)
1112 8.0xf8+4.0x9,2.DM1,11+8.D8:D1c:::movhu
1113 "movhu"
1114 *mn10300
1115 {
1116 /* OP_F89300 (); */
1117 PC = cia;
1118 store_half (State.regs[REG_SP] + (D8),
1119 State.regs[REG_D0 + DM1]);
1120 }
1121
1122
1123 // 1111 1010 1001 Dm11 d16.....; movhu Dm,(d16,SP) (d16 is zero-extended.)
1124 8.0xfa+4.0x9,2.DM1,11+8.IMM16A+8.IMM16B:D2c:::movhu
1125 "movhu"
1126 *mn10300
1127 {
1128 /* OP_FA930000 (); */
1129 PC = cia;
1130 store_half (State.regs[REG_SP] + FETCH16(IMM16A, IMM16B),
1131 State.regs[REG_D0 + DM1]);
1132 }
1133
1134
1135 // 1111 1100 1001 Dm11 d32.....; movhu Dm,(d32,SP)
1136 8.0xfc+4.0x9,2.DM1,11+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4d:::movhu
1137 "movhu"
1138 *mn10300
1139 {
1140 /* OP_FC930000 (); */
1141 PC = cia;
1142 store_half (State.regs[REG_SP] + FETCH32(IMM32A, IMM32B, IMM32C, IMM32D),
1143 State.regs[REG_D0 + DM1]);
1144 }
1145
1146
1147 // 1111 0100 11Dm DiAn; movhu Dm,(Di,An)
1148 8.0xf4+11,2.DM2,2.DI,2.AN0:D0c:::movhu
1149 "movhu"
1150 *mn10300
1151 {
1152 /* OP_F4C0 (); */
1153 PC = cia;
1154 store_half ((State.regs[REG_A0 + AN0] + State.regs[REG_D0 + DI]),
1155 State.regs[REG_D0 + DM2]);
1156 }
1157
1158
1159 // 0000 Dm11 abs16...; movhu Dm,(abs16) (abs16 is zero-extended)
1160 4.0x0,2.DM1,11+8.IMM16A+8.IMM16B:S2a:::movhu
1161 "movhu"
1162 *mn10300
1163 {
1164 /* OP_30000 (); */
1165 PC = cia;
1166 store_half (FETCH16(IMM16A, IMM16B), State.regs[REG_D0 + DM1]);
1167 }
1168
1169
1170 // 1111 1100 1000 Dm11 abs32...; movhu Dm,(abs32)
1171 8.0xfc+4.0x8,2.DM1,11+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4e:::movhu
1172 "movhu"
1173 *mn10300
1174 {
1175 /* OP_FC830000 (); */
1176 PC = cia;
1177 store_half (FETCH32(IMM32A, IMM32B, IMM32C, IMM32D),
1178 State.regs[REG_D0 + DM1]);
1179 }
1180
1181
1182 // 1111 0010 1101 00Dn; ext Dn
1183 8.0xf2+4.0xd,00,2.DN0:D0:::ext
1184 "ext"
1185 *mn10300
1186 {
1187 /* OP_F2D0 (); */
1188 PC = cia;
1189 if (State.regs[REG_D0 + DN0] & 0x80000000)
1190 State.regs[REG_MDR] = -1;
1191 else
1192 State.regs[REG_MDR] = 0;
1193 }
1194
1195
1196 // 0001 00Dn; extb Dn
1197 4.0x1,00,2.DN0:S0:::extb
1198 "extb"
1199 *mn10300
1200 {
1201 /* OP_10 (); */
1202 PC = cia;
1203 State.regs[REG_D0 + DN0] = EXTEND8 (State.regs[REG_D0 + DN0]);
1204 }
1205
1206
1207 // 0001 01Dn; extbu Dn
1208 4.0x1,01,2.DN0:S0:::extbu
1209 "extbu"
1210 *mn10300
1211 {
1212 /* OP_14 (); */
1213 PC = cia;
1214 State.regs[REG_D0 + DN0] &= 0xff;
1215 }
1216
1217
1218 // 0001 10Dn; exth Dn
1219 4.0x1,10,2.DN0:S0:::exth
1220 "exth"
1221 *mn10300
1222 {
1223 /* OP_18 (); */
1224 PC = cia;
1225 State.regs[REG_D0 + DN0] = EXTEND16 (State.regs[REG_D0 + DN0]);
1226 }
1227
1228
1229 // 0001 11Dn; exthu Dn
1230 4.0x1,11,2.DN0:S0:::exthu
1231 "exthu"
1232 *mn10300
1233 {
1234 /* OP_1C (); */
1235 PC = cia;
1236 State.regs[REG_D0 + DN0] &= 0xffff;
1237 }
1238
1239
1240 // 0000 Dn00; clr Dn
1241 4.0x0,2.DN1,00:S0:::clr
1242 "clr"
1243 *mn10300
1244 {
1245 /* OP_0 (); */
1246 PC = cia;
1247 State.regs[REG_D0 + DN1] = 0;
1248
1249 PSW |= PSW_Z;
1250 PSW &= ~(PSW_V | PSW_C | PSW_N);
1251 }
1252
1253
1254 // 1110 DmDn; add Dm,Dn
1255 4.0xe,2.DM1,2.DN0:S0:::add
1256 "add"
1257 *mn10300
1258 {
1259 /* OP_E0 (); */
1260 PC = cia;
1261 genericAdd(State.regs[REG_D0 + DM1], REG_D0 + DN0);
1262 }
1263
1264 // 1111 0001 0110 DmAn; add Dm,An
1265 8.0xf1+4.0x6,2.DM1,2.AN0:D0:::add
1266 "add"
1267 *mn10300
1268 {
1269 /* OP_F160 (); */
1270 PC = cia;
1271 genericAdd(State.regs[REG_D0 + DM1], REG_A0 + AN0);
1272 }
1273
1274
1275 // 1111 0001 0101 AmDn; add Am,Dn
1276 8.0xf1+4.0x5,2.AM1,2.DN0:D0a:::add
1277 "add"
1278 *mn10300
1279 {
1280 /* OP_F150 (); */
1281 PC = cia;
1282 genericAdd(State.regs[REG_A0 + AM1], REG_D0 + DN0);
1283 }
1284
1285
1286 // 1111 0001 0111 AmAn; add Am,An
1287 8.0xf1+4.0x7,2.AM1,2.AN0:D0b:::add
1288 "add"
1289 *mn10300
1290 {
1291 /* OP_F170 (); */
1292 PC = cia;
1293 genericAdd(State.regs[REG_A0 + AM1], REG_A0 + AN0);
1294 }
1295
1296
1297 // 0010 10Dn imm8....; add imm8,Dn (imm8 is sign-extended)
1298 4.0x2,10,2.DN0+8.IMM8:S1:::add
1299 "add"
1300 *mn10300
1301 {
1302 /* OP_2800 (); */
1303 PC = cia;
1304 genericAdd(EXTEND8(IMM8), REG_D0 + DN0);
1305 }
1306
1307
1308 // 1111 1010 1100 00Dn imm16...; add imm16,Dn
1309 8.0xfa+4.0xc,00,2.DN0+8.IMM16A+8.IMM16B:D2:::add
1310 "add"
1311 *mn10300
1312 {
1313 /* OP_FAC00000 (); */
1314 PC = cia;
1315 genericAdd(EXTEND16(FETCH16(IMM16A, IMM16B)), REG_D0 + DN0);
1316 }
1317
1318
1319 // 1111 1100 1100 00Dn imm32...; add imm32,Dn
1320 8.0xfc+4.0xc,00,2.DN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4:::add
1321 "add"
1322 *mn10300
1323 {
1324 /* OP_FCC00000 (); */
1325 PC = cia;
1326 genericAdd(FETCH32(IMM32A, IMM32B, IMM32C, IMM32D), REG_D0 + DN0);
1327 }
1328
1329
1330 // 0010 00An imm8....; add imm8,An (imm8 is sign-extended)
1331 4.0x2,00,2.AN0+8.IMM8:S1a:::add
1332 "add"
1333 *mn10300
1334 {
1335 /* OP_2000 (); */
1336 PC = cia;
1337 genericAdd(EXTEND8(IMM8), REG_A0 + AN0);
1338 }
1339
1340
1341 // 1111 1010 1101 00An imm16...; add imm16,An (imm16 is sign-extended.)
1342 8.0xfa+4.0xd,00,2.AN0+8.IMM16A+8.IMM16B:D2a:::add
1343 "add"
1344 *mn10300
1345 {
1346 /* OP_FAD00000 (); */
1347 PC = cia;
1348 genericAdd(EXTEND16(FETCH16(IMM16A, IMM16B)), REG_A0 + AN0);
1349 }
1350
1351
1352 // 1111 1100 1101 00An imm32...; add imm32,An
1353 8.0xfc+4.0xd,00,2.AN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4a:::add
1354 "add"
1355 *mn10300
1356 {
1357 /* OP_FCD00000 (); */
1358 PC = cia;
1359 genericAdd(FETCH32(IMM32A, IMM32B, IMM32C, IMM32D), REG_A0 + AN0);
1360 }
1361
1362
1363 // 1111 1000 1111 1110 imm8....; add imm8,SP (imm8 is sign-extended.)
1364 8.0xf8+8.0xfe+8.IMM8:D1:::add
1365 "add"
1366 *mn10300
1367 {
1368 /* OP_F8FE00 (); */
1369 unsigned long imm;
1370
1371 /* Note: no PSW changes. */
1372 PC = cia;
1373 imm = EXTEND8 (IMM8);
1374 State.regs[REG_SP] += imm;
1375 }
1376
1377
1378 // 1111 1010 1111 1110 imm16...; add imm16,SP (imm16 is sign-extended.)
1379 8.0xfa+8.0xfe+8.IMM16A+8.IMM16B:D2b:::add
1380 "add"
1381 *mn10300
1382 {
1383 /* OP_FAFE0000 (); */
1384 unsigned long imm;
1385
1386 /* Note: no PSW changes. */
1387 PC = cia;
1388 imm = EXTEND16 (FETCH16(IMM16A, IMM16B));
1389 State.regs[REG_SP] += imm;
1390 }
1391
1392
1393 // 1111 1100 1111 1110 imm32...; add imm32,SP
1394 8.0xfc+8.0xfe+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4b:::add
1395 "add"
1396 *mn10300
1397 {
1398 /* OP_FCFE0000 (); */
1399 unsigned long imm;
1400
1401 /* Note: no PSW changes. */
1402 PC = cia;
1403 imm = FETCH32(IMM32A, IMM32B, IMM32C, IMM32D);
1404 State.regs[REG_SP] += imm;
1405 }
1406
1407
1408 // 1111 0001 0100 DmDn; addc Dm,Dn
1409 8.0xf1+4.0x4,2.DM1,2.DN0:D0:::addc
1410 "addc"
1411 *mn10300
1412 {
1413 /* OP_F140 (); */
1414 int z, c, n, v;
1415 unsigned long reg1, reg2, sum;
1416
1417 PC = cia;
1418 reg1 = State.regs[REG_D0 + DM1];
1419 reg2 = State.regs[REG_D0 + DN0];
1420 sum = reg1 + reg2 + ((PSW & PSW_C) != 0);
1421 State.regs[REG_D0 + DN0] = sum;
1422
1423 z = ((PSW & PSW_Z) != 0) && (sum == 0);
1424 n = (sum & 0x80000000);
1425 c = (sum < reg1) || (sum < reg2);
1426 v = ((reg2 & 0x80000000) == (reg1 & 0x80000000)
1427 && (reg2 & 0x80000000) != (sum & 0x80000000));
1428
1429 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1430 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1431 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
1432 }
1433
1434
1435 // 1111 0001 0000 DmDn; sub Dm,Dn
1436 8.0xf1+4.0x0,2.DM1,2.DN0:D0:::sub
1437 "sub"
1438 *mn10300
1439 {
1440 /* OP_F100 (); */
1441 PC = cia;
1442 genericSub(State.regs[REG_D0 + DM1], REG_D0 + DN0);
1443 }
1444
1445 // 1111 0001 0010 DmAn; sub DmAn
1446 8.0xf1+4.0x2,2.DM1,2.AN0:D0a:::sub
1447 "sub"
1448 *mn10300
1449 {
1450 /* OP_F120 (); */
1451 PC = cia;
1452 genericSub(State.regs[REG_D0 + DM1], REG_A0 + AN0);
1453 }
1454
1455
1456 // 1111 0001 0001 AmDn; sub AmDn
1457 8.0xf1+4.0x1,2.AM1,2.DN0:D0b:::sub
1458 "sub"
1459 *mn10300
1460 {
1461 /* OP_F110 (); */
1462 PC = cia;
1463 genericSub(State.regs[REG_A0 + AM1], REG_D0 + DN0);
1464 }
1465
1466
1467 // 1111 0001 0011 AmAn; sub Am,An
1468 8.0xf1+4.0x3,2.AM1,2.AN0:D0c:::sub
1469 "sub"
1470 *mn10300
1471 {
1472 /* OP_F130 (); */
1473 PC = cia;
1474 genericSub(State.regs[REG_A0 + AM1], REG_A0 + AN0);
1475 }
1476
1477
1478 // 1111 1100 1100 01Dn imm32...; sub imm32,Dn
1479 8.0xfc+4.0xc,01,2.DN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4:::sub
1480 "sub"
1481 *mn10300
1482 {
1483 /* OP_FCC40000 (); */
1484 PC = cia;
1485 genericSub(FETCH32(IMM32A, IMM32B, IMM32C, IMM32D), REG_D0 + DN0);
1486 }
1487
1488
1489 // 1111 1100 1101 01An imm32...; sub imm32,An
1490 8.0xfc+4.0xd,01,2.AN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4a:::sub
1491 "sub"
1492 *mn10300
1493 {
1494 /* OP_FCD40000 (); */
1495 PC = cia;
1496 genericSub(FETCH32(IMM32A, IMM32B, IMM32C, IMM32D), REG_A0 + AN0);
1497 }
1498
1499
1500 // 1111 0001 1000 DmDn; subc Dm,Dn
1501 8.0xf1+4.0x8,2.DM1,2.DN0:D0:::subc
1502 "subc"
1503 *mn10300
1504 {
1505 /* OP_F180 (); */
1506 int z, c, n, v;
1507 unsigned long reg1, reg2, difference;
1508
1509 PC = cia;
1510 reg1 = State.regs[REG_D0 + DM1];
1511 reg2 = State.regs[REG_D0 + DN0];
1512 difference = reg2 - reg1 - ((PSW & PSW_C) != 0);
1513 State.regs[REG_D0 + DN0] = difference;
1514
1515 z = ((PSW & PSW_Z) != 0) && (difference == 0);
1516 n = (difference & 0x80000000);
1517 c = (reg1 > reg2);
1518 v = ((reg2 & 0x80000000) != (reg1 & 0x80000000)
1519 && (reg2 & 0x80000000) != (difference & 0x80000000));
1520
1521 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1522 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1523 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
1524 }
1525
1526
1527 // 1111 0010 0100 DmDn; mul Dm,Dn
1528 8.0xf2+4.0x4,2.DM1,2.DN0:D0:::mul
1529 "mul"
1530 *mn10300
1531 {
1532 /* OP_F240 (); */
1533 unsigned long long temp;
1534 int n, z;
1535
1536 PC = cia;
1537 temp = ((signed64)(signed32)State.regs[REG_D0 + DN0]
1538 * (signed64)(signed32)State.regs[REG_D0 + DM1]);
1539 State.regs[REG_D0 + DN0] = temp & 0xffffffff;
1540 State.regs[REG_MDR] = (temp & 0xffffffff00000000LL) >> 32;;
1541 z = (State.regs[REG_D0 + DN0] == 0);
1542 n = (State.regs[REG_D0 + DN0] & 0x80000000) != 0;
1543 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1544 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
1545 }
1546
1547
1548 // 1111 0010 0101 DmDn; mulu Dm,Dn
1549 8.0xf2+4.0x5,2.DM1,2.DN0:D0:::mulu
1550 "mulu"
1551 *mn10300
1552 {
1553 /* OP_F250 (); */
1554 unsigned long long temp;
1555 int n, z;
1556
1557 PC = cia;
1558 temp = ((unsigned64)State.regs[REG_D0 + DN0]
1559 * (unsigned64)State.regs[REG_D0 + DM1]);
1560 State.regs[REG_D0 + DN0] = temp & 0xffffffff;
1561 State.regs[REG_MDR] = (temp & 0xffffffff00000000LL) >> 32;
1562 z = (State.regs[REG_D0 + DN0] == 0);
1563 n = (State.regs[REG_D0 + DN0] & 0x80000000) != 0;
1564 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1565 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
1566 }
1567
1568
1569 // 1111 0010 0110 DmDn; div Dm,Dn
1570 8.0xf2+4.0x6,2.DM1,2.DN0:D0:::div
1571 "div"
1572 *mn10300
1573 {
1574 /* OP_F260 (); */
1575 signed64 temp;
1576 signed32 denom;
1577 int n, z, v;
1578
1579 PC = cia;
1580 denom = (signed32)State.regs[REG_D0 + DM1];
1581
1582 temp = State.regs[REG_MDR];
1583 temp <<= 32;
1584 temp |= State.regs[REG_D0 + DN0];
1585 if ( !(v = (0 == denom)) )
1586 {
1587 State.regs[REG_MDR] = temp % (signed32)State.regs[REG_D0 + DM1];
1588 temp /= (signed32)State.regs[REG_D0 + DM1];
1589 State.regs[REG_D0 + DN0] = temp & 0xffffffff;
1590 }
1591 else
1592 {
1593 State.regs[REG_MDR] = temp;
1594 State.regs[REG_D0 + DN0] = 0xff;
1595 }
1596 z = (State.regs[REG_D0 + DN0] == 0);
1597 n = (State.regs[REG_D0 + DN0] & 0x80000000) != 0;
1598 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1599 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (v ? PSW_V : 0));
1600 }
1601
1602
1603 // 1111 0010 0111 DmDn; divu Dm,Dn
1604 8.0xf2+4.0x7,2.DM1,2.DN0:D0:::divu
1605 "divu"
1606 *mn10300
1607 {
1608 /* OP_F270 (); */
1609 unsigned64 temp;
1610 unsigned32 denom;
1611 int n, z, v;
1612
1613 PC = cia;
1614 denom = (unsigned32)State.regs[REG_D0 + DM1];
1615 temp = State.regs[REG_MDR];
1616 temp <<= 32;
1617 temp |= State.regs[REG_D0 + DN0];
1618 if ( !(v = (0 == denom)) )
1619 {
1620 State.regs[REG_MDR] = temp % State.regs[REG_D0 + DM1];
1621 temp /= State.regs[REG_D0 + DM1];
1622 State.regs[REG_D0 + DN0] = temp & 0xffffffff;
1623 }
1624 else
1625 {
1626 State.regs[REG_MDR] = temp;
1627 State.regs[REG_D0 + DN0] = 0xff;
1628 }
1629 z = (State.regs[REG_D0 + DN0] == 0);
1630 n = (State.regs[REG_D0 + DN0] & 0x80000000) != 0;
1631 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1632 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (v ? PSW_V : 0));
1633 }
1634
1635
1636 // 0100 Dn00; inc Dn
1637 4.0x4,2.DN1,00:S0:::inc
1638 "inc"
1639 *mn10300
1640 {
1641 /* OP_40 (); */
1642 unsigned int imm;
1643
1644 PC = cia;
1645 imm = 1;
1646 genericAdd(imm, REG_D0 + DN1);
1647 }
1648
1649
1650 // 0100 An01
1651 4.0x4,2.AN1,01:S0a:::inc
1652 "inc"
1653 *mn10300
1654 {
1655 /* OP_41 (); */
1656 PC = cia;
1657 State.regs[REG_A0 + AN1] += 1;
1658 }
1659
1660
1661 // 0101 00An; inc4 An
1662 4.0x5,00,2.AN0:S0:::inc4
1663 "inc4"
1664 *mn10300
1665 {
1666 /* OP_50 (); */
1667 PC = cia;
1668 State.regs[REG_A0 + AN0] += 4;
1669 }
1670
1671
1672 // 1010 DnDn imm8....; cmp imm8,Dn (imm8 is sign-extended.)
1673 4.0xa,2.DM1,2.DN0=DM1+IMM8:S0i:::cmp
1674 "cmp"
1675 *mn10300
1676 {
1677 PC = cia;
1678 /* OP_A000 (); */
1679 genericCmp(EXTEND8 (IMM8), State.regs[REG_D0 + DN0]);
1680 }
1681
1682
1683 // 1010 DmDn; cmp Dm,Dn (Dm != Dn, see above when Dm == Dn)
1684 4.0xa,2.DM1,2.DN0!DM1:S0:::cmp
1685 "cmp"
1686 *mn10300
1687 {
1688 PC = cia;
1689 /* OP_A0 (); */
1690 genericCmp(State.regs[REG_D0 + DM1], State.regs[REG_D0 + DN0]);
1691 }
1692
1693
1694 // 1111 0001 1010 DmAn; cmp Dm,An
1695 8.0xf1+4.0xa,2.DM1,2.AN0:D0:::cmp
1696 "cmp"
1697 *mn10300
1698 {
1699 /* OP_F1A0 (); */
1700 PC = cia;
1701 genericCmp(State.regs[REG_D0 + DM1], State.regs[REG_A0 + AN0]);
1702 }
1703
1704
1705 // 1111 0001 1001 AmDn; cmp Am,Dn
1706 8.0xf1+4.0x9,2.AM1,2.DN0:D0a:::cmp
1707 "cmp"
1708 *mn10300
1709 {
1710 /* OP_F190 (); */
1711 PC = cia;
1712 genericCmp(State.regs[REG_A0 + AM1], State.regs[REG_D0 + DN0]);
1713 }
1714
1715
1716 // 1011 AnAn imm8....; cmp imm8,An (imm8 is zero-extended.)
1717 4.0xb,2.AM1,2.AN0=AM1+IMM8:S0ai:::cmp
1718 "cmp"
1719 *mn10300
1720 {
1721 PC = cia;
1722 /* OP_B000 (); */
1723 genericCmp(IMM8,
1724 State.regs[REG_A0 + AN0]);
1725 }
1726
1727
1728 // 1011 AmAn; cmp Am,An (Dm != Dn, see above when Dm == Dn)
1729 4.0xb,2.AM1,2.AN0!AM1:S0a:::cmp
1730 "cmp"
1731 *mn10300
1732 {
1733 PC = cia;
1734 /* OP_B0 (); */
1735 genericCmp(State.regs[REG_A0 + AM1], State.regs[REG_A0 + AN0]);
1736 }
1737
1738
1739 // 1111 1010 1100 10Dn imm16...; cmp imm16,Dn (imm16 is sign-extended.)
1740 8.0xfa+4.0xc,10,2.DN0+8.IMM16A+8.IMM16B:D2:::cmp
1741 "cmp"
1742 *mn10300
1743 {
1744 /* OP_FAC80000 (); */
1745 PC = cia;
1746 genericCmp(EXTEND16(FETCH16(IMM16A, IMM16B)),
1747 State.regs[REG_D0 + DN0]);
1748 }
1749
1750
1751 // 1111 1100 1100 10Dn imm32...; cmp imm32,Dn
1752 8.0xfc+4.0xc,10,2.DN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4:::cmp
1753 "cmp"
1754 *mn10300
1755 {
1756 /* OP_FCC80000 (); */
1757 PC = cia;
1758 genericCmp(FETCH32(IMM32A, IMM32B, IMM32C, IMM32D),
1759 State.regs[REG_D0 + DN0]);
1760 }
1761
1762
1763 // 1111 1010 1101 10An imm16...; cmp imm16,An (imm16 is zero-extended.)
1764 8.0xfa+4.0xd,10,2.AN0+8.IMM16A+8.IMM16B:D2a:::cmp
1765 "cmp"
1766 *mn10300
1767 {
1768 /* OP_FAD80000 (); */
1769 PC = cia;
1770 genericCmp(FETCH16(IMM16A, IMM16B),
1771 State.regs[REG_A0 + AN0]);
1772 }
1773
1774
1775 // 1111 1100 1101 10An imm32...; cmp imm32,An
1776 8.0xfc+4.0xd,10,2.AN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4a:::cmp
1777 "cmp"
1778 *mn10300
1779 {
1780 /* OP_FCD80000 (); */
1781 PC = cia;
1782 genericCmp(FETCH32(IMM32A, IMM32B, IMM32C, IMM32D),
1783 State.regs[REG_A0 + AN0]);
1784 }
1785
1786
1787 // 1111 0010 0000 DmDn; and Dm,Dn
1788 8.0xf2+4.0x0,2.DM1,2.DN0:D0:::and
1789 "and"
1790 *mn10300
1791 {
1792 /* OP_F200 (); */
1793 int n, z;
1794
1795 PC = cia;
1796 State.regs[REG_D0 + DN0] &= State.regs[REG_D0 + DM1];
1797 z = (State.regs[REG_D0 + DN0] == 0);
1798 n = (State.regs[REG_D0 + DN0] & 0x80000000) != 0;
1799 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1800 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
1801 }
1802
1803
1804 // 1111 1000 1110 00Dn imm8....; and imm8,Dn (imm8 is zero-extended.)
1805 8.0xf8+4.0xe,00,2.DN0+8.IMM8:D1:::and
1806 "and"
1807 *mn10300
1808 {
1809 /* OP_F8E000 (); */
1810 int n, z;
1811
1812 PC = cia;
1813 State.regs[REG_D0 + DN0] &= IMM8;
1814 z = (State.regs[REG_D0 + DN0] == 0);
1815 n = (State.regs[REG_D0 + DN0] & 0x80000000) != 0;
1816 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1817 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
1818 }
1819
1820
1821 // 1111 1010 1110 00Dn imm16...; and imm16,Dn (imm16 is zero-extended.)
1822 8.0xfa+4.0xe,00,2.DN0+8.IMM16A+8.IMM16B:D2:::and
1823 "and"
1824 *mn10300
1825 {
1826 /* OP_FAE00000 (); */
1827 int n, z;
1828
1829 PC = cia;
1830 State.regs[REG_D0 + DN0] &= FETCH16(IMM16A, IMM16B);
1831 z = (State.regs[REG_D0 + DN0] == 0);
1832 n = (State.regs[REG_D0 + DN0] & 0x80000000) != 0;
1833 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1834 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
1835 }
1836
1837
1838 // 1111 1100 1110 00Dn imm32...; and imm32,Dn
1839 8.0xfc+4.0xe,00,2.DN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4:::and
1840 "and"
1841 *mn10300
1842 {
1843 /* OP_FCE00000 (); */
1844 int n, z;
1845
1846 PC = cia;
1847 State.regs[REG_D0 + DN0]
1848 &= FETCH32(IMM32A, IMM32B, IMM32C, IMM32D);
1849 z = (State.regs[REG_D0 + DN0] == 0);
1850 n = (State.regs[REG_D0 + DN0] & 0x80000000) != 0;
1851 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1852 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
1853 }
1854
1855
1856 // 1111 1010 1111 1100 imm16...; and imm16,PSW (imm16 is zero-extended.)
1857 8.0xfa+8.0xfc+8.IMM16A+8.IMM16B:D2a:::and
1858 "and"
1859 *mn10300
1860 {
1861 /* OP_FAFC0000 (); */
1862 PC = cia;
1863 PSW &= FETCH16(IMM16A, IMM16B);
1864 }
1865
1866
1867
1868 // 1111 0010 0001 DmDn; or DmDn
1869 8.0xf2+4.0x1,2.DM1,2.DN0:D0:::or
1870 "or"
1871 *mn10300
1872 {
1873 /* OP_F210 (); */
1874 PC = cia;
1875 genericOr(State.regs[REG_D0 + DM1], REG_D0 + DN0);
1876 }
1877
1878
1879 // 1111 1000 1110 01Dn imm8....; or imm8,Dn (imm8 is zero-extended.)n
1880 8.0xf8+4.0xe,01,2.DN0+8.IMM8:D1:::or
1881 "or"
1882 *mn10300
1883 {
1884 /* OP_F8E400 (); */
1885 PC = cia;
1886 genericOr(IMM8, REG_D0 + DN0);
1887 }
1888
1889
1890 // 1111 1010 1110 01Dn imm16...; or imm16,DN (imm16 is zero-extended.)
1891 8.0xfa+4.0xe,01,2.DN0+8.IMM16A+8.IMM16B:D2:::or
1892 "or"
1893 *mn10300
1894 {
1895 /* OP_FAE40000 (); */
1896 PC = cia;
1897 genericOr(FETCH16(IMM16A, IMM16B), REG_D0 + DN0);
1898 }
1899
1900
1901 // 1111 1100 1110 01Dn imm32...; or imm32,Dn
1902 8.0xfc+4.0xe,01,2.DN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4:::or
1903 "or"
1904 *mn10300
1905 {
1906 /* OP_FCE40000 (); */
1907 PC = cia;
1908 genericOr(FETCH32(IMM32A, IMM32B, IMM32C, IMM32D), REG_D0 + DN0);
1909 }
1910
1911
1912 // 1111 1010 1111 1101 imm16...; or imm16,PSW (imm16 is zero-extended.)
1913 8.0xfa+8.0xfd+8.IMM16A+8.IMM16B:D2a:::or
1914 "or"
1915 *mn10300
1916 {
1917 /* OP_FAFD0000 (); */
1918 PC = cia;
1919 PSW |= FETCH16(IMM16A, IMM16B);
1920 }
1921
1922
1923 // 1111 0010 0010 DmDn; xor Dm,Dn
1924 8.0xf2+4.0x2,2.DM1,2.DN0:D0:::xor
1925 "xor"
1926 *mn10300
1927 {
1928 /* OP_F220 (); */
1929 PC = cia;
1930 genericXor(State.regs[REG_D0 + DM1], REG_D0 + DN0);
1931 }
1932
1933
1934 // 1111 1010 1110 10Dn imm16...; xor imm16,Dn (imm16 is zero-extended.)
1935 8.0xfa+4.0xe,10,2.DN0+8.IMM16A+8.IMM16B:D2:::xor
1936 "xor"
1937 *mn10300
1938 {
1939 /* OP_FAE80000 (); */
1940 PC = cia;
1941 genericXor(FETCH16(IMM16A, IMM16B), REG_D0 + DN0);
1942 }
1943
1944
1945 // 1111 1100 1110 10Dn imm32...; xor imm32,Dn
1946 8.0xfc+4.0xe,10,2.DN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4:::xor
1947 "xor"
1948 *mn10300
1949 {
1950 /* OP_FCE80000 (); */
1951 PC = cia;
1952 genericXor(FETCH32(IMM32A, IMM32B, IMM32C, IMM32D), REG_D0 + DN0);
1953 }
1954
1955
1956 // 1111 0010 0011 00Dn; not Dn
1957 8.0xf2+4.0x3,00,2.DN0:D0:::not
1958 "not"
1959 *mn10300
1960 {
1961 /* OP_F230 (); */
1962 int n, z;
1963
1964 PC = cia;
1965 State.regs[REG_D0 + DN0] = ~State.regs[REG_D0 + DN0];
1966 z = (State.regs[REG_D0 + DN0] == 0);
1967 n = (State.regs[REG_D0 + DN0] & 0x80000000) != 0;
1968 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1969 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
1970 }
1971
1972
1973 // 1111 1000 1110 11Dn imm8....; btst imm8,Dn (imm8 is zero-extended.)
1974 8.0xf8+4.0xe,11,2.DN0+8.IMM8:D1:::btst
1975 "btst"
1976 *mn10300
1977 {
1978 /* OP_F8EC00 (); */
1979 PC = cia;
1980 genericBtst(IMM8, State.regs[REG_D0 + DN0]);
1981 }
1982
1983
1984 // 1111 1010 1110 11Dn imm16.....; btst imm16,Dn (imm16 is zero-extended.)
1985 8.0xfa+4.0xe,11,2.DN0+8.IMM16A+8.IMM16B:D2:::btst
1986 "btst"
1987 *mn10300
1988 {
1989 /* OP_FAEC0000 (); */
1990 PC = cia;
1991 genericBtst(FETCH16(IMM16A, IMM16B), State.regs[REG_D0 + DN0]);
1992 }
1993
1994
1995 // 1111 1100 1110 11Dn imm32...; btst imm32,Dn
1996 8.0xfc+4.0xe,11,2.DN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4:::btst
1997 "btst"
1998 *mn10300
1999 {
2000 /* OP_FCEC0000 (); */
2001 PC = cia;
2002 genericBtst(FETCH32(IMM32A, IMM32B, IMM32C, IMM32D),
2003 State.regs[REG_D0 + DN0]);
2004 }
2005
2006
2007 // 1111 1110 0000 0010 abs32... imm8....; btst imm8,(abs32) (imm8 is zero-extended., processing unit: byte)
2008 8.0xfe+8.0x02+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D+8.IMM8:D5:::btst
2009 "btst"
2010 *mn10300
2011 {
2012 /* OP_FE020000 (); */
2013 PC = cia;
2014 genericBtst(IMM8,
2015 load_byte(FETCH32(IMM32A, IMM32B, IMM32C, IMM32D)));
2016 }
2017
2018
2019 // 1111 1010 1111 10An d8...... imm8....;
2020 // btst imm8,(d8,An) (d8 is sign-extended,imm8 is zero-extended., processing unit: byte)
2021 8.0xfa+4.0xf,10,2.AN0+8.D8+8.IMM8:D2a:::btst
2022 "btst"
2023 *mn10300
2024 {
2025 /* OP_FAF80000 (); */
2026 PC = cia;
2027 genericBtst(IMM8,
2028 load_byte(State.regs[REG_A0 + AN0] + EXTEND8(D8)));
2029 }
2030
2031
2032 // 1111 0000 1000 DmAn; bset Dm,(An) (Processing unit byte)
2033 8.0xf0+4.8,2.DM1,2.AN0:D0:::bset
2034 "bset"
2035 *mn10300
2036 {
2037 /* OP_F080 (); */
2038 unsigned long temp;
2039 int z;
2040
2041 PC = cia;
2042 temp = load_byte (State.regs[REG_A0 + AN0]);
2043 z = (temp & State.regs[REG_D0 + DM1]) == 0;
2044 temp |= State.regs[REG_D0 + DM1];
2045 store_byte (State.regs[REG_A0 + AN0], temp);
2046 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
2047 PSW |= (z ? PSW_Z : 0);
2048 }
2049
2050
2051 // 1111 1110 0000 0000 abs32... imm8....;
2052 // bset imm8,(abs32) (imm8 is zero-extended., processing unit: byte)
2053 8.0xfe+8.0x00+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D+8.IMM8:D5:::bset
2054 "bset"
2055 *mn10300
2056 {
2057 /* OP_FE000000 (); */
2058 unsigned long temp;
2059 int z;
2060
2061 PC = cia;
2062 temp = load_byte (FETCH32(IMM32A, IMM32B, IMM32C, IMM32D));
2063 z = (temp & IMM8) == 0;
2064 temp |= IMM8;
2065 store_byte (FETCH32(IMM32A, IMM32B, IMM32C, IMM32D), temp);
2066 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
2067 PSW |= (z ? PSW_Z : 0);
2068 }
2069
2070
2071 // 1111 1010 1111 00AnAn d8...... imm8....;
2072 // bset imm8,(d8,An) (d8 is sign-extended, imm8 is zero-extended., processing unit: byte)
2073 8.0xfa+4.0xf,00,2.AN0+8.D8+8.IMM8:D2:::bset
2074 "bset"
2075 *mn10300
2076 {
2077 /* OP_FAF00000 (); */
2078 unsigned long temp;
2079 int z;
2080
2081 PC = cia;
2082 temp = load_byte ((State.regs[REG_A0 + AN0] + EXTEND8 (D8)));
2083 z = (temp & (IMM8)) == 0;
2084 temp |= (IMM8);
2085 store_byte ((State.regs[REG_A0 + AN0] + EXTEND8 (D8)), temp);
2086 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
2087 PSW |= (z ? PSW_Z : 0);
2088 }
2089
2090
2091 // 1111 0000 1001 DmAn; bclr Dm,(An) (Processing unit byte)
2092 8.0xf0+4.0x9,2.DM1,2.AN0:D0:::bclr
2093 "bclr"
2094 *mn10300
2095 {
2096 /* OP_F090 (); */
2097 unsigned long temp;
2098 int z;
2099
2100 PC = cia;
2101 temp = load_byte (State.regs[REG_A0 + AN0]);
2102 z = (temp & State.regs[REG_D0 + DM1]) == 0;
2103 temp = temp & ~State.regs[REG_D0 + DM1];
2104 store_byte (State.regs[REG_A0 + AN0], temp);
2105 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
2106 PSW |= (z ? PSW_Z : 0);
2107 }
2108
2109
2110 // 1111 1110 0000 0001 abs32... imm8....;
2111 // bclr imm8,(abs32) (imm8 is zero-extended., processing unit: byte)
2112 8.0xfe+8.0x01+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D+8.IMM8:D5:::bclr
2113 "bclr"
2114 *mn10300
2115 {
2116 /* OP_FE010000 (); */
2117 unsigned long temp;
2118 int z;
2119
2120 PC = cia;
2121 temp = load_byte (FETCH32(IMM32A, IMM32B, IMM32C, IMM32D));
2122 z = (temp & IMM8) == 0;
2123 temp = temp & ~(IMM8);
2124 store_byte (FETCH32(IMM32A, IMM32B, IMM32C, IMM32D), temp);
2125 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
2126 PSW |= (z ? PSW_Z : 0);
2127 }
2128
2129
2130 // 1111 1010 1111 01An d8...... imm8....;
2131 // bclr imm8,(d8,An) (d8 is sign-extended, imm8 is zero-extended., processing unit: byte)
2132 8.0xfa+4.0xf,01,2.AN0+8.D8+8.IMM8:D2:::bclr
2133 "bclr"
2134 *mn10300
2135 {
2136 /* OP_FAF40000 (); */
2137 unsigned long temp;
2138 int z;
2139
2140 PC = cia;
2141 temp = load_byte ((State.regs[REG_A0 + AN0] + EXTEND8 (D8)));
2142 z = (temp & (IMM8)) == 0;
2143 temp = temp & ~(IMM8);
2144 store_byte ((State.regs[REG_A0 + AN0] + EXTEND8 (D8)), temp);
2145 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
2146 PSW |= (z ? PSW_Z : 0);
2147 }
2148
2149
2150 // 1111 0010 1011 DmDn; asr Dm,Dn
2151 8.0xf2+4.0xb,2.DM1,2.DN0:D0:::asr
2152 "asr"
2153 *mn10300
2154 {
2155 /* OP_F2B0 (); */
2156 long temp;
2157 int z, n, c;
2158
2159 PC = cia;
2160 temp = State.regs[REG_D0 + DN0];
2161 c = temp & 1;
2162 temp >>= State.regs[REG_D0 + DM1];
2163 State.regs[REG_D0 + DN0] = temp;
2164 z = (State.regs[REG_D0 + DN0] == 0);
2165 n = (State.regs[REG_D0 + DN0] & 0x80000000) != 0;
2166 PSW &= ~(PSW_Z | PSW_N | PSW_C);
2167 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
2168 }
2169
2170
2171 // 1111 1000 1100 10Dn imm8...; asr imm8,Dn (imm8 is zero-extended.)
2172 8.0xf8+4.0xc,10,2.DN0+8.IMM8:D1:::asr
2173 "asr"
2174 *mn10300
2175 {
2176 /* OP_F8C800 (); */
2177 long temp;
2178 int z, n, c;
2179
2180 PC = cia;
2181 temp = State.regs[REG_D0 + DN0];
2182 c = temp & 1;
2183 temp >>= IMM8;
2184 State.regs[REG_D0 + DN0] = temp;
2185 z = (State.regs[REG_D0 + DN0] == 0);
2186 n = (State.regs[REG_D0 + DN0] & 0x80000000) != 0;
2187 PSW &= ~(PSW_Z | PSW_N | PSW_C);
2188 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
2189 }
2190
2191
2192 // 1111 0010 1010 DmDn; lsr Dm,Dn
2193 8.0xf2+4.0xa,2.DM1,2.DN0:D0:::lsr
2194 "lsr"
2195 *mn10300
2196 {
2197 /* OP_F2A0 (); */
2198 int z, n, c;
2199
2200 PC = cia;
2201 c = State.regs[REG_D0 + DN0] & 1;
2202 State.regs[REG_D0 + DN0]
2203 >>= State.regs[REG_D0 + DM1];
2204 z = (State.regs[REG_D0 + DN0] == 0);
2205 n = (State.regs[REG_D0 + DN0] & 0x80000000) != 0;
2206 PSW &= ~(PSW_Z | PSW_N | PSW_C);
2207 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
2208 }
2209
2210
2211 // 1111 1000 1100 01Dn imm8...; lsr imm8,Dn (imm8 is zero-extended.)
2212 8.0xf8+4.0xc,01,2.DN0+8.IMM8:D1:::lsr
2213 "lsr"
2214 *mn10300
2215 {
2216 /* OP_F8C400 (); */
2217 int z, n, c;
2218
2219 PC = cia;
2220 c = State.regs[REG_D0 + DN0] & 1;
2221 State.regs[REG_D0 + DN0] >>= IMM8;
2222 z = (State.regs[REG_D0 + DN0] == 0);
2223 n = (State.regs[REG_D0 + DN0] & 0x80000000) != 0;
2224 PSW &= ~(PSW_Z | PSW_N | PSW_C);
2225 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
2226 }
2227
2228
2229 // 1111 0010 1001 DmDn; asl Dm,Dn
2230 8.0xf2+4.0x9,2.DM1,2.DN0:D0:::asl
2231 "asl"
2232 *mn10300
2233 {
2234 /* OP_F290 (); */
2235 int n, z;
2236
2237 PC = cia;
2238 State.regs[REG_D0 + DN0]
2239 <<= State.regs[REG_D0 + DM1];
2240 z = (State.regs[REG_D0 + DN0] == 0);
2241 n = (State.regs[REG_D0 + DN0] & 0x80000000) != 0;
2242 PSW &= ~(PSW_Z | PSW_N);
2243 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
2244 }
2245
2246
2247 // 1111 1000 1100 00Dn imm8...; asl imm8,Dn (imm8 is zero-extended.)
2248 8.0xf8+4.0xc,00,2.DN0+8.IMM8:D1:::asl
2249 "asl"
2250 *mn10300
2251 {
2252 /* OP_F8C000 (); */
2253 int n, z;
2254
2255 PC = cia;
2256 State.regs[REG_D0 + DN0] <<= IMM8;
2257 z = (State.regs[REG_D0 + DN0] == 0);
2258 n = (State.regs[REG_D0 + DN0] & 0x80000000) != 0;
2259 PSW &= ~(PSW_Z | PSW_N);
2260 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
2261 }
2262
2263
2264 // 0101 01Dn; als2 Dn
2265 4.0x5,01,2.DN0:S0:::asl2
2266 "asl2"
2267 *mn10300
2268 {
2269 /* OP_54 (); */
2270 int n, z;
2271 PC = cia;
2272
2273 State.regs[REG_D0 + DN0] <<= 2;
2274 z = (State.regs[REG_D0 + DN0] == 0);
2275 n = (State.regs[REG_D0 + DN0] & 0x80000000) != 0;
2276 PSW &= ~(PSW_Z | PSW_N);
2277 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
2278 }
2279
2280
2281 // 1111 0010 1000 01Dn; ror Dn
2282 8.0xf2+4.0x8,01,2.DN0:D0:::ror
2283 "ror"
2284 *mn10300
2285 {
2286 /* OP_F284 (); */
2287 unsigned long value;
2288 int c,n,z;
2289
2290 PC = cia;
2291 value = State.regs[REG_D0 + DN0];
2292 c = (value & 0x1);
2293
2294 value >>= 1;
2295 value |= ((PSW & PSW_C) != 0) ? 0x80000000 : 0;
2296 State.regs[REG_D0 + DN0] = value;
2297 z = (value == 0);
2298 n = (value & 0x80000000) != 0;
2299 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
2300 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
2301 }
2302
2303
2304 // 1111 0010 1000 00Dn; rol Dn
2305 8.0xf2+4.0x8,00,2.DN0:D0:::rol
2306 "rol"
2307 *mn10300
2308 {
2309 /* OP_F280 (); */
2310 unsigned long value;
2311 int c,n,z;
2312
2313 PC = cia;
2314 value = State.regs[REG_D0 + DN0];
2315 c = (value & 0x80000000) ? 1 : 0;
2316
2317 value <<= 1;
2318 value |= ((PSW & PSW_C) != 0);
2319 State.regs[REG_D0 + DN0] = value;
2320 z = (value == 0);
2321 n = (value & 0x80000000) != 0;
2322 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
2323 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
2324 }
2325
2326
2327 // 1100 1000 d8......; beq (d8,PC) (d8 is sign-extended)
2328 8.0xc8+8.D8:S1:::beq
2329 "beq"
2330 *mn10300
2331 {
2332 /* OP_C800 (); */
2333 PC = cia;
2334 if ((PSW & PSW_Z))
2335 {
2336 State.regs[REG_PC] += EXTEND8 (D8);
2337 nia = PC;
2338 }
2339 }
2340
2341
2342 // 1100 1001 d8......; bne (d8,PC) (d8 is sign-extended)
2343 8.0xc9+8.D8:S1:::bne
2344 "bne"
2345 *mn10300
2346 {
2347 /* OP_C900 (); */
2348 PC = cia;
2349 if (!(PSW & PSW_Z))
2350 {
2351 State.regs[REG_PC] += EXTEND8 (D8);
2352 nia = PC;
2353 }
2354 }
2355
2356
2357 // 1100 0001 d8......; bgt (d8,PC) (d8 is sign-extended)
2358 8.0xc1+8.D8:S1:::bgt
2359 "bgt"
2360 *mn10300
2361 {
2362 /* OP_C100 (); */
2363 PC = cia;
2364 if (!((PSW & PSW_Z)
2365 || (((PSW & PSW_N) != 0) ^ ((PSW & PSW_V) != 0))))
2366 {
2367 State.regs[REG_PC] += EXTEND8 (D8);
2368 nia = PC;
2369 }
2370 }
2371
2372
2373 // 1100 0010 d8......; bge (d8,PC) (d8 is sign-extended)
2374 8.0xc2+8.D8:S1:::bge
2375 "bge"
2376 *mn10300
2377 {
2378 /* OP_C200 (); */
2379 PC = cia;
2380 if (!(((PSW & PSW_N) != 0) ^ ((PSW & PSW_V) != 0)))
2381 {
2382 State.regs[REG_PC] += EXTEND8 (D8);
2383 nia = PC;
2384 }
2385 }
2386
2387
2388 // 1100 0011 d8......; ble (d8,PC) (d8 is sign-extended)
2389 8.0xc3+8.D8:S1:::ble
2390 "ble"
2391 *mn10300
2392 {
2393 /* OP_C300 (); */
2394 PC = cia;
2395 if ((PSW & PSW_Z)
2396 || (((PSW & PSW_N) != 0) ^ ((PSW & PSW_V) != 0)))
2397 {
2398 State.regs[REG_PC] += EXTEND8 (D8);
2399 nia = PC;
2400 }
2401 }
2402
2403
2404 // 1100 0000 d8......; blt (d8,PC) (d8 is sign-extended)
2405 8.0xc0+8.D8:S1:::blt
2406 "blt"
2407 *mn10300
2408 {
2409 /* OP_C000 (); */
2410 PC = cia;
2411 if (((PSW & PSW_N) != 0) ^ ((PSW & PSW_V) != 0))
2412 {
2413 State.regs[REG_PC] += EXTEND8 (D8);
2414 nia = PC;
2415 }
2416 }
2417
2418
2419 // 1100 0101 d8......; bhi (d8,PC) (d8 is sign-extended)
2420 8.0xc5+8.D8:S1:::bhi
2421 "bhi"
2422 *mn10300
2423 {
2424 /* OP_C500 (); */
2425 PC = cia;
2426 if (!(((PSW & PSW_C) != 0) || (PSW & PSW_Z) != 0))
2427 {
2428 State.regs[REG_PC] += EXTEND8 (D8);
2429 nia = PC;
2430 }
2431 }
2432
2433
2434 // 1100 0110 d8......; bcc (d8,PC) (d8 is sign-extended)
2435 8.0xc6+8.D8:S1:::bcc
2436 "bcc"
2437 *mn10300
2438 {
2439 /* OP_C600 (); */
2440 PC = cia;
2441 if (!(PSW & PSW_C))
2442 {
2443 State.regs[REG_PC] += EXTEND8 (D8);
2444 nia = PC;
2445 }
2446 }
2447
2448
2449 // 1100 0101 d8......; bls (d8,PC) (d8 is sign-extended)
2450 8.0xc7+8.D8:S1:::bls
2451 "bls"
2452 *mn10300
2453 {
2454 /* OP_C700 (); */
2455 PC = cia;
2456 if (((PSW & PSW_C) != 0) || (PSW & PSW_Z) != 0)
2457 {
2458 State.regs[REG_PC] += EXTEND8 (D8);
2459 nia = PC;
2460 }
2461 }
2462
2463
2464 // 1100 0100 d8......; bcs (d8,PC) (d8 is sign-extended)
2465 8.0xc4+8.D8:S1:::bcs
2466 "bcs"
2467 *mn10300
2468 {
2469 /* OP_C400 (); */
2470 PC = cia;
2471 if (PSW & PSW_C)
2472 {
2473 State.regs[REG_PC] += EXTEND8 (D8);
2474 nia = PC;
2475 }
2476 }
2477
2478
2479 // 1111 1000 1110 1000 d8......; bvc (d8,PC) (d8 is sign-extended)
2480 8.0xf8+8.0xe8+8.D8:D1:::bvc
2481 "bvc"
2482 *mn10300
2483 {
2484 /* OP_F8E800 (); */
2485 PC = cia;
2486 if (!(PSW & PSW_V))
2487 {
2488 State.regs[REG_PC] += EXTEND8 (D8);
2489 nia = PC;
2490 }
2491 }
2492
2493
2494 // 1111 1000 1110 1001 d8......; bvs (d8,PC) (d8 is sign-extended)
2495 8.0xf8+8.0xe9+8.D8:D1:::bvs
2496 "bvs"
2497 *mn10300
2498 {
2499 /* OP_F8E900 (); */
2500 PC = cia;
2501 if (PSW & PSW_V)
2502 {
2503 State.regs[REG_PC] += EXTEND8 (D8);
2504 nia = PC;
2505 }
2506 }
2507
2508
2509 // 1111 1000 1110 1010 d8......; bnc (d8,PC) (d8 is sign-extended)
2510 8.0xf8+8.0xea+8.D8:D1:::bnc
2511 "bnc"
2512 *mn10300
2513 {
2514 /* OP_F8EA00 (); */
2515 PC = cia;
2516 if (!(PSW & PSW_N))
2517 {
2518 State.regs[REG_PC] += EXTEND8 (D8);
2519 nia = PC;
2520 }
2521 }
2522
2523
2524 // 1111 1000 1110 1010 d8......; bns (d8,PC) (d8 is sign-extended)
2525 8.0xf8+8.0xeb+8.D8:D1:::bns
2526 "bns"
2527 *mn10300
2528 {
2529 /* OP_F8EB00 (); */
2530 PC = cia;
2531 if (PSW & PSW_N)
2532 {
2533 State.regs[REG_PC] += EXTEND8 (D8);
2534 nia = PC;
2535 }
2536 }
2537
2538
2539 // 1100 1010 d8......; bra (d8,PC) (d8 is sign-extended)
2540 8.0xca+8.D8:S1:::bra
2541 "bra"
2542 *mn10300
2543 {
2544 /* OP_CA00 (); */
2545 PC = cia;
2546 State.regs[REG_PC] += EXTEND8 (D8);
2547 nia = PC;
2548 }
2549
2550
2551 // 1101 1000; leq
2552 8.0xd8:S0:::leq
2553 "leq"
2554 *mn10300
2555 {
2556 /* OP_D8 (); */
2557 PC = cia;
2558 if (PSW & PSW_Z)
2559 {
2560 State.regs[REG_PC] = State.regs[REG_LAR] - 4;
2561 nia = PC;
2562 }
2563 }
2564
2565
2566 // 1101 1001; lne
2567 8.0xd9:S0:::lne
2568 "lne"
2569 *mn10300
2570 {
2571 /* OP_D9 (); */
2572 PC = cia;
2573 if (!(PSW & PSW_Z))
2574 {
2575 State.regs[REG_PC] = State.regs[REG_LAR] - 4;
2576 nia = PC;
2577 }
2578 }
2579
2580
2581 // 1101 0001; lgt
2582 8.0xd1:S0:::lgt
2583 "lgt"
2584 *mn10300
2585 {
2586 /* OP_D1 (); */
2587 PC = cia;
2588 if (!((PSW & PSW_Z)
2589 || (((PSW & PSW_N) != 0) ^ ((PSW & PSW_V) != 0))))
2590 {
2591 State.regs[REG_PC] = State.regs[REG_LAR] - 4;
2592 nia = PC;
2593 }
2594 }
2595
2596
2597 // 1101 0010; lge
2598 8.0xd2:S0:::lge
2599 "lge"
2600 *mn10300
2601 {
2602 /* OP_D2 (); */
2603 PC = cia;
2604 if (!(((PSW & PSW_N) != 0) ^ ((PSW & PSW_V) != 0)))
2605 {
2606 State.regs[REG_PC] = State.regs[REG_LAR] - 4;
2607 nia = PC;
2608 }
2609 }
2610
2611
2612 // 1101 0011; lle
2613 8.0xd3:S0:::lle
2614 "lle"
2615 *mn10300
2616 {
2617 /* OP_D3 (); */
2618 PC = cia;
2619 if ((PSW & PSW_Z)
2620 || (((PSW & PSW_N) != 0) ^ ((PSW & PSW_V) != 0)))
2621 {
2622 State.regs[REG_PC] = State.regs[REG_LAR] - 4;
2623 nia = PC;
2624 }
2625 }
2626
2627
2628 // 1101 0000; llt
2629 8.0xd0:S0:::llt
2630 "llt"
2631 *mn10300
2632 {
2633 /* OP_D0 (); */
2634 PC = cia;
2635 if (((PSW & PSW_N) != 0) ^ ((PSW & PSW_V) != 0))
2636 {
2637 State.regs[REG_PC] = State.regs[REG_LAR] - 4;
2638 nia = PC;
2639 }
2640 }
2641
2642
2643 // 1101 0101; lhi
2644 8.0xd5:S0:::lhi
2645 "lhi"
2646 *mn10300
2647 {
2648 /* OP_D5 (); */
2649 PC = cia;
2650 if (!(((PSW & PSW_C) != 0) || (PSW & PSW_Z) != 0))
2651 {
2652 State.regs[REG_PC] = State.regs[REG_LAR] - 4;
2653 nia = PC;
2654 }
2655 }
2656
2657
2658 // 1101 0110; lcc
2659 8.0xd6:S0:::lcc
2660 "lcc"
2661 *mn10300
2662 {
2663 /* OP_D6 (); */
2664 PC = cia;
2665 if (!(PSW & PSW_C))
2666 {
2667 State.regs[REG_PC] = State.regs[REG_LAR] - 4;
2668 nia = PC;
2669 }
2670 }
2671
2672
2673 // 1101 0111; lls
2674 8.0xd7:S0:::lls
2675 "lls"
2676 *mn10300
2677 {
2678 /* OP_D7 (); */
2679 PC = cia;
2680 if (((PSW & PSW_C) != 0) || (PSW & PSW_Z) != 0)
2681 {
2682 State.regs[REG_PC] = State.regs[REG_LAR] - 4;
2683 nia = PC;
2684 }
2685 }
2686
2687
2688 // 1101 0100; lcs
2689 8.0xd4:S0:::lcs
2690 "lcs"
2691 *mn10300
2692 {
2693 /* OP_D4 (); */
2694 PC = cia;
2695 if (PSW & PSW_C)
2696 {
2697 State.regs[REG_PC] = State.regs[REG_LAR] - 4;
2698 nia = PC;
2699 }
2700 }
2701
2702
2703 // 1101 1010; lra
2704 8.0xda:S0:::lra
2705 "lra"
2706 *mn10300
2707 {
2708 /* OP_DA (); */
2709 PC = cia;
2710 State.regs[REG_PC] = State.regs[REG_LAR] - 4;
2711 nia = PC;
2712 }
2713
2714
2715 // 1101 1010; setlb
2716 8.0xdb:S0:::setlb
2717 "setlb"
2718 *mn10300
2719 {
2720 /* OP_DB (); */
2721 PC = cia;
2722 State.regs[REG_LIR] = load_word (State.regs[REG_PC] + 1);
2723 State.regs[REG_LAR] = State.regs[REG_PC] + 5;
2724 }
2725
2726
2727 // 1111 0000 1111 01An; jmp (An)
2728 8.0xf0+4.0xf,01,2.AN0:D0:::jmp
2729 "jmp"
2730 *mn10300
2731 {
2732 /* OP_F0F4 (); */
2733 PC = State.regs[REG_A0 + AN0];
2734 nia = PC;
2735 }
2736
2737
2738 // 1100 1100 d16.....; jmp (d16,PC) (d16 is sign-extended.)
2739 8.0xcc+8.D16A+8.D16B:S2:::jmp
2740 "jmp"
2741 *mn10300
2742 {
2743 /* OP_CC0000 (); */
2744 PC = cia + EXTEND16(FETCH16(D16A, D16B));
2745 nia = PC;
2746 }
2747
2748
2749 // 1101 1100 d32........; jmp (d32, PC)
2750 8.0xdc+8.D32A+8.D32B+8.D32C+8.D32D:S4:::jmp
2751 "jmp"
2752 *mn10300
2753 {
2754 /* OP_DC000000 (); */
2755 PC = cia + FETCH32(D32A, D32B, D32C, D32D);
2756 nia = PC;
2757 }
2758
2759
2760 // 1111 0000 1111 00An; calls (An)
2761 8.0xf0+4.0xf,00,2.AN0:D0:::calls
2762 "calls"
2763 *mn10300
2764 {
2765 /* OP_F0F0 (); */
2766 unsigned int next_pc, sp;
2767
2768 PC = cia;
2769 sp = State.regs[REG_SP];
2770 next_pc = State.regs[REG_PC] + 2;
2771 store_word(sp, next_pc);
2772 State.regs[REG_MDR] = next_pc;
2773 State.regs[REG_PC] = State.regs[REG_A0 + AN0];
2774 nia = PC;
2775 }
2776
2777
2778 // 1111 1010 1111 1111 d16.....; calls (d16,PC) (d16 is sign-extended.)
2779 8.0xfa+8.0xff+8.D16A+8.D16B:D2:::calls
2780 "calls"
2781 *mn10300
2782 {
2783 /* OP_FAFF0000 (); */
2784 unsigned int next_pc, sp;
2785
2786 PC = cia;
2787 sp = State.regs[REG_SP];
2788 next_pc = State.regs[REG_PC] + 4;
2789 store_word(sp, next_pc);
2790 State.regs[REG_MDR] = next_pc;
2791 State.regs[REG_PC] += EXTEND16 (FETCH16(D16A, D16B));
2792 nia = PC;
2793 }
2794
2795
2796 // 1111 1100 1111 1111 d32.....; calls (d32,PC)
2797 8.0xfc+8.0xff+8.D32A+8.D32B+8.D32C+8.D32D:D4:::calls
2798 "calls"
2799 *mn10300
2800 {
2801 /* OP_FCFF0000 (); */
2802 unsigned int next_pc, sp;
2803
2804 PC = cia;
2805 sp = State.regs[REG_SP];
2806 next_pc = State.regs[REG_PC] + 6;
2807 store_word(sp, next_pc);
2808 State.regs[REG_MDR] = next_pc;
2809 State.regs[REG_PC] += FETCH32(D32A, D32B, D32C, D32D);
2810 nia = PC;
2811 }
2812
2813
2814 // 1111 0000 1111 1100; rets
2815 8.0xf0+8.0xfc:D0:::rets
2816 "rets"
2817 *mn10300
2818 {
2819 /* OP_F0FC (); */
2820 unsigned int sp;
2821
2822 sp = State.regs[REG_SP];
2823 State.regs[REG_PC] = load_word(sp);
2824 nia = PC;
2825 }
2826
2827
2828 // 1111 0000 1111 1101; rti
2829 8.0xf0+8.0xfd:D0:::rti
2830 "rti"
2831 *mn10300
2832 {
2833 /* OP_F0FD (); */
2834 unsigned int sp;
2835
2836 sp = State.regs[REG_SP];
2837 PSW = load_half(sp);
2838 State.regs[REG_PC] = load_word(sp+4);
2839 State.regs[REG_SP] +=8;
2840 nia = PC;
2841 }
2842
2843
2844 // 1111 0000 1111 1110; trap
2845 8.0xf0+8.0xfe:D0:::trap
2846 "trap"
2847 *mn10300
2848 {
2849 /* OP_F0FE (); */
2850 unsigned int sp, next_pc;
2851
2852 PC = cia;
2853 sp = State.regs[REG_SP];
2854 next_pc = State.regs[REG_PC] + 2;
2855 store_word(sp, next_pc);
2856 nia = PC;
2857 }
2858
2859
2860 // 1111 0000 1111 1111; rtm
2861 8.0xf0+8.0xff:D0:::rtm
2862 "rtm"
2863 *mn10300
2864 {
2865 /* OP_F0FF (); */
2866 PC = cia;
2867 abort ();
2868 }
2869
2870
2871 // 1100 1011; nop
2872 8.0xcb:S0:::nop
2873 "nop"
2874 *mn10300
2875 {
2876 /* OP_CB (); */
2877 PC = cia;
2878 }
2879
2880
2881 // 1111 0101 0000 DmDn; udf20 Dm,Dn
2882 8.0xf5+4.0x0,2.DM1,2.DN0:D0:::putx
2883 "putx"
2884 *mn10300
2885 {
2886 /* OP_F500 (); */
2887 PC = cia;
2888 State.regs[REG_MDRQ] = State.regs[REG_D0 + DN0];
2889 }
2890
2891
2892 // 1111 0110 1111 DmDn; udf15 Dm,Dn
2893 8.0xf6+4.0xf,2.DM1,2.DN0:D0:::getx
2894 "getx"
2895 *mn10300
2896 {
2897 /* OP_F6F0 (); */
2898 int z, n;
2899
2900 PC = cia;
2901 z = (State.regs[REG_MDRQ] == 0);
2902 n = ((State.regs[REG_MDRQ] & 0x80000000) != 0);
2903 State.regs[REG_D0 + DN0] = State.regs[REG_MDRQ];
2904
2905 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
2906 PSW |= (z ? PSW_Z : 0) | (n ? PSW_N : 0);
2907 }
2908
2909
2910 // 1111 0110 0000 DmDn; udf00 Dm,Dn
2911 8.0xf6+4.0x0,2.DM1,2.DN0:D0:::mulq
2912 "mulq"
2913 *mn10300
2914 {
2915 /* OP_F600 (); */
2916 unsigned long long temp;
2917 int n, z;
2918
2919 PC = cia;
2920 temp = ((signed64)(signed32)State.regs[REG_D0 + DN0]
2921 * (signed64)(signed32)State.regs[REG_D0 + DM1]);
2922 State.regs[REG_D0 + DN0] = temp & 0xffffffff;
2923 State.regs[REG_MDRQ] = (temp & 0xffffffff00000000LL) >> 32;;
2924 z = (State.regs[REG_D0 + DN0] == 0);
2925 n = (State.regs[REG_D0 + DN0] & 0x80000000) != 0;
2926 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
2927 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
2928 }
2929
2930
2931 // 1111 1001 0000 00Dn imm8....; udf00 imm8,Dn (imm8 is sign-extended.)
2932 8.0xf9+4.0x,00,2.DN0+8.IMM8:D1:::mulq
2933 "mulq"
2934 *mn10300
2935 {
2936 /* OP_F90000 (); */
2937 unsigned long long temp;
2938 int n, z;
2939
2940 PC = cia;
2941 temp = ((signed64)(signed32)State.regs[REG_D0 + DN0]
2942 * (signed64)(signed32)EXTEND8 (IMM8));
2943 State.regs[REG_D0 + DN0] = temp & 0xffffffff;
2944 State.regs[REG_MDRQ] = (temp & 0xffffffff00000000LL) >> 32;;
2945 z = (State.regs[REG_D0 + DN0] == 0);
2946 n = (State.regs[REG_D0 + DN0] & 0x80000000) != 0;
2947 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
2948 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
2949 }
2950
2951
2952 // 1111 1011 0000 00Dn imm16...; udf00 imm16,Dn (imm16 is sign-extended.)
2953 8.0xfb+4.0x0,00,2.DN0+8.IMM16A+8.IMM16B:D2:::mulq
2954 "mulq"
2955 *mn10300
2956 {
2957 /* OP_FB000000 (); */
2958 unsigned long long temp;
2959 int n, z;
2960
2961 PC = cia;
2962 temp = ((signed64)(signed32)State.regs[REG_D0 + DN0]
2963 * (signed64)(signed32)EXTEND16 (FETCH16(IMM16A, IMM16B)));
2964 State.regs[REG_D0 + DN0] = temp & 0xffffffff;
2965 State.regs[REG_MDRQ] = (temp & 0xffffffff00000000LL) >> 32;;
2966 z = (State.regs[REG_D0 + DN0] == 0);
2967 n = (State.regs[REG_D0 + DN0] & 0x80000000) != 0;
2968 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
2969 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
2970 }
2971
2972
2973 // 1111 1101 0000 00Dn imm32...; udf00 imm32,Dn
2974 8.0xfd+4.0x0,00,2.DN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4:::mulq
2975 "mulq"
2976 *mn10300
2977 {
2978 /* OP_FD000000 (); */
2979 unsigned long long temp;
2980 int n, z;
2981
2982 PC = cia;
2983 temp = ((signed64)(signed32)State.regs[REG_D0 + DN0]
2984 * (signed64)(signed32)(FETCH32(IMM32A, IMM32B, IMM32C, IMM32D)));
2985 State.regs[REG_D0 + DN0] = temp & 0xffffffff;
2986 State.regs[REG_MDRQ] = (temp & 0xffffffff00000000LL) >> 32;;
2987 z = (State.regs[REG_D0 + DN0] == 0);
2988 n = (State.regs[REG_D0 + DN0] & 0x80000000) != 0;
2989 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
2990 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
2991 }
2992
2993
2994 // 1111 0110 0001 DmDn; udf01 Dm,Dn
2995 8.0xf6+4.0x1,2.DM1,2.DN0:D0:::mulqu
2996 "mulqu"
2997 *mn10300
2998 {
2999 /* OP_F610 (); */
3000 unsigned long long temp;
3001 int n, z;
3002
3003 PC = cia;
3004 temp = ((unsigned64) State.regs[REG_D0 + DN0]
3005 * (unsigned64) State.regs[REG_D0 + DM1]);
3006 State.regs[REG_D0 + DN0] = temp & 0xffffffff;
3007 State.regs[REG_MDRQ] = (temp & 0xffffffff00000000LL) >> 32;;
3008 z = (State.regs[REG_D0 + DN0] == 0);
3009 n = (State.regs[REG_D0 + DN0] & 0x80000000) != 0;
3010 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
3011 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
3012 }
3013
3014
3015 // 1111 1001 0001 01Dn imm8....; udfu01 imm8,Dn (imm8 is zero-extended.)
3016 8.0xf9+4.0x1,01,2.DN0+8.IMM8:D1:::mulqu
3017 "mulqu"
3018 *mn10300
3019 {
3020 /* OP_F91400 (); */
3021 unsigned long long temp;
3022 int n, z;
3023
3024 PC = cia;
3025 temp = ((unsigned64)State.regs[REG_D0 + DN0]
3026 * (unsigned64)EXTEND8 (IMM8));
3027 State.regs[REG_D0 + DN0] = temp & 0xffffffff;
3028 State.regs[REG_MDRQ] = (temp & 0xffffffff00000000LL) >> 32;;
3029 z = (State.regs[REG_D0 + DN0] == 0);
3030 n = (State.regs[REG_D0 + DN0] & 0x80000000) != 0;
3031 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
3032 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
3033 }
3034
3035
3036 // 1111 1011 0001 01Dn imm16...; udfu01 imm16,Dn (imm16 is zero-extended.)
3037 8.0xfb+4.0x1,01,2.DN0+8.IMM16A+8.IMM16B:D2:::mulqu
3038 "mulqu"
3039 *mn10300
3040 {
3041 /* OP_FB140000 (); */
3042 unsigned long long temp;
3043 int n, z;
3044
3045 PC = cia;
3046 temp = ((unsigned64)State.regs[REG_D0 + DN0]
3047 * (unsigned64) EXTEND16 (FETCH16(IMM16A, IMM16B)));
3048 State.regs[REG_D0 + DN0] = temp & 0xffffffff;
3049 State.regs[REG_MDRQ] = (temp & 0xffffffff00000000LL) >> 32;;
3050 z = (State.regs[REG_D0 + DN0] == 0);
3051 n = (State.regs[REG_D0 + DN0] & 0x80000000) != 0;
3052 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
3053 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
3054 }
3055
3056
3057 // 1111 1101 0001 01Dn imm32...; udfu01 imm32,Dn
3058 8.0xfd+4.0x1,01,2.DN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4:::mulqu
3059 "mulqu"
3060 *mn10300
3061 {
3062 /* OP_FD140000 (); */
3063 unsigned long long temp;
3064 int n, z;
3065
3066 PC = cia;
3067 temp = ((unsigned64)State.regs[REG_D0 + DN0]
3068 * (unsigned64)(FETCH32(IMM32A, IMM32B, IMM32C, IMM32D)));
3069 State.regs[REG_D0 + DN0] = temp & 0xffffffff;
3070 State.regs[REG_MDRQ] = (temp & 0xffffffff00000000LL) >> 32;;
3071 z = (State.regs[REG_D0 + DN0] == 0);
3072 n = (State.regs[REG_D0 + DN0] & 0x80000000) != 0;
3073 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
3074 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
3075 }
3076
3077
3078 // 1111 0110 0100 DmDn; udf04 Dm,Dn
3079 8.0xf6+4.0x4,2.DM1,2.DN0:D0:::sat16
3080 "sat16"
3081 *mn10300
3082 {
3083 /* OP_F640 (); */
3084 int temp;
3085
3086 PC = cia;
3087 temp = State.regs[REG_D0 + DM1];
3088 temp = (temp > 0x7fff ? 0x7fff : temp);
3089 temp = (temp < -0x8000 ? -0x8000 : temp);
3090 State.regs[REG_D0 + DN0] = temp;
3091 }
3092
3093
3094 // 1111 0110 0101 DmDn; udf05 Dm,Dn
3095 8.0xf6+4.0x5,2.DM1,2.DN0:D0:::sat24
3096 "sat24"
3097 *mn10300
3098 {
3099 /* OP_F650 (); */
3100 int temp;
3101
3102 PC = cia;
3103 temp = State.regs[REG_D0 + DM1];
3104 temp = (temp > 0x7fffff ? 0x7fffff : temp);
3105 temp = (temp < -0x800000 ? -0x800000 : temp);
3106 State.regs[REG_D0 + DN0] = temp;
3107 }
3108
3109
3110 // 1111 0110 0111 DmDn; udf07 Dm,Dn
3111 8.0xf6+4.0x7,2.DM1,2.DN0:D0:::bsch
3112 "bsch"
3113 *mn10300
3114 {
3115 /* OP_F670 (); */
3116 int temp, c;
3117
3118 PC = cia;
3119 temp = State.regs[REG_D0 + DM1];
3120 temp <<= (State.regs[REG_D0 + DN0] & 0x1f);
3121 c = (temp != 0 ? 1 : 0);
3122 PSW &= ~(PSW_C);
3123 PSW |= (c ? PSW_C : 0);
3124 }
3125
3126
3127 // 1111 0000 1100 0000; syscall
3128 8.0xf0+8.0xc0:D0:::syscall
3129 "syscall"
3130 *mn10300
3131 {
3132 /* OP_F0C0 (); */
3133 PC = cia;
3134 do_syscall ();
3135 }
3136
3137
3138 // 1111 1111; break
3139 8.0xff:S0:::break
3140 "break"
3141 *mn10300
3142 {
3143 /* OP_FF (); */
3144 PC = cia;
3145 program_interrupt(SD, CPU, cia, SIM_SIGTRAP);
3146 }
3147
3148 // 1100 1110 regs....; movm (SP),regs
3149 8.0xce+8.REGS:S1:::movm
3150 "movm"
3151 *mn10300
3152 {
3153 /* OP_CE00 (); */
3154 unsigned long sp = State.regs[REG_SP];
3155 unsigned long mask;
3156
3157 PC = cia;
3158 mask = REGS;
3159
3160 if (mask & 0x8)
3161 {
3162 sp += 4;
3163 State.regs[REG_LAR] = load_word (sp);
3164 sp += 4;
3165 State.regs[REG_LIR] = load_word (sp);
3166 sp += 4;
3167 State.regs[REG_MDR] = load_word (sp);
3168 sp += 4;
3169 State.regs[REG_A0 + 1] = load_word (sp);
3170 sp += 4;
3171 State.regs[REG_A0] = load_word (sp);
3172 sp += 4;
3173 State.regs[REG_D0 + 1] = load_word (sp);
3174 sp += 4;
3175 State.regs[REG_D0] = load_word (sp);
3176 sp += 4;
3177 }
3178
3179 if (mask & 0x10)
3180 {
3181 State.regs[REG_A0 + 3] = load_word (sp);
3182 sp += 4;
3183 }
3184
3185 if (mask & 0x20)
3186 {
3187 State.regs[REG_A0 + 2] = load_word (sp);
3188 sp += 4;
3189 }
3190
3191 if (mask & 0x40)
3192 {
3193 State.regs[REG_D0 + 3] = load_word (sp);
3194 sp += 4;
3195 }
3196
3197 if (mask & 0x80)
3198 {
3199 State.regs[REG_D0 + 2] = load_word (sp);
3200 sp += 4;
3201 }
3202
3203
3204 /* And make sure to update the stack pointer. */
3205 State.regs[REG_SP] = sp;
3206 }
3207
3208
3209 // 1100 1111 regs....; movm regs,(SP)
3210 8.0xcf+8.REGS:S1a:::movm
3211 "movm"
3212 *mn10300
3213 {
3214 /* OP_CF00 (); */
3215 unsigned long sp = State.regs[REG_SP];
3216 unsigned long mask;
3217
3218 PC = cia;
3219 mask = REGS;
3220
3221
3222 if (mask & 0x80)
3223 {
3224 sp -= 4;
3225 store_word (sp, State.regs[REG_D0 + 2]);
3226 }
3227
3228 if (mask & 0x40)
3229 {
3230 sp -= 4;
3231 store_word (sp, State.regs[REG_D0 + 3]);
3232 }
3233
3234 if (mask & 0x20)
3235 {
3236 sp -= 4;
3237 store_word (sp, State.regs[REG_A0 + 2]);
3238 }
3239
3240 if (mask & 0x10)
3241 {
3242 sp -= 4;
3243 store_word (sp, State.regs[REG_A0 + 3]);
3244 }
3245
3246 if (mask & 0x8)
3247 {
3248 sp -= 4;
3249 store_word (sp, State.regs[REG_D0]);
3250 sp -= 4;
3251 store_word (sp, State.regs[REG_D0 + 1]);
3252 sp -= 4;
3253 store_word (sp, State.regs[REG_A0]);
3254 sp -= 4;
3255 store_word (sp, State.regs[REG_A0 + 1]);
3256 sp -= 4;
3257 store_word (sp, State.regs[REG_MDR]);
3258 sp -= 4;
3259 store_word (sp, State.regs[REG_LIR]);
3260 sp -= 4;
3261 store_word (sp, State.regs[REG_LAR]);
3262 sp -= 4;
3263 }
3264
3265 /* And make sure to update the stack pointer. */
3266 State.regs[REG_SP] = sp;
3267 }
3268
3269 // 1100 1101 d16..... regs.... imm8....;
3270 // call (d16,PC),regs,imm8 (d16 is sign-extended., imm8 is zero-extended.)
3271 8.0xcd+8.D16A+8.D16B+8.REGS+8.IMM8:S4:::call
3272 "call"
3273 *mn10300
3274 {
3275 /* OP_CD000000 (); */
3276 unsigned int next_pc, sp;
3277 unsigned long mask;
3278
3279 PC = cia;
3280 sp = State.regs[REG_SP];
3281 next_pc = PC + 5;
3282 store_word(sp, next_pc);
3283
3284 mask = REGS;
3285
3286
3287 if (mask & 0x80)
3288 {
3289 sp -= 4;
3290 store_word (sp, State.regs[REG_D0 + 2]);
3291 }
3292
3293 if (mask & 0x40)
3294 {
3295 sp -= 4;
3296 store_word (sp, State.regs[REG_D0 + 3]);
3297 }
3298
3299 if (mask & 0x20)
3300 {
3301 sp -= 4;
3302 store_word (sp, State.regs[REG_A0 + 2]);
3303 }
3304
3305 if (mask & 0x10)
3306 {
3307 sp -= 4;
3308 store_word (sp, State.regs[REG_A0 + 3]);
3309 }
3310
3311 if (mask & 0x8)
3312 {
3313 sp -= 4;
3314 store_word (sp, State.regs[REG_D0]);
3315 sp -= 4;
3316 store_word (sp, State.regs[REG_D0 + 1]);
3317 sp -= 4;
3318 store_word (sp, State.regs[REG_A0]);
3319 sp -= 4;
3320 store_word (sp, State.regs[REG_A0 + 1]);
3321 sp -= 4;
3322 store_word (sp, State.regs[REG_MDR]);
3323 sp -= 4;
3324 store_word (sp, State.regs[REG_LIR]);
3325 sp -= 4;
3326 store_word (sp, State.regs[REG_LAR]);
3327 sp -= 4;
3328 }
3329
3330 /* Update the stack pointer, note that the register saves to do not
3331 modify SP. The SP adjustment is derived totally from the imm8
3332 field. */
3333 State.regs[REG_SP] -= IMM8;
3334 State.regs[REG_MDR] = next_pc;
3335 State.regs[REG_PC] += EXTEND16 (FETCH16(D16A, D16B));
3336 nia = PC;
3337 }
3338
3339
3340 // 1101 1101 d32..... regs.... imm8....;
3341 // call (d32,PC),regs,imm8 (imm8 is zero-extended.)
3342 8.0xdd+8.D32A+8.D32B+8.D32C+8.D32D+8.REGS+8.IMM8:S6:::call
3343 "call"
3344 *mn10300
3345 {
3346 /* OP_DD000000 (); */
3347 unsigned int next_pc, sp;
3348 unsigned long mask;
3349
3350 PC = cia;
3351 sp = State.regs[REG_SP];
3352 next_pc = State.regs[REG_PC] + 7;
3353 /* could assert that nia == next_pc here */
3354 store_word(sp, next_pc);
3355
3356 mask = REGS;
3357
3358
3359 if (mask & 0x80)
3360 {
3361 sp -= 4;
3362 store_word (sp, State.regs[REG_D0 + 2]);
3363 }
3364
3365 if (mask & 0x40)
3366 {
3367 sp -= 4;
3368 store_word (sp, State.regs[REG_D0 + 3]);
3369 }
3370
3371 if (mask & 0x20)
3372 {
3373 sp -= 4;
3374 store_word (sp, State.regs[REG_A0 + 2]);
3375 }
3376
3377 if (mask & 0x10)
3378 {
3379 sp -= 4;
3380 store_word (sp, State.regs[REG_A0 + 3]);
3381 }
3382
3383 if (mask & 0x8)
3384 {
3385 sp -= 4;
3386 store_word (sp, State.regs[REG_D0]);
3387 sp -= 4;
3388 store_word (sp, State.regs[REG_D0 + 1]);
3389 sp -= 4;
3390 store_word (sp, State.regs[REG_A0]);
3391 sp -= 4;
3392 store_word (sp, State.regs[REG_A0 + 1]);
3393 sp -= 4;
3394 store_word (sp, State.regs[REG_MDR]);
3395 sp -= 4;
3396 store_word (sp, State.regs[REG_LIR]);
3397 sp -= 4;
3398 store_word (sp, State.regs[REG_LAR]);
3399 sp -= 4;
3400 }
3401
3402 /* Update the stack pointer, note that the register saves to do not
3403 modify SP. The SP adjustment is derived totally from the imm8
3404 field. */
3405 State.regs[REG_SP] -= IMM8;
3406 State.regs[REG_MDR] = next_pc;
3407 State.regs[REG_PC] += FETCH32(D32A, D32B, D32C, D32D);
3408 nia = PC;
3409 }
3410
3411
3412 // 1101 1111 regs.... imm8....; ret regs,imm8 (imm8 is zero-extended.)
3413 8.0xdf+8.REGS+8.IMM8:S2:::ret
3414 "ret"
3415 *mn10300
3416 {
3417 /* OP_DF0000 (); */
3418 unsigned int sp, offset;
3419 unsigned long mask;
3420
3421 PC = cia;
3422 State.regs[REG_SP] += IMM8;
3423 sp = State.regs[REG_SP];
3424
3425 offset = -4;
3426 mask = REGS;
3427
3428
3429 if (mask & 0x80)
3430 {
3431 State.regs[REG_D0 + 2] = load_word (sp + offset);
3432 offset -= 4;
3433 }
3434
3435 if (mask & 0x40)
3436 {
3437 State.regs[REG_D0 + 3] = load_word (sp + offset);
3438 offset -= 4;
3439 }
3440
3441 if (mask & 0x20)
3442 {
3443 State.regs[REG_A0 + 2] = load_word (sp + offset);
3444 offset -= 4;
3445 }
3446
3447 if (mask & 0x10)
3448 {
3449 State.regs[REG_A0 + 3] = load_word (sp + offset);
3450 offset -= 4;
3451 }
3452
3453 if (mask & 0x8)
3454 {
3455 State.regs[REG_D0] = load_word (sp + offset);
3456 offset -= 4;
3457 State.regs[REG_D0 + 1] = load_word (sp + offset);
3458 offset -= 4;
3459 State.regs[REG_A0] = load_word (sp + offset);
3460 offset -= 4;
3461 State.regs[REG_A0 + 1] = load_word (sp + offset);
3462 offset -= 4;
3463 State.regs[REG_MDR] = load_word (sp + offset);
3464 offset -= 4;
3465 State.regs[REG_LIR] = load_word (sp + offset);
3466 offset -= 4;
3467 State.regs[REG_LAR] = load_word (sp + offset);
3468 offset -= 4;
3469 }
3470
3471 /* Restore the PC value. */
3472 State.regs[REG_PC] = load_word(sp);
3473 nia = PC;
3474 }
3475
3476
3477 // 1101 1110 regs.... imm8....; retf regs,imm8 (imm8 is zero-extended.)
3478 8.0xde+8.REGS+8.IMM8:S2:::retf
3479 "retf"
3480 *mn10300
3481 {
3482 /* OP_DE0000 (); */
3483 unsigned int sp, offset;
3484 unsigned long mask;
3485
3486 PC = cia;
3487 State.regs[REG_SP] += IMM8;
3488 sp = State.regs[REG_SP];
3489 State.regs[REG_PC] = State.regs[REG_MDR] - 3;
3490
3491 offset = -4;
3492 mask = REGS;
3493
3494
3495 if (mask & 0x80)
3496 {
3497 State.regs[REG_D0 + 2] = load_word (sp + offset);
3498 offset -= 4;
3499 }
3500
3501 if (mask & 0x40)
3502 {
3503 State.regs[REG_D0 + 3] = load_word (sp + offset);
3504 offset -= 4;
3505 }
3506
3507 if (mask & 0x20)
3508 {
3509 State.regs[REG_A0 + 2] = load_word (sp + offset);
3510 offset -= 4;
3511 }
3512
3513 if (mask & 0x10)
3514 {
3515 State.regs[REG_A0 + 3] = load_word (sp + offset);
3516 offset -= 4;
3517 }
3518
3519 if (mask & 0x8)
3520 {
3521 State.regs[REG_D0] = load_word (sp + offset);
3522 offset -= 4;
3523 State.regs[REG_D0 + 1] = load_word (sp + offset);
3524 offset -= 4;
3525 State.regs[REG_A0] = load_word (sp + offset);
3526 offset -= 4;
3527 State.regs[REG_A0 + 1] = load_word (sp + offset);
3528 offset -= 4;
3529 State.regs[REG_MDR] = load_word (sp + offset);
3530 offset -= 4;
3531 State.regs[REG_LIR] = load_word (sp + offset);
3532 offset -= 4;
3533 State.regs[REG_LAR] = load_word (sp + offset);
3534 offset -= 4;
3535 }
3536 }
3537
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