sim/mn10300/mn10300_sim.h

   1 #include <stdio.h>
   2 #include <ctype.h>
   3 #include "ansidecl.h"
   4 #include "gdb/callback.h"
   5 #include "opcode/mn10300.h"
   6 #include <limits.h>
   7 #include "gdb/remote-sim.h"
   8 #include "bfd.h"
   9 #include "sim-fpu.h"
  10
  11 extern host_callback *mn10300_callback;
  12 extern SIM_DESC simulator;
  13
  14 typedef unsigned8 uint8;
  15 typedef signed8 int8;
  16 typedef unsigned16 uint16;
  17 typedef signed16 int16;
  18 typedef unsigned32 uint32;
  19 typedef signed32 int32;
  20
  21 typedef struct
  22 {
  23   uint32 low, high;
  24 } dword;
  25 typedef uint32 reg_t;
  26
  27 struct simops
  28 {
  29   long opcode;
  30   long mask;
  31   void (*func)();
  32   int length;
  33   int format;
  34   int numops;
  35   int operands[16];
  36 };
  37
  38 /* The current state of the processor; registers, memory, etc.  */
  39
  40 struct _state
  41 {
  42   reg_t regs[32];               /* registers, d0-d3, a0-a3, sp, pc, mdr, psw,
  43                                    lir, lar, mdrq, plus some room for processor
  44                                    specific regs.  */
  45   union
  46   {
  47     reg_t fs[32]; /* FS0-31 */
  48     dword fd[16]; /* FD0,2,...,30 */
  49   } fpregs;
  50
  51   /* All internal state modified by signal_exception() that may need to be
  52      rolled back for passing moment-of-exception image back to gdb. */
  53   reg_t exc_trigger_regs[32];
  54   reg_t exc_suspend_regs[32];
  55   int exc_suspended;
  56
  57 #define SIM_CPU_EXCEPTION_TRIGGER(SD,CPU,CIA) mn10300_cpu_exception_trigger(SD,CPU,CIA)
  58 #define SIM_CPU_EXCEPTION_SUSPEND(SD,CPU,EXC) mn10300_cpu_exception_suspend(SD,CPU,EXC)
  59 #define SIM_CPU_EXCEPTION_RESUME(SD,CPU,EXC) mn10300_cpu_exception_resume(SD,CPU,EXC)
  60 };
  61
  62 extern struct _state State;
  63
  64 #define PC      (State.regs[REG_PC])
  65 #define SP      (State.regs[REG_SP])
  66
  67 #define PSW (State.regs[11])
  68 #define PSW_Z 0x1
  69 #define PSW_N 0x2
  70 #define PSW_C 0x4
  71 #define PSW_V 0x8
  72 #define PSW_IE LSBIT (11)
  73 #define PSW_LM LSMASK (10, 8)
  74
  75 #define EXTRACT_PSW_LM LSEXTRACTED16 (PSW, 10, 8)
  76 #define INSERT_PSW_LM(l) LSINSERTED16 ((l), 10, 8)
  77
  78 #define REG_D0 0
  79 #define REG_A0 4
  80 #define REG_SP 8
  81 #define REG_PC 9
  82 #define REG_MDR 10
  83 #define REG_PSW 11
  84 #define REG_LIR 12
  85 #define REG_LAR 13
  86 #define REG_MDRQ 14
  87 #define REG_E0 15
  88 #define REG_SSP 23
  89 #define REG_MSP 24
  90 #define REG_USP 25
  91 #define REG_MCRH 26
  92 #define REG_MCRL 27
  93 #define REG_MCVF 28
  94
  95 #define REG_FPCR 29
  96
  97 #define FPCR (State.regs[REG_FPCR])
  98
  99 #define FCC_MASK LSMASK (21, 18)
 100 #define RM_MASK  LSMASK (17, 16) /* Must always be zero.  */
 101 #define EC_MASK  LSMASK (14, 10)
 102 #define EE_MASK  LSMASK ( 9,  5)
 103 #define EF_MASK  LSMASK ( 4,  0)
 104 #define FPCR_MASK (FCC_MASK | EC_MASK | EE_MASK | EF_MASK)
 105
 106 #define FCC_L LSBIT (21)
 107 #define FCC_G LSBIT (20)
 108 #define FCC_E LSBIT (19)
 109 #define FCC_U LSBIT (18)
 110
 111 #define EC_V LSBIT (14)
 112 #define EC_Z LSBIT (13)
 113 #define EC_O LSBIT (12)
 114 #define EC_U LSBIT (11)
 115 #define EC_I LSBIT (10)
 116
 117 #define EE_V LSBIT (9)
 118 #define EE_Z LSBIT (8)
 119 #define EE_O LSBIT (7)
 120 #define EE_U LSBIT (6)
 121 #define EE_I LSBIT (5)
 122
 123 #define EF_V LSBIT (4)
 124 #define EF_Z LSBIT (3)
 125 #define EF_O LSBIT (2)
 126 #define EF_U LSBIT (1)
 127 #define EF_I LSBIT (0)
 128
 129 #define PSW_FE LSBIT(20)
 130 #define FPU_DISABLED !(PSW & PSW_FE)
 131
 132 #define XS2FS(X,S) State.fpregs.fs[((X<<4)|(S))]
 133 #define AS2FS(A,S) State.fpregs.fs[((A<<2)|(S))]
 134 #define Xf2FD(X,f) State.fpregs.fd[((X<<3)|(f))]
 135
 136 #define FS2FPU(FS,F) sim_fpu_32to (&(F), (FS))
 137 #define FD2FPU(FD,F) sim_fpu_232to (&(F), ((FD).high), ((FD).low))
 138 #define FPU2FS(F,FS) sim_fpu_to32 (&(FS), &(F))
 139 #define FPU2FD(F,FD) sim_fpu_to232 (&((FD).high), &((FD).low), &(F))
 140
 141 #define FETCH32(a,b,c,d) \
 142  ((a)+((b)<<8)+((c)<<16)+((d)<<24))
 143
 144 #define FETCH24(a,b,c) \
 145  ((a)+((b)<<8)+((c)<<16))
 146
 147 #define FETCH16(a,b) ((a)+((b)<<8))
 148
 149 #define load_byte(ADDR) \
 150 sim_core_read_unaligned_1 (STATE_CPU (simulator, 0), PC, read_map, (ADDR))
 151
 152 #define load_half(ADDR) \
 153 sim_core_read_unaligned_2 (STATE_CPU (simulator, 0), PC, read_map, (ADDR))
 154
 155 #define load_word(ADDR) \
 156 sim_core_read_unaligned_4 (STATE_CPU (simulator, 0), PC, read_map, (ADDR))
 157
 158 #define load_dword(ADDR) \
 159 u642dw (sim_core_read_unaligned_8 (STATE_CPU (simulator, 0), \
 160                                    PC, read_map, (ADDR)))
 161
 162 static INLINE dword
 163 u642dw (unsigned64 dw)
 164 {
 165   dword r;
 166
 167   r.low = (unsigned32)dw;
 168   r.high = (unsigned32)(dw >> 32);
 169   return r;
 170 }
 171
 172 #define store_byte(ADDR, DATA) \
 173 sim_core_write_unaligned_1 (STATE_CPU (simulator, 0), \
 174                             PC, write_map, (ADDR), (DATA))
 175
 176
 177 #define store_half(ADDR, DATA) \
 178 sim_core_write_unaligned_2 (STATE_CPU (simulator, 0), \
 179                             PC, write_map, (ADDR), (DATA))
 180
 181
 182 #define store_word(ADDR, DATA) \
 183 sim_core_write_unaligned_4 (STATE_CPU (simulator, 0), \
 184                             PC, write_map, (ADDR), (DATA))
 185 #define store_dword(ADDR, DATA) \
 186 sim_core_write_unaligned_8 (STATE_CPU (simulator, 0), \
 187                             PC, write_map, (ADDR), dw2u64 (DATA))
 188
 189 static INLINE unsigned64
 190 dw2u64 (dword data)
 191 {
 192   return data.low | (((unsigned64)data.high) << 32);
 193 }
 194
 195 /* Function declarations.  */
 196
 197 INLINE_SIM_MAIN (void) genericAdd (unsigned32 source, unsigned32 destReg);
 198 INLINE_SIM_MAIN (void) genericSub (unsigned32 source, unsigned32 destReg);
 199 INLINE_SIM_MAIN (void) genericCmp (unsigned32 leftOpnd, unsigned32 rightOpnd);
 200 INLINE_SIM_MAIN (void) genericOr (unsigned32 source, unsigned32 destReg);
 201 INLINE_SIM_MAIN (void) genericXor (unsigned32 source, unsigned32 destReg);
 202 INLINE_SIM_MAIN (void) genericBtst (unsigned32 leftOpnd, unsigned32 rightOpnd);
 203 INLINE_SIM_MAIN (int) syscall_read_mem (host_callback *cb,
 204                                         struct cb_syscall *sc,
 205                                         unsigned long taddr,
 206                                         char *buf,
 207                                         int bytes);
 208 INLINE_SIM_MAIN (int) syscall_write_mem (host_callback *cb,
 209                                          struct cb_syscall *sc,
 210                                          unsigned long taddr,
 211                                          const char *buf,
 212                                          int bytes);
 213 INLINE_SIM_MAIN (void) do_syscall (void);
 214 void program_interrupt (SIM_DESC sd, sim_cpu *cpu, sim_cia cia, SIM_SIGNAL sig);
 215
 216 void mn10300_cpu_exception_trigger(SIM_DESC sd, sim_cpu* cpu, address_word pc);
 217 void mn10300_cpu_exception_suspend(SIM_DESC sd, sim_cpu* cpu, int exception);
 218 void mn10300_cpu_exception_resume(SIM_DESC sd, sim_cpu* cpu, int exception);
 219
 220 void fpu_disabled_exception     (SIM_DESC, sim_cpu *, address_word);
 221 void fpu_unimp_exception        (SIM_DESC, sim_cpu *, address_word);
 222 void fpu_check_signal_exception (SIM_DESC, sim_cpu *, address_word);
 223
 224 extern const struct fp_prec_t
 225 {
 226   void (* reg2val) (const void *, sim_fpu *);
 227   int (*  round)   (sim_fpu *);
 228   void (* val2reg) (const sim_fpu *, void *);
 229 } fp_single_prec, fp_double_prec;
 230
 231 #define FP_SINGLE (&fp_single_prec)
 232 #define FP_DOUBLE (&fp_double_prec)
 233
 234 void fpu_rsqrt  (SIM_DESC, sim_cpu *, address_word, const void *, void *, const struct fp_prec_t *);
 235 void fpu_sqrt   (SIM_DESC, sim_cpu *, address_word, const void *, void *, const struct fp_prec_t *);
 236 void fpu_cmp    (SIM_DESC, sim_cpu *, address_word, const void *, const void *, const struct fp_prec_t *);
 237 void fpu_add    (SIM_DESC, sim_cpu *, address_word, const void *, const void *, void *, const struct fp_prec_t *);
 238 void fpu_sub    (SIM_DESC, sim_cpu *, address_word, const void *, const void *, void *, const struct fp_prec_t *);
 239 void fpu_mul    (SIM_DESC, sim_cpu *, address_word, const void *, const void *, void *, const struct fp_prec_t *);
 240 void fpu_div    (SIM_DESC, sim_cpu *, address_word, const void *, const void *, void *, const struct fp_prec_t *);
 241 void fpu_fmadd  (SIM_DESC, sim_cpu *, address_word, const void *, const void *, const void *, void *, const struct fp_prec_t *);
 242 void fpu_fmsub  (SIM_DESC, sim_cpu *, address_word, const void *, const void *, const void *, void *, const struct fp_prec_t *);
 243 void fpu_fnmadd (SIM_DESC, sim_cpu *, address_word, const void *, const void *, const void *, void *, const struct fp_prec_t *);
 244 void fpu_fnmsub (SIM_DESC, sim_cpu *, address_word, const void *, const void *, const void *, void *, const struct fp_prec_t *);