1 /* Main simulator entry points specific to the OR1K.
2 Copyright (C) 2017-2021 Free Software Foundation, Inc.
4 This file is part of GDB, the GNU debugger.
6 This program is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3 of the License, or
9 (at your option) any later version.
11 This program is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with this program. If not, see <http://www.gnu.org/licenses/>. */
20 #include "sim-options.h"
21 #include "libiberty.h"
27 static void free_state (SIM_DESC
);
30 /* Cover function of sim_state_free to free the cpu buffers as well. */
33 free_state (SIM_DESC sd
)
35 if (STATE_MODULES (sd
) != NULL
)
36 sim_module_uninstall (sd
);
37 sim_cpu_free_all (sd
);
41 /* Defaults for user passed arguments. */
42 static const USI or1k_default_vr
= 0x0;
43 static const USI or1k_default_upr
= 0x0
44 | SPR_FIELD_MASK_SYS_UPR_UP
;
45 static const USI or1k_default_cpucfgr
= 0x0
46 | SPR_FIELD_MASK_SYS_CPUCFGR_OB32S
47 | SPR_FIELD_MASK_SYS_CPUCFGR_OF32S
;
51 static UWI or1k_cpucfgr
;
57 OPTION_OR1K_CPUCFGR
= OPTION_START
,
60 /* Setup help and handlers for the user defined arguments. */
61 DECLARE_OPTION_HANDLER (or1k_option_handler
);
63 static const OPTION or1k_options
[] = {
64 {{"or1k-cpucfgr", required_argument
, NULL
, OPTION_OR1K_CPUCFGR
},
65 '\0', "INTEGER|default", "Set simulator CPUCFGR value",
67 {{"or1k-vr", required_argument
, NULL
, OPTION_OR1K_VR
},
68 '\0', "INTEGER|default", "Set simulator VR value",
70 {{"or1k-upr", required_argument
, NULL
, OPTION_OR1K_UPR
},
71 '\0', "INTEGER|default", "Set simulator UPR value",
73 {{NULL
, no_argument
, NULL
, 0}, '\0', NULL
, NULL
, NULL
}
76 /* Handler for parsing user defined arguments. Currently we support
77 configuring some of the CPU implementation specific registers including
78 the Version Register (VR), the Unit Present Register (UPR) and the CPU
79 Configuration Register (CPUCFGR). */
81 or1k_option_handler (SIM_DESC sd
, sim_cpu
*cpu
, int opt
, char *arg
,
87 if (strcmp ("default", arg
) == 0)
88 or1k_vr
= or1k_default_vr
;
94 n
= strtoull (arg
, &endptr
, 0);
95 if (*arg
!= '\0' && *endptr
== '\0')
102 case OPTION_OR1K_UPR
:
103 if (strcmp ("default", arg
) == 0)
104 or1k_upr
= or1k_default_upr
;
107 unsigned long long n
;
110 n
= strtoull (arg
, &endptr
, 0);
111 if (*arg
!= '\0' && *endptr
== '\0')
116 (sd
, "invalid argument to option --or1k-upr: `%s'\n", arg
);
122 case OPTION_OR1K_CPUCFGR
:
123 if (strcmp ("default", arg
) == 0)
124 or1k_cpucfgr
= or1k_default_cpucfgr
;
127 unsigned long long n
;
130 n
= strtoull (arg
, &endptr
, 0);
131 if (*arg
!= '\0' && *endptr
== '\0')
136 (sd
, "invalid argument to option --or1k-cpucfgr: `%s'\n", arg
);
143 sim_io_eprintf (sd
, "Unknown or1k option %d\n", opt
);
150 /* Create an instance of the simulator. */
153 sim_open (SIM_OPEN_KIND kind
, host_callback
*callback
, struct bfd
*abfd
,
156 SIM_DESC sd
= sim_state_alloc (kind
, callback
);
160 /* The cpu data is kept in a separately allocated chunk of memory. */
161 if (sim_cpu_alloc_all (sd
, 1) != SIM_RC_OK
)
167 /* Perform initial sim setups. */
168 if (sim_pre_argv_init (sd
, argv
[0]) != SIM_RC_OK
)
174 or1k_upr
= or1k_default_upr
;
175 or1k_vr
= or1k_default_vr
;
176 or1k_cpucfgr
= or1k_default_cpucfgr
;
177 sim_add_option_table (sd
, NULL
, or1k_options
);
179 /* Parse the user passed arguments. */
180 if (sim_parse_args (sd
, argv
) != SIM_RC_OK
)
186 /* Allocate core managed memory if none specified by user.
187 Use address 4 here in case the user wanted address 0 unmapped. */
188 if (sim_core_read_buffer (sd
, NULL
, read_map
, &c
, 4, 1) == 0)
190 sim_do_commandf (sd
, "memory region 0,0x%x", OR1K_DEFAULT_MEM_SIZE
);
193 /* Check for/establish the reference program image. */
194 if (sim_analyze_program (sd
,
195 (STATE_PROG_ARGV (sd
) != NULL
196 ? *STATE_PROG_ARGV (sd
)
197 : NULL
), abfd
) != SIM_RC_OK
)
203 /* Establish any remaining configuration options. */
204 if (sim_config (sd
) != SIM_RC_OK
)
210 if (sim_post_argv_init (sd
) != SIM_RC_OK
)
216 /* Make sure delay slot mode is consistent with the loaded binary. */
217 if (STATE_ARCHITECTURE (sd
)->mach
== bfd_mach_or1knd
)
218 or1k_cpucfgr
|= SPR_FIELD_MASK_SYS_CPUCFGR_ND
;
220 or1k_cpucfgr
&= ~SPR_FIELD_MASK_SYS_CPUCFGR_ND
;
222 /* Open a copy of the cpu descriptor table and initialize the
223 disassembler. These initialization functions are generated by CGEN
224 using the binutils scheme cpu description files. */
227 or1k_cgen_cpu_open_1 (STATE_ARCHITECTURE (sd
)->printable_name
,
229 for (i
= 0; i
< MAX_NR_PROCESSORS
; ++i
)
231 SIM_CPU
*cpu
= STATE_CPU (sd
, i
);
232 CPU_CPU_DESC (cpu
) = cd
;
233 CPU_DISASSEMBLER (cpu
) = sim_cgen_disassemble_insn
;
235 or1k_cgen_init_dis (cd
);
238 /* Initialize various cgen things not done by common framework.
239 Must be done after or1k_cgen_cpu_open. */
242 /* Do some final OpenRISC sim specific initializations. */
243 for (c
= 0; c
< MAX_NR_PROCESSORS
; ++c
)
245 SIM_CPU
*cpu
= STATE_CPU (sd
, i
);
246 /* Only needed for profiling, but the structure member is small. */
247 memset (CPU_OR1K_MISC_PROFILE (cpu
), 0,
248 sizeof (*CPU_OR1K_MISC_PROFILE (cpu
)));
250 or1k_cpu_init (sd
, cpu
, or1k_vr
, or1k_upr
, or1k_cpucfgr
);
258 sim_create_inferior (SIM_DESC sd
, struct bfd
*abfd
,
259 char * const *argv
, char * const *envp
)
261 SIM_CPU
*current_cpu
= STATE_CPU (sd
, 0);
265 addr
= bfd_get_start_address (abfd
);
268 sim_pc_set (current_cpu
, addr
);