sim/ppc/std-config.h

   1 /*  This file is part of the program psim.
   2
   3     Copyright 1994, 1995, 2002 Andrew Cagney <cagney@highland.com.au>
   4
   5     This program is free software; you can redistribute it and/or modify
   6     it under the terms of the GNU General Public License as published by
   7     the Free Software Foundation; either version 3 of the License, or
   8     (at your option) any later version.
   9
  10     This program is distributed in the hope that it will be useful,
  11     but WITHOUT ANY WARRANTY; without even the implied warranty of
  12     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13     GNU General Public License for more details.
  14
  15     You should have received a copy of the GNU General Public License
  16     along with this program; if not, see <http://www.gnu.org/licenses/>.
  17
  18     */
  19
  20
  21 #ifndef _PSIM_CONFIG_H_
  22 #define _PSIM_CONFIG_H_
  23
  24
  25 /* endianness of the host/target:
  26
  27    If the build process is aware (at compile time) of the endianness
  28    of the host/target it is able to eliminate slower generic endian
  29    handling code.
  30
  31    Possible values are 0 (unknown), LITTLE_ENDIAN, BIG_ENDIAN */
  32
  33 #ifndef LITTLE_ENDIAN
  34 #define LITTLE_ENDIAN 1234
  35 #endif
  36 #ifndef BIG_ENDIAN
  37 #define BIG_ENDIAN 4321
  38 #endif
  39
  40 #ifdef WORDS_BIGENDIAN
  41 # define HOST_BYTE_ORDER BIG_ENDIAN
  42 #else
  43 # define HOST_BYTE_ORDER LITTLE_ENDIAN
  44 #endif
  45
  46 #ifndef WITH_TARGET_BYTE_ORDER
  47 #define WITH_TARGET_BYTE_ORDER          0 /*unknown*/
  48 #endif
  49
  50 extern int current_target_byte_order;
  51 #define CURRENT_TARGET_BYTE_ORDER (WITH_TARGET_BYTE_ORDER \
  52                                    ? WITH_TARGET_BYTE_ORDER \
  53                                    : current_target_byte_order)
  54
  55
  56 /* PowerPC XOR endian.
  57
  58    In addition to the above, the simulator can support the PowerPC's
  59    horrible XOR endian mode.  This feature makes it possible to
  60    control the endian mode of a processor using the MSR. */
  61
  62 #ifndef WITH_XOR_ENDIAN
  63 #define WITH_XOR_ENDIAN         8
  64 #endif
  65
  66
  67 /* SMP support:
  68
  69    Sets a limit on the number of processors that can be simulated.  If
  70    WITH_SMP is set to zero (0), the simulator is restricted to
  71    suporting only on processor (and as a consequence leaves the SMP
  72    code out of the build process).
  73
  74    The actual number of processors is taken from the device
  75    /options/smp@<nr-cpu> */
  76
  77 #ifndef WITH_SMP
  78 #define WITH_SMP                        5
  79 #endif
  80 #if WITH_SMP
  81 #define MAX_NR_PROCESSORS               WITH_SMP
  82 #else
  83 #define MAX_NR_PROCESSORS               1
  84 #endif
  85
  86
  87 /* Word size of host/target:
  88
  89    Set these according to your host and target requirements.  At this
  90    point in time, I've only compiled (not run) for a 64bit and never
  91    built for a 64bit host.  This will always remain a compile time
  92    option */
  93
  94 #ifndef WITH_TARGET_WORD_BITSIZE
  95 #define WITH_TARGET_WORD_BITSIZE        32 /* compiled only */
  96 #endif
  97
  98 #ifndef WITH_HOST_WORD_BITSIZE
  99 #define WITH_HOST_WORD_BITSIZE          32 /* 64bit ready? */
 100 #endif
 101
 102
 103 /* Program environment:
 104
 105    Three environments are available - UEA (user), VEA (virtual) and
 106    OEA (perating).  The former two are environment that users would
 107    expect to see (VEA includes things like coherency and the time
 108    base) while OEA is what an operating system expects to see.  By
 109    setting these to specific values, the build process is able to
 110    eliminate non relevent environment code
 111
 112    CURRENT_ENVIRONMENT specifies which of vea or oea is required for
 113    the current runtime. */
 114
 115 #define ALL_ENVIRONMENT                 0
 116 #define USER_ENVIRONMENT                1
 117 #define VIRTUAL_ENVIRONMENT             2
 118 #define OPERATING_ENVIRONMENT           3
 119
 120 extern int current_environment;
 121 #define CURRENT_ENVIRONMENT (WITH_ENVIRONMENT \
 122                              ? WITH_ENVIRONMENT \
 123                              : current_environment)
 124
 125
 126 /* Optional VEA/OEA code:
 127
 128    The below, required for the OEA model may also be included in the
 129    VEA model however, as far as I can tell only make things
 130    slower... */
 131
 132
 133 /* Events.  Devices modeling real H/W need to be able to efficiently
 134    schedule things to do at known times in the future.  The event
 135    queue implements this.  Unfortunatly this adds the need to check
 136    for any events once each full instruction cycle. */
 137
 138 #define WITH_EVENTS                     (WITH_ENVIRONMENT != USER_ENVIRONMENT)
 139
 140
 141 /* Time base:
 142
 143    The PowerPC architecture includes the addition of both a time base
 144    register and a decrement timer.  Like events adds to the overhead
 145    of of some instruction cycles. */
 146
 147 #ifndef WITH_TIME_BASE
 148 #define WITH_TIME_BASE                  (WITH_ENVIRONMENT != USER_ENVIRONMENT)
 149 #endif
 150
 151
 152 /* Callback/Default Memory.
 153
 154    Core includes a builtin memory type (raw_memory) that is
 155    implemented using an array.  raw_memory does not require any
 156    additional functions etc.
 157
 158    Callback memory is where the core calls a core device for the data
 159    it requires.
 160
 161    Default memory is an extenstion of this where for addresses that do
 162    not map into either a callback or core memory range a default map
 163    can be used.
 164
 165    The OEA model uses callback memory for devices and default memory
 166    for buses.
 167
 168    The VEA model uses callback memory to capture `page faults'.
 169
 170    While it may be possible to eliminate callback/default memory (and
 171    hence also eliminate an additional test per memory fetch) it
 172    probably is not worth the effort.
 173
 174    BTW, while raw_memory could have been implemented as a callback,
 175    profiling has shown that there is a biger win (at least for the
 176    x86) in eliminating a function call for the most common
 177    (raw_memory) case. */
 178
 179 #define WITH_CALLBACK_MEMORY            1
 180
 181
 182 /* Alignment:
 183
 184    The PowerPC may or may not handle miss aligned transfers.  An
 185    implementation normally handles miss aligned transfers in big
 186    endian mode but generates an exception in little endian mode.
 187
 188    This model.  Instead allows both little and big endian modes to
 189    either take exceptions or handle miss aligned transfers.
 190
 191    If 0 is specified then for big-endian mode miss alligned accesses
 192    are permitted (NONSTRICT_ALIGNMENT) while in little-endian mode the
 193    processor will fault on them (STRICT_ALIGNMENT). */
 194
 195 #define NONSTRICT_ALIGNMENT             1
 196 #define STRICT_ALIGNMENT                2
 197
 198 #ifndef WITH_ALIGNMENT
 199 #define WITH_ALIGNMENT                  0
 200 #endif
 201
 202 extern int current_alignment;
 203 #define CURRENT_ALIGNMENT (WITH_ALIGNMENT \
 204                            ? WITH_ALIGNMENT \
 205                            : current_alignment)
 206
 207
 208 /* Floating point suport:
 209
 210    Still under development. */
 211
 212 #define SOFT_FLOATING_POINT             1
 213 #define HARD_FLOATING_POINT             2
 214
 215 #ifndef WITH_FLOATING_POINT
 216 #define WITH_FLOATING_POINT             HARD_FLOATING_POINT
 217 #endif
 218 extern int current_floating_point;
 219 #define CURRENT_FLOATING_POINT (WITH_FLOATING_POINT \
 220                                 ? WITH_FLOATING_POINT \
 221                                 : current_floating_point)
 222
 223
 224 /* Debugging:
 225
 226    Control the inclusion of debugging code. */
 227
 228 /* Whether to check instructions for reserved bits being set */
 229
 230 #ifndef WITH_RESERVED_BITS
 231 #define WITH_RESERVED_BITS              1
 232 #endif
 233
 234 /* include monitoring code */
 235
 236 #define MONITOR_INSTRUCTION_ISSUE       1
 237 #define MONITOR_LOAD_STORE_UNIT         2
 238 #ifndef WITH_MON
 239 #define WITH_MON                        (MONITOR_LOAD_STORE_UNIT \
 240                                          | MONITOR_INSTRUCTION_ISSUE)
 241 #endif
 242
 243 /* Current CPU model (models are in the generated models.h include file)  */
 244 #ifndef WITH_MODEL
 245 #define WITH_MODEL                      0
 246 #endif
 247
 248 #define CURRENT_MODEL (WITH_MODEL       \
 249                        ? WITH_MODEL     \
 250                        : current_model)
 251
 252 #ifndef WITH_DEFAULT_MODEL
 253 #define WITH_DEFAULT_MODEL              DEFAULT_MODEL
 254 #endif
 255
 256 #define MODEL_ISSUE_IGNORE              (-1)
 257 #define MODEL_ISSUE_PROCESS             1
 258
 259 #ifndef WITH_MODEL_ISSUE
 260 #define WITH_MODEL_ISSUE                0
 261 #endif
 262
 263 extern int current_model_issue;
 264 #define CURRENT_MODEL_ISSUE (WITH_MODEL_ISSUE   \
 265                              ? WITH_MODEL_ISSUE \
 266                              : current_model_issue)
 267
 268 /* Whether or not input/output just uses stdio, or uses printf_filtered for
 269    output, and polling input for input.  */
 270
 271 #define DONT_USE_STDIO                  2
 272 #define DO_USE_STDIO                    1
 273
 274 extern int current_stdio;
 275 #define CURRENT_STDIO (WITH_STDIO       \
 276                        ? WITH_STDIO     \
 277                        : current_stdio)
 278
 279
 280
 281 /* INLINE CODE SELECTION:
 282
 283    GCC -O3 attempts to inline any function or procedure in scope.  The
 284    options below facilitate fine grained control over what is and what
 285    isn't made inline.  For instance it can control things down to a
 286    specific modules static routines.  Doing this allows the compiler
 287    to both eliminate the overhead of function calls and (as a
 288    consequence) also eliminate further dead code.
 289
 290    On a CISC (x86) I've found that I can achieve an order of magnitude
 291    speed improvement (x3-x5).  In the case of RISC (sparc) while the
 292    performance gain isn't as great it is still significant.
 293
 294    Each module is controled by the macro <module>_INLINE which can
 295    have the values described below
 296
 297        0  Do not inline any thing for the given module
 298
 299    The following additional values are `bit fields' and can be
 300    combined.
 301
 302       REVEAL_MODULE:
 303
 304          Include the C file for the module into the file being compiled
 305          but do not make the functions within the module inline.
 306
 307          While of no apparent benefit, this makes it possible for the
 308          included module, when compiled to inline its calls to what
 309          would otherwize be external functions.
 310
 311       INLINE_MODULE:
 312
 313          Make external functions within the module `inline'.  Thus if
 314          the module is included into a file being compiled, calls to
 315          its funtions can be eliminated. 2 implies 1.
 316
 317       PSIM_INLINE_LOCALS:
 318
 319          Make internal (static) functions within the module `inline'.
 320
 321    The following abreviations are available:
 322
 323       INCLUDE_MODULE == (REVEAL_MODULE | INLINE_MODULE)
 324
 325       ALL_INLINE == (REVEAL_MODULE | INLINE_MODULE | PSIM_INLINE_LOCALS)
 326
 327    In addition to this, modules have been put into two categories.
 328
 329          Simple modules - eg sim-endian.h bits.h
 330
 331          Because these modules are small and simple and do not have
 332          any complex interpendencies they are configured, if
 333          <module>_INLINE is so enabled, to inline themselves in all
 334          modules that include those files.
 335
 336          For the default build, this is a real win as all byte
 337          conversion and bit manipulation functions are inlined.
 338
 339          Complex modules - the rest
 340
 341          These are all handled using the files inline.h and inline.c.
 342          psim.c includes the above which in turn include any remaining
 343          code.
 344
 345    IMPLEMENTATION:
 346
 347    The inline ability is enabled by prefixing every data / function
 348    declaration and definition with one of the following:
 349
 350
 351        INLINE_<module>
 352
 353        Prefix to any global function that is a candidate for being
 354        inline.
 355
 356        values - `', `static', `static INLINE'
 357
 358
 359        EXTERN_<module>
 360
 361        Prefix to any global data structures for the module.  Global
 362        functions that are not to be inlined shall also be prefixed
 363        with this.
 364
 365        values - `', `static', `static'
 366
 367
 368        STATIC_INLINE_<module>
 369
 370        Prefix to any local (static) function that is a candidate for
 371        being made inline.
 372
 373        values - `static', `static INLINE'
 374
 375
 376        static
 377
 378        Prefix all local data structures.  Local functions that are not
 379        to be inlined shall also be prefixed with this.
 380
 381        values - `static', `static'
 382
 383        nb: will not work for modules that are being inlined for every
 384        use (white lie).
 385
 386
 387        extern
 388        #ifndef _INLINE_C_
 389        #endif
 390
 391        Prefix to any declaration of a global object (function or
 392        variable) that should not be inlined and should have only one
 393        definition.  The #ifndef wrapper goes around the definition
 394        propper to ensure that only one copy is generated.
 395
 396        nb: this will not work when a module is being inlined for every
 397        use.
 398
 399
 400        STATIC_<module>
 401
 402        Replaced by either `static' or `EXTERN_MODULE'.
 403
 404
 405    REALITY CHECK:
 406
 407    This is not for the faint hearted.  I've seen GCC get up to 500mb
 408    trying to compile what this can create.
 409
 410    Some of the modules do not yet implement the WITH_INLINE_STATIC
 411    option.  Instead they use the macro STATIC_INLINE to control their
 412    local function.
 413
 414    Because of the way that GCC parses __attribute__(), the macro's
 415    need to be adjacent to the function name rather than at the start
 416    of the line vis:
 417
 418         int STATIC_INLINE_MODULE f(void);
 419         void INLINE_MODULE *g(void);
 420
 421    */
 422
 423 #define REVEAL_MODULE                   1
 424 #define INLINE_MODULE                   2
 425 #define INCLUDE_MODULE                  (INLINE_MODULE | REVEAL_MODULE)
 426 #define PSIM_INLINE_LOCALS                      4
 427 #define ALL_INLINE                      7
 428
 429 /* Your compilers inline reserved word */
 430
 431 #ifndef INLINE
 432 #if defined(__GNUC__) && defined(__OPTIMIZE__)
 433 #define INLINE __inline__
 434 #else
 435 #define INLINE /*inline*/
 436 #endif
 437 #endif
 438
 439
 440 /* Default prefix for static functions */
 441
 442 #ifndef STATIC_INLINE
 443 #define STATIC_INLINE static INLINE
 444 #endif
 445
 446 /* Default macro to simplify control several of key the inlines */
 447
 448 #ifndef DEFAULT_INLINE
 449 #define DEFAULT_INLINE                  PSIM_INLINE_LOCALS
 450 #endif
 451
 452 /* Code that converts between hosts and target byte order.  Used on
 453    every memory access (instruction and data).  See sim-endian.h for
 454    additional byte swapping configuration information.  This module
 455    can inline for all callers */
 456
 457 #ifndef SIM_ENDIAN_INLINE
 458 #define SIM_ENDIAN_INLINE               (DEFAULT_INLINE ? ALL_INLINE : 0)
 459 #endif
 460
 461 /* Low level bit manipulation routines. This module can inline for all
 462    callers */
 463
 464 #ifndef BITS_INLINE
 465 #define BITS_INLINE                     (DEFAULT_INLINE ? ALL_INLINE : 0)
 466 #endif
 467
 468 /* Code that gives access to various CPU internals such as registers.
 469    Used every time an instruction is executed */
 470
 471 #ifndef CPU_INLINE
 472 #define CPU_INLINE                      (DEFAULT_INLINE ? ALL_INLINE : 0)
 473 #endif
 474
 475 /* Code that translates between an effective and real address.  Used
 476    by every load or store. */
 477
 478 #ifndef VM_INLINE
 479 #define VM_INLINE                       DEFAULT_INLINE
 480 #endif
 481
 482 /* Code that loads/stores data to/from the memory data structure.
 483    Used by every load or store */
 484
 485 #ifndef CORE_INLINE
 486 #define CORE_INLINE                     DEFAULT_INLINE
 487 #endif
 488
 489 /* Code to check for and process any events scheduled in the future.
 490    Called once per instruction cycle */
 491
 492 #ifndef EVENTS_INLINE
 493 #define EVENTS_INLINE                   (DEFAULT_INLINE ? ALL_INLINE : 0)
 494 #endif
 495
 496 /* Code monotoring the processors performance.  It counts events on
 497    every instruction cycle */
 498
 499 #ifndef MON_INLINE
 500 #define MON_INLINE                      (DEFAULT_INLINE ? ALL_INLINE : 0)
 501 #endif
 502
 503 /* Code called on the rare occasions that an interrupt occures. */
 504
 505 #ifndef INTERRUPTS_INLINE
 506 #define INTERRUPTS_INLINE               DEFAULT_INLINE
 507 #endif
 508
 509 /* Code called on the rare occasion that either gdb or the device tree
 510    need to manipulate a register within a processor */
 511
 512 #ifndef REGISTERS_INLINE
 513 #define REGISTERS_INLINE                DEFAULT_INLINE
 514 #endif
 515
 516 /* Code called on the rare occasion that a processor is manipulating
 517    real hardware instead of RAM.
 518
 519    Also, most of the functions in devices.c are always called through
 520    a jump table. */
 521
 522 #ifndef DEVICE_INLINE
 523 #define DEVICE_INLINE                   (DEFAULT_INLINE ? PSIM_INLINE_LOCALS : 0)
 524 #endif
 525
 526 /* Code called used while the device tree is being built.
 527
 528    Inlining this is of no benefit */
 529
 530 #ifndef TREE_INLINE
 531 #define TREE_INLINE                     (DEFAULT_INLINE ? PSIM_INLINE_LOCALS : 0)
 532 #endif
 533
 534 /* Code called whenever information on a Special Purpose Register is
 535    required.  Called by the mflr/mtlr pseudo instructions */
 536
 537 #ifndef SPREG_INLINE
 538 #define SPREG_INLINE                    DEFAULT_INLINE
 539 #endif
 540
 541 /* Functions modeling the semantics of each instruction.  Two cases to
 542    consider, firstly of idecode is implemented with a switch then this
 543    allows the idecode function to inline each semantic function
 544    (avoiding a call).  The second case is when idecode is using a
 545    table, even then while the semantic functions can't be inlined,
 546    setting it to one still enables each semantic function to inline
 547    anything they call (if that code is marked for being inlined).
 548
 549    WARNING: you need lots (like 200mb of swap) of swap.  Setting this
 550    to 1 is useful when using a table as it enables the sematic code to
 551    inline all of their called functions */
 552
 553 #ifndef SEMANTICS_INLINE
 554 #define SEMANTICS_INLINE                (DEFAULT_INLINE & ~INLINE_MODULE)
 555 #endif
 556
 557 /* When using the instruction cache, code to decode an instruction and
 558    install it into the cache.  Normally called when ever there is a
 559    miss in the instruction cache. */
 560
 561 #ifndef ICACHE_INLINE
 562 #define ICACHE_INLINE                   (DEFAULT_INLINE & ~INLINE_MODULE)
 563 #endif
 564
 565 /* General functions called by semantics functions but part of the
 566    instruction table.  Although called by the semantic functions the
 567    frequency of calls is low.  Consequently the need to inline this
 568    code is reduced. */
 569
 570 #ifndef SUPPORT_INLINE
 571 #define SUPPORT_INLINE                  PSIM_INLINE_LOCALS
 572 #endif
 573
 574 /* Model specific code used in simulating functional units.  Note, it actaully
 575    pays NOT to inline the PowerPC model functions (at least on the x86).  This
 576    is because if it is inlined, each PowerPC instruction gets a separate copy
 577    of the code, which is not friendly to the cache.  */
 578
 579 #ifndef MODEL_INLINE
 580 #define MODEL_INLINE                    (DEFAULT_INLINE & ~INLINE_MODULE)
 581 #endif
 582
 583 /* Code to print out what options we were compiled with.  Because this
 584    is called at process startup, it doesn't have to be inlined, but
 585    if it isn't brought in and the model routines are inline, the model
 586    routines will be pulled in twice.  */
 587
 588 #ifndef OPTIONS_INLINE
 589 #define OPTIONS_INLINE                  MODEL_INLINE
 590 #endif
 591
 592 /* idecode acts as the hub of the system, everything else is imported
 593    into this file */
 594
 595 #ifndef IDECOCE_INLINE
 596 #define IDECODE_INLINE                  PSIM_INLINE_LOCALS
 597 #endif
 598
 599 /* psim, isn't actually inlined */
 600
 601 #ifndef PSIM_INLINE
 602 #define PSIM_INLINE                     PSIM_INLINE_LOCALS
 603 #endif
 604
 605 /* Code to emulate os or rom compatibility.  This code is called via a
 606    table and hence there is little benefit in making it inline */
 607
 608 #ifndef OS_EMUL_INLINE
 609 #define OS_EMUL_INLINE                  0
 610 #endif
 611
 612 #endif /* _PSIM_CONFIG_H */