sim/riscv/ChangeLog

   1 2021-04-21  Mike Frysinger  <vapier@gentoo.org>
   2
   3         * aclocal.m4: Regenerate.
   4
   5 2021-04-21  Simon Marchi  <simon.marchi@polymtl.ca>
   6
   7         * configure: Regenerate.
   8
   9 2021-04-18  Mike Frysinger  <vapier@gentoo.org>
  10
  11         * configure: Regenerate.
  12
  13 2021-04-12  Mike Frysinger  <vapier@gentoo.org>
  14
  15         * interp.c (sim_open): Delete 3rd arg to sim_cpu_alloc_all.
  16
  17 2021-04-02  Mike Frysinger  <vapier@gentoo.org>
  18
  19         * aclocal.m4, configure: Regenerate.
  20
  21 2021-02-28  Mike Frysinger  <vapier@gentoo.org>
  22
  23         * configure: Regenerate.
  24
  25 2021-02-21  Mike Frysinger  <vapier@gentoo.org>
  26
  27         * configure.ac (AC_CONFIG_MACRO_DIRS): Replace common with m4.
  28         * aclocal.m4, configure: Regenerate.
  29
  30 2021-02-13  Mike Frysinger  <vapier@gentoo.org>
  31
  32         * configure.ac: Replace sinclude with AC_CONFIG_MACRO_DIRS.
  33         * aclocal.m4, configure: Regenerate.
  34
  35 2021-02-06  Mike Frysinger  <vapier@gentoo.org>
  36
  37         * configure: Regenerate.
  38
  39 2021-02-04  Mike Frysinger  <vapier@gentoo.org>
  40
  41         * sim-main.c: Include gdb/sim-riscv.h.
  42         (reg_fetch, reg_store): Define.
  43         (initialize_cpu): Assign reg_fetch & reg_store.
  44
  45 2021-02-04  Mike Frysinger  <vapier@gentoo.org>
  46
  47         * Makefile.in, configure.ac, interp.c, machs.c, machs.h,
  48         model_list.def, sim-main.c, sim-main.h: New files.
  49         * aclocal.m4, config.in, configure: Regenerated.