sim/sh/interp.c

   1 /* Simulator for the Hitachi SH architecture.
   2
   3    Written by Steve Chamberlain of Cygnus Support.
   4    sac@cygnus.com
   5
   6    This file is part of SH sim
   7
   8
   9                 THIS SOFTWARE IS NOT COPYRIGHTED
  10
  11    Cygnus offers the following for use in the public domain.  Cygnus
  12    makes no warranty with regard to the software or it's performance
  13    and the user accepts the software "AS IS" with all faults.
  14
  15    CYGNUS DISCLAIMS ANY WARRANTIES, EXPRESS OR IMPLIED, WITH REGARD TO
  16    THIS SOFTWARE INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  17    MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.
  18
  19 */
  20
  21 #include "config.h"
  22
  23 #include <signal.h>
  24 #ifdef HAVE_UNISTD_H
  25 #include <unistd.h>
  26 #endif
  27
  28 #include "sysdep.h"
  29 #include "bfd.h"
  30 #include "gdb/callback.h"
  31 #include "gdb/remote-sim.h"
  32 #include "gdb/sim-sh.h"
  33
  34 /* This file is local - if newlib changes, then so should this.  */
  35 #include "syscall.h"
  36
  37 #include <math.h>
  38
  39 #ifdef _WIN32
  40 #include <float.h>              /* Needed for _isnan() */
  41 #define isnan _isnan
  42 #endif
  43
  44 #ifndef SIGBUS
  45 #define SIGBUS SIGSEGV
  46 #endif
  47
  48 #ifndef SIGQUIT
  49 #define SIGQUIT SIGTERM
  50 #endif
  51
  52 #ifndef SIGTRAP
  53 #define SIGTRAP 5
  54 #endif
  55
  56 extern unsigned char sh_jump_table[], sh_dsp_table[0x1000], ppi_table[];
  57
  58 int sim_write (SIM_DESC sd, SIM_ADDR addr, unsigned char *buffer, int size);
  59
  60 #define O_RECOMPILE 85
  61 #define DEFINE_TABLE
  62 #define DISASSEMBLER_TABLE
  63
  64 /* Define the rate at which the simulator should poll the host
  65    for a quit. */
  66 #define POLL_QUIT_INTERVAL 0x60000
  67
  68 typedef union
  69 {
  70
  71   struct
  72   {
  73     int regs[16];
  74     int pc;
  75
  76     /* System registers.  For sh-dsp this also includes A0 / X0 / X1 / Y0 / Y1
  77        which are located in fregs, i.e. strictly speaking, these are
  78        out-of-bounds accesses of sregs.i .  This wart of the code could be
  79        fixed by making fregs part of sregs, and including pc too - to avoid
  80        alignment repercussions - but this would cause very onerous union /
  81        structure nesting, which would only be managable with anonymous
  82        unions and structs.  */
  83     union
  84       {
  85         struct
  86           {
  87             int mach;
  88             int macl;
  89             int pr;
  90             int dummy3, dummy4;
  91             int fpul; /* A1 for sh-dsp -  but only for movs etc.  */
  92             int fpscr; /* dsr for sh-dsp */
  93           } named;
  94         int i[7];
  95       } sregs;
  96
  97     /* sh3e / sh-dsp */
  98     union fregs_u
  99       {
 100         float f[16];
 101         double d[8];
 102         int i[16];
 103       }
 104     fregs[2];
 105
 106     /* Control registers; on the SH4, ldc / stc is privileged, except when
 107        accessing gbr.  */
 108     union
 109       {
 110         struct
 111           {
 112             int sr;
 113             int gbr;
 114             int vbr;
 115             int ssr;
 116             int spc;
 117             int mod;
 118             /* sh-dsp */
 119             int rs;
 120             int re;
 121             /* sh3 */
 122             int bank[8];
 123           } named;
 124         int i[16];
 125       } cregs;
 126
 127     unsigned char *insn_end;
 128
 129     int ticks;
 130     int stalls;
 131     int memstalls;
 132     int cycles;
 133     int insts;
 134
 135     int prevlock;
 136     int thislock;
 137     int exception;
 138
 139     int end_of_registers;
 140
 141     int msize;
 142 #define PROFILE_FREQ 1
 143 #define PROFILE_SHIFT 2
 144     int profile;
 145     unsigned short *profile_hist;
 146     unsigned char *memory;
 147     int xyram_select, xram_start, yram_start;
 148     unsigned char *xmem;
 149     unsigned char *ymem;
 150     unsigned char *xmem_offset;
 151     unsigned char *ymem_offset;
 152   }
 153   asregs;
 154   int asints[40];
 155 } saved_state_type;
 156
 157 saved_state_type saved_state;
 158
 159 struct loop_bounds { unsigned char *start, *end; };
 160
 161 /* These variables are at file scope so that functions other than
 162    sim_resume can use the fetch/store macros */
 163
 164 static int target_little_endian;
 165 static int global_endianw, endianb;
 166 static int target_dsp;
 167 static int host_little_endian;
 168 static char **prog_argv;
 169
 170 #if 1
 171 static int maskw = 0;
 172 #endif
 173
 174 static SIM_OPEN_KIND sim_kind;
 175 static char *myname;
 176
 177
 178 /* Short hand definitions of the registers */
 179
 180 #define SBIT(x) ((x)&sbit)
 181 #define R0      saved_state.asregs.regs[0]
 182 #define Rn      saved_state.asregs.regs[n]
 183 #define Rm      saved_state.asregs.regs[m]
 184 #define UR0     (unsigned int)(saved_state.asregs.regs[0])
 185 #define UR      (unsigned int)R
 186 #define UR      (unsigned int)R
 187 #define SR0     saved_state.asregs.regs[0]
 188 #define CREG(n) (saved_state.asregs.cregs.i[(n)])
 189 #define GBR     saved_state.asregs.cregs.named.gbr
 190 #define VBR     saved_state.asregs.cregs.named.vbr
 191 #define SSR     saved_state.asregs.cregs.named.ssr
 192 #define SPC     saved_state.asregs.cregs.named.spc
 193 #define SREG(n) (saved_state.asregs.sregs.i[(n)])
 194 #define MACH    saved_state.asregs.sregs.named.mach
 195 #define MACL    saved_state.asregs.sregs.named.macl
 196 #define PR      saved_state.asregs.sregs.named.pr
 197 #define FPUL    saved_state.asregs.sregs.named.fpul
 198
 199 #define PC insn_ptr
 200
 201
 202
 203 /* Alternate bank of registers r0-r7 */
 204
 205 /* Note: code controling SR handles flips between BANK0 and BANK1 */
 206 #define Rn_BANK(n) (saved_state.asregs.cregs.named.bank[(n)])
 207 #define SET_Rn_BANK(n, EXP) do { saved_state.asregs.cregs.named.bank[(n)] = (EXP); } while (0)
 208
 209
 210 /* Manipulate SR */
 211
 212 #define SR_MASK_DMY (1 << 11)
 213 #define SR_MASK_DMX (1 << 10)
 214 #define SR_MASK_M (1 << 9)
 215 #define SR_MASK_Q (1 << 8)
 216 #define SR_MASK_I (0xf << 4)
 217 #define SR_MASK_S (1 << 1)
 218 #define SR_MASK_T (1 << 0)
 219
 220 #define SR_MASK_BL (1 << 28)
 221 #define SR_MASK_RB (1 << 29)
 222 #define SR_MASK_MD (1 << 30)
 223 #define SR_MASK_RC 0x0fff0000
 224 #define SR_RC_INCREMENT -0x00010000
 225
 226 #define M       ((saved_state.asregs.cregs.named.sr & SR_MASK_M) != 0)
 227 #define Q       ((saved_state.asregs.cregs.named.sr & SR_MASK_Q) != 0)
 228 #define S       ((saved_state.asregs.cregs.named.sr & SR_MASK_S) != 0)
 229 #define T       ((saved_state.asregs.cregs.named.sr & SR_MASK_T) != 0)
 230
 231 #define SR_BL ((saved_state.asregs.cregs.named.sr & SR_MASK_BL) != 0)
 232 #define SR_RB ((saved_state.asregs.cregs.named.sr & SR_MASK_RB) != 0)
 233 #define SR_MD ((saved_state.asregs.cregs.named.sr & SR_MASK_MD) != 0)
 234 #define SR_DMY ((saved_state.asregs.cregs.named.sr & SR_MASK_DMY) != 0)
 235 #define SR_DMX ((saved_state.asregs.cregs.named.sr & SR_MASK_DMX) != 0)
 236 #define SR_RC ((saved_state.asregs.cregs.named.sr & SR_MASK_RC))
 237
 238 /* Note: don't use this for privileged bits */
 239 #define SET_SR_BIT(EXP, BIT) \
 240 do { \
 241   if ((EXP) & 1) \
 242     saved_state.asregs.cregs.named.sr |= (BIT); \
 243   else \
 244     saved_state.asregs.cregs.named.sr &= ~(BIT); \
 245 } while (0)
 246
 247 #define SET_SR_M(EXP) SET_SR_BIT ((EXP), SR_MASK_M)
 248 #define SET_SR_Q(EXP) SET_SR_BIT ((EXP), SR_MASK_Q)
 249 #define SET_SR_S(EXP) SET_SR_BIT ((EXP), SR_MASK_S)
 250 #define SET_SR_T(EXP) SET_SR_BIT ((EXP), SR_MASK_T)
 251
 252 /* stc currently relies on being able to read SR without modifications.  */
 253 #define GET_SR() (saved_state.asregs.cregs.named.sr - 0)
 254
 255 #define SET_SR(x) set_sr (x)
 256
 257 #define SET_RC(x) \
 258   (saved_state.asregs.cregs.named.sr \
 259    = saved_state.asregs.cregs.named.sr & 0xf000ffff | ((x) & 0xfff) << 16)
 260
 261 /* Manipulate FPSCR */
 262
 263 #define FPSCR_MASK_FR (1 << 21)
 264 #define FPSCR_MASK_SZ (1 << 20)
 265 #define FPSCR_MASK_PR (1 << 19)
 266
 267 #define FPSCR_FR  ((GET_FPSCR() & FPSCR_MASK_FR) != 0)
 268 #define FPSCR_SZ  ((GET_FPSCR() & FPSCR_MASK_SZ) != 0)
 269 #define FPSCR_PR  ((GET_FPSCR() & FPSCR_MASK_PR) != 0)
 270
 271 /* Count the number of arguments in an argv.  */
 272 static int
 273 count_argc (char **argv)
 274 {
 275   int i;
 276
 277   if (! argv)
 278     return -1;
 279
 280   for (i = 0; argv[i] != NULL; ++i)
 281     continue;
 282   return i;
 283 }
 284
 285 static void
 286 set_fpscr1 (x)
 287         int x;
 288 {
 289   int old = saved_state.asregs.sregs.named.fpscr;
 290   saved_state.asregs.sregs.named.fpscr = (x);
 291   /* swap the floating point register banks */
 292   if ((saved_state.asregs.sregs.named.fpscr ^ old) & FPSCR_MASK_FR
 293       /* Ignore bit change if simulating sh-dsp.  */
 294       && ! target_dsp)
 295     {
 296       union fregs_u tmpf = saved_state.asregs.fregs[0];
 297       saved_state.asregs.fregs[0] = saved_state.asregs.fregs[1];
 298       saved_state.asregs.fregs[1] = tmpf;
 299     }
 300 }
 301
 302 /* sts relies on being able to read fpscr directly.  */
 303 #define GET_FPSCR()  (saved_state.asregs.sregs.named.fpscr)
 304 #define SET_FPSCR(x) \
 305 do { \
 306   set_fpscr1 (x); \
 307 } while (0)
 308
 309 #define DSR  (saved_state.asregs.sregs.named.fpscr)
 310
 311 int
 312 fail ()
 313 {
 314   abort ();
 315 }
 316
 317 #define RAISE_EXCEPTION(x) \
 318   (saved_state.asregs.exception = x, saved_state.asregs.insn_end = 0)
 319
 320 /* This function exists mainly for the purpose of setting a breakpoint to
 321    catch simulated bus errors when running the simulator under GDB.  */
 322
 323 void
 324 raise_exception (x)
 325      int x;
 326 {
 327   RAISE_EXCEPTION(x);
 328 }
 329
 330 void
 331 raise_buserror ()
 332 {
 333   raise_exception (SIGBUS);
 334 }
 335
 336 #define PROCESS_SPECIAL_ADDRESS(addr, endian, ptr, bits_written, \
 337                                 forbidden_addr_bits, data, retval) \
 338 do { \
 339   if (addr & forbidden_addr_bits) \
 340     { \
 341       raise_buserror (); \
 342       return retval; \
 343     } \
 344   else if ((addr & saved_state.asregs.xyram_select) \
 345            == saved_state.asregs.xram_start) \
 346     ptr = (void *) &saved_state.asregs.xmem_offset[addr ^ endian]; \
 347   else if ((addr & saved_state.asregs.xyram_select) \
 348            == saved_state.asregs.yram_start) \
 349     ptr = (void *) &saved_state.asregs.ymem_offset[addr ^ endian]; \
 350   else if ((unsigned) addr >> 24 == 0xf0 \
 351            && bits_written == 32 && (data & 1) == 0) \
 352     /* This invalidates (if not associative) or might invalidate \
 353        (if associative) an instruction cache line.  This is used for \
 354        trampolines.  Since we don't simulate the cache, this is a no-op \
 355        as far as the simulator is concerned.  */ \
 356     return retval; \
 357   else \
 358     { \
 359       if (bits_written == 8 && addr > 0x5000000) \
 360         IOMEM (addr, 1, data); \
 361       /* We can't do anything useful with the other stuff, so fail.  */ \
 362       raise_buserror (); \
 363       return retval; \
 364     } \
 365 } while (0)
 366
 367 /* FIXME: sim_resume should be renamed to sim_engine_run.  sim_resume
 368    being implemented by ../common/sim_resume.c and the below should
 369    make a call to sim_engine_halt */
 370
 371 #define BUSERROR(addr, mask) ((addr) & (mask))
 372
 373 #define WRITE_BUSERROR(addr, mask, data, addr_func) \
 374   do \
 375     { \
 376       if (addr & mask) \
 377         { \
 378           addr_func (addr, data); \
 379           return; \
 380         } \
 381     } \
 382   while (0)
 383
 384 #define READ_BUSERROR(addr, mask, addr_func) \
 385   do \
 386     { \
 387       if (addr & mask) \
 388         return addr_func (addr); \
 389     } \
 390   while (0)
 391
 392 /* Define this to enable register lifetime checking.
 393    The compiler generates "add #0,rn" insns to mark registers as invalid,
 394    the simulator uses this info to call fail if it finds a ref to an invalid
 395    register before a def
 396
 397    #define PARANOID
 398 */
 399
 400 #ifdef PARANOID
 401 int valid[16];
 402 #define CREF(x)  if(!valid[x]) fail();
 403 #define CDEF(x)  valid[x] = 1;
 404 #define UNDEF(x) valid[x] = 0;
 405 #else
 406 #define CREF(x)
 407 #define CDEF(x)
 408 #define UNDEF(x)
 409 #endif
 410
 411 static void parse_and_set_memory_size PARAMS ((char *str));
 412 static int IOMEM PARAMS ((int addr, int write, int value));
 413 static struct loop_bounds get_loop_bounds PARAMS((int, int, unsigned char *,
 414                                                   unsigned char *, int, int));
 415 static void process_wlat_addr PARAMS((int, int));
 416 static void process_wwat_addr PARAMS((int, int));
 417 static void process_wbat_addr PARAMS((int, int));
 418 static int process_rlat_addr PARAMS((int));
 419 static int process_rwat_addr PARAMS((int));
 420 static int process_rbat_addr PARAMS((int));
 421 static void INLINE wlat_fast PARAMS ((unsigned char *, int, int, int));
 422 static void INLINE wwat_fast PARAMS ((unsigned char *, int, int, int, int));
 423 static void INLINE wbat_fast PARAMS ((unsigned char *, int, int, int));
 424 static int INLINE rlat_fast PARAMS ((unsigned char *, int, int));
 425 static int INLINE rwat_fast PARAMS ((unsigned char *, int, int, int));
 426 static int INLINE rbat_fast PARAMS ((unsigned char *, int, int));
 427
 428 static host_callback *callback;
 429
 430
 431
 432 /* Floating point registers */
 433
 434 #define DR(n) (get_dr (n))
 435 static double
 436 get_dr (n)
 437      int n;
 438 {
 439   n = (n & ~1);
 440   if (host_little_endian)
 441     {
 442       union
 443       {
 444         int i[2];
 445         double d;
 446       } dr;
 447       dr.i[1] = saved_state.asregs.fregs[0].i[n + 0];
 448       dr.i[0] = saved_state.asregs.fregs[0].i[n + 1];
 449       return dr.d;
 450     }
 451   else
 452     return (saved_state.asregs.fregs[0].d[n >> 1]);
 453 }
 454
 455 #define SET_DR(n, EXP) set_dr ((n), (EXP))
 456 static void
 457 set_dr (n, exp)
 458      int n;
 459      double exp;
 460 {
 461   n = (n & ~1);
 462   if (host_little_endian)
 463     {
 464       union
 465       {
 466         int i[2];
 467         double d;
 468       } dr;
 469       dr.d = exp;
 470       saved_state.asregs.fregs[0].i[n + 0] = dr.i[1];
 471       saved_state.asregs.fregs[0].i[n + 1] = dr.i[0];
 472     }
 473   else
 474     saved_state.asregs.fregs[0].d[n >> 1] = exp;
 475 }
 476
 477 #define SET_FI(n,EXP) (saved_state.asregs.fregs[0].i[(n)] = (EXP))
 478 #define FI(n) (saved_state.asregs.fregs[0].i[(n)])
 479
 480 #define FR(n) (saved_state.asregs.fregs[0].f[(n)])
 481 #define SET_FR(n,EXP) (saved_state.asregs.fregs[0].f[(n)] = (EXP))
 482
 483 #define XD_TO_XF(n) ((((n) & 1) << 5) | ((n) & 0x1e))
 484 #define XF(n) (saved_state.asregs.fregs[(n) >> 5].i[(n) & 0x1f])
 485 #define SET_XF(n,EXP) (saved_state.asregs.fregs[(n) >> 5].i[(n) & 0x1f] = (EXP))
 486
 487 #define RS saved_state.asregs.cregs.named.rs
 488 #define RE saved_state.asregs.cregs.named.re
 489 #define MOD (saved_state.asregs.cregs.named.mod)
 490 #define SET_MOD(i) \
 491 (MOD = (i), \
 492  MOD_ME = (unsigned) MOD >> 16 | (SR_DMY ? ~0xffff : (SR_DMX ? 0 : 0x10000)), \
 493  MOD_DELTA = (MOD & 0xffff) - ((unsigned) MOD >> 16))
 494
 495 #define DSP_R(n) saved_state.asregs.sregs.i[(n)]
 496 #define DSP_GRD(n) DSP_R ((n) + 8)
 497 #define GET_DSP_GRD(n) ((n | 2) == 7 ? SEXT (DSP_GRD (n)) : SIGN32 (DSP_R (n)))
 498 #define A1 DSP_R (5)
 499 #define A0 DSP_R (7)
 500 #define X0 DSP_R (8)
 501 #define X1 DSP_R (9)
 502 #define Y0 DSP_R (10)
 503 #define Y1 DSP_R (11)
 504 #define M0 DSP_R (12)
 505 #define A1G DSP_R (13)
 506 #define M1 DSP_R (14)
 507 #define A0G DSP_R (15)
 508 /* DSP_R (16) / DSP_GRD (16) are used as a fake destination for pcmp.  */
 509 #define MOD_ME DSP_GRD (17)
 510 #define MOD_DELTA DSP_GRD (18)
 511
 512 #define FP_OP(n, OP, m) \
 513 { \
 514   if (FPSCR_PR) \
 515     { \
 516       if (((n) & 1) || ((m) & 1)) \
 517         RAISE_EXCEPTION (SIGILL); \
 518       else \
 519         SET_DR(n, (DR(n) OP DR(m))); \
 520     } \
 521   else \
 522     SET_FR(n, (FR(n) OP FR(m))); \
 523 } while (0)
 524
 525 #define FP_UNARY(n, OP) \
 526 { \
 527   if (FPSCR_PR) \
 528     { \
 529       if ((n) & 1) \
 530         RAISE_EXCEPTION (SIGILL); \
 531       else \
 532         SET_DR(n, (OP (DR(n)))); \
 533     } \
 534   else \
 535     SET_FR(n, (OP (FR(n)))); \
 536 } while (0)
 537
 538 #define FP_CMP(n, OP, m) \
 539 { \
 540   if (FPSCR_PR) \
 541     { \
 542       if (((n) & 1) || ((m) & 1)) \
 543         RAISE_EXCEPTION (SIGILL); \
 544       else \
 545         SET_SR_T (DR(n) OP DR(m)); \
 546     } \
 547   else \
 548     SET_SR_T (FR(n) OP FR(m)); \
 549 } while (0)
 550
 551 static void
 552 set_sr (new_sr)
 553      int new_sr;
 554 {
 555   /* do we need to swap banks */
 556   int old_gpr = SR_MD && SR_RB;
 557   int new_gpr = (new_sr & SR_MASK_MD) && (new_sr & SR_MASK_RB);
 558   if (old_gpr != new_gpr)
 559     {
 560       int i, tmp;
 561       for (i = 0; i < 8; i++)
 562         {
 563           tmp = saved_state.asregs.cregs.named.bank[i];
 564           saved_state.asregs.cregs.named.bank[i] = saved_state.asregs.regs[i];
 565           saved_state.asregs.regs[i] = tmp;
 566         }
 567     }
 568   saved_state.asregs.cregs.named.sr = new_sr;
 569   SET_MOD (MOD);
 570 }
 571
 572 static void INLINE
 573 wlat_fast (memory, x, value, maskl)
 574      unsigned char *memory;
 575 {
 576   int v = value;
 577   unsigned int *p = (unsigned int *)(memory + x);
 578   WRITE_BUSERROR (x, maskl, v, process_wlat_addr);
 579   *p = v;
 580 }
 581
 582 static void INLINE
 583 wwat_fast (memory, x, value, maskw, endianw)
 584      unsigned char *memory;
 585 {
 586   int v = value;
 587   unsigned short *p = (unsigned short *)(memory + (x ^ endianw));
 588   WRITE_BUSERROR (x, maskw, v, process_wwat_addr);
 589   *p = v;
 590 }
 591
 592 static void INLINE
 593 wbat_fast (memory, x, value, maskb)
 594      unsigned char *memory;
 595 {
 596   unsigned char *p = memory + (x ^ endianb);
 597   WRITE_BUSERROR (x, maskb, value, process_wbat_addr);
 598
 599   p[0] = value;
 600 }
 601
 602 /* Read functions */
 603
 604 static int INLINE
 605 rlat_fast (memory, x, maskl)
 606      unsigned char *memory;
 607 {
 608   unsigned int *p = (unsigned int *)(memory + x);
 609   READ_BUSERROR (x, maskl, process_rlat_addr);
 610
 611   return *p;
 612 }
 613
 614 static int INLINE
 615 rwat_fast (memory, x, maskw, endianw)
 616      unsigned char *memory;
 617      int x, maskw, endianw;
 618 {
 619   unsigned short *p = (unsigned short *)(memory + (x ^ endianw));
 620   READ_BUSERROR (x, maskw, process_rwat_addr);
 621
 622   return *p;
 623 }
 624
 625 static int INLINE
 626 riat_fast (insn_ptr, endianw)
 627      unsigned char *insn_ptr;
 628 {
 629   unsigned short *p = (unsigned short *)((size_t) insn_ptr ^ endianw);
 630
 631   return *p;
 632 }
 633
 634 static int INLINE
 635 rbat_fast (memory, x, maskb)
 636      unsigned char *memory;
 637 {
 638   unsigned char *p = memory + (x ^ endianb);
 639   READ_BUSERROR (x, maskb, process_rbat_addr);
 640
 641   return *p;
 642 }
 643
 644 #define RWAT(x)         (rwat_fast (memory, x, maskw, endianw))
 645 #define RLAT(x)         (rlat_fast (memory, x, maskl))
 646 #define RBAT(x)         (rbat_fast (memory, x, maskb))
 647 #define RIAT(p)         (riat_fast ((p), endianw))
 648 #define WWAT(x,v)       (wwat_fast (memory, x, v, maskw, endianw))
 649 #define WLAT(x,v)       (wlat_fast (memory, x, v, maskl))
 650 #define WBAT(x,v)       (wbat_fast (memory, x, v, maskb))
 651
 652 #define RUWAT(x)  (RWAT(x) & 0xffff)
 653 #define RSWAT(x)  ((short)(RWAT(x)))
 654 #define RSBAT(x)  (SEXT(RBAT(x)))
 655
 656 #define RDAT(x, n) (do_rdat (memory, (x), (n), (maskl)))
 657 static int
 658 do_rdat (memory, x, n, maskl)
 659      char *memory;
 660      int x;
 661      int n;
 662      int maskl;
 663 {
 664   int f0;
 665   int f1;
 666   int i = (n & 1);
 667   int j = (n & ~1);
 668   f0 = rlat_fast (memory, x + 0, maskl);
 669   f1 = rlat_fast (memory, x + 4, maskl);
 670   saved_state.asregs.fregs[i].i[(j + 0)] = f0;
 671   saved_state.asregs.fregs[i].i[(j + 1)] = f1;
 672   return 0;
 673 }
 674
 675 #define WDAT(x, n) (do_wdat (memory, (x), (n), (maskl)))
 676 static int
 677 do_wdat (memory, x, n, maskl)
 678      char *memory;
 679      int x;
 680      int n;
 681      int maskl;
 682 {
 683   int f0;
 684   int f1;
 685   int i = (n & 1);
 686   int j = (n & ~1);
 687   f0 = saved_state.asregs.fregs[i].i[(j + 0)];
 688   f1 = saved_state.asregs.fregs[i].i[(j + 1)];
 689   wlat_fast (memory, (x + 0), f0, maskl);
 690   wlat_fast (memory, (x + 4), f1, maskl);
 691   return 0;
 692 }
 693
 694 static void
 695 process_wlat_addr (addr, value)
 696      int addr;
 697      int value;
 698 {
 699   unsigned int *ptr;
 700
 701   PROCESS_SPECIAL_ADDRESS (addr, endianb, ptr, 32, 3, value, );
 702   *ptr = value;
 703 }
 704
 705 static void
 706 process_wwat_addr (addr, value)
 707      int addr;
 708      int value;
 709 {
 710   unsigned short *ptr;
 711
 712   PROCESS_SPECIAL_ADDRESS (addr, endianb, ptr, 16, 1, value, );
 713   *ptr = value;
 714 }
 715
 716 static void
 717 process_wbat_addr (addr, value)
 718      int addr;
 719      int value;
 720 {
 721   unsigned char *ptr;
 722
 723   PROCESS_SPECIAL_ADDRESS (addr, endianb, ptr, 8, 0, value, );
 724   *ptr = value;
 725 }
 726
 727 static int
 728 process_rlat_addr (addr)
 729      int addr;
 730 {
 731   unsigned char *ptr;
 732
 733   PROCESS_SPECIAL_ADDRESS (addr, endianb, ptr, -32, 3, -1, 0);
 734   return *ptr;
 735 }
 736
 737 static int
 738 process_rwat_addr (addr)
 739      int addr;
 740 {
 741   unsigned char *ptr;
 742
 743   PROCESS_SPECIAL_ADDRESS (addr, endianb, ptr, -16, 1, -1, 0);
 744   return *ptr;
 745 }
 746
 747 static int
 748 process_rbat_addr (addr)
 749      int addr;
 750 {
 751   unsigned char *ptr;
 752
 753   PROCESS_SPECIAL_ADDRESS (addr, endianb, ptr, -8, 0, -1, 0);
 754   return *ptr;
 755 }
 756
 757 #define SEXT(x)         (((x &  0xff) ^ (~0x7f))+0x80)
 758 #define SEXT12(x)       (((x & 0xfff) ^ 0x800) - 0x800)
 759 #define SEXTW(y)        ((int)((short)y))
 760 #if 0
 761 #define SEXT32(x)       ((int)((x & 0xffffffff) ^ 0x80000000U) - 0x7fffffff - 1)
 762 #else
 763 #define SEXT32(x)       ((int)(x))
 764 #endif
 765 #define SIGN32(x)       (SEXT32 (x) >> 31)
 766
 767 /* convert pointer from target to host value.  */
 768 #define PT2H(x) ((x) + memory)
 769 /* convert pointer from host to target value.  */
 770 #define PH2T(x) ((x) - memory)
 771
 772 #define SKIP_INSN(p) ((p) += ((RIAT (p) & 0xfc00) == 0xf800 ? 4 : 2))
 773
 774 #define SET_NIP(x) nip = (x); CHECK_INSN_PTR (nip);
 775
 776 #define Delay_Slot(TEMPPC)      iword = RIAT (TEMPPC); goto top;
 777
 778 #define CHECK_INSN_PTR(p) \
 779 do { \
 780   if (saved_state.asregs.exception || PH2T (p) & maskw) \
 781     saved_state.asregs.insn_end = 0; \
 782   else if (p < loop.end) \
 783     saved_state.asregs.insn_end = loop.end; \
 784   else \
 785     saved_state.asregs.insn_end = mem_end; \
 786 } while (0)
 787
 788 #ifdef ACE_FAST
 789
 790 #define MA(n)
 791 #define L(x)
 792 #define TL(x)
 793 #define TB(x)
 794
 795 #else
 796
 797 #define MA(n) \
 798   do { memstalls += ((((int) PC & 3) != 0) ? (n) : ((n) - 1)); } while (0)
 799
 800 #define L(x)   thislock = x;
 801 #define TL(x)  if ((x) == prevlock) stalls++;
 802 #define TB(x,y)  if ((x) == prevlock || (y)==prevlock) stalls++;
 803
 804 #endif
 805
 806 #if defined(__GO32__) || defined(_WIN32)
 807 int sim_memory_size = 19;
 808 #else
 809 int sim_memory_size = 24;
 810 #endif
 811
 812 static int sim_profile_size = 17;
 813 static int nsamples;
 814
 815 #undef TB
 816 #define TB(x,y)
 817
 818 #define SMR1 (0x05FFFEC8)       /* Channel 1  serial mode register */
 819 #define BRR1 (0x05FFFEC9)       /* Channel 1  bit rate register */
 820 #define SCR1 (0x05FFFECA)       /* Channel 1  serial control register */
 821 #define TDR1 (0x05FFFECB)       /* Channel 1  transmit data register */
 822 #define SSR1 (0x05FFFECC)       /* Channel 1  serial status register */
 823 #define RDR1 (0x05FFFECD)       /* Channel 1  receive data register */
 824
 825 #define SCI_RDRF         0x40   /* Recieve data register full */
 826 #define SCI_TDRE        0x80    /* Transmit data register empty */
 827
 828 static int
 829 IOMEM (addr, write, value)
 830      int addr;
 831      int write;
 832      int value;
 833 {
 834   if (write)
 835     {
 836       switch (addr)
 837         {
 838         case TDR1:
 839           if (value != '\r')
 840             {
 841               putchar (value);
 842               fflush (stdout);
 843             }
 844           break;
 845         }
 846     }
 847   else
 848     {
 849       switch (addr)
 850         {
 851         case RDR1:
 852           return getchar ();
 853         }
 854     }
 855   return 0;
 856 }
 857
 858 static int
 859 get_now ()
 860 {
 861   return time ((long *) 0);
 862 }
 863
 864 static int
 865 now_persec ()
 866 {
 867   return 1;
 868 }
 869
 870 static FILE *profile_file;
 871
 872 static unsigned INLINE
 873 swap (n)
 874      unsigned n;
 875 {
 876   if (endianb)
 877     n = (n << 24 | (n & 0xff00) << 8
 878          | (n & 0xff0000) >> 8 | (n & 0xff000000) >> 24);
 879   return n;
 880 }
 881
 882 static unsigned short INLINE
 883 swap16 (n)
 884      unsigned short n;
 885 {
 886   if (endianb)
 887     n = n << 8 | (n & 0xff00) >> 8;
 888   return n;
 889 }
 890
 891 static void
 892 swapout (n)
 893      int n;
 894 {
 895   if (profile_file)
 896     {
 897       union { char b[4]; int n; } u;
 898       u.n = swap (n);
 899       fwrite (u.b, 4, 1, profile_file);
 900     }
 901 }
 902
 903 static void
 904 swapout16 (n)
 905      int n;
 906 {
 907   union { char b[4]; int n; } u;
 908   u.n = swap16 (n);
 909   fwrite (u.b, 2, 1, profile_file);
 910 }
 911
 912 /* Turn a pointer in a register into a pointer into real memory. */
 913
 914 static char *
 915 ptr (x)
 916      int x;
 917 {
 918   return (char *) (x + saved_state.asregs.memory);
 919 }
 920
 921 static int
 922 strswaplen (str)
 923      int str;
 924 {
 925   unsigned char *memory = saved_state.asregs.memory;
 926   int start, end;
 927   int endian = endianb;
 928
 929   if (! endian)
 930     return 0;
 931   end = str;
 932   for (end = str; memory[end ^ endian]; end++) ;
 933   return end - str;
 934 }
 935
 936 static void
 937 strnswap (str, len)
 938      int str;
 939      int len;
 940 {
 941   int *start, *end;
 942
 943   if (! endianb || ! len)
 944     return;
 945   start = (int *) ptr (str & ~3);
 946   end = (int *) ptr (str + len);
 947   do
 948     {
 949       int old = *start;
 950       *start = (old << 24 | (old & 0xff00) << 8
 951                 | (old & 0xff0000) >> 8 | (old & 0xff000000) >> 24);
 952       start++;
 953     }
 954   while (start < end);
 955 }
 956
 957 /* Simulate a monitor trap, put the result into r0 and errno into r1 */
 958
 959 static void
 960 trap (i, regs, memory, maskl, maskw, endianw)
 961      int i;
 962      int *regs;
 963      unsigned char *memory;
 964 {
 965   switch (i)
 966     {
 967     case 1:
 968       printf ("%c", regs[0]);
 969       break;
 970     case 2:
 971       raise_exception (SIGQUIT);
 972       break;
 973     case 3:                     /* FIXME: for backwards compat, should be removed */
 974     case 34:
 975       {
 976         extern int errno;
 977         int perrno = errno;
 978         errno = 0;
 979
 980         switch (regs[4])
 981           {
 982
 983 #if !defined(__GO32__) && !defined(_WIN32)
 984           case SYS_fork:
 985             regs[0] = fork ();
 986             break;
 987 /* This would work only if endianness matched between host and target.
 988    Besides, it's quite dangerous.  */
 989 #if 0
 990           case SYS_execve:
 991             regs[0] = execve (ptr (regs[5]), (char **)ptr (regs[6]), (char **)ptr (regs[7]));
 992             break;
 993           case SYS_execv:
 994             regs[0] = execve (ptr (regs[5]),(char **) ptr (regs[6]), 0);
 995             break;
 996 #endif
 997           case SYS_pipe:
 998             {
 999               regs[0] = (BUSERROR (regs[5], maskl)
1000                          ? -EINVAL
1001                          : pipe ((int *) ptr (regs[5])));
1002             }
1003             break;
1004
1005           case SYS_wait:
1006             regs[0] = wait (ptr (regs[5]));
1007             break;
1008 #endif /* !defined(__GO32__) && !defined(_WIN32) */
1009
1010           case SYS_read:
1011             strnswap (regs[6], regs[7]);
1012             regs[0]
1013               = callback->read (callback, regs[5], ptr (regs[6]), regs[7]);
1014             strnswap (regs[6], regs[7]);
1015             break;
1016           case SYS_write:
1017             strnswap (regs[6], regs[7]);
1018             if (regs[5] == 1)
1019               regs[0] = (int)callback->write_stdout (callback, ptr(regs[6]), regs[7]);
1020             else
1021               regs[0] = (int)callback->write (callback, regs[5], ptr (regs[6]), regs[7]);
1022             strnswap (regs[6], regs[7]);
1023             break;
1024           case SYS_lseek:
1025             regs[0] = callback->lseek (callback,regs[5], regs[6], regs[7]);
1026             break;
1027           case SYS_close:
1028             regs[0] = callback->close (callback,regs[5]);
1029             break;
1030           case SYS_open:
1031             {
1032               int len = strswaplen (regs[5]);
1033               strnswap (regs[5], len);
1034               regs[0] = callback->open (callback,ptr (regs[5]), regs[6]);
1035               strnswap (regs[5], len);
1036               break;
1037             }
1038           case SYS_exit:
1039             /* EXIT - caller can look in r5 to work out the reason */
1040             raise_exception (SIGQUIT);
1041             regs[0] = regs[5];
1042             break;
1043
1044           case SYS_stat:        /* added at hmsi */
1045             /* stat system call */
1046             {
1047               struct stat host_stat;
1048               int buf;
1049               int len = strswaplen (regs[5]);
1050
1051               strnswap (regs[5], len);
1052               regs[0] = stat (ptr (regs[5]), &host_stat);
1053               strnswap (regs[5], len);
1054
1055               buf = regs[6];
1056
1057               WWAT (buf, host_stat.st_dev);
1058               buf += 2;
1059               WWAT (buf, host_stat.st_ino);
1060               buf += 2;
1061               WLAT (buf, host_stat.st_mode);
1062               buf += 4;
1063               WWAT (buf, host_stat.st_nlink);
1064               buf += 2;
1065               WWAT (buf, host_stat.st_uid);
1066               buf += 2;
1067               WWAT (buf, host_stat.st_gid);
1068               buf += 2;
1069               WWAT (buf, host_stat.st_rdev);
1070               buf += 2;
1071               WLAT (buf, host_stat.st_size);
1072               buf += 4;
1073               WLAT (buf, host_stat.st_atime);
1074               buf += 4;
1075               WLAT (buf, 0);
1076               buf += 4;
1077               WLAT (buf, host_stat.st_mtime);
1078               buf += 4;
1079               WLAT (buf, 0);
1080               buf += 4;
1081               WLAT (buf, host_stat.st_ctime);
1082               buf += 4;
1083               WLAT (buf, 0);
1084               buf += 4;
1085               WLAT (buf, 0);
1086               buf += 4;
1087               WLAT (buf, 0);
1088               buf += 4;
1089             }
1090             break;
1091
1092 #ifndef _WIN32
1093           case SYS_chown:
1094             {
1095               int len = strswaplen (regs[5]);
1096
1097               strnswap (regs[5], len);
1098               regs[0] = chown (ptr (regs[5]), regs[6], regs[7]);
1099               strnswap (regs[5], len);
1100               break;
1101             }
1102 #endif /* _WIN32 */
1103           case SYS_chmod:
1104             {
1105               int len = strswaplen (regs[5]);
1106
1107               strnswap (regs[5], len);
1108               regs[0] = chmod (ptr (regs[5]), regs[6]);
1109               strnswap (regs[5], len);
1110               break;
1111             }
1112           case SYS_utime:
1113             {
1114               /* Cast the second argument to void *, to avoid type mismatch
1115                  if a prototype is present.  */
1116               int len = strswaplen (regs[5]);
1117
1118               strnswap (regs[5], len);
1119               regs[0] = utime (ptr (regs[5]), (void *) ptr (regs[6]));
1120               strnswap (regs[5], len);
1121               break;
1122             }
1123           case SYS_argc:
1124             regs[0] = count_argc (prog_argv);
1125             break;
1126           case SYS_argnlen:
1127             if (regs[5] < count_argc (prog_argv))
1128               regs[0] = strlen (prog_argv[regs[5]]);
1129             else
1130               regs[0] = -1;
1131             break;
1132           case SYS_argn:
1133             if (regs[5] < count_argc (prog_argv))
1134               {
1135                 /* Include the termination byte.  */
1136                 int i = strlen (prog_argv[regs[5]]) + 1;
1137                 regs[0] = sim_write (0, regs[6], prog_argv[regs[5]], i);
1138               }
1139             else
1140               regs[0] = -1;
1141             break;
1142           case SYS_time:
1143             regs[0] = get_now ();
1144             break;
1145           default:
1146             regs[0] = -1;
1147             break;
1148           }
1149         regs[1] = callback->get_errno (callback);
1150         errno = perrno;
1151       }
1152       break;
1153
1154     case 0xc3:
1155     case 255:
1156       raise_exception (SIGTRAP);
1157       break;
1158     }
1159
1160 }
1161
1162 void
1163 control_c (sig, code, scp, addr)
1164      int sig;
1165      int code;
1166      char *scp;
1167      char *addr;
1168 {
1169   raise_exception (SIGINT);
1170 }
1171
1172 static int
1173 div1 (R, iRn2, iRn1/*, T*/)
1174      int *R;
1175      int iRn1;
1176      int iRn2;
1177      /* int T;*/
1178 {
1179   unsigned long tmp0;
1180   unsigned char old_q, tmp1;
1181
1182   old_q = Q;
1183   SET_SR_Q ((unsigned char) ((0x80000000 & R[iRn1]) != 0));
1184   R[iRn1] <<= 1;
1185   R[iRn1] |= (unsigned long) T;
1186
1187   switch (old_q)
1188     {
1189     case 0:
1190       switch (M)
1191         {
1192         case 0:
1193           tmp0 = R[iRn1];
1194           R[iRn1] -= R[iRn2];
1195           tmp1 = (R[iRn1] > tmp0);
1196           switch (Q)
1197             {
1198             case 0:
1199               SET_SR_Q (tmp1);
1200               break;
1201             case 1:
1202               SET_SR_Q ((unsigned char) (tmp1 == 0));
1203               break;
1204             }
1205           break;
1206         case 1:
1207           tmp0 = R[iRn1];
1208           R[iRn1] += R[iRn2];
1209           tmp1 = (R[iRn1] < tmp0);
1210           switch (Q)
1211             {
1212             case 0:
1213               SET_SR_Q ((unsigned char) (tmp1 == 0));
1214               break;
1215             case 1:
1216               SET_SR_Q (tmp1);
1217               break;
1218             }
1219           break;
1220         }
1221       break;
1222     case 1:
1223       switch (M)
1224         {
1225         case 0:
1226           tmp0 = R[iRn1];
1227           R[iRn1] += R[iRn2];
1228           tmp1 = (R[iRn1] < tmp0);
1229           switch (Q)
1230             {
1231             case 0:
1232               SET_SR_Q (tmp1);
1233               break;
1234             case 1:
1235               SET_SR_Q ((unsigned char) (tmp1 == 0));
1236               break;
1237             }
1238           break;
1239         case 1:
1240           tmp0 = R[iRn1];
1241           R[iRn1] -= R[iRn2];
1242           tmp1 = (R[iRn1] > tmp0);
1243           switch (Q)
1244             {
1245             case 0:
1246               SET_SR_Q ((unsigned char) (tmp1 == 0));
1247               break;
1248             case 1:
1249               SET_SR_Q (tmp1);
1250               break;
1251             }
1252           break;
1253         }
1254       break;
1255     }
1256   /*T = (Q == M);*/
1257   SET_SR_T (Q == M);
1258   /*return T;*/
1259 }
1260
1261 static void
1262 dmul (sign, rm, rn)
1263      int sign;
1264      unsigned int rm;
1265      unsigned int rn;
1266 {
1267   unsigned long RnL, RnH;
1268   unsigned long RmL, RmH;
1269   unsigned long temp0, temp1, temp2, temp3;
1270   unsigned long Res2, Res1, Res0;
1271
1272   RnL = rn & 0xffff;
1273   RnH = (rn >> 16) & 0xffff;
1274   RmL = rm & 0xffff;
1275   RmH = (rm >> 16) & 0xffff;
1276   temp0 = RmL * RnL;
1277   temp1 = RmH * RnL;
1278   temp2 = RmL * RnH;
1279   temp3 = RmH * RnH;
1280   Res2 = 0;
1281   Res1 = temp1 + temp2;
1282   if (Res1 < temp1)
1283     Res2 += 0x00010000;
1284   temp1 = (Res1 << 16) & 0xffff0000;
1285   Res0 = temp0 + temp1;
1286   if (Res0 < temp0)
1287     Res2 += 1;
1288   Res2 += ((Res1 >> 16) & 0xffff) + temp3;
1289
1290   if (sign)
1291     {
1292       if (rn & 0x80000000)
1293         Res2 -= rm;
1294       if (rm & 0x80000000)
1295         Res2 -= rn;
1296     }
1297
1298   MACH = Res2;
1299   MACL = Res0;
1300 }
1301
1302 static void
1303 macw (regs, memory, n, m, endianw)
1304      int *regs;
1305      unsigned char *memory;
1306      int m, n;
1307      int endianw;
1308 {
1309   long tempm, tempn;
1310   long prod, macl, sum;
1311
1312   tempm=RSWAT(regs[m]); regs[m]+=2;
1313   tempn=RSWAT(regs[n]); regs[n]+=2;
1314
1315   macl = MACL;
1316   prod = (long)(short) tempm * (long)(short) tempn;
1317   sum = prod + macl;
1318   if (S)
1319     {
1320       if ((~(prod ^ macl) & (sum ^ prod)) < 0)
1321         {
1322           /* MACH's lsb is a sticky overflow bit.  */
1323           MACH |= 1;
1324           /* Store the smallest negative number in MACL if prod is
1325              negative, and the largest positive number otherwise.  */
1326           sum = 0x7fffffff + (prod < 0);
1327         }
1328     }
1329   else
1330     {
1331       long mach;
1332       /* Add to MACH the sign extended product, and carry from low sum.  */
1333       mach = MACH + (-(prod < 0)) + ((unsigned long) sum < prod);
1334       /* Sign extend at 10:th bit in MACH.  */
1335       MACH = (mach & 0x1ff) | -(mach & 0x200);
1336     }
1337   MACL = sum;
1338 }
1339
1340 static struct loop_bounds
1341 get_loop_bounds (rs, re, memory, mem_end, maskw, endianw)
1342      int rs, re;
1343      unsigned char *memory, *mem_end;
1344      int maskw, endianw;
1345 {
1346   struct loop_bounds loop;
1347
1348   if (SR_RC)
1349     {
1350       if (RS >= RE)
1351         {
1352           loop.start = PT2H (RE - 4);
1353           SKIP_INSN (loop.start);
1354           loop.end = loop.start;
1355           if (RS - RE == 0)
1356             SKIP_INSN (loop.end);
1357           if (RS - RE <= 2)
1358             SKIP_INSN (loop.end);
1359           SKIP_INSN (loop.end);
1360         }
1361       else
1362         {
1363           loop.start = PT2H (RS);
1364           loop.end = PT2H (RE - 4);
1365           SKIP_INSN (loop.end);
1366           SKIP_INSN (loop.end);
1367           SKIP_INSN (loop.end);
1368           SKIP_INSN (loop.end);
1369         }
1370       if (loop.end >= mem_end)
1371         loop.end = PT2H (0);
1372     }
1373   else
1374     loop.end = PT2H (0);
1375
1376   return loop;
1377 }
1378
1379 static void
1380 ppi_insn();
1381
1382 #include "ppi.c"
1383
1384 /* Set the memory size to the power of two provided. */
1385
1386 void
1387 sim_size (power)
1388      int power;
1389
1390 {
1391   saved_state.asregs.msize = 1 << power;
1392
1393   sim_memory_size = power;
1394
1395   if (saved_state.asregs.memory)
1396     {
1397       free (saved_state.asregs.memory);
1398     }
1399
1400   saved_state.asregs.memory =
1401     (unsigned char *) calloc (64, saved_state.asregs.msize / 64);
1402
1403   if (!saved_state.asregs.memory)
1404     {
1405       fprintf (stderr,
1406                "Not enough VM for simulation of %d bytes of RAM\n",
1407                saved_state.asregs.msize);
1408
1409       saved_state.asregs.msize = 1;
1410       saved_state.asregs.memory = (unsigned char *) calloc (1, 1);
1411     }
1412 }
1413
1414 static void
1415 init_dsp (abfd)
1416      struct _bfd *abfd;
1417 {
1418   int was_dsp = target_dsp;
1419   unsigned long mach = bfd_get_mach (abfd);
1420
1421   if (mach == bfd_mach_sh_dsp || mach == bfd_mach_sh3_dsp)
1422     {
1423       int ram_area_size, xram_start, yram_start;
1424       int new_select;
1425
1426       target_dsp = 1;
1427       if (mach == bfd_mach_sh_dsp)
1428         {
1429           /* SH7410 (orig. sh-sdp):
1430              4KB each for X & Y memory;
1431              On-chip X RAM 0x0800f000-0x0800ffff
1432              On-chip Y RAM 0x0801f000-0x0801ffff  */
1433           xram_start = 0x0800f000;
1434           ram_area_size = 0x1000;
1435         }
1436       if (mach == bfd_mach_sh3_dsp)
1437         {
1438           /* SH7612:
1439              8KB each for X & Y memory;
1440              On-chip X RAM 0x1000e000-0x1000ffff
1441              On-chip Y RAM 0x1001e000-0x1001ffff  */
1442           xram_start = 0x1000e000;
1443           ram_area_size = 0x2000;
1444         }
1445       yram_start = xram_start + 0x10000;
1446       new_select = ~(ram_area_size - 1);
1447       if (saved_state.asregs.xyram_select != new_select)
1448         {
1449           saved_state.asregs.xyram_select = new_select;
1450           free (saved_state.asregs.xmem);
1451           free (saved_state.asregs.ymem);
1452           saved_state.asregs.xmem = (unsigned char *) calloc (1, ram_area_size);
1453           saved_state.asregs.ymem = (unsigned char *) calloc (1, ram_area_size);
1454
1455           /* Disable use of X / Y mmeory if not allocated.  */
1456           if (! saved_state.asregs.xmem || ! saved_state.asregs.ymem)
1457             {
1458               saved_state.asregs.xyram_select = 0;
1459               if (saved_state.asregs.xmem)
1460                 free (saved_state.asregs.xmem);
1461               if (saved_state.asregs.ymem)
1462                 free (saved_state.asregs.ymem);
1463             }
1464         }
1465       saved_state.asregs.xram_start = xram_start;
1466       saved_state.asregs.yram_start = yram_start;
1467       saved_state.asregs.xmem_offset = saved_state.asregs.xmem - xram_start;
1468       saved_state.asregs.ymem_offset = saved_state.asregs.ymem - yram_start;
1469     }
1470   else
1471     {
1472       target_dsp = 0;
1473       if (saved_state.asregs.xyram_select)
1474         {
1475           saved_state.asregs.xyram_select = 0;
1476           free (saved_state.asregs.xmem);
1477           free (saved_state.asregs.ymem);
1478         }
1479     }
1480
1481   if (! saved_state.asregs.xyram_select)
1482     {
1483       saved_state.asregs.xram_start = 1;
1484       saved_state.asregs.yram_start = 1;
1485     }
1486
1487   if (target_dsp != was_dsp)
1488     {
1489       int i, tmp;
1490
1491       for (i = sizeof sh_dsp_table - 1; i >= 0; i--)
1492         {
1493           tmp = sh_jump_table[0xf000 + i];
1494           sh_jump_table[0xf000 + i] = sh_dsp_table[i];
1495           sh_dsp_table[i] = tmp;
1496         }
1497     }
1498 }
1499
1500 static void
1501 init_pointers ()
1502 {
1503   host_little_endian = 0;
1504   *(char*)&host_little_endian = 1;
1505   host_little_endian &= 1;
1506
1507   if (saved_state.asregs.msize != 1 << sim_memory_size)
1508     {
1509       sim_size (sim_memory_size);
1510     }
1511
1512   if (saved_state.asregs.profile && !profile_file)
1513     {
1514       profile_file = fopen ("gmon.out", "wb");
1515       /* Seek to where to put the call arc data */
1516       nsamples = (1 << sim_profile_size);
1517
1518       fseek (profile_file, nsamples * 2 + 12, 0);
1519
1520       if (!profile_file)
1521         {
1522           fprintf (stderr, "Can't open gmon.out\n");
1523         }
1524       else
1525         {
1526           saved_state.asregs.profile_hist =
1527             (unsigned short *) calloc (64, (nsamples * sizeof (short) / 64));
1528         }
1529     }
1530 }
1531
1532 static void
1533 dump_profile ()
1534 {
1535   unsigned int minpc;
1536   unsigned int maxpc;
1537   unsigned short *p;
1538   int i;
1539
1540   p = saved_state.asregs.profile_hist;
1541   minpc = 0;
1542   maxpc = (1 << sim_profile_size);
1543
1544   fseek (profile_file, 0L, 0);
1545   swapout (minpc << PROFILE_SHIFT);
1546   swapout (maxpc << PROFILE_SHIFT);
1547   swapout (nsamples * 2 + 12);
1548   for (i = 0; i < nsamples; i++)
1549     swapout16 (saved_state.asregs.profile_hist[i]);
1550
1551 }
1552
1553 static void
1554 gotcall (from, to)
1555      int from;
1556      int to;
1557 {
1558   swapout (from);
1559   swapout (to);
1560   swapout (1);
1561 }
1562
1563 #define MMASKB ((saved_state.asregs.msize -1) & ~0)
1564
1565 int
1566 sim_stop (sd)
1567      SIM_DESC sd;
1568 {
1569   raise_exception (SIGINT);
1570   return 1;
1571 }
1572
1573 void
1574 sim_resume (sd, step, siggnal)
1575      SIM_DESC sd;
1576      int step, siggnal;
1577 {
1578   register unsigned char *insn_ptr;
1579   unsigned char *mem_end;
1580   struct loop_bounds loop;
1581   register int cycles = 0;
1582   register int stalls = 0;
1583   register int memstalls = 0;
1584   register int insts = 0;
1585   register int prevlock;
1586   register int thislock;
1587   register unsigned int doprofile;
1588   register int pollcount = 0;
1589   /* endianw is used for every insn fetch, hence it makes sense to cache it.
1590      endianb is used less often.  */
1591   register int endianw = global_endianw;
1592
1593   int tick_start = get_now ();
1594   void (*prev) ();
1595   void (*prev_fpe) ();
1596
1597   register unsigned char *jump_table = sh_jump_table;
1598
1599   register int *R = &(saved_state.asregs.regs[0]);
1600   /*register int T;*/
1601 #ifndef PR
1602   register int PR;
1603 #endif
1604
1605   register int maskb = ~((saved_state.asregs.msize - 1) & ~0);
1606   register int maskw = ~((saved_state.asregs.msize - 1) & ~1);
1607   register int maskl = ~((saved_state.asregs.msize - 1) & ~3);
1608   register unsigned char *memory;
1609   register unsigned int sbit = ((unsigned int) 1 << 31);
1610
1611   prev = signal (SIGINT, control_c);
1612   prev_fpe = signal (SIGFPE, SIG_IGN);
1613
1614   init_pointers ();
1615   saved_state.asregs.exception = 0;
1616
1617   memory = saved_state.asregs.memory;
1618   mem_end = memory + saved_state.asregs.msize;
1619
1620   loop = get_loop_bounds (RS, RE, memory, mem_end, maskw, endianw);
1621   insn_ptr = PT2H (saved_state.asregs.pc);
1622   CHECK_INSN_PTR (insn_ptr);
1623
1624 #ifndef PR
1625   PR = saved_state.asregs.sregs.named.pr;
1626 #endif
1627   /*T = GET_SR () & SR_MASK_T;*/
1628   prevlock = saved_state.asregs.prevlock;
1629   thislock = saved_state.asregs.thislock;
1630   doprofile = saved_state.asregs.profile;
1631
1632   /* If profiling not enabled, disable it by asking for
1633      profiles infrequently. */
1634   if (doprofile == 0)
1635     doprofile = ~0;
1636
1637  loop:
1638   if (step && insn_ptr < saved_state.asregs.insn_end)
1639     {
1640       if (saved_state.asregs.exception)
1641         /* This can happen if we've already been single-stepping and
1642            encountered a loop end.  */
1643         saved_state.asregs.insn_end = insn_ptr;
1644       else
1645         {
1646           saved_state.asregs.exception = SIGTRAP;
1647           saved_state.asregs.insn_end = insn_ptr + 2;
1648         }
1649     }
1650
1651   while (insn_ptr < saved_state.asregs.insn_end)
1652     {
1653       register unsigned int iword = RIAT (insn_ptr);
1654       register unsigned int ult;
1655       register unsigned char *nip = insn_ptr + 2;
1656
1657 #ifndef ACE_FAST
1658       insts++;
1659 #endif
1660     top:
1661
1662 #include "code.c"
1663
1664
1665       insn_ptr = nip;
1666
1667       if (--pollcount < 0)
1668         {
1669           pollcount = POLL_QUIT_INTERVAL;
1670           if ((*callback->poll_quit) != NULL
1671               && (*callback->poll_quit) (callback))
1672             {
1673               sim_stop (sd);
1674             }
1675         }
1676
1677 #ifndef ACE_FAST
1678       prevlock = thislock;
1679       thislock = 30;
1680       cycles++;
1681
1682       if (cycles >= doprofile)
1683         {
1684
1685           saved_state.asregs.cycles += doprofile;
1686           cycles -= doprofile;
1687           if (saved_state.asregs.profile_hist)
1688             {
1689               int n = PH2T (insn_ptr) >> PROFILE_SHIFT;
1690               if (n < nsamples)
1691                 {
1692                   int i = saved_state.asregs.profile_hist[n];
1693                   if (i < 65000)
1694                     saved_state.asregs.profile_hist[n] = i + 1;
1695                 }
1696
1697             }
1698         }
1699 #endif
1700     }
1701   if (saved_state.asregs.insn_end == loop.end)
1702     {
1703       saved_state.asregs.cregs.named.sr += SR_RC_INCREMENT;
1704       if (SR_RC)
1705         insn_ptr = loop.start;
1706       else
1707         {
1708           saved_state.asregs.insn_end = mem_end;
1709           loop.end = PT2H (0);
1710         }
1711       goto loop;
1712     }
1713
1714   if (saved_state.asregs.exception == SIGILL
1715       || saved_state.asregs.exception == SIGBUS)
1716     {
1717       insn_ptr -= 2;
1718     }
1719   /* Check for SIGBUS due to insn fetch.  */
1720   else if (! saved_state.asregs.exception)
1721     saved_state.asregs.exception = SIGBUS;
1722
1723   saved_state.asregs.ticks += get_now () - tick_start;
1724   saved_state.asregs.cycles += cycles;
1725   saved_state.asregs.stalls += stalls;
1726   saved_state.asregs.memstalls += memstalls;
1727   saved_state.asregs.insts += insts;
1728   saved_state.asregs.pc = PH2T (insn_ptr);
1729 #ifndef PR
1730   saved_state.asregs.sregs.named.pr = PR;
1731 #endif
1732
1733   saved_state.asregs.prevlock = prevlock;
1734   saved_state.asregs.thislock = thislock;
1735
1736   if (profile_file)
1737     {
1738       dump_profile ();
1739     }
1740
1741   signal (SIGFPE, prev_fpe);
1742   signal (SIGINT, prev);
1743 }
1744
1745 int
1746 sim_write (sd, addr, buffer, size)
1747      SIM_DESC sd;
1748      SIM_ADDR addr;
1749      unsigned char *buffer;
1750      int size;
1751 {
1752   int i;
1753
1754   init_pointers ();
1755
1756   for (i = 0; i < size; i++)
1757     {
1758       saved_state.asregs.memory[(MMASKB & (addr + i)) ^ endianb] = buffer[i];
1759     }
1760   return size;
1761 }
1762
1763 int
1764 sim_read (sd, addr, buffer, size)
1765      SIM_DESC sd;
1766      SIM_ADDR addr;
1767      unsigned char *buffer;
1768      int size;
1769 {
1770   int i;
1771
1772   init_pointers ();
1773
1774   for (i = 0; i < size; i++)
1775     {
1776       buffer[i] = saved_state.asregs.memory[(MMASKB & (addr + i)) ^ endianb];
1777     }
1778   return size;
1779 }
1780
1781 int
1782 sim_store_register (sd, rn, memory, length)
1783      SIM_DESC sd;
1784      int rn;
1785      unsigned char *memory;
1786      int length;
1787 {
1788   unsigned val;
1789
1790   init_pointers ();
1791   val = swap (* (int *)memory);
1792   switch (rn)
1793     {
1794     case SIM_SH_R0_REGNUM: case SIM_SH_R1_REGNUM: case SIM_SH_R2_REGNUM:
1795     case SIM_SH_R3_REGNUM: case SIM_SH_R4_REGNUM: case SIM_SH_R5_REGNUM:
1796     case SIM_SH_R6_REGNUM: case SIM_SH_R7_REGNUM: case SIM_SH_R8_REGNUM:
1797     case SIM_SH_R9_REGNUM: case SIM_SH_R10_REGNUM: case SIM_SH_R11_REGNUM:
1798     case SIM_SH_R12_REGNUM: case SIM_SH_R13_REGNUM: case SIM_SH_R14_REGNUM:
1799     case SIM_SH_R15_REGNUM:
1800       saved_state.asregs.regs[rn] = val;
1801       break;
1802     case SIM_SH_PC_REGNUM:
1803       saved_state.asregs.pc = val;
1804       break;
1805     case SIM_SH_PR_REGNUM:
1806       PR = val;
1807       break;
1808     case SIM_SH_GBR_REGNUM:
1809       GBR = val;
1810       break;
1811     case SIM_SH_VBR_REGNUM:
1812       VBR = val;
1813       break;
1814     case SIM_SH_MACH_REGNUM:
1815       MACH = val;
1816       break;
1817     case SIM_SH_MACL_REGNUM:
1818       MACL = val;
1819       break;
1820     case SIM_SH_SR_REGNUM:
1821       SET_SR (val);
1822       break;
1823     case SIM_SH_FPUL_REGNUM:
1824       FPUL = val;
1825       break;
1826     case SIM_SH_FPSCR_REGNUM:
1827       SET_FPSCR (val);
1828       break;
1829     case SIM_SH_FR0_REGNUM: case SIM_SH_FR1_REGNUM: case SIM_SH_FR2_REGNUM:
1830     case SIM_SH_FR3_REGNUM: case SIM_SH_FR4_REGNUM: case SIM_SH_FR5_REGNUM:
1831     case SIM_SH_FR6_REGNUM: case SIM_SH_FR7_REGNUM: case SIM_SH_FR8_REGNUM:
1832     case SIM_SH_FR9_REGNUM: case SIM_SH_FR10_REGNUM: case SIM_SH_FR11_REGNUM:
1833     case SIM_SH_FR12_REGNUM: case SIM_SH_FR13_REGNUM: case SIM_SH_FR14_REGNUM:
1834     case SIM_SH_FR15_REGNUM:
1835       SET_FI (rn - SIM_SH_FR0_REGNUM, val);
1836       break;
1837     case SIM_SH_DSR_REGNUM:
1838       DSR = val;
1839       break;
1840     case SIM_SH_A0G_REGNUM:
1841       A0G = val;
1842       break;
1843     case SIM_SH_A0_REGNUM:
1844       A0 = val;
1845       break;
1846     case SIM_SH_A1G_REGNUM:
1847       A1G = val;
1848       break;
1849     case SIM_SH_A1_REGNUM:
1850       A1 = val;
1851       break;
1852     case SIM_SH_M0_REGNUM:
1853       M0 = val;
1854       break;
1855     case SIM_SH_M1_REGNUM:
1856       M1 = val;
1857       break;
1858     case SIM_SH_X0_REGNUM:
1859       X0 = val;
1860       break;
1861     case SIM_SH_X1_REGNUM:
1862       X1 = val;
1863       break;
1864     case SIM_SH_Y0_REGNUM:
1865       Y0 = val;
1866       break;
1867     case SIM_SH_Y1_REGNUM:
1868       Y1 = val;
1869       break;
1870     case SIM_SH_MOD_REGNUM:
1871       SET_MOD (val);
1872       break;
1873     case SIM_SH_RS_REGNUM:
1874       RS = val;
1875       break;
1876     case SIM_SH_RE_REGNUM:
1877       RE = val;
1878       break;
1879     case SIM_SH_SSR_REGNUM:
1880       SSR = val;
1881       break;
1882     case SIM_SH_SPC_REGNUM:
1883       SPC = val;
1884       break;
1885     /* The rn_bank idiosyncracies are not due to hardware differences, but to
1886        a weird aliasing naming scheme for sh3 / sh3e / sh4.  */
1887     case SIM_SH_R0_BANK0_REGNUM: case SIM_SH_R1_BANK0_REGNUM:
1888     case SIM_SH_R2_BANK0_REGNUM: case SIM_SH_R3_BANK0_REGNUM:
1889     case SIM_SH_R4_BANK0_REGNUM: case SIM_SH_R5_BANK0_REGNUM:
1890     case SIM_SH_R6_BANK0_REGNUM: case SIM_SH_R7_BANK0_REGNUM:
1891       if (SR_MD && SR_RB)
1892         Rn_BANK (rn - SIM_SH_R0_BANK0_REGNUM) = val;
1893       else
1894         saved_state.asregs.regs[rn - SIM_SH_R0_BANK0_REGNUM] = val;
1895       break;
1896     case SIM_SH_R0_BANK1_REGNUM: case SIM_SH_R1_BANK1_REGNUM:
1897     case SIM_SH_R2_BANK1_REGNUM: case SIM_SH_R3_BANK1_REGNUM:
1898     case SIM_SH_R4_BANK1_REGNUM: case SIM_SH_R5_BANK1_REGNUM:
1899     case SIM_SH_R6_BANK1_REGNUM: case SIM_SH_R7_BANK1_REGNUM:
1900       if (SR_MD && SR_RB)
1901         saved_state.asregs.regs[rn - SIM_SH_R0_BANK1_REGNUM] = val;
1902       else
1903         Rn_BANK (rn - SIM_SH_R0_BANK1_REGNUM) = val;
1904       break;
1905     case SIM_SH_R0_BANK_REGNUM: case SIM_SH_R1_BANK_REGNUM:
1906     case SIM_SH_R2_BANK_REGNUM: case SIM_SH_R3_BANK_REGNUM:
1907     case SIM_SH_R4_BANK_REGNUM: case SIM_SH_R5_BANK_REGNUM:
1908     case SIM_SH_R6_BANK_REGNUM: case SIM_SH_R7_BANK_REGNUM:
1909       SET_Rn_BANK (rn - SIM_SH_R0_BANK_REGNUM, val);
1910       break;
1911     default:
1912       return 0;
1913     }
1914   return -1;
1915 }
1916
1917 int
1918 sim_fetch_register (sd, rn, memory, length)
1919      SIM_DESC sd;
1920      int rn;
1921      unsigned char *memory;
1922      int length;
1923 {
1924   int val;
1925
1926   init_pointers ();
1927   switch (rn)
1928     {
1929     case SIM_SH_R0_REGNUM: case SIM_SH_R1_REGNUM: case SIM_SH_R2_REGNUM:
1930     case SIM_SH_R3_REGNUM: case SIM_SH_R4_REGNUM: case SIM_SH_R5_REGNUM:
1931     case SIM_SH_R6_REGNUM: case SIM_SH_R7_REGNUM: case SIM_SH_R8_REGNUM:
1932     case SIM_SH_R9_REGNUM: case SIM_SH_R10_REGNUM: case SIM_SH_R11_REGNUM:
1933     case SIM_SH_R12_REGNUM: case SIM_SH_R13_REGNUM: case SIM_SH_R14_REGNUM:
1934     case SIM_SH_R15_REGNUM:
1935       val = saved_state.asregs.regs[rn];
1936       break;
1937     case SIM_SH_PC_REGNUM:
1938       val = saved_state.asregs.pc;
1939       break;
1940     case SIM_SH_PR_REGNUM:
1941       val = PR;
1942       break;
1943     case SIM_SH_GBR_REGNUM:
1944       val = GBR;
1945       break;
1946     case SIM_SH_VBR_REGNUM:
1947       val = VBR;
1948       break;
1949     case SIM_SH_MACH_REGNUM:
1950       val = MACH;
1951       break;
1952     case SIM_SH_MACL_REGNUM:
1953       val = MACL;
1954       break;
1955     case SIM_SH_SR_REGNUM:
1956       val = GET_SR ();
1957       break;
1958     case SIM_SH_FPUL_REGNUM:
1959       val = FPUL;
1960       break;
1961     case SIM_SH_FPSCR_REGNUM:
1962       val = GET_FPSCR ();
1963       break;
1964     case SIM_SH_FR0_REGNUM: case SIM_SH_FR1_REGNUM: case SIM_SH_FR2_REGNUM:
1965     case SIM_SH_FR3_REGNUM: case SIM_SH_FR4_REGNUM: case SIM_SH_FR5_REGNUM:
1966     case SIM_SH_FR6_REGNUM: case SIM_SH_FR7_REGNUM: case SIM_SH_FR8_REGNUM:
1967     case SIM_SH_FR9_REGNUM: case SIM_SH_FR10_REGNUM: case SIM_SH_FR11_REGNUM:
1968     case SIM_SH_FR12_REGNUM: case SIM_SH_FR13_REGNUM: case SIM_SH_FR14_REGNUM:
1969     case SIM_SH_FR15_REGNUM:
1970       val = FI (rn - SIM_SH_FR0_REGNUM);
1971       break;
1972     case SIM_SH_DSR_REGNUM:
1973       val = DSR;
1974       break;
1975     case SIM_SH_A0G_REGNUM:
1976       val = SEXT (A0G);
1977       break;
1978     case SIM_SH_A0_REGNUM:
1979       val = A0;
1980       break;
1981     case SIM_SH_A1G_REGNUM:
1982       val = SEXT (A1G);
1983       break;
1984     case SIM_SH_A1_REGNUM:
1985       val = A1;
1986       break;
1987     case SIM_SH_M0_REGNUM:
1988       val = M0;
1989       break;
1990     case SIM_SH_M1_REGNUM:
1991       val = M1;
1992       break;
1993     case SIM_SH_X0_REGNUM:
1994       val = X0;
1995       break;
1996     case SIM_SH_X1_REGNUM:
1997       val = X1;
1998       break;
1999     case SIM_SH_Y0_REGNUM:
2000       val = Y0;
2001       break;
2002     case SIM_SH_Y1_REGNUM:
2003       val = Y1;
2004       break;
2005     case SIM_SH_MOD_REGNUM:
2006       val = MOD;
2007       break;
2008     case SIM_SH_RS_REGNUM:
2009       val = RS;
2010       break;
2011     case SIM_SH_RE_REGNUM:
2012       val = RE;
2013       break;
2014     case SIM_SH_SSR_REGNUM:
2015       val = SSR;
2016       break;
2017     case SIM_SH_SPC_REGNUM:
2018       val = SPC;
2019       break;
2020     /* The rn_bank idiosyncracies are not due to hardware differences, but to
2021        a weird aliasing naming scheme for sh3 / sh3e / sh4.  */
2022     case SIM_SH_R0_BANK0_REGNUM: case SIM_SH_R1_BANK0_REGNUM:
2023     case SIM_SH_R2_BANK0_REGNUM: case SIM_SH_R3_BANK0_REGNUM:
2024     case SIM_SH_R4_BANK0_REGNUM: case SIM_SH_R5_BANK0_REGNUM:
2025     case SIM_SH_R6_BANK0_REGNUM: case SIM_SH_R7_BANK0_REGNUM:
2026       val = (SR_MD && SR_RB
2027              ? Rn_BANK (rn - SIM_SH_R0_BANK0_REGNUM)
2028              : saved_state.asregs.regs[rn - SIM_SH_R0_BANK0_REGNUM]);
2029       break;
2030     case SIM_SH_R0_BANK1_REGNUM: case SIM_SH_R1_BANK1_REGNUM:
2031     case SIM_SH_R2_BANK1_REGNUM: case SIM_SH_R3_BANK1_REGNUM:
2032     case SIM_SH_R4_BANK1_REGNUM: case SIM_SH_R5_BANK1_REGNUM:
2033     case SIM_SH_R6_BANK1_REGNUM: case SIM_SH_R7_BANK1_REGNUM:
2034       val = (! SR_MD || ! SR_RB
2035              ? Rn_BANK (rn - SIM_SH_R0_BANK1_REGNUM)
2036              : saved_state.asregs.regs[rn - SIM_SH_R0_BANK1_REGNUM]);
2037       break;
2038     case SIM_SH_R0_BANK_REGNUM: case SIM_SH_R1_BANK_REGNUM:
2039     case SIM_SH_R2_BANK_REGNUM: case SIM_SH_R3_BANK_REGNUM:
2040     case SIM_SH_R4_BANK_REGNUM: case SIM_SH_R5_BANK_REGNUM:
2041     case SIM_SH_R6_BANK_REGNUM: case SIM_SH_R7_BANK_REGNUM:
2042       val = Rn_BANK (rn - SIM_SH_R0_BANK_REGNUM);
2043       break;
2044     default:
2045       return 0;
2046     }
2047   * (int *) memory = swap (val);
2048   return -1;
2049 }
2050
2051 int
2052 sim_trace (sd)
2053      SIM_DESC sd;
2054 {
2055   return 0;
2056 }
2057
2058 void
2059 sim_stop_reason (sd, reason, sigrc)
2060      SIM_DESC sd;
2061      enum sim_stop *reason;
2062      int *sigrc;
2063 {
2064   /* The SH simulator uses SIGQUIT to indicate that the program has
2065      exited, so we must check for it here and translate it to exit.  */
2066   if (saved_state.asregs.exception == SIGQUIT)
2067     {
2068       *reason = sim_exited;
2069       *sigrc = saved_state.asregs.regs[5];
2070     }
2071   else
2072     {
2073       *reason = sim_stopped;
2074       *sigrc = saved_state.asregs.exception;
2075     }
2076 }
2077
2078 void
2079 sim_info (sd, verbose)
2080      SIM_DESC sd;
2081      int verbose;
2082 {
2083   double timetaken = (double) saved_state.asregs.ticks / (double) now_persec ();
2084   double virttime = saved_state.asregs.cycles / 36.0e6;
2085
2086   callback->printf_filtered (callback, "\n\n# instructions executed  %10d\n",
2087                              saved_state.asregs.insts);
2088   callback->printf_filtered (callback, "# cycles                 %10d\n",
2089                              saved_state.asregs.cycles);
2090   callback->printf_filtered (callback, "# pipeline stalls        %10d\n",
2091                              saved_state.asregs.stalls);
2092   callback->printf_filtered (callback, "# misaligned load/store  %10d\n",
2093                              saved_state.asregs.memstalls);
2094   callback->printf_filtered (callback, "# real time taken        %10.4f\n",
2095                              timetaken);
2096   callback->printf_filtered (callback, "# virtual time taken     %10.4f\n",
2097                              virttime);
2098   callback->printf_filtered (callback, "# profiling size         %10d\n",
2099                              sim_profile_size);
2100   callback->printf_filtered (callback, "# profiling frequency    %10d\n",
2101                              saved_state.asregs.profile);
2102   callback->printf_filtered (callback, "# profile maxpc          %10x\n",
2103                              (1 << sim_profile_size) << PROFILE_SHIFT);
2104
2105   if (timetaken != 0)
2106     {
2107       callback->printf_filtered (callback, "# cycles/second          %10d\n",
2108                                  (int) (saved_state.asregs.cycles / timetaken));
2109       callback->printf_filtered (callback, "# simulation ratio       %10.4f\n",
2110                                  virttime / timetaken);
2111     }
2112 }
2113
2114 void
2115 sim_set_profile (n)
2116      int n;
2117 {
2118   saved_state.asregs.profile = n;
2119 }
2120
2121 void
2122 sim_set_profile_size (n)
2123      int n;
2124 {
2125   sim_profile_size = n;
2126 }
2127
2128 SIM_DESC
2129 sim_open (kind, cb, abfd, argv)
2130      SIM_OPEN_KIND kind;
2131      host_callback *cb;
2132      struct _bfd *abfd;
2133      char **argv;
2134 {
2135   char **p;
2136   int endian_set = 0;
2137   int i;
2138   union
2139     {
2140       int i;
2141       short s[2];
2142       char c[4];
2143     }
2144   mem_word;
2145
2146   sim_kind = kind;
2147   myname = argv[0];
2148   callback = cb;
2149
2150   for (p = argv + 1; *p != NULL; ++p)
2151     {
2152       if (strcmp (*p, "-E") == 0)
2153         {
2154           ++p;
2155           if (*p == NULL)
2156             {
2157               /* FIXME: This doesn't use stderr, but then the rest of the
2158                  file doesn't either.  */
2159               callback->printf_filtered (callback, "Missing argument to `-E'.\n");
2160               return 0;
2161             }
2162           target_little_endian = strcmp (*p, "big") != 0;
2163           endian_set = 1;
2164         }
2165       else if (isdigit (**p))
2166         parse_and_set_memory_size (*p);
2167     }
2168
2169   if (abfd != NULL && ! endian_set)
2170       target_little_endian = ! bfd_big_endian (abfd);
2171
2172   if (abfd)
2173     init_dsp (abfd);
2174
2175   for (i = 4; (i -= 2) >= 0; )
2176     mem_word.s[i >> 1] = i;
2177   global_endianw = mem_word.i >> (target_little_endian ? 0 : 16) & 0xffff;
2178
2179   for (i = 4; --i >= 0; )
2180     mem_word.c[i] = i;
2181   endianb = mem_word.i >> (target_little_endian ? 0 : 24) & 0xff;
2182
2183   /* fudge our descriptor for now */
2184   return (SIM_DESC) 1;
2185 }
2186
2187 static void
2188 parse_and_set_memory_size (str)
2189      char *str;
2190 {
2191   int n;
2192
2193   n = strtol (str, NULL, 10);
2194   if (n > 0 && n <= 24)
2195     sim_memory_size = n;
2196   else
2197     callback->printf_filtered (callback, "Bad memory size %d; must be 1 to 24, inclusive\n", n);
2198 }
2199
2200 void
2201 sim_close (sd, quitting)
2202      SIM_DESC sd;
2203      int quitting;
2204 {
2205   /* nothing to do */
2206 }
2207
2208 SIM_RC
2209 sim_load (sd, prog, abfd, from_tty)
2210      SIM_DESC sd;
2211      char *prog;
2212      bfd *abfd;
2213      int from_tty;
2214 {
2215   extern bfd *sim_load_file (); /* ??? Don't know where this should live.  */
2216   bfd *prog_bfd;
2217
2218   prog_bfd = sim_load_file (sd, myname, callback, prog, abfd,
2219                             sim_kind == SIM_OPEN_DEBUG,
2220                             0, sim_write);
2221   if (prog_bfd == NULL)
2222     return SIM_RC_FAIL;
2223   if (abfd == NULL)
2224     bfd_close (prog_bfd);
2225   return SIM_RC_OK;
2226 }
2227
2228 SIM_RC
2229 sim_create_inferior (sd, prog_bfd, argv, env)
2230      SIM_DESC sd;
2231      struct _bfd *prog_bfd;
2232      char **argv;
2233      char **env;
2234 {
2235   /* Clear the registers. */
2236   memset (&saved_state, 0,
2237           (char*)&saved_state.asregs.end_of_registers - (char*)&saved_state);
2238
2239   /* Set the PC.  */
2240   if (prog_bfd != NULL)
2241     saved_state.asregs.pc = bfd_get_start_address (prog_bfd);
2242
2243   /* Record the program's arguments. */
2244   prog_argv = argv;
2245
2246   return SIM_RC_OK;
2247 }
2248
2249 void
2250 sim_do_command (sd, cmd)
2251      SIM_DESC sd;
2252      char *cmd;
2253 {
2254   char *sms_cmd = "set-memory-size";
2255   int cmdsize;
2256
2257   if (cmd == NULL || *cmd == '\0')
2258     {
2259       cmd = "help";
2260     }
2261
2262   cmdsize = strlen (sms_cmd);
2263   if (strncmp (cmd, sms_cmd, cmdsize) == 0 && strchr (" \t", cmd[cmdsize]) != NULL)
2264     {
2265       parse_and_set_memory_size (cmd + cmdsize + 1);
2266     }
2267   else if (strcmp (cmd, "help") == 0)
2268     {
2269       (callback->printf_filtered) (callback, "List of SH simulator commands:\n\n");
2270       (callback->printf_filtered) (callback, "set-memory-size <n> -- Set the number of address bits to use\n");
2271       (callback->printf_filtered) (callback, "\n");
2272     }
2273   else
2274     {
2275       (callback->printf_filtered) (callback, "Error: \"%s\" is not a valid SH simulator command.\n", cmd);
2276     }
2277 }
2278
2279 void
2280 sim_set_callbacks (p)
2281      host_callback *p;
2282 {
2283   callback = p;
2284 }