sim/sh64/sh64.c

   1 /* SH5 simulator support code
   2    Copyright (C) 2000-2017 Free Software Foundation, Inc.
   3    Contributed by Red Hat, Inc.
   4
   5 This file is part of the GNU simulators.
   6
   7 This program is free software; you can redistribute it and/or modify
   8 it under the terms of the GNU General Public License as published by
   9 the Free Software Foundation; either version 3 of the License, or
  10 (at your option) any later version.
  11
  12 This program is distributed in the hope that it will be useful,
  13 but WITHOUT ANY WARRANTY; without even the implied warranty of
  14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15 GNU General Public License for more details.
  16
  17 You should have received a copy of the GNU General Public License
  18 along with this program.  If not, see <http://www.gnu.org/licenses/>.  */
  19
  20 #define WANT_CPU
  21 #define WANT_CPU_SH64
  22
  23 #include "sim-main.h"
  24 #include "sim-fpu.h"
  25 #include "cgen-mem.h"
  26 #include "cgen-ops.h"
  27
  28 #include "gdb/callback.h"
  29 #include "defs-compact.h"
  30
  31 #include "bfd.h"
  32 /* From include/gdb/.  */
  33 #include "gdb/sim-sh.h"
  34
  35 #define SYS_exit        1
  36 #define SYS_read        3
  37 #define SYS_write       4
  38 #define SYS_open        5
  39 #define SYS_close       6
  40 #define SYS_lseek       19
  41 #define SYS_time        23
  42 #define SYS_argc        172
  43 #define SYS_argnlen     173
  44 #define SYS_argn        174
  45
  46 IDESC * sh64_idesc_media;
  47 IDESC * sh64_idesc_compact;
  48
  49 BI
  50 sh64_endian (SIM_CPU *current_cpu)
  51 {
  52   return (CURRENT_TARGET_BYTE_ORDER == BIG_ENDIAN);
  53 }
  54
  55 SF
  56 sh64_fldi0 (SIM_CPU *current_cpu)
  57 {
  58   SF result;
  59   sim_fpu_to32 (&result, &sim_fpu_zero);
  60   return result;
  61 }
  62
  63 SF
  64 sh64_fldi1 (SIM_CPU *current_cpu)
  65 {
  66   SF result;
  67   sim_fpu_to32 (&result, &sim_fpu_one);
  68   return result;
  69 }
  70
  71 DF
  72 sh64_fabsd(SIM_CPU *current_cpu, DF drgh)
  73 {
  74   DF result;
  75   sim_fpu f, fres;
  76
  77   sim_fpu_64to (&f, drgh);
  78   sim_fpu_abs (&fres, &f);
  79   sim_fpu_to64 (&result, &fres);
  80   return result;
  81 }
  82
  83 SF
  84 sh64_fabss(SIM_CPU *current_cpu, SF frgh)
  85 {
  86   SF result;
  87   sim_fpu f, fres;
  88
  89   sim_fpu_32to (&f, frgh);
  90   sim_fpu_abs (&fres, &f);
  91   sim_fpu_to32 (&result, &fres);
  92   return result;
  93 }
  94
  95 DF
  96 sh64_faddd(SIM_CPU *current_cpu, DF drg, DF drh)
  97 {
  98   DF result;
  99   sim_fpu f1, f2, fres;
 100
 101   sim_fpu_64to (&f1, drg);
 102   sim_fpu_64to (&f2, drh);
 103   sim_fpu_add (&fres, &f1, &f2);
 104   sim_fpu_to64 (&result, &fres);
 105   return result;
 106 }
 107
 108 SF
 109 sh64_fadds(SIM_CPU *current_cpu, SF frg, SF frh)
 110 {
 111   SF result;
 112   sim_fpu f1, f2, fres;
 113
 114   sim_fpu_32to (&f1, frg);
 115   sim_fpu_32to (&f2, frh);
 116   sim_fpu_add (&fres, &f1, &f2);
 117   sim_fpu_to32 (&result, &fres);
 118   return result;
 119 }
 120
 121 BI
 122 sh64_fcmpeqd(SIM_CPU *current_cpu, DF drg, DF drh)
 123 {
 124   sim_fpu f1, f2;
 125
 126   sim_fpu_64to (&f1, drg);
 127   sim_fpu_64to (&f2, drh);
 128   return sim_fpu_is_eq (&f1, &f2);
 129 }
 130
 131 BI
 132 sh64_fcmpeqs(SIM_CPU *current_cpu, SF frg, SF frh)
 133 {
 134   sim_fpu f1, f2;
 135
 136   sim_fpu_32to (&f1, frg);
 137   sim_fpu_32to (&f2, frh);
 138   return sim_fpu_is_eq (&f1, &f2);
 139 }
 140
 141 BI
 142 sh64_fcmpged(SIM_CPU *current_cpu, DF drg, DF drh)
 143 {
 144   sim_fpu f1, f2;
 145
 146   sim_fpu_64to (&f1, drg);
 147   sim_fpu_64to (&f2, drh);
 148   return sim_fpu_is_ge (&f1, &f2);
 149 }
 150
 151 BI
 152 sh64_fcmpges(SIM_CPU *current_cpu, SF frg, SF frh)
 153 {
 154   sim_fpu f1, f2;
 155
 156   sim_fpu_32to (&f1, frg);
 157   sim_fpu_32to (&f2, frh);
 158   return sim_fpu_is_ge (&f1, &f2);
 159 }
 160
 161 BI
 162 sh64_fcmpgtd(SIM_CPU *current_cpu, DF drg, DF drh)
 163 {
 164   sim_fpu f1, f2;
 165
 166   sim_fpu_64to (&f1, drg);
 167   sim_fpu_64to (&f2, drh);
 168   return sim_fpu_is_gt (&f1, &f2);
 169 }
 170
 171 BI
 172 sh64_fcmpgts(SIM_CPU *current_cpu, SF frg, SF frh)
 173 {
 174   sim_fpu f1, f2;
 175
 176   sim_fpu_32to (&f1, frg);
 177   sim_fpu_32to (&f2, frh);
 178   return sim_fpu_is_gt (&f1, &f2);
 179 }
 180
 181 BI
 182 sh64_fcmpund(SIM_CPU *current_cpu, DF drg, DF drh)
 183 {
 184   sim_fpu f1, f2;
 185
 186   sim_fpu_64to (&f1, drg);
 187   sim_fpu_64to (&f2, drh);
 188   return (sim_fpu_is_nan (&f1) || sim_fpu_is_nan (&f2));
 189 }
 190
 191 BI
 192 sh64_fcmpuns(SIM_CPU *current_cpu, SF frg, SF frh)
 193 {
 194   sim_fpu f1, f2;
 195
 196   sim_fpu_32to (&f1, frg);
 197   sim_fpu_32to (&f2, frh);
 198   return (sim_fpu_is_nan (&f1) || sim_fpu_is_nan (&f2));
 199 }
 200
 201 SF
 202 sh64_fcnvds(SIM_CPU *current_cpu, DF drgh)
 203 {
 204   union {
 205     unsigned long long ll;
 206     double d;
 207   } f1;
 208
 209   union {
 210     unsigned long l;
 211     float f;
 212   } f2;
 213
 214   f1.ll = drgh;
 215   f2.f = (float) f1.d;
 216
 217   return (SF) f2.l;
 218 }
 219
 220 DF
 221 sh64_fcnvsd(SIM_CPU *current_cpu, SF frgh)
 222 {
 223   DF result;
 224   sim_fpu f;
 225
 226   sim_fpu_32to (&f, frgh);
 227   sim_fpu_to64 (&result, &f);
 228   return result;
 229 }
 230
 231 DF
 232 sh64_fdivd(SIM_CPU *current_cpu, DF drg, DF drh)
 233 {
 234   DF result;
 235   sim_fpu f1, f2, fres;
 236
 237   sim_fpu_64to (&f1, drg);
 238   sim_fpu_64to (&f2, drh);
 239   sim_fpu_div (&fres, &f1, &f2);
 240   sim_fpu_to64 (&result, &fres);
 241   return result;
 242 }
 243
 244 SF
 245 sh64_fdivs(SIM_CPU *current_cpu, SF frg, SF frh)
 246 {
 247   SF result;
 248   sim_fpu f1, f2, fres;
 249
 250   sim_fpu_32to (&f1, frg);
 251   sim_fpu_32to (&f2, frh);
 252   sim_fpu_div (&fres, &f1, &f2);
 253   sim_fpu_to32 (&result, &fres);
 254   return result;
 255 }
 256
 257 DF
 258 sh64_floatld(SIM_CPU *current_cpu, SF frgh)
 259 {
 260   DF result;
 261   sim_fpu f;
 262
 263   sim_fpu_i32to (&f, frgh, sim_fpu_round_default);
 264   sim_fpu_to64 (&result, &f);
 265   return result;
 266 }
 267
 268 SF
 269 sh64_floatls(SIM_CPU *current_cpu, SF frgh)
 270 {
 271   SF result;
 272   sim_fpu f;
 273
 274   sim_fpu_i32to (&f, frgh, sim_fpu_round_default);
 275   sim_fpu_to32 (&result, &f);
 276   return result;
 277 }
 278
 279 DF
 280 sh64_floatqd(SIM_CPU *current_cpu, DF drgh)
 281 {
 282   DF result;
 283   sim_fpu f;
 284
 285   sim_fpu_i64to (&f, drgh, sim_fpu_round_default);
 286   sim_fpu_to64 (&result, &f);
 287   return result;
 288 }
 289
 290 SF
 291 sh64_floatqs(SIM_CPU *current_cpu, DF drgh)
 292 {
 293   SF result;
 294   sim_fpu f;
 295
 296   sim_fpu_i64to (&f, drgh, sim_fpu_round_default);
 297   sim_fpu_to32 (&result, &f);
 298   return result;
 299 }
 300
 301 SF
 302 sh64_fmacs(SIM_CPU *current_cpu, SF fr0, SF frm, SF frn)
 303 {
 304   SF result;
 305   sim_fpu m1, m2, a1, fres;
 306
 307   sim_fpu_32to (&m1, fr0);
 308   sim_fpu_32to (&m2, frm);
 309   sim_fpu_32to (&a1, frn);
 310
 311   sim_fpu_mul (&fres, &m1, &m2);
 312   sim_fpu_add (&fres, &fres, &a1);
 313
 314   sim_fpu_to32 (&result, &fres);
 315   return result;
 316 }
 317
 318 DF
 319 sh64_fmuld(SIM_CPU *current_cpu, DF drg, DF drh)
 320 {
 321   DF result;
 322   sim_fpu f1, f2, fres;
 323
 324   sim_fpu_64to (&f1, drg);
 325   sim_fpu_64to (&f2, drh);
 326   sim_fpu_mul (&fres, &f1, &f2);
 327   sim_fpu_to64 (&result, &fres);
 328   return result;
 329 }
 330
 331 SF
 332 sh64_fmuls(SIM_CPU *current_cpu, SF frg, SF frh)
 333 {
 334   SF result;
 335   sim_fpu f1, f2, fres;
 336
 337   sim_fpu_32to (&f1, frg);
 338   sim_fpu_32to (&f2, frh);
 339   sim_fpu_mul (&fres, &f1, &f2);
 340   sim_fpu_to32 (&result, &fres);
 341   return result;
 342 }
 343
 344 DF
 345 sh64_fnegd(SIM_CPU *current_cpu, DF drgh)
 346 {
 347   DF result;
 348   sim_fpu f1, f2;
 349
 350   sim_fpu_64to (&f1, drgh);
 351   sim_fpu_neg (&f2, &f1);
 352   sim_fpu_to64 (&result, &f2);
 353   return result;
 354 }
 355
 356 SF
 357 sh64_fnegs(SIM_CPU *current_cpu, SF frgh)
 358 {
 359   SF result;
 360   sim_fpu f, fres;
 361
 362   sim_fpu_32to (&f, frgh);
 363   sim_fpu_neg (&fres, &f);
 364   sim_fpu_to32 (&result, &fres);
 365   return result;
 366 }
 367
 368 DF
 369 sh64_fsqrtd(SIM_CPU *current_cpu, DF drgh)
 370 {
 371   DF result;
 372   sim_fpu f, fres;
 373
 374   sim_fpu_64to (&f, drgh);
 375   sim_fpu_sqrt (&fres, &f);
 376   sim_fpu_to64 (&result, &fres);
 377   return result;
 378 }
 379
 380 SF
 381 sh64_fsqrts(SIM_CPU *current_cpu, SF frgh)
 382 {
 383   SF result;
 384   sim_fpu f, fres;
 385
 386   sim_fpu_32to (&f, frgh);
 387   sim_fpu_sqrt (&fres, &f);
 388   sim_fpu_to32 (&result, &fres);
 389   return result;
 390 }
 391
 392 DF
 393 sh64_fsubd(SIM_CPU *current_cpu, DF drg, DF drh)
 394 {
 395   DF result;
 396   sim_fpu f1, f2, fres;
 397
 398   sim_fpu_64to (&f1, drg);
 399   sim_fpu_64to (&f2, drh);
 400   sim_fpu_sub (&fres, &f1, &f2);
 401   sim_fpu_to64 (&result, &fres);
 402   return result;
 403 }
 404
 405 SF
 406 sh64_fsubs(SIM_CPU *current_cpu, SF frg, SF frh)
 407 {
 408   SF result;
 409   sim_fpu f1, f2, fres;
 410
 411   sim_fpu_32to (&f1, frg);
 412   sim_fpu_32to (&f2, frh);
 413   sim_fpu_sub (&fres, &f1, &f2);
 414   sim_fpu_to32 (&result, &fres);
 415   return result;
 416 }
 417
 418 SF
 419 sh64_ftrcdl(SIM_CPU *current_cpu, DF drgh)
 420 {
 421   SI result;
 422   sim_fpu f;
 423
 424   sim_fpu_64to (&f, drgh);
 425   sim_fpu_to32i (&result, &f, sim_fpu_round_zero);
 426   return (SF) result;
 427 }
 428
 429 SF
 430 sh64_ftrcsl(SIM_CPU *current_cpu, SF frgh)
 431 {
 432   SI result;
 433   sim_fpu f;
 434
 435   sim_fpu_32to (&f, frgh);
 436   sim_fpu_to32i (&result, &f, sim_fpu_round_zero);
 437   return (SF) result;
 438 }
 439
 440 DF
 441 sh64_ftrcdq(SIM_CPU *current_cpu, DF drgh)
 442 {
 443   DI result;
 444   sim_fpu f;
 445
 446   sim_fpu_64to (&f, drgh);
 447   sim_fpu_to64i (&result, &f, sim_fpu_round_zero);
 448   return (DF) result;
 449 }
 450
 451 DF
 452 sh64_ftrcsq(SIM_CPU *current_cpu, SF frgh)
 453 {
 454   DI result;
 455   sim_fpu f;
 456
 457   sim_fpu_32to (&f, frgh);
 458   sim_fpu_to64i (&result, &f, sim_fpu_round_zero);
 459   return (DF) result;
 460 }
 461
 462 VOID
 463 sh64_ftrvs(SIM_CPU *cpu, unsigned g, unsigned h, unsigned f)
 464 {
 465   int i, j;
 466
 467   for (i = 0; i < 4; i++)
 468     {
 469       SF result;
 470       sim_fpu sum;
 471       sim_fpu_32to (&sum, 0);
 472
 473       for (j = 0; j < 4; j++)
 474         {
 475           sim_fpu f1, f2, temp;
 476           sim_fpu_32to (&f1, sh64_h_fr_get (cpu, (g + i) + (j * 4)));
 477           sim_fpu_32to (&f2, sh64_h_fr_get (cpu, h + j));
 478           sim_fpu_mul (&temp, &f1, &f2);
 479           sim_fpu_add (&sum, &sum, &temp);
 480         }
 481       sim_fpu_to32 (&result, &sum);
 482       sh64_h_fr_set (cpu, f + i, result);
 483     }
 484 }
 485
 486 VOID
 487 sh64_fipr (SIM_CPU *cpu, unsigned m, unsigned n)
 488 {
 489   SF result = sh64_fmuls (cpu, sh64_h_fvc_get (cpu, m), sh64_h_fvc_get (cpu, n));
 490   result = sh64_fadds (cpu, result, sh64_fmuls (cpu, sh64_h_frc_get (cpu, m + 1), sh64_h_frc_get (cpu, n + 1)));
 491   result = sh64_fadds (cpu, result, sh64_fmuls (cpu, sh64_h_frc_get (cpu, m + 2), sh64_h_frc_get (cpu, n + 2)));
 492   result = sh64_fadds (cpu, result, sh64_fmuls (cpu, sh64_h_frc_get (cpu, m + 3), sh64_h_frc_get (cpu, n + 3)));
 493   sh64_h_frc_set (cpu, n + 3, result);
 494 }
 495
 496 SF
 497 sh64_fiprs (SIM_CPU *cpu, unsigned g, unsigned h)
 498 {
 499   SF temp = sh64_fmuls (cpu, sh64_h_fr_get (cpu, g), sh64_h_fr_get (cpu, h));
 500   temp = sh64_fadds (cpu, temp, sh64_fmuls (cpu, sh64_h_fr_get (cpu, g + 1), sh64_h_fr_get (cpu, h + 1)));
 501   temp = sh64_fadds (cpu, temp, sh64_fmuls (cpu, sh64_h_fr_get (cpu, g + 2), sh64_h_fr_get (cpu, h + 2)));
 502   temp = sh64_fadds (cpu, temp, sh64_fmuls (cpu, sh64_h_fr_get (cpu, g + 3), sh64_h_fr_get (cpu, h + 3)));
 503   return temp;
 504 }
 505
 506 VOID
 507 sh64_fldp (SIM_CPU *cpu, PCADDR pc, DI rm, DI rn, unsigned f)
 508 {
 509   sh64_h_fr_set (cpu, f,     GETMEMSF (cpu, pc, rm + rn));
 510   sh64_h_fr_set (cpu, f + 1, GETMEMSF (cpu, pc, rm + rn + 4));
 511 }
 512
 513 VOID
 514 sh64_fstp (SIM_CPU *cpu, PCADDR pc, DI rm, DI rn, unsigned f)
 515 {
 516   SETMEMSF (cpu, pc, rm + rn,     sh64_h_fr_get (cpu, f));
 517   SETMEMSF (cpu, pc, rm + rn + 4, sh64_h_fr_get (cpu, f + 1));
 518 }
 519
 520 VOID
 521 sh64_ftrv (SIM_CPU *cpu, UINT ignored)
 522 {
 523   /* TODO: Unimplemented.  */
 524 }
 525
 526 VOID
 527 sh64_pref (SIM_CPU *cpu, SI addr)
 528 {
 529   /* TODO: Unimplemented.  */
 530 }
 531
 532 /* Read a null terminated string from memory, return in a buffer */
 533 static char *
 534 fetch_str (current_cpu, pc, addr)
 535      SIM_CPU *current_cpu;
 536      PCADDR pc;
 537      DI addr;
 538 {
 539   char *buf;
 540   int nr = 0;
 541   while (sim_core_read_1 (current_cpu,
 542                           pc, read_map, addr + nr) != 0)
 543     nr++;
 544   buf = NZALLOC (char, nr + 1);
 545   sim_read (CPU_STATE (current_cpu), addr, buf, nr);
 546   return buf;
 547 }
 548
 549 static void
 550 trap_handler (SIM_CPU *current_cpu, int shmedia_abi_p, UQI trapnum, PCADDR pc)
 551 {
 552   char ch;
 553   switch (trapnum)
 554     {
 555     case 1:
 556       ch = GET_H_GRC (0);
 557       sim_io_write_stdout (CPU_STATE (current_cpu), &ch, 1);
 558       fflush (stdout);
 559       break;
 560     case 2:
 561       sim_engine_halt (CPU_STATE (current_cpu), current_cpu, NULL, pc, sim_stopped, SIM_SIGTRAP);
 562       break;
 563     case 34:
 564       {
 565         int i;
 566         int ret_reg = (shmedia_abi_p) ? 2 : 0;
 567         char *buf;
 568         DI PARM1 = GET_H_GR ((shmedia_abi_p) ? 3 : 5);
 569         DI PARM2 = GET_H_GR ((shmedia_abi_p) ? 4 : 6);
 570         DI PARM3 = GET_H_GR ((shmedia_abi_p) ? 5 : 7);
 571
 572         switch (GET_H_GR ((shmedia_abi_p) ? 2 : 4))
 573           {
 574           case SYS_write:
 575             buf = zalloc (PARM3);
 576             sim_read (CPU_STATE (current_cpu), PARM2, buf, PARM3);
 577             SET_H_GR (ret_reg,
 578                       sim_io_write (CPU_STATE (current_cpu),
 579                                     PARM1, buf, PARM3));
 580             free (buf);
 581             break;
 582
 583           case SYS_lseek:
 584             SET_H_GR (ret_reg,
 585                       sim_io_lseek (CPU_STATE (current_cpu),
 586                                     PARM1, PARM2, PARM3));
 587             break;
 588
 589           case SYS_exit:
 590             sim_engine_halt (CPU_STATE (current_cpu), current_cpu,
 591                              NULL, pc, sim_exited, PARM1);
 592             break;
 593
 594           case SYS_read:
 595             buf = zalloc (PARM3);
 596             SET_H_GR (ret_reg,
 597                       sim_io_read (CPU_STATE (current_cpu),
 598                                    PARM1, buf, PARM3));
 599             sim_write (CPU_STATE (current_cpu), PARM2, buf, PARM3);
 600             free (buf);
 601             break;
 602
 603           case SYS_open:
 604             buf = fetch_str (current_cpu, pc, PARM1);
 605             SET_H_GR (ret_reg,
 606                       sim_io_open (CPU_STATE (current_cpu),
 607                                    buf, PARM2));
 608             free (buf);
 609             break;
 610
 611           case SYS_close:
 612             SET_H_GR (ret_reg,
 613                       sim_io_close (CPU_STATE (current_cpu), PARM1));
 614             break;
 615
 616           case SYS_time:
 617             SET_H_GR (ret_reg, time (0));
 618             break;
 619
 620           case SYS_argc:
 621             SET_H_GR (ret_reg, countargv (STATE_PROG_ARGV (CPU_STATE (current_cpu))));
 622             break;
 623
 624           case SYS_argnlen:
 625             if (PARM1 < countargv (STATE_PROG_ARGV (CPU_STATE (current_cpu))))
 626               SET_H_GR (ret_reg,
 627                         strlen (STATE_PROG_ARGV (CPU_STATE (current_cpu)) [PARM1]));
 628             else
 629               SET_H_GR (ret_reg, -1);
 630             break;
 631
 632           case SYS_argn:
 633             if (PARM1 < countargv (STATE_PROG_ARGV (CPU_STATE (current_cpu))))
 634               {
 635                 /* Include the NULL byte.  */
 636                 i = strlen (STATE_PROG_ARGV (CPU_STATE (current_cpu)) [PARM1]) + 1;
 637                 sim_write (CPU_STATE (current_cpu),
 638                            PARM2,
 639                            STATE_PROG_ARGV (CPU_STATE (current_cpu)) [PARM1],
 640                            i);
 641
 642                 /* Just for good measure.  */
 643                 SET_H_GR (ret_reg, i);
 644                 break;
 645               }
 646             else
 647               SET_H_GR (ret_reg, -1);
 648             break;
 649
 650           default:
 651             SET_H_GR (ret_reg, -1);
 652           }
 653       }
 654       break;
 655     case 253:
 656       puts ("pass");
 657       exit (0);
 658     case 254:
 659       puts ("fail");
 660       exit (1);
 661     case 0xc3:
 662       /* fall through.  */
 663     case 255:
 664       sim_engine_halt (CPU_STATE (current_cpu), current_cpu, NULL, pc, sim_stopped, SIM_SIGTRAP);
 665       break;
 666     }
 667 }
 668
 669 void
 670 sh64_trapa (SIM_CPU *current_cpu, DI rm, PCADDR pc)
 671 {
 672   trap_handler (current_cpu, 1, (UQI) rm & 0xff, pc);
 673 }
 674
 675 void
 676 sh64_compact_trapa (SIM_CPU *current_cpu, UQI trapnum, PCADDR pc)
 677 {
 678   int mach_sh5_p;
 679
 680   /* If this is an SH5 executable, this is SHcompact code running in
 681      the SHmedia ABI.  */
 682
 683   mach_sh5_p =
 684     (bfd_get_mach (STATE_PROG_BFD (CPU_STATE (current_cpu))) == bfd_mach_sh5);
 685
 686   trap_handler (current_cpu, mach_sh5_p, trapnum, pc);
 687 }
 688
 689 DI
 690 sh64_nsb (SIM_CPU *current_cpu, DI rm)
 691 {
 692   int result = 0, count;
 693   UDI source = (UDI) rm;
 694
 695   if ((source >> 63))
 696     source = ~source;
 697   source <<= 1;
 698
 699   for (count = 32; count; count >>= 1)
 700     {
 701       UDI newval = source << count;
 702
 703       if ((newval >> count) == source)
 704         {
 705           result |= count;
 706           source = newval;
 707         }
 708     }
 709
 710   return result;
 711 }
 712
 713 void
 714 sh64_break (SIM_CPU *current_cpu, PCADDR pc)
 715 {
 716   SIM_DESC sd = CPU_STATE (current_cpu);
 717   sim_engine_halt (sd, current_cpu, NULL, pc, sim_stopped, SIM_SIGTRAP);
 718 }
 719
 720 SI
 721 sh64_movua (SIM_CPU *current_cpu, PCADDR pc, SI rn)
 722 {
 723   SI v;
 724   int i;
 725
 726   /* Move the data one byte at a time to avoid alignment problems.
 727      Be aware of endianness.  */
 728   v = 0;
 729   for (i = 0; i < 4; ++i)
 730     v = (v << 8) | (GETMEMQI (current_cpu, pc, rn + i) & 0xff);
 731
 732   v = T2H_4 (v);
 733   return v;
 734 }
 735
 736 void
 737 set_isa (SIM_CPU *current_cpu, int mode)
 738 {
 739   /* Do nothing.  */
 740 }
 741
 742 /* The semantic code invokes this for invalid (unrecognized) instructions.  */
 743
 744 SEM_PC
 745 sim_engine_invalid_insn (SIM_CPU *current_cpu, IADDR cia, SEM_PC vpc)
 746 {
 747   SIM_DESC sd = CPU_STATE (current_cpu);
 748   sim_engine_halt (sd, current_cpu, NULL, cia, sim_stopped, SIM_SIGILL);
 749
 750   return vpc;
 751 }
 752
 753
 754 /* Process an address exception.  */
 755
 756 void
 757 sh64_core_signal (SIM_DESC sd, SIM_CPU *current_cpu, sim_cia cia,
 758                   unsigned int map, int nr_bytes, address_word addr,
 759                   transfer_type transfer, sim_core_signals sig)
 760 {
 761   sim_core_signal (sd, current_cpu, cia, map, nr_bytes, addr,
 762                    transfer, sig);
 763 }
 764
 765
 766 /* Initialize cycle counting for an insn.
 767    FIRST_P is non-zero if this is the first insn in a set of parallel
 768    insns.  */
 769
 770 void
 771 sh64_compact_model_insn_before (SIM_CPU *cpu, int first_p)
 772 {
 773   /* Do nothing.  */
 774 }
 775
 776 void
 777 sh64_media_model_insn_before (SIM_CPU *cpu, int first_p)
 778 {
 779   /* Do nothing.  */
 780 }
 781
 782 /* Record the cycles computed for an insn.
 783    LAST_P is non-zero if this is the last insn in a set of parallel insns,
 784    and we update the total cycle count.
 785    CYCLES is the cycle count of the insn.  */
 786
 787 void
 788 sh64_compact_model_insn_after(SIM_CPU *cpu, int last_p, int cycles)
 789 {
 790   /* Do nothing.  */
 791 }
 792
 793 void
 794 sh64_media_model_insn_after(SIM_CPU *cpu, int last_p, int cycles)
 795 {
 796   /* Do nothing.  */
 797 }
 798
 799 int
 800 sh64_fetch_register (SIM_CPU *cpu, int nr, unsigned char *buf, int len)
 801 {
 802   /* Fetch general purpose registers. */
 803   if (nr >= SIM_SH64_R0_REGNUM
 804       && nr < (SIM_SH64_R0_REGNUM + SIM_SH64_NR_R_REGS)
 805       && len == 8)
 806     {
 807       *((unsigned64*) buf) =
 808         H2T_8 (sh64_h_gr_get (cpu, nr - SIM_SH64_R0_REGNUM));
 809       return len;
 810     }
 811
 812   /* Fetch PC.  */
 813   if (nr == SIM_SH64_PC_REGNUM && len == 8)
 814     {
 815       *((unsigned64*) buf) = H2T_8 (sh64_h_pc_get (cpu) | sh64_h_ism_get (cpu));
 816       return len;
 817     }
 818
 819   /* Fetch status register (SR).  */
 820   if (nr == SIM_SH64_SR_REGNUM && len == 8)
 821     {
 822       *((unsigned64*) buf) = H2T_8 (sh64_h_sr_get (cpu));
 823       return len;
 824     }
 825
 826   /* Fetch saved status register (SSR) and PC (SPC).  */
 827   if ((nr == SIM_SH64_SSR_REGNUM || nr == SIM_SH64_SPC_REGNUM)
 828       && len == 8)
 829     {
 830       *((unsigned64*) buf) = 0;
 831       return len;
 832     }
 833
 834   /* Fetch target registers.  */
 835   if (nr >= SIM_SH64_TR0_REGNUM
 836       && nr < (SIM_SH64_TR0_REGNUM + SIM_SH64_NR_TR_REGS)
 837       && len == 8)
 838     {
 839       *((unsigned64*) buf) =
 840         H2T_8 (sh64_h_tr_get (cpu, nr - SIM_SH64_TR0_REGNUM));
 841       return len;
 842     }
 843
 844   /* Fetch floating point registers.  */
 845   if (nr >= SIM_SH64_FR0_REGNUM
 846       && nr < (SIM_SH64_FR0_REGNUM + SIM_SH64_NR_FP_REGS)
 847       && len == 4)
 848     {
 849       *((unsigned32*) buf) =
 850         H2T_4 (sh64_h_fr_get (cpu, nr - SIM_SH64_FR0_REGNUM));
 851       return len;
 852     }
 853
 854   /* We should never get here.  */
 855   return 0;
 856 }
 857
 858 int
 859 sh64_store_register (SIM_CPU *cpu, int nr, unsigned char *buf, int len)
 860 {
 861   /* Store general purpose registers. */
 862   if (nr >= SIM_SH64_R0_REGNUM
 863       && nr < (SIM_SH64_R0_REGNUM + SIM_SH64_NR_R_REGS)
 864       && len == 8)
 865     {
 866       sh64_h_gr_set (cpu, nr - SIM_SH64_R0_REGNUM, T2H_8 (*((unsigned64*)buf)));
 867       return len;
 868     }
 869
 870   /* Store PC.  */
 871   if (nr == SIM_SH64_PC_REGNUM && len == 8)
 872     {
 873       unsigned64 new_pc = T2H_8 (*((unsigned64*)buf));
 874       sh64_h_pc_set (cpu, new_pc);
 875       return len;
 876     }
 877
 878   /* Store status register (SR).  */
 879   if (nr == SIM_SH64_SR_REGNUM && len == 8)
 880     {
 881       sh64_h_sr_set (cpu, T2H_8 (*((unsigned64*)buf)));
 882       return len;
 883     }
 884
 885   /* Store saved status register (SSR) and PC (SPC).  */
 886   if (nr == SIM_SH64_SSR_REGNUM || nr == SIM_SH64_SPC_REGNUM)
 887     {
 888       /* Do nothing.  */
 889       return len;
 890     }
 891
 892   /* Store target registers.  */
 893   if (nr >= SIM_SH64_TR0_REGNUM
 894       && nr < (SIM_SH64_TR0_REGNUM + SIM_SH64_NR_TR_REGS)
 895       && len == 8)
 896     {
 897       sh64_h_tr_set (cpu, nr - SIM_SH64_TR0_REGNUM, T2H_8 (*((unsigned64*)buf)));
 898       return len;
 899     }
 900
 901   /* Store floating point registers.  */
 902   if (nr >= SIM_SH64_FR0_REGNUM
 903       && nr < (SIM_SH64_FR0_REGNUM + SIM_SH64_NR_FP_REGS)
 904       && len == 4)
 905     {
 906       sh64_h_fr_set (cpu, nr - SIM_SH64_FR0_REGNUM, T2H_4 (*((unsigned32*)buf)));
 907       return len;
 908     }
 909
 910   /* We should never get here.  */
 911   return 0;
 912 }
 913
 914 void
 915 sh64_engine_run_full(SIM_CPU *cpu)
 916 {
 917   if (sh64_h_ism_get (cpu) == ISM_MEDIA)
 918     {
 919       if (!sh64_idesc_media)
 920         {
 921           sh64_media_init_idesc_table (cpu);
 922           sh64_idesc_media = CPU_IDESC (cpu);
 923         }
 924       else
 925         CPU_IDESC (cpu) = sh64_idesc_media;
 926       sh64_media_engine_run_full (cpu);
 927     }
 928   else
 929     {
 930       if (!sh64_idesc_compact)
 931         {
 932           sh64_compact_init_idesc_table (cpu);
 933           sh64_idesc_compact = CPU_IDESC (cpu);
 934         }
 935       else
 936         CPU_IDESC (cpu) = sh64_idesc_compact;
 937       sh64_compact_engine_run_full (cpu);
 938     }
 939 }
 940
 941 void
 942 sh64_engine_run_fast (SIM_CPU *cpu)
 943 {
 944   if (sh64_h_ism_get (cpu) == ISM_MEDIA)
 945     {
 946       if (!sh64_idesc_media)
 947         {
 948           sh64_media_init_idesc_table (cpu);
 949           sh64_idesc_media = CPU_IDESC (cpu);
 950         }
 951       else
 952         CPU_IDESC (cpu) = sh64_idesc_media;
 953       sh64_media_engine_run_fast (cpu);
 954     }
 955   else
 956     {
 957       if (!sh64_idesc_compact)
 958         {
 959           sh64_compact_init_idesc_table (cpu);
 960           sh64_idesc_compact = CPU_IDESC (cpu);
 961         }
 962       else
 963         CPU_IDESC (cpu) = sh64_idesc_compact;
 964       sh64_compact_engine_run_fast (cpu);
 965     }
 966 }
 967
 968 static void
 969 sh64_prepare_run (SIM_CPU *cpu)
 970 {
 971   /* Nothing.  */
 972 }
 973
 974 static const CGEN_INSN *
 975 sh64_get_idata (SIM_CPU *cpu, int inum)
 976 {
 977   return CPU_IDESC (cpu) [inum].idata;
 978 }
 979
 980 static void
 981 sh64_init_cpu (SIM_CPU *cpu)
 982 {
 983   CPU_REG_FETCH (cpu) = sh64_fetch_register;
 984   CPU_REG_STORE (cpu) = sh64_store_register;
 985   CPU_PC_FETCH (cpu) = sh64_h_pc_get;
 986   CPU_PC_STORE (cpu) = sh64_h_pc_set;
 987   CPU_GET_IDATA (cpu) = sh64_get_idata;
 988   /* Only used by profiling.  0 disables it. */
 989   CPU_MAX_INSNS (cpu) = 0;
 990   CPU_INSN_NAME (cpu) = cgen_insn_name;
 991   CPU_FULL_ENGINE_FN (cpu) = sh64_engine_run_full;
 992 #if WITH_FAST
 993   CPU_FAST_ENGINE_FN (cpu) = sh64_engine_run_fast;
 994 #else
 995   CPU_FAST_ENGINE_FN (cpu) = sh64_engine_run_full;
 996 #endif
 997 }
 998
 999 static void
1000 shmedia_init_cpu (SIM_CPU *cpu)
1001 {
1002   sh64_init_cpu (cpu);
1003 }
1004
1005 static void
1006 shcompact_init_cpu (SIM_CPU *cpu)
1007 {
1008   sh64_init_cpu (cpu);
1009 }
1010
1011 static void
1012 sh64_model_init()
1013 {
1014   /* Do nothing.  */
1015 }
1016
1017 static const SIM_MODEL sh_models [] =
1018 {
1019   { "sh2",        & sh2_mach,         MODEL_SH5, NULL, sh64_model_init },
1020   { "sh2e",       & sh2e_mach,        MODEL_SH5, NULL, sh64_model_init },
1021   { "sh2a",       & sh2a_fpu_mach,    MODEL_SH5, NULL, sh64_model_init },
1022   { "sh2a_nofpu", & sh2a_nofpu_mach,  MODEL_SH5, NULL, sh64_model_init },
1023   { "sh3",        & sh3_mach,         MODEL_SH5, NULL, sh64_model_init },
1024   { "sh3e",       & sh3_mach,         MODEL_SH5, NULL, sh64_model_init },
1025   { "sh4",        & sh4_mach,         MODEL_SH5, NULL, sh64_model_init },
1026   { "sh4_nofpu",  & sh4_nofpu_mach,   MODEL_SH5, NULL, sh64_model_init },
1027   { "sh4a",       & sh4a_mach,        MODEL_SH5, NULL, sh64_model_init },
1028   { "sh4a_nofpu", & sh4a_nofpu_mach,  MODEL_SH5, NULL, sh64_model_init },
1029   { "sh4al",      & sh4al_mach,       MODEL_SH5, NULL, sh64_model_init },
1030   { "sh5",        & sh5_mach,         MODEL_SH5, NULL, sh64_model_init },
1031   { 0 }
1032 };
1033
1034 static const SIM_MACH_IMP_PROPERTIES sh5_imp_properties =
1035 {
1036   sizeof (SIM_CPU),
1037 #if WITH_SCACHE
1038   sizeof (SCACHE)
1039 #else
1040   0
1041 #endif
1042 };
1043
1044 const SIM_MACH sh2_mach =
1045 {
1046   "sh2", "sh2", MACH_SH5,
1047   16, 16, &sh_models[0], &sh5_imp_properties,
1048   shcompact_init_cpu,
1049   sh64_prepare_run
1050 };
1051
1052 const SIM_MACH sh2e_mach =
1053 {
1054   "sh2e", "sh2e", MACH_SH5,
1055   16, 16, &sh_models[1], &sh5_imp_properties,
1056   shcompact_init_cpu,
1057   sh64_prepare_run
1058 };
1059
1060 const SIM_MACH sh2a_fpu_mach =
1061 {
1062   "sh2a", "sh2a", MACH_SH5,
1063   16, 16, &sh_models[2], &sh5_imp_properties,
1064   shcompact_init_cpu,
1065   sh64_prepare_run
1066 };
1067
1068 const SIM_MACH sh2a_nofpu_mach =
1069 {
1070   "sh2a_nofpu", "sh2a_nofpu", MACH_SH5,
1071   16, 16, &sh_models[3], &sh5_imp_properties,
1072   shcompact_init_cpu,
1073   sh64_prepare_run
1074 };
1075
1076 const SIM_MACH sh3_mach =
1077 {
1078   "sh3", "sh3", MACH_SH5,
1079   16, 16, &sh_models[4], &sh5_imp_properties,
1080   shcompact_init_cpu,
1081   sh64_prepare_run
1082 };
1083
1084 const SIM_MACH sh3e_mach =
1085 {
1086   "sh3e", "sh3e", MACH_SH5,
1087   16, 16, &sh_models[5], &sh5_imp_properties,
1088   shcompact_init_cpu,
1089   sh64_prepare_run
1090 };
1091
1092 const SIM_MACH sh4_mach =
1093 {
1094   "sh4", "sh4", MACH_SH5,
1095   16, 16, &sh_models[6], &sh5_imp_properties,
1096   shcompact_init_cpu,
1097   sh64_prepare_run
1098 };
1099
1100 const SIM_MACH sh4_nofpu_mach =
1101 {
1102   "sh4_nofpu", "sh4_nofpu", MACH_SH5,
1103   16, 16, &sh_models[7], &sh5_imp_properties,
1104   shcompact_init_cpu,
1105   sh64_prepare_run
1106 };
1107
1108 const SIM_MACH sh4a_mach =
1109 {
1110   "sh4a", "sh4a", MACH_SH5,
1111   16, 16, &sh_models[8], &sh5_imp_properties,
1112   shcompact_init_cpu,
1113   sh64_prepare_run
1114 };
1115
1116 const SIM_MACH sh4a_nofpu_mach =
1117 {
1118   "sh4a_nofpu", "sh4a_nofpu", MACH_SH5,
1119   16, 16, &sh_models[9], &sh5_imp_properties,
1120   shcompact_init_cpu,
1121   sh64_prepare_run
1122 };
1123
1124 const SIM_MACH sh4al_mach =
1125 {
1126   "sh4al", "sh4al", MACH_SH5,
1127   16, 16, &sh_models[10], &sh5_imp_properties,
1128   shcompact_init_cpu,
1129   sh64_prepare_run
1130 };
1131
1132 const SIM_MACH sh5_mach =
1133 {
1134   "sh5", "sh5", MACH_SH5,
1135   32, 32, &sh_models[11], &sh5_imp_properties,
1136   shmedia_init_cpu,
1137   sh64_prepare_run
1138 };