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[thirdparty/binutils-gdb.git] / sim / sparc / sim-main.h
1 /* Main header for sparc. */
2
3 #ifndef SIM_MAIN_H
4 #define SIM_MAIN_H
5
6 #define USING_SIM_BASE_H /* FIXME: quick hack */
7
8 /* FIXME: For now always provide sparc32 support. */
9 #define HAVE_SPARC32
10 #undef HAVE_SPARC64 /* FIXME:wip */
11
12 /* ??? May eventually want this model (and perhaps runtime) selectable. */
13 #define NWINDOWS 8
14
15 struct _sim_cpu; /* FIXME: should be in sim-basics.h */
16 typedef struct _sim_cpu SIM_CPU;
17
18 #include "symcat.h"
19 #include "sim-basics.h"
20 #include "cgen-types.h"
21 #include "cpu-opc.h"
22 #include "arch.h"
23
24 /* These must be defined before sim-base.h. */
25 typedef USI sim_cia;
26 typedef int SEMRES;
27
28 #define CIA_GET(cpu) CPU_PC_GET (cpu)
29 #define CIA_SET(cpu,val) CPU_PC_SET ((cpu), (val))
30
31 #define SIM_ENGINE_HALT_HOOK(sd, cpu, cia) \
32 do { \
33 if (cpu) /* null if ctrl-c */ \
34 sim_pc_set ((cpu), (cia)); \
35 } while (0)
36 #define SIM_ENGINE_RESTART_HOOK(sd, cpu, cia) \
37 do { \
38 sim_pc_set ((cpu), (cia)); \
39 } while (0)
40
41 #include "sim-base.h"
42 #include "cgen-sim.h"
43
44 #ifdef WANT_CPU
45 #include "cpu-sim.h"
46 #endif
47 #if defined (WANT_CPU_SPARC32)
48 #include "regs32.h"
49 #include "trap32.h"
50 #elif defined (WANT_CPU_SPARC64)
51 #include "regs64.h"
52 #include "trap64.h"
53 #endif
54 \f
55 /* The sim_cpu struct. */
56
57 struct _sim_cpu {
58 /* sim/common cpu base. */
59 sim_cpu_base base;
60
61 /* Static parts of cgen. */
62 CGEN_CPU cgen_cpu;
63
64 /* CPU specific parts go here.
65 Note that in files that don't need to access these pieces WANT_CPU_FOO
66 won't be defined and thus these parts won't appear. This is ok in the
67 sense that things work. It is a source of bugs though.
68 One has to of course be careful to not take the size of this
69 struct and no structure members accessed in non-cpu specific files can
70 go after here. Oh for a better language. */
71
72 #if defined (WANT_CPU_SPARC32)
73
74 /* Machine generated registers. */
75 SPARC32_CPU_DATA cpu_data;
76 #if 0
77 /* Working variables for generating profiling information. */
78 SPARC32_CPU_PROFILE cpu_profile;
79 #endif
80 /* Actual values of the window regs. */
81 SI win_regs[NWINDOWS][16];
82 /* g0-g7, normal and alternate
83 ??? handling the alternate regs still wip, need REAL_GREGS to dtrt. */
84 SI global_regs[2][8];
85 /* Working copies of integer regs, swapped in/out on each window change.
86 ??? Doing things this way means the .cpu file needn't mark these as
87 virtual. */
88 SI current_regs[32];
89
90 #elif defined (WANT_CPU_SPARC64)
91
92 /* Machine generated registers. */
93 SPARC64_CPU_DATA cpu_data;
94 #if 0
95 /* Working variables for generating profiling information. */
96 SPARC64_CPU_PROFILE cpu_profile;
97 #endif
98 /* Actual values of the window regs. */
99 DI win_regs[NWINDOWS][16];
100 /* g0-g7, normal and alternate */
101 DI global_regs[2][8];
102 /* Working copies of integer regs, swapped in/out on each window change.
103 ??? Doing things this way means .cpu file needn't mark these as
104 virtual. */
105 DI current_regs[32];
106
107 #endif
108 };
109
110 #define ARCH32_P(cpu) 1 /*FIXME*/
111 #define ARCH64_P(cpu) (! ARCH32_P (cpu))
112 \f
113 /* The sim_state struct. */
114
115 struct sim_state {
116 sim_cpu *cpu;
117 #define STATE_CPU(sd, n) (/*&*/ (sd)->cpu)
118
119 CGEN_STATE cgen_state;
120
121 sim_state_base base;
122 };
123 \f
124 /* Misc. */
125
126 /* Catch address exceptions. */
127 extern SIM_CORE_SIGNAL_FN sparc_core_signal;
128 #define SIM_CORE_SIGNAL(SD,CPU,CIA,MAP,NR_BYTES,ADDR,TRANSFER,ERROR) \
129 sparc_core_signal ((SD), (CPU), (CIA), (MAP), (NR_BYTES), (ADDR), \
130 (TRANSFER), (ERROR))
131
132 /* Default memory size. */
133 #define SPARC_DEFAULT_MEM_SIZE 0x800000 /* 8M */
134
135 #endif /* SIM_MAIN_H */