sim/testsuite/ChangeLog

   1 Fri Feb  5 12:41:11 1999  Doug Evans  <devans@canuck.cygnus.com>
   2
   3         * lib/sim-defs.exp (sim_run): Print simulator arguments log message.
   4
   5 1999-01-05  Doug Evans  <devans@casey.cygnus.com>
   6
   7         * lib/sim-defs.exp (run_sim_test): New arg all_machs.
   8         * sim/fr30/allinsn.exp: Update.
   9         * sim/fr30/misc.exp: Update.
  10         * sim/m32r/allinsn.exp: Update.
  11         * sim/m32r/misc.exp: Update.
  12
  13 Fri Dec 18 17:19:34 1998  Dave Brolley  <brolley@cygnus.com>
  14
  15         * sim/fr30/ldres.cgs: New testcase.
  16         * sim/fr30/copld.cgs: New testcase.
  17         * sim/fr30/copst.cgs: New testcase.
  18         * sim/fr30/copsv.cgs: New testcase.
  19         * sim/fr30/nop.cgs: New testcase.
  20         * sim/fr30/andccr.cgs: New testcase.
  21         * sim/fr30/orccr.cgs: New testcase.
  22         * sim/fr30/addsp.cgs: New testcase.
  23         * sim/fr30/stilm.cgs: New testcase.
  24         * sim/fr30/extsb.cgs: New testcase.
  25         * sim/fr30/extub.cgs: New testcase.
  26         * sim/fr30/extsh.cgs: New testcase.
  27         * sim/fr30/extuh.cgs: New testcase.
  28         * sim/fr30/enter.cgs: New testcase.
  29         * sim/fr30/leave.cgs: New testcase.
  30         * sim/fr30/xchb.cgs: New testcase.
  31         * sim/fr30/dmovb.cgs: New testcase.
  32         * sim/fr30/dmov.cgs: New testcase.
  33         * sim/fr30/dmovh.cgs: New testcase.
  34
  35 Thu Dec 17 17:18:43 1998  Dave Brolley  <brolley@cygnus.com>
  36
  37         * sim/fr30/testutils.inc (take_branch{_d},no_branch{_d}): New macros.
  38         * sim/fr30/ret.cgs: Add tests fir ret:d.
  39         * sim/fr30/inte.cgs: New testcase.
  40         * sim/fr30/reti.cgs: New testcase.
  41         * sim/fr30/bra.cgs: New testcase.
  42         * sim/fr30/bno.cgs: New testcase.
  43         * sim/fr30/beq.cgs: New testcase.
  44         * sim/fr30/bne.cgs: New testcase.
  45         * sim/fr30/bc.cgs: New testcase.
  46         * sim/fr30/bnc.cgs: New testcase.
  47         * sim/fr30/bn.cgs: New testcase.
  48         * sim/fr30/bp.cgs: New testcase.
  49         * sim/fr30/bv.cgs: New testcase.
  50         * sim/fr30/bnv.cgs: New testcase.
  51         * sim/fr30/blt.cgs: New testcase.
  52         * sim/fr30/bge.cgs: New testcase.
  53         * sim/fr30/ble.cgs: New testcase.
  54         * sim/fr30/bgt.cgs: New testcase.
  55         * sim/fr30/bls.cgs: New testcase.
  56         * sim/fr30/bhi.cgs: New testcase.
  57
  58 Tue Dec 15 17:47:13 1998  Dave Brolley  <brolley@cygnus.com>
  59
  60         * sim/fr30/div.cgs (int): Add signed division scenario.
  61         * sim/fr30/int.cgs (int): Complete testcase.
  62         * sim/fr30/testutils.inc (_start): Initialize tbr.
  63         (test_s_user,test_s_system,set_i,test_i): New macros.
  64
  65 1998-12-14  Doug Evans  <devans@casey.cygnus.com>
  66
  67         * lib/sim-defs.exp (run_sim_test): New option xerror, for expected
  68         errors.  Translate \n sequences in expected output to newline char.
  69         (slurp_options): Make parentheses optional.
  70         (sim_run): Look for board_info sim,options.
  71         * sim/fr30/hello.ms: Add trailing \n to expected output.
  72         * sim/m32r/hello.ms: Ditto.
  73         * sim/m32r/hw-trap.ms: Ditto.
  74
  75         * sim/m32r/trap.cgs: Properly align trap2_handler.
  76
  77         * sim/m32r/uread16.ms: New testcase.
  78         * sim/m32r/uread32.ms: New testcase.
  79         * sim/m32r/uwrite16.ms: New testcase.
  80         * sim/m32r/uwrite32.ms: New testcase.
  81
  82 1998-12-14  Dave Brolley  <brolley@cygnus.com>
  83
  84         * sim/fr30/call.cgs: Test ret here as well.
  85         * sim/fr30/ld.cgs: Remove bogus comment.
  86         * sim/fr30/testutils.inc (save_rp,restore_rp): New macros.
  87         * sim/fr30/div.ms: New testcase.
  88         * sim/fr30/st.cgs: New testcase.
  89         * sim/fr30/sth.cgs: New testcase.
  90         * sim/fr30/stb.cgs: New testcase.
  91         * sim/fr30/mov.cgs: New testcase.
  92         * sim/fr30/jmp.cgs: New testcase.
  93         * sim/fr30/ret.cgs: New testcase.
  94         * sim/fr30/int.cgs: New testcase.
  95
  96 Thu Dec 10 18:46:25 1998  Dave Brolley  <brolley@cygnus.com>
  97
  98         * sim/fr30/div0s.cgs: New testcase.
  99         * sim/fr30/div0u.cgs: New testcase.
 100         * sim/fr30/div1.cgs: New testcase.
 101         * sim/fr30/div2.cgs: New testcase.
 102         * sim/fr30/div3.cgs: New testcase.
 103         * sim/fr30/div4s.cgs: New testcase.
 104         * sim/fr30/testutils.inc (mvi_h_dr,set_dbits,test_dbits): New Macros.
 105
 106 Tue Dec  8 13:16:53 1998  Dave Brolley  <brolley@cygnus.com>
 107
 108         * sim/fr30/testutils.inc (set_s_user): Correct Mask.
 109         (set_s_system): Correct Mask.
 110         * sim/fr30/ld.cgs (ld): Move previously failing test back
 111         into place.
 112         * sim/fr30/ldm0.cgs: New testcase.
 113         * sim/fr30/ldm1.cgs: New testcase.
 114         * sim/fr30/stm0.cgs: New testcase.
 115         * sim/fr30/stm1.cgs: New testcase.
 116
 117 Thu Dec  3 14:20:03 1998  Dave Brolley  <brolley@cygnus.com>
 118
 119         * sim/fr30/ld.cgs: Implement more loads.
 120         * sim/fr30/call.cgs: New testcase.
 121         * sim/fr30/testutils.inc (testr_h_dr): New macro.
 122         (set_s_user,set_s_system): New macros.
 123
 124         * sim/fr30: New Directory.
 125
 126 Wed Nov 18 10:50:19 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 127
 128         * common/bits-gen.c (main): Add BYTE_ORDER so that it matches
 129         recent sim/common/sim-basics.h changes.
 130         * common/Makefile.in: Update.
 131
 132 Fri Oct 30 00:37:31 1998  Felix Lee  <flee@cygnus.com>
 133
 134         * lib/sim-defs.exp (sim_run): download target program to remote
 135         host, if necessary.  for unix-driven win32 testing.
 136
 137 Tue Sep 15 14:56:22 1998  Doug Evans  <devans@canuck.cygnus.com>
 138
 139         * sim/m32r/testutils.inc (test_h_gr): Use mvaddr_h_gr.
 140         * sim/m32r/rte.cgs: Test bbpc,bbpsw.
 141         * sim/m32r/trap.cgs: Test bbpc,bbpsw.
 142
 143 Fri Jul 24 09:40:34 1998  Doug Evans  <devans@canuck.cygnus.com>
 144
 145         * Makefile.in (clean,mostlyclean): Change leading spaces to a tab.
 146
 147 Wed Jul  1 15:57:54 1998  Doug Evans  <devans@seba.cygnus.com>
 148
 149         * sim/m32r/hw-trap.ms: New testcase.
 150
 151 Wed Jun 10 10:53:20 1998  Doug Evans  <devans@seba.cygnus.com>
 152
 153         * sim/m32r/addx.cgs: Add another test.
 154         * sim/m32r/jmp.cgs: Add another test.
 155
 156 Mon Jun  8 16:08:27 1998  Doug Evans  <devans@canuck.cygnus.com>
 157
 158         * sim/m32r/trap.cgs: Test trap 2.
 159
 160 Mon Jun  1 18:54:22 1998  Frank Ch. Eigler  <fche@cygnus.com>
 161
 162         * lib/sim-defs.exp (sim_run): Add possible environment variable
 163         list to simulator run.
 164
 165 Thu May 28 14:59:46 1998 Jillian Ye <jillian@cygnus.com>
 166
 167         * Makefile.in: Take RUNTEST out of FLAG_TO_PASS
 168                        so that make check can be invoked recursively.
 169
 170 Thu May 14 11:48:35 1998  Doug Evans  <devans@canuck.cygnus.com>
 171
 172         * config/default.exp (CC,SIM): Delete.
 173
 174         * lib/sim-defs.exp (sim_run): Fix handling of output redirection.
 175         New arg prog_opts.  All callers updated.
 176
 177 Fri May  8 18:10:28 1998  Jillian Ye <jillian@cygnus.com>
 178
 179         * Makefile.in: Made "check" the target of two
 180           dependencies (test1, test2) so that test2 get a chance to
 181           run even when test1 failed if "make -k check" is used.
 182
 183 Fri May  8 14:41:28 1998  Doug Evans  <devans@canuck.cygnus.com>
 184
 185         * lib/sim-defs.exp (sim_version): Simplify.
 186         (sim_run): Implement.
 187         (run_sim_test): Use sim_run.
 188         (sim_compile): New proc.
 189
 190 Mon May  4 17:59:11 1998  Frank Ch. Eigler  <fche@cygnus.com>
 191
 192         * config/default.exp: Added C compiler settings.
 193
 194 Wed Apr 22 12:26:28 1998  Doug Evans  <devans@canuck.cygnus.com>
 195
 196         * Makefile.in (TARGET_FLAGS_TO_PASS): Delete LIBS, LDFLAGS.
 197
 198 Tue Apr 21 10:49:03 1998  Doug Evans  <devans@canuck.cygnus.com>
 199
 200         * lib/sim-defs.exp (run_sim_test): Don't exit early if one mach fails,
 201         try all machs.
 202
 203         * sim/m32r/addx.cgs: Test (-1)+(-1)+1.
 204
 205 Fri Apr 17 16:00:52 1998  Doug Evans  <devans@canuck.cygnus.com>
 206
 207         * sim/m32r/mv[ft]achi.cgs: Fix expected result
 208         (sign extension of top 8 bits).
 209
 210 Wed Feb 25 11:01:17 1998  Doug Evans  <devans@canuck.cygnus.com>
 211
 212         * Makefile.in (RUNTEST): Fix path to runtest.
 213
 214
 215 Fri Feb 20 11:00:02 1998  Nick Clifton  <nickc@cygnus.com>
 216
 217         * sim/m32r/unlock.cgs: Fixed test.
 218         * sim/m32r/mvfc.cgs: Fixed test.
 219         * sim/m32r/remu.cgs: Fixed test.
 220
 221         * sim/m32r/bnc24.cgs: Test long BNC instruction.
 222         * sim/m32r/bnc8.cgs: Test short BNC instruction.
 223         * sim/m32r/ld-plus.cgs: Test LD instruction.
 224         * sim/m32r/macwhi.cgs: Test MACWHI instruction.
 225         * sim/m32r/macwlo.cgs: Test MACWLO instruction.
 226         * sim/m32r/mulwhi.cgs: Test MULWHI instruction.
 227         * sim/m32r/mulwlo.cgs: Test MULWLO instruction.
 228         * sim/m32r/mvfachi.cgs: Test MVFACHI instruction.
 229         * sim/m32r/mvfaclo.cgs: Test MVFACLO instruction.
 230         * sim/m32r/mvtaclo.cgs: Test MVTACLO instruction.
 231         * sim/m32r/addv.cgs: Test ADDV instruction.
 232         * sim/m32r/addv3.cgs: Test ADDV3 instruction.
 233         * sim/m32r/addx.cgs: Test ADDX instruction.
 234         * sim/m32r/lock.cgs: Test LOCK instruction.
 235         * sim/m32r/neg.cgs: Test NEG instruction.
 236         * sim/m32r/not.cgs: Test NOT instruction.
 237         * sim/m32r/unlock.cgs: Test UNLOCK instruction.
 238 Thu Feb 19 11:15:45 1998  Nick Clifton  <nickc@cygnus.com>
 239
 240         * sim/m32r/testutils.inc (mvaddr_h_gr): new macro to load an
 241         address into a general register.
 242
 243         * sim/m32r/or3.cgs: Test OR3 instruction.
 244         * sim/m32r/rach.cgs: Test RACH instruction.
 245         * sim/m32r/rem.cgs: Test REM instruction.
 246         * sim/m32r/sub.cgs: Test SUB instruction.
 247         * sim/m32r/mv.cgs: Test MV instruction.
 248         * sim/m32r/mul.cgs: Test MUL instruction.
 249         * sim/m32r/bl24.cgs: Test long BL instruction.
 250         * sim/m32r/bl8.cgs: Test short BL instruction.
 251         * sim/m32r/blez.cgs: Test BLEZ instruction.
 252         * sim/m32r/bltz.cgs: Test BLTZ instruction.
 253         * sim/m32r/bne.cgs: Test BNE instruction.
 254         * sim/m32r/bnez.cgs: Test BNEZ instruction.
 255         * sim/m32r/bra24.cgs: Test long BRA instruction.
 256         * sim/m32r/bra8.cgs: Test short BRA instruction.
 257         * sim/m32r/jl.cgs: Test JL instruction.
 258         * sim/m32r/or.cgs: Test OR instruction.
 259         * sim/m32r/jmp.cgs: Test JMP instruction.
 260         * sim/m32r/and.cgs: Test AND instruction.
 261         * sim/m32r/and3.cgs: Test AND3 instruction.
 262         * sim/m32r/beq.cgs: Test BEQ instruction.
 263         * sim/m32r/beqz.cgs: Test BEQZ instruction.
 264         * sim/m32r/bgez.cgs: Test BGEZ instruction.
 265         * sim/m32r/bgtz.cgs: Test BGTZ instruction.
 266         * sim/m32r/cmp.cgs: Test CMP instruction.
 267         * sim/m32r/cmpi.cgs: Test CMPI instruction.
 268         * sim/m32r/cmpu.cgs: Test CMPU instruction.
 269         * sim/m32r/cmpui.cgs: Test CMPUI instruction.
 270         * sim/m32r/div.cgs: Test DIV instruction.
 271         * sim/m32r/divu.cgs: Test DIVU instruction.
 272         * sim/m32r/cmpeq.cgs: Test CMPEQ instruction.
 273         * sim/m32r/sll.cgs: Test SLL instruction.
 274         * sim/m32r/sll3.cgs: Test SLL3 instruction.
 275         * sim/m32r/slli.cgs: Test SLLI instruction.
 276         * sim/m32r/sra.cgs: Test SRA instruction.
 277         * sim/m32r/sra3.cgs: Test SRA3 instruction.
 278         * sim/m32r/srai.cgs: Test SRAI instruction.
 279         * sim/m32r/srl.cgs: Test SRL instruction.
 280         * sim/m32r/srl3.cgs: Test SRL3 instruction.
 281         * sim/m32r/srli.cgs: Test SRLI instruction.
 282         * sim/m32r/xor3.cgs: Test XOR3 instruction.
 283         * sim/m32r/xor.cgs: Test XOR instruction.
 284 Tue Feb 17 12:46:05 1998  Doug Evans  <devans@seba.cygnus.com>
 285
 286         * config/default.exp: New file.
 287         * lib/sim-defs.exp: New file.
 288         * sim/m32r/*: m32r dejagnu simulator testsuite.
 289
 290         * Makefile.in (build_alias): Define.
 291         (arch): Define.
 292         (RUNTEST_FOR_TARGET): Delete.
 293         (RUNTEST): Fix.
 294         (check): Depend on site.exp.  Run dejagnu.
 295         (site.exp): New target.
 296         * configure.in (arch): Define from target_cpu.
 297         * configure: Regenerate.
 298
 299 Wed Sep 17 10:21:26 1997  Andrew Cagney  <cagney@b1.cygnus.com>
 300
 301         * common/bits-gen.c (gen_bit): Pass in the full name of the macro.
 302         (gen_mask): Ditto.
 303
 304         * common/bits-tst.c (main): Add tests for LSSEXT, MSSEXT.
 305         (calc): Add support for 8 bit version of macros.
 306         (main): Add tests for 8 bit versions of macros.
 307         (check_sext): Check SEXT of zero clears bits.
 308
 309         * common/bits-gen.c (main): Generate tests for 8 bit versions of
 310         macros.
 311
 312 Thu Sep 11 13:04:40 1997  Andrew Cagney  <cagney@b1.cygnus.com>
 313
 314         * common/Make-common.in: New file, provide generic rules for
 315         running checks.
 316
 317 Mon Sep  1 16:43:55 1997  Andrew Cagney  <cagney@b1.cygnus.com>
 318
 319         * configure.in (configdirs): Test for the target directory instead
 320         of matching on a target.
 321