sim/testsuite/sim/fr30/div1.cgs

   1 # fr30 testcase for div1 $Ri
   2 # mach(): fr30
   3
   4         .include "testutils.inc"
   5
   6         START
   7
   8         .text
   9         .global div1
  10 div1:
  11         ; Test div1 $Ri
  12         ; example from the manual -- all status bits 0
  13         mvi_h_gr        0x00ffffff,r2
  14         mvi_h_dr        0x00ffffff,mdh
  15         mvi_h_dr        0x00000000,mdl
  16         set_dbits       0x0
  17         set_cc          0x00
  18         div1            r2
  19         test_cc         0 0 0 0
  20         test_dbits      0x0
  21         test_h_gr       0x00ffffff,r2
  22         test_h_dr       0x00ffffff,mdh  ; misprinted in manual?
  23         test_h_dr       0x00000001,mdl
  24
  25         ; D0 == 1
  26         set_dbits       0x1
  27         set_cc          0x00
  28         div1            r2
  29         test_cc         0 0 0 0
  30         test_dbits      0x1
  31         test_h_gr       0x00ffffff,r2
  32         test_h_dr       0x01fffffe,mdh
  33         test_h_dr       0x00000002,mdl
  34
  35         ; D1 == 1
  36         set_dbits       0x2
  37         set_cc          0x00
  38         div1            r2
  39         test_cc         0 0 0 0
  40         test_dbits      0x2
  41         test_h_gr       0x00ffffff,r2
  42         test_h_dr       0x03fffffc,mdh
  43         test_h_dr       0x00000004,mdl
  44
  45         ; D0 == 1, D1 == 1
  46         set_dbits       0x3
  47         set_cc          0x00
  48         div1            r2
  49         test_cc         0 0 0 0
  50         test_dbits      0x3
  51         test_h_gr       0x00ffffff,r2
  52         test_h_dr       0x08fffff7,mdh
  53         test_h_dr       0x00000009,mdl
  54
  55         ; C == 1
  56         mvi_h_gr        0x11ffffef,r2
  57         set_dbits       0x0
  58         set_cc          0x00
  59         div1            r2
  60         test_cc         0 0 0 1
  61         test_dbits      0x0
  62         test_h_gr       0x11ffffef,r2
  63         test_h_dr       0x11ffffee,mdh
  64         test_h_dr       0x00000012,mdl
  65
  66         ; D0 == 1, C == 1
  67         mvi_h_gr        0x23ffffdd,r2
  68         set_dbits       0x1
  69         set_cc          0x00
  70         div1            r2
  71         test_cc         0 0 0 1
  72         test_dbits      0x1
  73         test_h_gr       0x23ffffdd,r2
  74         test_h_dr       0xffffffff,mdh
  75         test_h_dr       0x00000025,mdl
  76
  77         ; D1 == 1, C == 1
  78         mvi_h_gr        0x00000003,r2
  79         set_dbits       0x2
  80         set_cc          0x00
  81         div1            r2
  82         test_cc         0 0 0 1
  83         test_dbits      0x2
  84         test_h_gr       0x00000003,r2
  85         test_h_dr       0x00000001,mdh
  86         test_h_dr       0x0000004b,mdl
  87
  88         ; D0 == 1, D1 == 1, C == 1
  89         mvi_h_gr        0xfffffffe,r2
  90         set_dbits       0x3
  91         set_cc          0x00
  92         div1            r2
  93         test_cc         0 0 0 1
  94         test_dbits      0x3
  95         test_h_gr       0xfffffffe,r2
  96         test_h_dr       0x00000002,mdh
  97         test_h_dr       0x00000096,mdl
  98
  99         ; remainder is zero
 100         mvi_h_gr        0x00000004,r2
 101         set_dbits       0x0
 102         set_cc          0x00
 103         div1            r2
 104         test_cc         0 1 0 0
 105         test_dbits      0x0
 106         test_h_gr       0x00000004,r2
 107         test_h_dr       0x00000000,mdh
 108         test_h_dr       0x0000012d,mdl
 109
 110         pass
 111
 112
 113