sim/testsuite/sim/fr30/eor.cgs

   1 # fr30 testcase for eor $Rj,$Ri, eor $Rj,@$Ri
   2 # mach(): fr30
   3
   4         .include "testutils.inc"
   5
   6         START
   7
   8         .text
   9         .global eor
  10 eor:
  11         ; Test eor $Rj,$Ri
  12         mvi_h_gr        0xaaaaaaaa,r7
  13         mvi_h_gr        0x55555555,r8
  14         set_cc          0x07            ; Set mask opposite of expected
  15         eor             r7,r8
  16         test_cc         1 0 1 1
  17         test_h_gr       0xffffffff,r8
  18
  19         mvi_h_gr        0x00000000,r7
  20         mvi_h_gr        0x00000000,r8
  21         set_cc          0x08            ; Set mask opposite of expected
  22         eor             r7,r8
  23         test_cc         0 1 0 0
  24         test_h_gr       0x00000000,r8
  25
  26         mvi_h_gr        0xaaaaaaaa,r7
  27         mvi_h_gr        0xaaaaaaaa,r8
  28         set_cc          0x0b            ; Set mask opposite of expected
  29         eor             r7,r8
  30         test_cc         0 1 1 1
  31         test_h_gr       0x00000000,r8
  32
  33         mvi_h_gr        0xdead0000,r7
  34         mvi_h_gr        0x0000beef,r8
  35         set_cc          0x05            ; Set mask opposite of expected
  36         eor             r7,r8
  37         test_cc         1 0 0 1
  38         test_h_gr       0xdeadbeef,r8
  39
  40         ; Test eor $Rj,@$Ri
  41         mvi_h_gr        0xaaaaaaaa,r7
  42         mvi_h_mem       0x55555555,sp
  43         set_cc          0x07            ; Set mask opposite of expected
  44         eor             r7,@sp
  45         test_cc         1 0 1 1
  46         test_h_mem      0xffffffff,sp
  47
  48         mvi_h_gr        0x00000000,r7
  49         mvi_h_mem       0x00000000,sp
  50         set_cc          0x08            ; Set mask opposite of expected
  51         eor             r7,@sp
  52         test_cc         0 1 0 0
  53         test_h_mem      0x00000000,sp
  54
  55         mvi_h_gr        0xaaaaaaaa,r7
  56         mvi_h_mem       0xaaaaaaaa,sp
  57         set_cc          0x0b            ; Set mask opposite of expected
  58         eor             r7,@sp
  59         test_cc         0 1 1 1
  60         test_h_mem      0x00000000,sp
  61
  62         mvi_h_gr        0xdead0000,r7
  63         mvi_h_mem       0x0000beef,sp
  64         set_cc          0x05            ; Set mask opposite of expected
  65         eor             r7,@sp
  66         test_cc         1 0 0 1
  67         test_h_mem      0xdeadbeef,sp
  68
  69         pass