sim/testsuite/sim/fr30/muluh.cgs

   1 # fr30 testcase for muluh $Rj,$Ri
   2 # mach(): fr30
   3
   4         .include "testutils.inc"
   5
   6         START
   7
   8         .text
   9         .global muluh
  10 muluh:
  11         ; Test muluh $Rj,$Ri
  12         ; Positive operands
  13         mvi_h_gr        0xdead0003,r7           ; multiply small numbers
  14         mvi_h_gr        0xbeef0002,r8
  15         set_cc          0x09            ; Set mask opposite of expected
  16         muluh           r7,r8
  17         test_cc         0 1 0 1
  18         test_h_dr       6,mdl
  19
  20         mvi_h_gr        0xdead0001,r7           ; multiply by 1
  21         mvi_h_gr        0xbeef0002,r8
  22         set_cc          0x08            ; Set mask opposite of expected
  23         muluh           r7,r8
  24         test_cc         0 1 0 0
  25         test_h_dr       2,mdl
  26
  27         mvi_h_gr        0xdead0002,r7           ; multiply by 1
  28         mvi_h_gr        0xbeef0001,r8
  29         set_cc          0x09            ; Set mask opposite of expected
  30         muluh           r7,r8
  31         test_cc         0 1 0 1
  32         test_h_dr       2,mdl
  33
  34         mvi_h_gr        0xdead0000,r7           ; multiply by 0
  35         mvi_h_gr        0xbeef0002,r8
  36         set_cc          0x09            ; Set mask opposite of expected
  37         muluh           r7,r8
  38         test_cc         0 1 0 1
  39         test_h_dr       0,mdl
  40
  41         mvi_h_gr        0xdead0002,r7           ; multiply by 0
  42         mvi_h_gr        0xbeef0000,r8
  43         set_cc          0x08            ; Set mask opposite of expected
  44         muluh           r7,r8
  45         test_cc         0 1 0 0
  46         test_h_dr       0,mdl
  47
  48         mvi_h_gr        0xdead3fff,r7   ; 15 bit result
  49         mvi_h_gr        0xbeef0002,r8
  50         set_cc          0x09            ; Set mask opposite of expected
  51         muluh           r7,r8
  52         test_cc         0 1 0 1
  53         test_h_dr       0x00007ffe,mdl
  54
  55         mvi_h_gr        0xdead4000,r7   ; 16 bit result
  56         mvi_h_gr        0xbeef0002,r8
  57         set_cc          0x08            ; Set mask opposite of expected
  58         muluh           r7,r8
  59         test_cc         0 1 0 0
  60         test_h_dr       0x00008000,mdl
  61
  62         mvi_h_gr        0xdead8000,r7   ; 17 bit result
  63         mvi_h_gr        0xbeef0002,r8
  64         set_cc          0x0b            ; Set mask opposite of expected
  65         muluh           r7,r8
  66         test_cc         0 1 1 1
  67         test_h_dr       0x00010000,mdl
  68
  69         mvi_h_gr        0xdead7fff,r7   ; max positive result
  70         mvi_h_gr        0xbeef7fff,r8
  71         set_cc          0x0b            ; Set mask opposite of expected
  72         muluh           r7,r8
  73         test_cc         0 1 1 1
  74         test_h_dr       0x3fff0001,mdl
  75
  76         mvi_h_gr        0xdead8000,r7   ; max positive result
  77         mvi_h_gr        0xbeef8000,r8
  78         set_cc          0x0b            ; Set mask opposite of expected
  79         muluh           r7,r8
  80         test_cc         0 1 1 1
  81         test_h_dr       0x40000000,mdl
  82
  83         mvi_h_gr        0xdeadffff,r7   ; max positive result
  84         mvi_h_gr        0xbeefffff,r8
  85         set_cc          0x07            ; Set mask opposite of expected
  86         muluh           r7,r8
  87         test_cc         1 0 1 1
  88         test_h_dr       0xfffe0001,mdl
  89
  90         pass