sim/testsuite/sim/m32r/trap.cgs

   1 # m32r testcase for trap #$uimm4
   2 # mach(): m32r m32rx
   3
   4         .include "testutils.inc"
   5
   6         start
   7
   8         .global trap
   9 trap:
  10
  11 ; Test 1: bbpsw = 0, bpsw = 1, psw = 0
  12
  13         ; bbsm = 0, bie = 0, bbcond = 0
  14         mvi_h_gr r4, 0
  15         mvtc r4, cr8
  16
  17         ; bsm = 1, bie = 1, bcond = 1, sm = 0, ie = 0, cond = 0
  18         mvi_h_gr r4, 0xc100
  19         mvtc r4, cr0
  20
  21         ; bbpc = 0
  22         mvaddr_h_gr r4, 0
  23         mvtc r4, bbpc
  24
  25         ; bpc = 42
  26         mvaddr_h_gr r4, 42
  27         mvtc r4, bpc
  28
  29         ; Copy trap2_handler to trap area of memory.
  30         ld24 r0,#0x48 ; address of trap 2 handler
  31         ld24 r1,#trap2_handler
  32         ld r2,@r1
  33         st r2,@r0
  34         ; Set up return address.
  35         ld24 r5,#trap2_ret1
  36
  37 trap_insn1:
  38         trap #2
  39         fail
  40
  41 trap2_ret1:
  42         ; test bbsm = 1, bbie = 1, bbcond = 1
  43         mvfc r4, cr8
  44         test_h_gr r4, 0xc1
  45
  46         ; test bsm = 0, bie = 0, bcond = 0, sm = 0, ie = 0, cond = 0
  47         mvfc r4, cr0
  48         test_h_gr r4, 0
  49
  50         ; test bbpc = 42
  51         mvfc r4, bbpc
  52         test_h_gr r4, 42
  53
  54         ; test bpc = proper return address
  55         mvfc r4, bpc
  56         test_h_gr r4, trap_insn1 + 4
  57
  58 ; Test 2: bbpsw = 1, bpsw = 0, psw = 1
  59
  60         ; bbsm = 1, bie = 1, bbcond = 1
  61         mvi_h_gr r4, 0xc1
  62         mvtc r4, cr8
  63
  64         ; bsm = 0, bie = 0, bcond = 0, sm = 1, ie = 1, cond = 1
  65         mvi_h_gr r4, 0xc1
  66         mvtc r4, cr0
  67
  68         ; bbpc = 42
  69         mvaddr_h_gr r4, 42
  70         mvtc r4, bbpc
  71
  72         ; bpc = 0
  73         mvaddr_h_gr r4, 0
  74         mvtc r4, bpc
  75
  76         ; Set up return address.
  77         ld24 r5,#trap2_ret2
  78
  79 trap_insn2:
  80         trap #2
  81         fail
  82
  83 trap2_ret2:
  84         ; test bbsm = 0, bbie = 0, bbcond = 0
  85         mvfc r4, cr8
  86         test_h_gr r4, 0
  87
  88         ; test bsm = 1, bie = 1, bcond = 1, sm = 1, ie = 0, cond = 0
  89         mvfc r4, cr0
  90         test_h_gr r4, 0xc180
  91
  92         ; test bbpc = 0
  93         mvfc r4, bbpc
  94         test_h_gr r4, 0
  95
  96         ; test bpc = proper return address
  97         mvfc r4, bpc
  98         test_h_gr r4, trap_insn2 + 4
  99
 100         pass
 101
 102         .data
 103
 104 ; Don't use rte as it will undo the effects of trap we're testing.
 105
 106         .p2align 2
 107 trap2_handler:
 108         jmp r5
 109         nop