sim/testsuite/sim/or1k/basic.S

   1 /* Tests some basic CPU instructions.
   2
   3    Copyright (C) 2017-2020 Free Software Foundation, Inc.
   4
   5    This program is free software; you can redistribute it and/or modify
   6    it under the terms of the GNU General Public License as published by
   7    the Free Software Foundation; either version 3 of the License, or
   8    (at your option) any later version.
   9
  10    This program is distributed in the hope that it will be useful,
  11    but WITHOUT ANY WARRANTY; without even the implied warranty of
  12    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13    GNU General Public License for more details.
  14
  15    You should have received a copy of the GNU General Public License
  16    along with this program.  If not, see <http://www.gnu.org/licenses/>.  */
  17
  18 # mach: or1k
  19 # output: report(0xffff0012);\n
  20 # output: report(0x12352af7);\n
  21 # output: report(0x7ffffffe);\n
  22 # output: report(0xffffa5a7);\n
  23 # output: report(0x000fffff);\n
  24 # output: report(0x00002800);\n
  25 # output: report(0x00000009);\n
  26 # output: report(0xdeaddead);\n
  27 # output: report(0xffff0000);\n
  28 # output: report(0x12345678);\n
  29 # output: report(0xabcdf0bd);\n
  30 # output: exit(0)\n
  31
  32 #include "or1k-asm-test-env.h"
  33
  34 #define FIRST_RAM_ADDR 0x00000000
  35
  36         STANDARD_TEST_HEADER
  37
  38         /* Early test begin.  */
  39
  40         /* Do this test upfront, as it modifies STACK_POINTER_R1.  */
  41
  42         l.addi  r1 , r0 , 0x1
  43         l.addi  r2 , r1 , 0x2
  44         l.addi  r3 , r2 , 0x4
  45         l.addi  r4 , r3 , 0x8
  46         l.addi  r5 , r4 , 0x10
  47         l.addi  r6 , r5 , 0x20
  48         l.addi  r7 , r6 , 0x40
  49         l.addi  r8 , r7 , 0x80
  50         l.addi  r9 , r8 , 0x100
  51         l.addi  r10, r9 , 0x200
  52         l.addi  r11, r10, 0x400
  53         l.addi  r12, r11, 0x800
  54         l.addi  r13, r12, 0x1000
  55         l.addi  r14, r13, 0x2000
  56         l.addi  r15, r14, 0x4000
  57         l.addi  r16, r15, 0x8000
  58
  59         l.sub   r31, r0 , r1
  60         l.sub   r30, r31, r2
  61         l.sub   r29, r30, r3
  62         l.sub   r28, r29, r4
  63         l.sub   r27, r28, r5
  64         l.sub   r26, r27, r6
  65         l.sub   r25, r26, r7
  66         l.sub   r24, r25, r8
  67         l.sub   r23, r24, r9
  68         l.sub   r22, r23, r10
  69         l.sub   r21, r22, r11
  70         l.sub   r20, r21, r12
  71         l.sub   r19, r20, r13
  72         l.sub   r18, r19, r14
  73         l.sub   r17, r18, r15
  74         l.sub   r16, r17, r16
  75
  76         /* We cannot use REPORT_REG_TO_CONSOLE here, as the stack is not
  77            set up yet.  */
  78         MOVE_REG NOP_REPORT_R3, r16
  79         REPORT_TO_CONSOLE /* Should be 0xffff0012  */
  80
  81         /* Early test end.  */
  82
  83         STANDARD_TEST_BODY
  84
  85         .section .text
  86 start_tests:
  87         PUSH LINK_REGISTER_R9
  88
  89         /* Read and write from RAM.  */
  90
  91         LOAD_IMMEDIATE r31, FIRST_RAM_ADDR
  92         l.sw    0(r31), r16
  93
  94         l.movhi r3,0x1234
  95         l.ori   r3,r3,0x5678
  96
  97         l.sw    4(r31),r3
  98
  99         l.lbz   r4,4(r31)
 100         l.add   r8,r8,r4
 101         l.sb    11(r31),r4
 102         l.lbz   r4,5(r31)
 103         l.add   r8,r8,r4
 104         l.sb    10(r31),r4
 105         l.lbz   r4,6(r31)
 106         l.add   r8,r8,r4
 107         l.sb    9(r31),r4
 108         l.lbz   r4,7(r31)
 109         l.add   r8,r8,r4
 110         l.sb    8(r31),r4
 111
 112         l.lbs   r4,8(r31)
 113         l.add   r8,r8,r4
 114         l.sb    7(r31),r4
 115         l.lbs   r4,9(r31)
 116         l.add   r8,r8,r4
 117         l.sb    6(r31),r4
 118         l.lbs   r4,10(r31)
 119         l.add   r8,r8,r4
 120         l.sb    5(r31),r4
 121         l.lbs   r4,11(r31)
 122         l.add   r8,r8,r4
 123         l.sb    4(r31),r4
 124
 125         l.lhz   r4,4(r31)
 126         l.add   r8,r8,r4
 127         l.sh    10(r31),r4
 128         l.lhz   r4,6(r31)
 129         l.add   r8,r8,r4
 130         l.sh    8(r31),r4
 131
 132         l.lhs   r4,8(r31)
 133         l.add   r8,r8,r4
 134         l.sh    6(r31),r4
 135         l.lhs   r4,10(r31)
 136         l.add   r8,r8,r4
 137         l.sh    4(r31),r4
 138
 139         l.lwz   r4,4(r31)
 140         l.add   r8,r8,r4
 141
 142         REPORT_REG_TO_CONSOLE r8 /* Should be 0x12352af7  */
 143
 144         l.lwz   r9,0(r31)
 145         l.add   r8,r9,r8
 146         l.sw    0(r31),r8
 147
 148         /* Test arithmetic operations.  */
 149
 150         l.addi  r3,r0,1
 151         l.addi  r4,r0,2
 152         l.addi  r5,r0,-1
 153         l.addi  r6,r0,-1
 154         l.addi  r8,r0,0
 155
 156         l.sub   r7,r5,r3
 157         l.sub   r8,r3,r5
 158         l.add   r8,r8,r7
 159
 160         l.div   r7,r7,r4
 161         l.add   r9,r3,r4
 162         l.mul   r7,r9,r7
 163         l.divu  r7,r7,r4
 164         l.add   r8,r8,r7
 165
 166         REPORT_REG_TO_CONSOLE r8 /* Should be 0x7ffffffe  */
 167
 168         l.lwz   r9,0(r31)
 169         l.add   r8,r9,r8
 170         l.sw    0(r31),r8
 171
 172         /* Test logical operations.  */
 173
 174         l.addi  r3,r0,1
 175         l.addi  r4,r0,2
 176         l.addi  r5,r0,-1
 177         l.addi  r6,r0,-1
 178         l.addi  r8,r0,0
 179
 180         l.andi  r8,r8,1
 181         l.and   r8,r8,r3
 182
 183         l.xori  r8,r5,0xa5a5
 184         l.xor   r8,r8,r5
 185
 186         l.ori   r8,r8,2
 187         l.or    r8,r8,r4
 188
 189         REPORT_REG_TO_CONSOLE r8 /* Should be 0xffffa5a7  */
 190
 191         l.lwz   r9,0(r31)
 192         l.add   r8,r9,r8
 193         l.sw    0(r31),r8
 194
 195         /* Test shifting operations.  */
 196
 197         l.addi  r3,r0,1
 198         l.addi  r4,r0,2
 199         l.addi  r5,r0,-1
 200         l.addi  r6,r0,-1
 201         l.addi  r8,r0,0
 202
 203         l.slli  r8,r5,6
 204         l.sll   r8,r8,r4
 205
 206         l.srli  r8,r8,6
 207         l.srl   r8,r8,r4
 208
 209         l.srai  r8,r8,2
 210         l.sra   r8,r8,r4
 211
 212         REPORT_REG_TO_CONSOLE r8 /* Should be 0x000fffff  */
 213
 214         l.lwz   r9,0(r31)
 215         l.add   r8,r9,r8
 216         l.sw    0(r31),r8
 217
 218         /* Test the CPU flag. */
 219
 220         l.addi  r3,r0,1
 221         l.addi  r4,r0,-2
 222         l.addi  r8,r0,0
 223
 224         l.sfeq  r3,r3
 225         l.mfspr r5,r0,17
 226         l.andi  r4,r5,0x200
 227         l.add   r8,r8,r4
 228
 229         l.sfeq  r3,r4
 230         l.mfspr r5,r0,17
 231         l.andi  r4,r5,0x200
 232         l.add   r8,r8,r4
 233
 234         l.sfeqi r3,1
 235         l.mfspr r5,r0,17
 236         l.andi  r4,r5,0x200
 237         l.add   r8,r8,r4
 238
 239         l.sfeqi r3,-2
 240         l.mfspr r5,r0,17
 241         l.andi  r4,r5,0x200
 242         l.add   r8,r8,r4
 243
 244         l.sfne  r3,r3
 245         l.mfspr r5,r0,17
 246         l.andi  r4,r5,0x200
 247         l.add   r8,r8,r4
 248
 249         l.sfne  r3,r4
 250         l.mfspr r5,r0,17
 251         l.andi  r4,r5,0x200
 252         l.add   r8,r8,r4
 253
 254         l.sfnei r3,1
 255         l.mfspr r5,r0,17
 256         l.andi  r4,r5,0x200
 257         l.add   r8,r8,r4
 258
 259         l.sfnei r3,-2
 260         l.mfspr r5,r0,17
 261         l.andi  r4,r5,0x200
 262         l.add   r8,r8,r4
 263
 264         l.sfgtu r3,r3
 265         l.mfspr r5,r0,17
 266         l.andi  r4,r5,0x200
 267         l.add   r8,r8,r4
 268
 269         l.sfgtu r3,r4
 270         l.mfspr r5,r0,17
 271         l.andi  r4,r5,0x200
 272         l.add   r8,r8,r4
 273
 274         l.sfgtui    r3,1
 275         l.mfspr r5,r0,17
 276         l.andi  r4,r5,0x200
 277         l.add   r8,r8,r4
 278
 279         l.sfgtui    r3,-2
 280         l.mfspr r5,r0,17
 281         l.andi  r4,r5,0x200
 282         l.add   r8,r8,r4
 283
 284         l.sfgeu r3,r3
 285         l.mfspr r5,r0,17
 286         l.andi  r4,r5,0x200
 287         l.add   r8,r8,r4
 288
 289         l.sfgeu r3,r4
 290         l.mfspr r5,r0,17
 291         l.andi  r4,r5,0x200
 292         l.add   r8,r8,r4
 293
 294         l.sfgeui    r3,1
 295         l.mfspr r5,r0,17
 296         l.andi  r4,r5,0x200
 297         l.add   r8,r8,r4
 298
 299         l.sfgeui    r3,-2
 300         l.mfspr r5,r0,17
 301         l.andi  r4,r5,0x200
 302         l.add   r8,r8,r4
 303
 304         l.sfltu r3,r3
 305         l.mfspr r5,r0,17
 306         l.andi  r4,r5,0x200
 307         l.add   r8,r8,r4
 308
 309         l.sfltu r3,r4
 310         l.mfspr r5,r0,17
 311         l.andi  r4,r5,0x200
 312         l.add   r8,r8,r4
 313
 314         l.sfltui    r3,1
 315         l.mfspr r5,r0,17
 316         l.andi  r4,r5,0x200
 317         l.add   r8,r8,r4
 318
 319         l.sfltui    r3,-2
 320         l.mfspr r5,r0,17
 321         l.andi  r4,r5,0x200
 322         l.add   r8,r8,r4
 323
 324         l.sfleu r3,r3
 325         l.mfspr r5,r0,17
 326         l.andi  r4,r5,0x200
 327         l.add   r8,r8,r4
 328
 329         l.sfleu r3,r4
 330         l.mfspr r5,r0,17
 331         l.andi  r4,r5,0x200
 332         l.add   r8,r8,r4
 333
 334         l.sfleui    r3,1
 335         l.mfspr r5,r0,17
 336         l.andi  r4,r5,0x200
 337         l.add   r8,r8,r4
 338
 339         l.sfleui    r3,-2
 340         l.mfspr r5,r0,17
 341         l.andi  r4,r5,0x200
 342         l.add   r8,r8,r4
 343
 344         l.sfgts r3,r3
 345         l.mfspr r5,r0,17
 346         l.andi  r4,r5,0x200
 347         l.add   r8,r8,r4
 348
 349         l.sfgts r3,r4
 350         l.mfspr r5,r0,17
 351         l.andi  r4,r5,0x200
 352         l.add   r8,r8,r4
 353
 354         l.sfgtsi    r3,1
 355         l.mfspr r5,r0,17
 356         l.andi  r4,r5,0x200
 357         l.add   r8,r8,r4
 358
 359         l.sfgtsi    r3,-2
 360         l.mfspr r5,r0,17
 361         l.andi  r4,r5,0x200
 362         l.add   r8,r8,r4
 363
 364         l.sfges r3,r3
 365         l.mfspr r5,r0,17
 366         l.andi  r4,r5,0x200
 367         l.add   r8,r8,r4
 368
 369         l.sfges r3,r4
 370         l.mfspr r5,r0,17
 371         l.andi  r4,r5,0x200
 372         l.add   r8,r8,r4
 373
 374         l.sfgesi    r3,1
 375         l.mfspr r5,r0,17
 376         l.andi  r4,r5,0x200
 377         l.add   r8,r8,r4
 378
 379         l.sfgesi    r3,-2
 380         l.mfspr r5,r0,17
 381         l.andi  r4,r5,0x200
 382         l.add   r8,r8,r4
 383
 384         l.sflts r3,r3
 385         l.mfspr r5,r0,17
 386         l.andi  r4,r5,0x200
 387         l.add   r8,r8,r4
 388
 389         l.sflts r3,r4
 390         l.mfspr r5,r0,17
 391         l.andi  r4,r5,0x200
 392         l.add   r8,r8,r4
 393
 394         l.sfltsi    r3,1
 395         l.mfspr r5,r0,17
 396         l.andi  r4,r5,0x200
 397         l.add   r8,r8,r4
 398
 399         l.sfltsi    r3,-2
 400         l.mfspr r5,r0,17
 401         l.andi  r4,r5,0x200
 402         l.add   r8,r8,r4
 403
 404         l.sfles r3,r3
 405         l.mfspr r5,r0,17
 406         l.andi  r4,r5,0x200
 407         l.add   r8,r8,r4
 408
 409         l.sfles r3,r4
 410         l.mfspr r5,r0,17
 411         l.andi  r4,r5,0x200
 412         l.add   r8,r8,r4
 413
 414         l.sflesi    r3,1
 415         l.mfspr r5,r0,17
 416         l.andi  r4,r5,0x200
 417         l.add   r8,r8,r4
 418
 419         l.sflesi    r3,-2
 420         l.mfspr r5,r0,17
 421         l.andi  r4,r5,0x200
 422         l.add   r8,r8,r4
 423
 424         REPORT_REG_TO_CONSOLE r8 /* Should be 0x00002800  */
 425
 426         l.lwz   r9,0(r31)
 427         l.add   r8,r9,r8
 428         l.sw    0(r31),r8
 429
 430         /* Test the jump instructions.  */
 431
 432         l.addi  r8,r0,0
 433
 434         OR1K_DELAYED (
 435         OR1K_INST (l.addi  r8,r8,1),
 436         OR1K_INST (l.j _T1)
 437         )
 438
 439 _T2:    OR1K_DELAYED (
 440         OR1K_INST (l.addi  r8,r8,1),
 441         OR1K_INST (l.jr    r9)
 442         )
 443
 444 _T1:    OR1K_DELAYED (
 445         OR1K_INST (l.addi  r8,r8,1),
 446         OR1K_INST (l.jal   _T2)
 447         )
 448
 449         l.sfeqi r0,0
 450         OR1K_DELAYED (
 451         OR1K_INST (l.addi  r8,r8,1),
 452         OR1K_INST (l.bf    _T3)
 453         )
 454
 455 _T3:    l.sfeqi r0,1
 456         OR1K_DELAYED (
 457         OR1K_INST (l.addi  r8,r8,1),
 458         OR1K_INST (l.bf    _T4)
 459         )
 460
 461         l.addi  r8,r8,1
 462
 463 _T4:    l.sfeqi r0,0
 464         OR1K_DELAYED (
 465         OR1K_INST (l.addi  r8,r8,1),
 466         OR1K_INST (l.bnf    _T5)
 467         )
 468
 469         l.addi  r8,r8,1
 470
 471 _T5:    l.sfeqi r0,1
 472         OR1K_DELAYED (
 473         OR1K_INST (l.addi  r8,r8,1),
 474         OR1K_INST (l.bnf    _T6)
 475         )
 476
 477         l.addi  r8,r8,1
 478
 479 _T6:    l.movhi r3,hi (_T7)
 480         l.ori  r3,r3,lo (_T7)
 481         l.mtspr r0,r3,32
 482         l.mfspr r5,r0,17
 483         l.mtspr r0,r5,64
 484         l.rfe
 485         l.addi  r8,r8,1 /* l.rfe should not have a delay slot  */
 486
 487         l.addi  r8,r8,1
 488
 489 _T7:    REPORT_REG_TO_CONSOLE r8 /* Should be 0x000000009  */
 490
 491         l.lwz   r9,0(r31)
 492         l.add   r8,r9,r8
 493         l.sw    0(r31),r8
 494
 495         l.lwz   r9,0(r31)
 496         l.movhi r3,0x4c69
 497         l.ori   r3,r3,0xe5f7
 498         l.add   r8,r8,r3
 499
 500         REPORT_REG_TO_CONSOLE r8 /* Should be 0xdeaddead  */
 501
 502         /* Test l.movhi, on 32-bit implementations it should not
 503            sign-extend anything.  */
 504
 505         l.movhi r3, -1
 506         REPORT_REG_TO_CONSOLE r3
 507
 508         /* Test l.cmov  */
 509
 510         LOAD_IMMEDIATE r14, 0x12345678
 511         LOAD_IMMEDIATE r15, 0xABCDF0BD
 512
 513         SET_SPR_SR_FLAGS  SPR_SR_F, r6, r7
 514         l.cmov r10, r14, r15
 515         CLEAR_SPR_SR_FLAGS SPR_SR_F, r6, r7
 516         l.cmov r11, r14, r15
 517
 518         REPORT_REG_TO_CONSOLE r10
 519         REPORT_REG_TO_CONSOLE r11
 520
 521         POP LINK_REGISTER_R9
 522         RETURN_TO_LINK_REGISTER_R9